./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8be7027f Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.5-wip.dk.perfect-tracechecks-8be7027-m [2024-11-12 21:44:44,312 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-12 21:44:44,383 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-12 21:44:44,390 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-12 21:44:44,391 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-12 21:44:44,420 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-12 21:44:44,421 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-12 21:44:44,421 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-12 21:44:44,423 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-12 21:44:44,423 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-12 21:44:44,424 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-12 21:44:44,425 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-12 21:44:44,425 INFO L153 SettingsManager]: * Use SBE=true [2024-11-12 21:44:44,425 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-12 21:44:44,427 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-12 21:44:44,427 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-12 21:44:44,427 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-12 21:44:44,428 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-12 21:44:44,428 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-12 21:44:44,429 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-12 21:44:44,429 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-12 21:44:44,429 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-12 21:44:44,430 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-12 21:44:44,430 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-12 21:44:44,430 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-12 21:44:44,431 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-12 21:44:44,431 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-12 21:44:44,431 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-12 21:44:44,431 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-12 21:44:44,432 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-12 21:44:44,432 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-12 21:44:44,432 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-12 21:44:44,433 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-12 21:44:44,433 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-12 21:44:44,433 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-12 21:44:44,433 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-12 21:44:44,434 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-12 21:44:44,434 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-12 21:44:44,435 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-12 21:44:44,435 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2024-11-12 21:44:44,731 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-12 21:44:44,753 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-12 21:44:44,756 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-12 21:44:44,758 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-12 21:44:44,759 INFO L274 PluginConnector]: CDTParser initialized [2024-11-12 21:44:44,760 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2024-11-12 21:44:46,192 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-12 21:44:46,407 INFO L384 CDTParser]: Found 1 translation units. [2024-11-12 21:44:46,407 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2024-11-12 21:44:46,418 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e1693f746/b9aec98cbebc465689a3a6138c98936b/FLAG96fe5f54c [2024-11-12 21:44:46,772 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e1693f746/b9aec98cbebc465689a3a6138c98936b [2024-11-12 21:44:46,774 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-12 21:44:46,776 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-12 21:44:46,778 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-12 21:44:46,778 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-12 21:44:46,784 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-12 21:44:46,784 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:44:46" (1/1) ... [2024-11-12 21:44:46,785 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5052f4e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:46, skipping insertion in model container [2024-11-12 21:44:46,785 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:44:46" (1/1) ... [2024-11-12 21:44:46,822 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-12 21:44:47,089 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:44:47,101 INFO L200 MainTranslator]: Completed pre-run [2024-11-12 21:44:47,146 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:44:47,174 INFO L204 MainTranslator]: Completed translation [2024-11-12 21:44:47,175 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47 WrapperNode [2024-11-12 21:44:47,175 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-12 21:44:47,176 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-12 21:44:47,177 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-12 21:44:47,177 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-12 21:44:47,184 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,195 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,248 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 822 [2024-11-12 21:44:47,249 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-12 21:44:47,249 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-12 21:44:47,250 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-12 21:44:47,250 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-12 21:44:47,265 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,265 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,270 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,308 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-12 21:44:47,308 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,309 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,318 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,326 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,328 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,331 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,335 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-12 21:44:47,336 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-12 21:44:47,336 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-12 21:44:47,336 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-12 21:44:47,337 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (1/1) ... [2024-11-12 21:44:47,343 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:44:47,366 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:47,382 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:44:47,385 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-12 21:44:47,430 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-12 21:44:47,430 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-12 21:44:47,430 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-12 21:44:47,430 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-12 21:44:47,538 INFO L238 CfgBuilder]: Building ICFG [2024-11-12 21:44:47,540 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-12 21:44:48,239 INFO L? ?]: Removed 144 outVars from TransFormulas that were not future-live. [2024-11-12 21:44:48,241 INFO L287 CfgBuilder]: Performing block encoding [2024-11-12 21:44:48,270 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-12 21:44:48,271 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-12 21:44:48,271 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:44:48 BoogieIcfgContainer [2024-11-12 21:44:48,271 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-12 21:44:48,272 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-12 21:44:48,272 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-12 21:44:48,276 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-12 21:44:48,277 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:44:48,277 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 09:44:46" (1/3) ... [2024-11-12 21:44:48,278 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fa19da8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:44:48, skipping insertion in model container [2024-11-12 21:44:48,278 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:44:48,278 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:47" (2/3) ... [2024-11-12 21:44:48,278 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fa19da8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:44:48, skipping insertion in model container [2024-11-12 21:44:48,278 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:44:48,278 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:44:48" (3/3) ... [2024-11-12 21:44:48,280 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2024-11-12 21:44:48,336 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2024-11-12 21:44:48,337 INFO L302 stractBuchiCegarLoop]: Hoare is None [2024-11-12 21:44:48,337 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-12 21:44:48,337 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-12 21:44:48,337 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-12 21:44:48,337 INFO L306 stractBuchiCegarLoop]: Difference is false [2024-11-12 21:44:48,338 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-12 21:44:48,338 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-12 21:44:48,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:48,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2024-11-12 21:44:48,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:48,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:48,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:48,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:48,406 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-12 21:44:48,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:48,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2024-11-12 21:44:48,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:48,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:48,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:48,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:48,435 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:48,436 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:48,445 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:48,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2024-11-12 21:44:48,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:48,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198227896] [2024-11-12 21:44:48,460 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:48,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:48,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:48,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:48,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198227896] [2024-11-12 21:44:48,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198227896] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:48,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [425369163] [2024-11-12 21:44:48,686 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:48,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:48,687 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:48,689 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:48,691 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-12 21:44:48,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:48,788 INFO L256 TraceCheckSpWp]: Trace formula consists of 160 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:44:48,793 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:48,852 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:48,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [425369163] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:48,886 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:48,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-12 21:44:48,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601999519] [2024-11-12 21:44:48,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:48,895 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:44:48,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:48,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1122762879, now seen corresponding path program 1 times [2024-11-12 21:44:48,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:48,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353197673] [2024-11-12 21:44:48,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:48,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:48,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:48,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:48,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353197673] [2024-11-12 21:44:48,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353197673] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:48,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [956889123] [2024-11-12 21:44:48,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:48,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:48,988 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:49,007 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:49,009 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-12 21:44:49,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:49,082 INFO L256 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-12 21:44:49,084 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:49,095 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:49,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [956889123] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:49,105 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:49,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:44:49,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955426812] [2024-11-12 21:44:49,106 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:49,107 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:49,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:49,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:44:49,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:44:49,145 INFO L87 Difference]: Start difference. First operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 5 states have (on average 15.0) internal successors, (75), 5 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:49,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:49,223 INFO L93 Difference]: Finished difference Result 327 states and 480 transitions. [2024-11-12 21:44:49,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 480 transitions. [2024-11-12 21:44:49,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-12 21:44:49,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 322 states and 475 transitions. [2024-11-12 21:44:49,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2024-11-12 21:44:49,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2024-11-12 21:44:49,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 475 transitions. [2024-11-12 21:44:49,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:49,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 475 transitions. [2024-11-12 21:44:49,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 475 transitions. [2024-11-12 21:44:49,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2024-11-12 21:44:49,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4751552795031055) internal successors, (475), 321 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:49,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 475 transitions. [2024-11-12 21:44:49,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 475 transitions. [2024-11-12 21:44:49,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-12 21:44:49,295 INFO L426 stractBuchiCegarLoop]: Abstraction has 322 states and 475 transitions. [2024-11-12 21:44:49,295 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-12 21:44:49,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 475 transitions. [2024-11-12 21:44:49,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-12 21:44:49,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:49,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:49,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:49,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:49,303 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:49,303 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:49,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:49,304 INFO L85 PathProgramCache]: Analyzing trace with hash -1620985853, now seen corresponding path program 1 times [2024-11-12 21:44:49,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:49,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993332233] [2024-11-12 21:44:49,305 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:49,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:49,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:49,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:49,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993332233] [2024-11-12 21:44:49,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993332233] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:49,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [27049247] [2024-11-12 21:44:49,392 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:49,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:49,392 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:49,397 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:49,398 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-12 21:44:49,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:49,473 INFO L256 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:44:49,474 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:49,509 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:49,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [27049247] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:49,547 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:49,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:44:49,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439379800] [2024-11-12 21:44:49,548 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:49,548 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:44:49,548 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:49,549 INFO L85 PathProgramCache]: Analyzing trace with hash 165039805, now seen corresponding path program 1 times [2024-11-12 21:44:49,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:49,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727600307] [2024-11-12 21:44:49,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:49,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:49,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:49,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:49,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727600307] [2024-11-12 21:44:49,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727600307] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:49,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115776398] [2024-11-12 21:44:49,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:49,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:49,649 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:49,651 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:49,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-12 21:44:49,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:49,725 INFO L256 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:49,727 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:49,793 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:49,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1115776398] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:49,850 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:49,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:49,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988596860] [2024-11-12 21:44:49,851 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:49,852 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:49,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:49,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:44:49,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:44:49,853 INFO L87 Difference]: Start difference. First operand 322 states and 475 transitions. cyclomatic complexity: 154 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:49,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:49,923 INFO L93 Difference]: Finished difference Result 322 states and 463 transitions. [2024-11-12 21:44:49,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 463 transitions. [2024-11-12 21:44:49,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-12 21:44:49,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 463 transitions. [2024-11-12 21:44:49,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2024-11-12 21:44:49,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2024-11-12 21:44:49,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 463 transitions. [2024-11-12 21:44:49,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:49,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 463 transitions. [2024-11-12 21:44:49,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 463 transitions. [2024-11-12 21:44:49,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2024-11-12 21:44:49,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.437888198757764) internal successors, (463), 321 states have internal predecessors, (463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:49,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 463 transitions. [2024-11-12 21:44:49,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 463 transitions. [2024-11-12 21:44:49,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:44:49,958 INFO L426 stractBuchiCegarLoop]: Abstraction has 322 states and 463 transitions. [2024-11-12 21:44:49,959 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-12 21:44:49,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 463 transitions. [2024-11-12 21:44:49,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-12 21:44:49,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:49,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:49,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:49,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:49,965 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:49,965 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:49,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:49,966 INFO L85 PathProgramCache]: Analyzing trace with hash 203937346, now seen corresponding path program 1 times [2024-11-12 21:44:49,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:49,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031189868] [2024-11-12 21:44:49,969 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:49,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:49,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:50,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031189868] [2024-11-12 21:44:50,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031189868] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:50,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [910763827] [2024-11-12 21:44:50,021 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:50,022 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:50,028 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:50,031 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-12 21:44:50,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,106 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:44:50,107 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:50,160 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:50,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [910763827] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:50,245 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:50,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:44:50,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799262451] [2024-11-12 21:44:50,247 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:50,249 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:44:50,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:50,250 INFO L85 PathProgramCache]: Analyzing trace with hash -238867073, now seen corresponding path program 1 times [2024-11-12 21:44:50,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:50,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211783168] [2024-11-12 21:44:50,250 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:50,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:50,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211783168] [2024-11-12 21:44:50,351 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211783168] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:50,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1627699444] [2024-11-12 21:44:50,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,351 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:50,351 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:50,354 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:50,355 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-12 21:44:50,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,417 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:50,418 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:50,462 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:50,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1627699444] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:50,513 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:50,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:50,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386992122] [2024-11-12 21:44:50,514 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:50,514 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:50,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:50,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:44:50,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:44:50,515 INFO L87 Difference]: Start difference. First operand 322 states and 463 transitions. cyclomatic complexity: 142 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 4 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:50,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:50,582 INFO L93 Difference]: Finished difference Result 552 states and 784 transitions. [2024-11-12 21:44:50,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 784 transitions. [2024-11-12 21:44:50,587 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2024-11-12 21:44:50,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 784 transitions. [2024-11-12 21:44:50,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2024-11-12 21:44:50,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2024-11-12 21:44:50,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 784 transitions. [2024-11-12 21:44:50,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:50,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 784 transitions. [2024-11-12 21:44:50,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 784 transitions. [2024-11-12 21:44:50,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 550. [2024-11-12 21:44:50,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 550 states, 550 states have (on average 1.4218181818181819) internal successors, (782), 549 states have internal predecessors, (782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:50,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 782 transitions. [2024-11-12 21:44:50,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 550 states and 782 transitions. [2024-11-12 21:44:50,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:44:50,621 INFO L426 stractBuchiCegarLoop]: Abstraction has 550 states and 782 transitions. [2024-11-12 21:44:50,621 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-12 21:44:50,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 550 states and 782 transitions. [2024-11-12 21:44:50,624 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 494 [2024-11-12 21:44:50,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:50,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:50,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:50,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:50,626 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:50,626 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:50,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:50,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2024-11-12 21:44:50,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:50,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721087119] [2024-11-12 21:44:50,627 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:50,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:50,639 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:50,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:50,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:50,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:50,676 INFO L85 PathProgramCache]: Analyzing trace with hash -142907201, now seen corresponding path program 1 times [2024-11-12 21:44:50,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:50,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134483435] [2024-11-12 21:44:50,677 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:50,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:50,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134483435] [2024-11-12 21:44:50,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134483435] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:50,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [323517200] [2024-11-12 21:44:50,721 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,721 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:50,721 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:50,723 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:50,724 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-12 21:44:50,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,787 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:50,789 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:50,833 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:50,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [323517200] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:50,877 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:50,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:50,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580032974] [2024-11-12 21:44:50,878 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:50,878 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:50,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:50,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:50,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:50,879 INFO L87 Difference]: Start difference. First operand 550 states and 782 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:50,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:50,900 INFO L93 Difference]: Finished difference Result 659 states and 935 transitions. [2024-11-12 21:44:50,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 935 transitions. [2024-11-12 21:44:50,904 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 567 [2024-11-12 21:44:50,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 935 transitions. [2024-11-12 21:44:50,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-12 21:44:50,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-12 21:44:50,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 935 transitions. [2024-11-12 21:44:50,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:50,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 935 transitions. [2024-11-12 21:44:50,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 935 transitions. [2024-11-12 21:44:50,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-12 21:44:50,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.4188163884673748) internal successors, (935), 658 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:50,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 935 transitions. [2024-11-12 21:44:50,920 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 935 transitions. [2024-11-12 21:44:50,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:50,922 INFO L426 stractBuchiCegarLoop]: Abstraction has 659 states and 935 transitions. [2024-11-12 21:44:50,922 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-12 21:44:50,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 935 transitions. [2024-11-12 21:44:50,925 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 567 [2024-11-12 21:44:50,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:50,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:50,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:50,926 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:50,926 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:50,926 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:50,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:50,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1665536133, now seen corresponding path program 1 times [2024-11-12 21:44:50,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:50,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255326895] [2024-11-12 21:44:50,927 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:50,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:50,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:50,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255326895] [2024-11-12 21:44:50,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255326895] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:50,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [982254912] [2024-11-12 21:44:50,979 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:50,979 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:50,980 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:50,982 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:50,983 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-12 21:44:51,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,043 INFO L256 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:44:51,044 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:51,058 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:51,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [982254912] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:51,075 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:51,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 3 [2024-11-12 21:44:51,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340146908] [2024-11-12 21:44:51,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:51,076 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:44:51,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:51,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1631669632, now seen corresponding path program 1 times [2024-11-12 21:44:51,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:51,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256060389] [2024-11-12 21:44:51,077 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:51,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:51,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256060389] [2024-11-12 21:44:51,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256060389] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:51,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1383714840] [2024-11-12 21:44:51,162 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,162 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:51,162 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:51,164 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:51,175 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-12 21:44:51,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,236 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:44:51,240 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:51,270 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:51,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1383714840] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:51,290 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:51,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:44:51,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251703659] [2024-11-12 21:44:51,290 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:51,291 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:51,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:51,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:44:51,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:44:51,291 INFO L87 Difference]: Start difference. First operand 659 states and 935 transitions. cyclomatic complexity: 278 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:51,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:51,310 INFO L93 Difference]: Finished difference Result 550 states and 774 transitions. [2024-11-12 21:44:51,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 550 states and 774 transitions. [2024-11-12 21:44:51,313 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 494 [2024-11-12 21:44:51,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 550 states to 550 states and 774 transitions. [2024-11-12 21:44:51,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 550 [2024-11-12 21:44:51,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 550 [2024-11-12 21:44:51,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 550 states and 774 transitions. [2024-11-12 21:44:51,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:51,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 550 states and 774 transitions. [2024-11-12 21:44:51,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states and 774 transitions. [2024-11-12 21:44:51,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 550. [2024-11-12 21:44:51,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 550 states, 550 states have (on average 1.4072727272727272) internal successors, (774), 549 states have internal predecessors, (774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:51,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 774 transitions. [2024-11-12 21:44:51,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 550 states and 774 transitions. [2024-11-12 21:44:51,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:51,332 INFO L426 stractBuchiCegarLoop]: Abstraction has 550 states and 774 transitions. [2024-11-12 21:44:51,332 INFO L333 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-12 21:44:51,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 550 states and 774 transitions. [2024-11-12 21:44:51,334 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 494 [2024-11-12 21:44:51,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:51,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:51,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:51,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:51,336 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:51,336 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:51,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:51,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2024-11-12 21:44:51,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:51,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338828602] [2024-11-12 21:44:51,337 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:51,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:51,344 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:51,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:51,355 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:51,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:51,355 INFO L85 PathProgramCache]: Analyzing trace with hash 300993473, now seen corresponding path program 1 times [2024-11-12 21:44:51,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:51,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508820893] [2024-11-12 21:44:51,356 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:51,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:51,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508820893] [2024-11-12 21:44:51,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508820893] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:51,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1383914793] [2024-11-12 21:44:51,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:51,430 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:51,433 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:51,434 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-12 21:44:51,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,500 INFO L256 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:44:51,501 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:51,513 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:51,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1383914793] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:51,533 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:51,533 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:44:51,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053600684] [2024-11-12 21:44:51,534 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:51,534 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:51,534 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:51,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:44:51,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:44:51,535 INFO L87 Difference]: Start difference. First operand 550 states and 774 transitions. cyclomatic complexity: 226 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:51,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:51,583 INFO L93 Difference]: Finished difference Result 564 states and 788 transitions. [2024-11-12 21:44:51,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 564 states and 788 transitions. [2024-11-12 21:44:51,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 508 [2024-11-12 21:44:51,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 564 states to 564 states and 788 transitions. [2024-11-12 21:44:51,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 564 [2024-11-12 21:44:51,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 564 [2024-11-12 21:44:51,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 564 states and 788 transitions. [2024-11-12 21:44:51,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:51,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 564 states and 788 transitions. [2024-11-12 21:44:51,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 564 states and 788 transitions. [2024-11-12 21:44:51,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 564 to 556. [2024-11-12 21:44:51,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 556 states have (on average 1.4028776978417266) internal successors, (780), 555 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:51,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 780 transitions. [2024-11-12 21:44:51,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 556 states and 780 transitions. [2024-11-12 21:44:51,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:44:51,599 INFO L426 stractBuchiCegarLoop]: Abstraction has 556 states and 780 transitions. [2024-11-12 21:44:51,599 INFO L333 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-12 21:44:51,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 556 states and 780 transitions. [2024-11-12 21:44:51,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 500 [2024-11-12 21:44:51,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:51,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:51,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:51,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:51,603 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:51,603 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:51,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:51,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2024-11-12 21:44:51,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:51,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245699892] [2024-11-12 21:44:51,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:51,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:51,611 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:51,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:51,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:51,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:51,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1971412679, now seen corresponding path program 1 times [2024-11-12 21:44:51,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:51,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112781623] [2024-11-12 21:44:51,624 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:51,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:51,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112781623] [2024-11-12 21:44:51,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112781623] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:51,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [749300904] [2024-11-12 21:44:51,716 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:51,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:51,716 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:51,718 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:51,720 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-12 21:44:51,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:51,785 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-12 21:44:51,786 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:51,812 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:51,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [749300904] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:51,820 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:51,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-12 21:44:51,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380840175] [2024-11-12 21:44:51,821 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:51,821 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:51,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:51,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-12 21:44:51,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-12 21:44:51,822 INFO L87 Difference]: Start difference. First operand 556 states and 780 transitions. cyclomatic complexity: 226 Second operand has 8 states, 8 states have (on average 10.375) internal successors, (83), 8 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:52,061 INFO L93 Difference]: Finished difference Result 580 states and 788 transitions. [2024-11-12 21:44:52,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 788 transitions. [2024-11-12 21:44:52,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 524 [2024-11-12 21:44:52,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 580 states and 788 transitions. [2024-11-12 21:44:52,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 580 [2024-11-12 21:44:52,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 580 [2024-11-12 21:44:52,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 580 states and 788 transitions. [2024-11-12 21:44:52,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:52,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 580 states and 788 transitions. [2024-11-12 21:44:52,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states and 788 transitions. [2024-11-12 21:44:52,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 580. [2024-11-12 21:44:52,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 580 states, 580 states have (on average 1.3586206896551725) internal successors, (788), 579 states have internal predecessors, (788), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 580 states to 580 states and 788 transitions. [2024-11-12 21:44:52,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 580 states and 788 transitions. [2024-11-12 21:44:52,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-12 21:44:52,077 INFO L426 stractBuchiCegarLoop]: Abstraction has 580 states and 788 transitions. [2024-11-12 21:44:52,078 INFO L333 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-12 21:44:52,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 580 states and 788 transitions. [2024-11-12 21:44:52,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 524 [2024-11-12 21:44:52,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:52,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:52,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,081 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:44:52,081 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:44:52,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2024-11-12 21:44:52,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328746095] [2024-11-12 21:44:52,082 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,093 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:52,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:52,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,129 INFO L85 PathProgramCache]: Analyzing trace with hash -1229293749, now seen corresponding path program 1 times [2024-11-12 21:44:52,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541831451] [2024-11-12 21:44:52,130 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:52,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541831451] [2024-11-12 21:44:52,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541831451] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:52,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1159480886] [2024-11-12 21:44:52,165 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:52,165 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:52,167 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:52,171 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-12 21:44:52,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,235 INFO L256 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:52,236 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:52,308 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:52,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1159480886] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:52,375 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:52,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:52,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722794265] [2024-11-12 21:44:52,375 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:52,376 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:44:52,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:52,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:52,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:52,376 INFO L87 Difference]: Start difference. First operand 580 states and 788 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:52,401 INFO L93 Difference]: Finished difference Result 806 states and 1081 transitions. [2024-11-12 21:44:52,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 806 states and 1081 transitions. [2024-11-12 21:44:52,405 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 746 [2024-11-12 21:44:52,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 806 states to 806 states and 1081 transitions. [2024-11-12 21:44:52,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2024-11-12 21:44:52,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2024-11-12 21:44:52,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 806 states and 1081 transitions. [2024-11-12 21:44:52,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:52,411 INFO L218 hiAutomatonCegarLoop]: Abstraction has 806 states and 1081 transitions. [2024-11-12 21:44:52,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states and 1081 transitions. [2024-11-12 21:44:52,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 806. [2024-11-12 21:44:52,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 806 states have (on average 1.3411910669975187) internal successors, (1081), 805 states have internal predecessors, (1081), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1081 transitions. [2024-11-12 21:44:52,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 806 states and 1081 transitions. [2024-11-12 21:44:52,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:52,425 INFO L426 stractBuchiCegarLoop]: Abstraction has 806 states and 1081 transitions. [2024-11-12 21:44:52,425 INFO L333 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-12 21:44:52,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 806 states and 1081 transitions. [2024-11-12 21:44:52,428 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 746 [2024-11-12 21:44:52,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:52,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:52,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,429 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,429 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:44:52,429 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:44:52,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2024-11-12 21:44:52,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158430563] [2024-11-12 21:44:52,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,437 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:52,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,445 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:52,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,446 INFO L85 PathProgramCache]: Analyzing trace with hash -616621386, now seen corresponding path program 1 times [2024-11-12 21:44:52,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609078038] [2024-11-12 21:44:52,446 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,449 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:52,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,451 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:52,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,452 INFO L85 PathProgramCache]: Analyzing trace with hash 945603068, now seen corresponding path program 1 times [2024-11-12 21:44:52,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705349098] [2024-11-12 21:44:52,452 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:52,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705349098] [2024-11-12 21:44:52,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705349098] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:52,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1950291810] [2024-11-12 21:44:52,479 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,480 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:52,480 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:52,487 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:52,499 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-12 21:44:52,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,563 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:52,564 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:52,632 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:52,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1950291810] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:52,709 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:52,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:52,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834393979] [2024-11-12 21:44:52,709 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:52,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:52,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:52,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:52,766 INFO L87 Difference]: Start difference. First operand 806 states and 1081 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:52,831 INFO L93 Difference]: Finished difference Result 1468 states and 1947 transitions. [2024-11-12 21:44:52,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1468 states and 1947 transitions. [2024-11-12 21:44:52,838 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1354 [2024-11-12 21:44:52,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1468 states to 1468 states and 1947 transitions. [2024-11-12 21:44:52,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1468 [2024-11-12 21:44:52,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1468 [2024-11-12 21:44:52,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1468 states and 1947 transitions. [2024-11-12 21:44:52,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:52,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1468 states and 1947 transitions. [2024-11-12 21:44:52,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1468 states and 1947 transitions. [2024-11-12 21:44:52,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1468 to 1392. [2024-11-12 21:44:52,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1392 states, 1392 states have (on average 1.3311781609195403) internal successors, (1853), 1391 states have internal predecessors, (1853), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:52,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1392 states to 1392 states and 1853 transitions. [2024-11-12 21:44:52,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1392 states and 1853 transitions. [2024-11-12 21:44:52,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:52,871 INFO L426 stractBuchiCegarLoop]: Abstraction has 1392 states and 1853 transitions. [2024-11-12 21:44:52,871 INFO L333 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-12 21:44:52,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1392 states and 1853 transitions. [2024-11-12 21:44:52,877 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1278 [2024-11-12 21:44:52,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:52,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:52,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:52,878 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:44:52,878 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:44:52,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,879 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2024-11-12 21:44:52,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129809654] [2024-11-12 21:44:52,879 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:52,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129809654] [2024-11-12 21:44:52,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129809654] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:52,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2113784658] [2024-11-12 21:44:52,898 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,898 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:52,898 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:52,900 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:52,902 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-12 21:44:52,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:52,965 INFO L256 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:52,966 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:52,971 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:52,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2113784658] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:52,978 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:52,978 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:52,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866412749] [2024-11-12 21:44:52,979 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:52,979 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:44:52,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:52,979 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 1 times [2024-11-12 21:44:52,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:52,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071188495] [2024-11-12 21:44:52,980 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:52,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:52,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,983 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:52,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:52,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:53,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:53,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:53,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:53,054 INFO L87 Difference]: Start difference. First operand 1392 states and 1853 transitions. cyclomatic complexity: 463 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:53,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:53,064 INFO L93 Difference]: Finished difference Result 1342 states and 1785 transitions. [2024-11-12 21:44:53,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1342 states and 1785 transitions. [2024-11-12 21:44:53,070 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1278 [2024-11-12 21:44:53,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1342 states to 1342 states and 1785 transitions. [2024-11-12 21:44:53,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1342 [2024-11-12 21:44:53,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1342 [2024-11-12 21:44:53,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1342 states and 1785 transitions. [2024-11-12 21:44:53,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:53,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1342 states and 1785 transitions. [2024-11-12 21:44:53,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1342 states and 1785 transitions. [2024-11-12 21:44:53,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1342 to 1342. [2024-11-12 21:44:53,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1342 states, 1342 states have (on average 1.3301043219076005) internal successors, (1785), 1341 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:53,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1342 states to 1342 states and 1785 transitions. [2024-11-12 21:44:53,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1342 states and 1785 transitions. [2024-11-12 21:44:53,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:53,097 INFO L426 stractBuchiCegarLoop]: Abstraction has 1342 states and 1785 transitions. [2024-11-12 21:44:53,097 INFO L333 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-12 21:44:53,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1342 states and 1785 transitions. [2024-11-12 21:44:53,102 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1278 [2024-11-12 21:44:53,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:53,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:53,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:53,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:53,103 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:44:53,103 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:44:53,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2024-11-12 21:44:53,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680207073] [2024-11-12 21:44:53,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,110 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:53,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,118 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:53,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,118 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 2 times [2024-11-12 21:44:53,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195867267] [2024-11-12 21:44:53,119 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,122 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:53,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:53,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,124 INFO L85 PathProgramCache]: Analyzing trace with hash -1934834854, now seen corresponding path program 1 times [2024-11-12 21:44:53,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484899578] [2024-11-12 21:44:53,125 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:53,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:53,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484899578] [2024-11-12 21:44:53,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1484899578] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:53,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [635659814] [2024-11-12 21:44:53,158 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,158 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:53,158 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:53,160 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:53,161 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-12 21:44:53,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:53,229 INFO L256 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:53,230 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:53,295 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:53,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [635659814] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:53,371 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:53,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:44:53,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720205703] [2024-11-12 21:44:53,372 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:53,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:53,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:53,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:53,428 INFO L87 Difference]: Start difference. First operand 1342 states and 1785 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:53,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:53,465 INFO L93 Difference]: Finished difference Result 1735 states and 2299 transitions. [2024-11-12 21:44:53,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1735 states and 2299 transitions. [2024-11-12 21:44:53,473 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1671 [2024-11-12 21:44:53,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1735 states to 1735 states and 2299 transitions. [2024-11-12 21:44:53,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1735 [2024-11-12 21:44:53,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1735 [2024-11-12 21:44:53,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1735 states and 2299 transitions. [2024-11-12 21:44:53,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:53,484 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1735 states and 2299 transitions. [2024-11-12 21:44:53,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1735 states and 2299 transitions. [2024-11-12 21:44:53,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1735 to 1691. [2024-11-12 21:44:53,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1691 states, 1691 states have (on average 1.326434062684802) internal successors, (2243), 1690 states have internal predecessors, (2243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:53,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 1691 states and 2243 transitions. [2024-11-12 21:44:53,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1691 states and 2243 transitions. [2024-11-12 21:44:53,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:53,509 INFO L426 stractBuchiCegarLoop]: Abstraction has 1691 states and 2243 transitions. [2024-11-12 21:44:53,509 INFO L333 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-12 21:44:53,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1691 states and 2243 transitions. [2024-11-12 21:44:53,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1627 [2024-11-12 21:44:53,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:53,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:53,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:53,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:53,516 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:44:53,516 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2024-11-12 21:44:53,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2024-11-12 21:44:53,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012917743] [2024-11-12 21:44:53,517 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,524 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:53,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:53,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1484720438, now seen corresponding path program 1 times [2024-11-12 21:44:53,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263528700] [2024-11-12 21:44:53,533 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,536 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:53,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:53,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:53,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:53,539 INFO L85 PathProgramCache]: Analyzing trace with hash 340499836, now seen corresponding path program 1 times [2024-11-12 21:44:53,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:53,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418665962] [2024-11-12 21:44:53,539 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:53,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:53,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:44:53,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418665962] [2024-11-12 21:44:53,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418665962] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:44:53,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [570934951] [2024-11-12 21:44:53,567 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:53,567 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:44:53,568 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:53,570 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:44:53,571 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-12 21:44:53,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:44:53,639 INFO L256 TraceCheckSpWp]: Trace formula consists of 181 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:44:53,640 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:44:53,709 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:44:53,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [570934951] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:44:53,818 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:44:53,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:44:53,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950471534] [2024-11-12 21:44:53,818 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:44:53,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:44:53,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:44:53,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:44:53,873 INFO L87 Difference]: Start difference. First operand 1691 states and 2243 transitions. cyclomatic complexity: 554 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:53,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:44:53,924 INFO L93 Difference]: Finished difference Result 2808 states and 3684 transitions. [2024-11-12 21:44:53,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2808 states and 3684 transitions. [2024-11-12 21:44:53,940 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2736 [2024-11-12 21:44:53,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2808 states to 2808 states and 3684 transitions. [2024-11-12 21:44:53,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2808 [2024-11-12 21:44:53,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2808 [2024-11-12 21:44:53,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2808 states and 3684 transitions. [2024-11-12 21:44:53,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:44:53,958 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2808 states and 3684 transitions. [2024-11-12 21:44:53,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2808 states and 3684 transitions. [2024-11-12 21:44:53,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2808 to 2760. [2024-11-12 21:44:54,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2760 states, 2760 states have (on average 1.317391304347826) internal successors, (3636), 2759 states have internal predecessors, (3636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:44:54,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2760 states to 2760 states and 3636 transitions. [2024-11-12 21:44:54,008 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2760 states and 3636 transitions. [2024-11-12 21:44:54,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:44:54,010 INFO L426 stractBuchiCegarLoop]: Abstraction has 2760 states and 3636 transitions. [2024-11-12 21:44:54,010 INFO L333 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-12 21:44:54,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2760 states and 3636 transitions. [2024-11-12 21:44:54,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2688 [2024-11-12 21:44:54,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:44:54,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:44:54,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:54,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:44:54,021 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:44:54,022 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" [2024-11-12 21:44:54,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:54,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2024-11-12 21:44:54,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:54,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780065547] [2024-11-12 21:44:54,023 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:54,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:54,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,030 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:54,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:54,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:54,041 INFO L85 PathProgramCache]: Analyzing trace with hash 887098260, now seen corresponding path program 1 times [2024-11-12 21:44:54,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:54,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141560529] [2024-11-12 21:44:54,041 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:54,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:54,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,044 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:54,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,047 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:54,047 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:44:54,047 INFO L85 PathProgramCache]: Analyzing trace with hash 802727514, now seen corresponding path program 1 times [2024-11-12 21:44:54,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:44:54,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370276532] [2024-11-12 21:44:54,048 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:44:54,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:44:54,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,056 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:54,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:44:54,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:54,836 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:44:54,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:44:55,014 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 09:44:55 BoogieIcfgContainer [2024-11-12 21:44:55,014 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-12 21:44:55,014 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-12 21:44:55,015 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-12 21:44:55,015 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-12 21:44:55,015 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:44:48" (3/4) ... [2024-11-12 21:44:55,017 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-12 21:44:55,085 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-12 21:44:55,086 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-12 21:44:55,086 INFO L158 Benchmark]: Toolchain (without parser) took 8310.81ms. Allocated memory was 176.2MB in the beginning and 257.9MB in the end (delta: 81.8MB). Free memory was 122.4MB in the beginning and 167.7MB in the end (delta: -45.2MB). Peak memory consumption was 35.0MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,087 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 96.5MB. Free memory is still 57.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-12 21:44:55,087 INFO L158 Benchmark]: CACSL2BoogieTranslator took 397.42ms. Allocated memory is still 176.2MB. Free memory was 122.4MB in the beginning and 105.7MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,087 INFO L158 Benchmark]: Boogie Procedure Inliner took 72.41ms. Allocated memory is still 176.2MB. Free memory was 105.7MB in the beginning and 102.5MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,087 INFO L158 Benchmark]: Boogie Preprocessor took 85.49ms. Allocated memory is still 176.2MB. Free memory was 102.0MB in the beginning and 97.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,088 INFO L158 Benchmark]: RCFGBuilder took 935.69ms. Allocated memory is still 176.2MB. Free memory was 97.8MB in the beginning and 99.8MB in the end (delta: -1.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,088 INFO L158 Benchmark]: BuchiAutomizer took 6741.78ms. Allocated memory was 176.2MB in the beginning and 257.9MB in the end (delta: 81.8MB). Free memory was 99.8MB in the beginning and 175.0MB in the end (delta: -75.2MB). Peak memory consumption was 9.5MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,088 INFO L158 Benchmark]: Witness Printer took 71.33ms. Allocated memory is still 257.9MB. Free memory was 175.0MB in the beginning and 167.7MB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-12 21:44:55,090 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 96.5MB. Free memory is still 57.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 397.42ms. Allocated memory is still 176.2MB. Free memory was 122.4MB in the beginning and 105.7MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 72.41ms. Allocated memory is still 176.2MB. Free memory was 105.7MB in the beginning and 102.5MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 85.49ms. Allocated memory is still 176.2MB. Free memory was 102.0MB in the beginning and 97.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 935.69ms. Allocated memory is still 176.2MB. Free memory was 97.8MB in the beginning and 99.8MB in the end (delta: -1.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 6741.78ms. Allocated memory was 176.2MB in the beginning and 257.9MB in the end (delta: 81.8MB). Free memory was 99.8MB in the beginning and 175.0MB in the end (delta: -75.2MB). Peak memory consumption was 9.5MB. Max. memory is 16.1GB. * Witness Printer took 71.33ms. Allocated memory is still 257.9MB. Free memory was 175.0MB in the beginning and 167.7MB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 2760 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.5s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 5.1s. Construction of modules took 0.4s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 12 MinimizatonAttempts, 178 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5089 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5089 mSDsluCounter, 11518 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5895 mSDsCounter, 145 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 505 IncrementalHoareTripleChecker+Invalid, 650 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 145 mSolverCounterUnsat, 5623 mSDtfsCounter, 505 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-12 21:44:55,130 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:55,325 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-11-12 21:44:55,528 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:55,727 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:55,927 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:56,127 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:56,327 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:56,527 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-12 21:44:56,728 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:56,930 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:57,128 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:57,328 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-12 21:44:57,529 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:57,729 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:57,929 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:58,129 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-12 21:44:58,330 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)