./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8be7027f Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.2.5-wip.dk.perfect-tracechecks-8be7027-m [2024-11-12 21:44:57,000 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-12 21:44:57,081 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-12 21:44:57,085 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-12 21:44:57,086 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-12 21:44:57,130 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-12 21:44:57,130 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-12 21:44:57,131 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-12 21:44:57,131 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-12 21:44:57,132 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-12 21:44:57,149 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-12 21:44:57,149 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-12 21:44:57,150 INFO L153 SettingsManager]: * Use SBE=true [2024-11-12 21:44:57,150 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-12 21:44:57,150 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-12 21:44:57,150 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-12 21:44:57,150 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-12 21:44:57,151 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-12 21:44:57,151 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-12 21:44:57,151 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-12 21:44:57,151 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-12 21:44:57,156 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-12 21:44:57,156 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-12 21:44:57,157 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-12 21:44:57,158 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-12 21:44:57,158 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-12 21:44:57,158 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-12 21:44:57,158 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-12 21:44:57,158 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-12 21:44:57,158 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-12 21:44:57,158 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-12 21:44:57,159 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-12 21:44:57,159 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-12 21:44:57,159 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2024-11-12 21:44:57,333 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-12 21:44:57,364 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-12 21:44:57,367 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-12 21:44:57,368 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-12 21:44:57,368 INFO L274 PluginConnector]: CDTParser initialized [2024-11-12 21:44:57,369 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2024-11-12 21:44:58,754 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-12 21:44:58,974 INFO L384 CDTParser]: Found 1 translation units. [2024-11-12 21:44:58,974 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2024-11-12 21:44:58,989 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae2614fb2/089463ad98054089a636c111a6cae5ba/FLAGbd366f0a5 [2024-11-12 21:44:59,021 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae2614fb2/089463ad98054089a636c111a6cae5ba [2024-11-12 21:44:59,024 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-12 21:44:59,029 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-12 21:44:59,030 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-12 21:44:59,034 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-12 21:44:59,043 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-12 21:44:59,044 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,045 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@784409fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59, skipping insertion in model container [2024-11-12 21:44:59,049 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,149 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-12 21:44:59,453 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:44:59,471 INFO L200 MainTranslator]: Completed pre-run [2024-11-12 21:44:59,523 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:44:59,564 INFO L204 MainTranslator]: Completed translation [2024-11-12 21:44:59,568 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59 WrapperNode [2024-11-12 21:44:59,568 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-12 21:44:59,570 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-12 21:44:59,570 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-12 21:44:59,570 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-12 21:44:59,581 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,599 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,651 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1665 [2024-11-12 21:44:59,652 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-12 21:44:59,653 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-12 21:44:59,653 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-12 21:44:59,653 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-12 21:44:59,677 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,678 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,687 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,713 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-12 21:44:59,714 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,714 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,731 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,746 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,750 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,758 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,767 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-12 21:44:59,768 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-12 21:44:59,768 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-12 21:44:59,768 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-12 21:44:59,773 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (1/1) ... [2024-11-12 21:44:59,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:44:59,800 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:44:59,824 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:44:59,828 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-12 21:44:59,861 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-12 21:44:59,861 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-12 21:44:59,862 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-12 21:44:59,862 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-12 21:44:59,946 INFO L238 CfgBuilder]: Building ICFG [2024-11-12 21:44:59,947 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-12 21:45:00,904 INFO L? ?]: Removed 318 outVars from TransFormulas that were not future-live. [2024-11-12 21:45:00,905 INFO L287 CfgBuilder]: Performing block encoding [2024-11-12 21:45:00,935 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-12 21:45:00,937 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-11-12 21:45:00,938 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:45:00 BoogieIcfgContainer [2024-11-12 21:45:00,938 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-12 21:45:00,939 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-12 21:45:00,939 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-12 21:45:00,942 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-12 21:45:00,942 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:45:00,942 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 09:44:59" (1/3) ... [2024-11-12 21:45:00,943 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5c23e567 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:45:00, skipping insertion in model container [2024-11-12 21:45:00,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:45:00,943 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:44:59" (2/3) ... [2024-11-12 21:45:00,943 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5c23e567 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:45:00, skipping insertion in model container [2024-11-12 21:45:00,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:45:00,943 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:45:00" (3/3) ... [2024-11-12 21:45:00,944 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2024-11-12 21:45:01,008 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2024-11-12 21:45:01,009 INFO L302 stractBuchiCegarLoop]: Hoare is None [2024-11-12 21:45:01,009 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-12 21:45:01,009 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-12 21:45:01,009 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-12 21:45:01,009 INFO L306 stractBuchiCegarLoop]: Difference is false [2024-11-12 21:45:01,010 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-12 21:45:01,010 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-12 21:45:01,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:01,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-12 21:45:01,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:01,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:01,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,076 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-12 21:45:01,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:01,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-12 21:45:01,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:01,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:01,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,102 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:01,103 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume false;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:01,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:01,108 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2024-11-12 21:45:01,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:01,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238424929] [2024-11-12 21:45:01,115 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:01,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:01,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:01,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238424929] [2024-11-12 21:45:01,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238424929] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:01,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2099213211] [2024-11-12 21:45:01,321 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:01,322 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:01,324 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:01,325 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-12 21:45:01,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:01,404 INFO L256 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:01,408 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:01,465 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:01,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2099213211] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:01,510 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:01,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:45:01,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103635752] [2024-11-12 21:45:01,513 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:01,516 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:01,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:01,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1316317370, now seen corresponding path program 1 times [2024-11-12 21:45:01,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:01,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902606233] [2024-11-12 21:45:01,517 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:01,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:01,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:01,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902606233] [2024-11-12 21:45:01,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902606233] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:01,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [830776939] [2024-11-12 21:45:01,548 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:01,549 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:01,567 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:01,569 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-12 21:45:01,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:01,634 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-12 21:45:01,636 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:01,639 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:01,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [830776939] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:01,645 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:01,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:45:01,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858279460] [2024-11-12 21:45:01,645 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:01,646 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:01,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:01,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:45:01,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:45:01,671 INFO L87 Difference]: Start difference. First operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:01,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:01,745 INFO L93 Difference]: Finished difference Result 693 states and 1017 transitions. [2024-11-12 21:45:01,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1017 transitions. [2024-11-12 21:45:01,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-12 21:45:01,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 688 states and 1012 transitions. [2024-11-12 21:45:01,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-12 21:45:01,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-12 21:45:01,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1012 transitions. [2024-11-12 21:45:01,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:01,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1012 transitions. [2024-11-12 21:45:01,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1012 transitions. [2024-11-12 21:45:01,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-12 21:45:01,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4709302325581395) internal successors, (1012), 687 states have internal predecessors, (1012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:01,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1012 transitions. [2024-11-12 21:45:01,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1012 transitions. [2024-11-12 21:45:01,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:01,823 INFO L426 stractBuchiCegarLoop]: Abstraction has 688 states and 1012 transitions. [2024-11-12 21:45:01,825 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-12 21:45:01,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1012 transitions. [2024-11-12 21:45:01,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-12 21:45:01,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:01,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:01,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:01,838 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:01,839 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:01,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:01,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1335173372, now seen corresponding path program 1 times [2024-11-12 21:45:01,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:01,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305205588] [2024-11-12 21:45:01,840 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:01,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:01,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:01,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305205588] [2024-11-12 21:45:01,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305205588] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:01,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [348900420] [2024-11-12 21:45:01,954 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:01,954 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:01,954 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:01,959 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:01,959 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-12 21:45:02,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,024 INFO L256 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:02,025 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:02,073 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:02,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [348900420] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:02,123 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:02,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:45:02,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1629551714] [2024-11-12 21:45:02,126 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:02,127 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:02,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:02,127 INFO L85 PathProgramCache]: Analyzing trace with hash 2034864633, now seen corresponding path program 1 times [2024-11-12 21:45:02,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:02,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054388437] [2024-11-12 21:45:02,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:02,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:02,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054388437] [2024-11-12 21:45:02,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054388437] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:02,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [207604467] [2024-11-12 21:45:02,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,197 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:02,197 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:02,198 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:02,199 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-12 21:45:02,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,272 INFO L256 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:02,273 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:02,353 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:02,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [207604467] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:02,411 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:02,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:02,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248033384] [2024-11-12 21:45:02,412 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:02,412 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:02,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:02,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:45:02,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:45:02,413 INFO L87 Difference]: Start difference. First operand 688 states and 1012 transitions. cyclomatic complexity: 325 Second operand has 4 states, 4 states have (on average 32.5) internal successors, (130), 4 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:02,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:02,482 INFO L93 Difference]: Finished difference Result 1224 states and 1780 transitions. [2024-11-12 21:45:02,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1224 states and 1780 transitions. [2024-11-12 21:45:02,488 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1132 [2024-11-12 21:45:02,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1224 states to 1224 states and 1780 transitions. [2024-11-12 21:45:02,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1224 [2024-11-12 21:45:02,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1224 [2024-11-12 21:45:02,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1224 states and 1780 transitions. [2024-11-12 21:45:02,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:02,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1224 states and 1780 transitions. [2024-11-12 21:45:02,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1224 states and 1780 transitions. [2024-11-12 21:45:02,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1224 to 1222. [2024-11-12 21:45:02,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1222 states have (on average 1.4549918166939444) internal successors, (1778), 1221 states have internal predecessors, (1778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:02,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1778 transitions. [2024-11-12 21:45:02,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1778 transitions. [2024-11-12 21:45:02,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:02,511 INFO L426 stractBuchiCegarLoop]: Abstraction has 1222 states and 1778 transitions. [2024-11-12 21:45:02,511 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-12 21:45:02,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1222 states and 1778 transitions. [2024-11-12 21:45:02,516 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:02,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:02,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:02,517 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:02,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:02,517 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:02,517 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:02,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:02,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1163831879, now seen corresponding path program 1 times [2024-11-12 21:45:02,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:02,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307066013] [2024-11-12 21:45:02,518 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:02,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:02,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307066013] [2024-11-12 21:45:02,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307066013] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:02,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1652667151] [2024-11-12 21:45:02,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:02,560 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:02,562 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:02,563 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-12 21:45:02,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,626 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:02,628 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:02,703 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:02,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1652667151] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:02,792 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:02,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:45:02,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859717161] [2024-11-12 21:45:02,792 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:02,793 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:02,793 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:02,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1161386938, now seen corresponding path program 1 times [2024-11-12 21:45:02,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:02,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524156648] [2024-11-12 21:45:02,794 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:02,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:02,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524156648] [2024-11-12 21:45:02,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524156648] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:02,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1226424084] [2024-11-12 21:45:02,857 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:02,857 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:02,857 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:02,859 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:02,863 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-12 21:45:02,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:02,965 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:02,968 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:03,034 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:03,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1226424084] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:03,101 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:03,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:03,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046764789] [2024-11-12 21:45:03,101 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:03,102 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:03,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:03,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:45:03,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:45:03,103 INFO L87 Difference]: Start difference. First operand 1222 states and 1778 transitions. cyclomatic complexity: 558 Second operand has 4 states, 4 states have (on average 37.25) internal successors, (149), 4 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:03,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:03,153 INFO L93 Difference]: Finished difference Result 1222 states and 1753 transitions. [2024-11-12 21:45:03,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1222 states and 1753 transitions. [2024-11-12 21:45:03,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:03,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1222 states to 1222 states and 1753 transitions. [2024-11-12 21:45:03,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1222 [2024-11-12 21:45:03,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1222 [2024-11-12 21:45:03,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1222 states and 1753 transitions. [2024-11-12 21:45:03,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:03,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1753 transitions. [2024-11-12 21:45:03,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states and 1753 transitions. [2024-11-12 21:45:03,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-12 21:45:03,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1222 states have (on average 1.434533551554828) internal successors, (1753), 1221 states have internal predecessors, (1753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:03,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1753 transitions. [2024-11-12 21:45:03,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1753 transitions. [2024-11-12 21:45:03,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:03,191 INFO L426 stractBuchiCegarLoop]: Abstraction has 1222 states and 1753 transitions. [2024-11-12 21:45:03,192 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-12 21:45:03,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1222 states and 1753 transitions. [2024-11-12 21:45:03,198 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:03,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:03,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:03,201 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:03,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:03,205 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:03,205 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:03,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:03,206 INFO L85 PathProgramCache]: Analyzing trace with hash 163277318, now seen corresponding path program 1 times [2024-11-12 21:45:03,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:03,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335828979] [2024-11-12 21:45:03,206 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:03,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:03,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335828979] [2024-11-12 21:45:03,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335828979] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:03,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [679542656] [2024-11-12 21:45:03,258 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:03,258 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:03,264 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:03,275 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-12 21:45:03,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,362 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:03,364 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:03,401 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:03,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [679542656] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:03,441 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:03,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-12 21:45:03,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131041677] [2024-11-12 21:45:03,442 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:03,442 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:03,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:03,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1901328571, now seen corresponding path program 1 times [2024-11-12 21:45:03,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:03,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792863860] [2024-11-12 21:45:03,444 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:03,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:03,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792863860] [2024-11-12 21:45:03,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792863860] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:03,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1148841290] [2024-11-12 21:45:03,487 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,487 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:03,488 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:03,490 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:03,494 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-12 21:45:03,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,559 INFO L256 TraceCheckSpWp]: Trace formula consists of 220 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:03,561 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:03,618 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:03,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1148841290] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:03,677 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:03,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:03,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29652000] [2024-11-12 21:45:03,678 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:03,678 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:03,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:03,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:45:03,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:45:03,679 INFO L87 Difference]: Start difference. First operand 1222 states and 1753 transitions. cyclomatic complexity: 533 Second operand has 5 states, 5 states have (on average 24.8) internal successors, (124), 5 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:03,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:03,733 INFO L93 Difference]: Finished difference Result 1317 states and 1855 transitions. [2024-11-12 21:45:03,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1317 states and 1855 transitions. [2024-11-12 21:45:03,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1225 [2024-11-12 21:45:03,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1317 states to 1317 states and 1855 transitions. [2024-11-12 21:45:03,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1317 [2024-11-12 21:45:03,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1317 [2024-11-12 21:45:03,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1317 states and 1855 transitions. [2024-11-12 21:45:03,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:03,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1317 states and 1855 transitions. [2024-11-12 21:45:03,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1317 states and 1855 transitions. [2024-11-12 21:45:03,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1317 to 1222. [2024-11-12 21:45:03,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1222 states have (on average 1.414075286415712) internal successors, (1728), 1221 states have internal predecessors, (1728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:03,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1728 transitions. [2024-11-12 21:45:03,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1728 transitions. [2024-11-12 21:45:03,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:03,760 INFO L426 stractBuchiCegarLoop]: Abstraction has 1222 states and 1728 transitions. [2024-11-12 21:45:03,760 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-12 21:45:03,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1222 states and 1728 transitions. [2024-11-12 21:45:03,764 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:03,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:03,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:03,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:03,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:03,766 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:03,766 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:03,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:03,767 INFO L85 PathProgramCache]: Analyzing trace with hash 554434378, now seen corresponding path program 1 times [2024-11-12 21:45:03,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:03,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543809626] [2024-11-12 21:45:03,767 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:03,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:03,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543809626] [2024-11-12 21:45:03,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543809626] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:03,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1394463384] [2024-11-12 21:45:03,795 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:03,795 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:03,797 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:03,798 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-12 21:45:03,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:03,860 INFO L256 TraceCheckSpWp]: Trace formula consists of 249 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:03,861 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:03,911 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:03,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1394463384] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:03,971 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:03,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:45:03,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22007241] [2024-11-12 21:45:03,972 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:03,973 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:03,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:03,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1351013052, now seen corresponding path program 1 times [2024-11-12 21:45:03,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:03,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183682286] [2024-11-12 21:45:03,974 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:03,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:03,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:04,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183682286] [2024-11-12 21:45:04,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183682286] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:04,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1351438231] [2024-11-12 21:45:04,014 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,014 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:04,014 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:04,019 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:04,021 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-12 21:45:04,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,114 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:04,116 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:04,174 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:04,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1351438231] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:04,228 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:04,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:04,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101487876] [2024-11-12 21:45:04,228 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:04,228 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:04,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:04,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:45:04,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:45:04,229 INFO L87 Difference]: Start difference. First operand 1222 states and 1728 transitions. cyclomatic complexity: 508 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:04,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:04,273 INFO L93 Difference]: Finished difference Result 1222 states and 1702 transitions. [2024-11-12 21:45:04,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1222 states and 1702 transitions. [2024-11-12 21:45:04,278 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:04,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1222 states to 1222 states and 1702 transitions. [2024-11-12 21:45:04,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1222 [2024-11-12 21:45:04,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1222 [2024-11-12 21:45:04,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1222 states and 1702 transitions. [2024-11-12 21:45:04,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:04,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1702 transitions. [2024-11-12 21:45:04,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states and 1702 transitions. [2024-11-12 21:45:04,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-12 21:45:04,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1222 states have (on average 1.392798690671031) internal successors, (1702), 1221 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:04,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1702 transitions. [2024-11-12 21:45:04,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1702 transitions. [2024-11-12 21:45:04,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:04,296 INFO L426 stractBuchiCegarLoop]: Abstraction has 1222 states and 1702 transitions. [2024-11-12 21:45:04,296 INFO L333 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-12 21:45:04,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1222 states and 1702 transitions. [2024-11-12 21:45:04,300 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:04,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:04,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:04,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:04,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:04,301 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:04,301 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:04,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:04,303 INFO L85 PathProgramCache]: Analyzing trace with hash 1538799047, now seen corresponding path program 1 times [2024-11-12 21:45:04,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:04,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108258507] [2024-11-12 21:45:04,303 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:04,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:04,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108258507] [2024-11-12 21:45:04,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108258507] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:04,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [564326451] [2024-11-12 21:45:04,324 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,324 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:04,324 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:04,328 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:04,329 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-12 21:45:04,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,390 INFO L256 TraceCheckSpWp]: Trace formula consists of 244 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:04,391 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:04,482 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:04,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [564326451] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:04,557 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:04,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:45:04,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198731279] [2024-11-12 21:45:04,557 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:04,558 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:04,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:04,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1581097860, now seen corresponding path program 1 times [2024-11-12 21:45:04,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:04,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588027935] [2024-11-12 21:45:04,558 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:04,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:04,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588027935] [2024-11-12 21:45:04,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588027935] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:04,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1753226094] [2024-11-12 21:45:04,581 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:04,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:04,583 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:04,585 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-12 21:45:04,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,645 INFO L256 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:04,647 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:04,699 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:04,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1753226094] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:04,754 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:04,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:04,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422029825] [2024-11-12 21:45:04,754 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:04,754 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:04,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:04,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:45:04,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:45:04,759 INFO L87 Difference]: Start difference. First operand 1222 states and 1702 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 4 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:04,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:04,791 INFO L93 Difference]: Finished difference Result 1222 states and 1693 transitions. [2024-11-12 21:45:04,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1222 states and 1693 transitions. [2024-11-12 21:45:04,795 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:04,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1222 states to 1222 states and 1693 transitions. [2024-11-12 21:45:04,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1222 [2024-11-12 21:45:04,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1222 [2024-11-12 21:45:04,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1222 states and 1693 transitions. [2024-11-12 21:45:04,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:04,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1693 transitions. [2024-11-12 21:45:04,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states and 1693 transitions. [2024-11-12 21:45:04,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-12 21:45:04,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1222 states have (on average 1.3854337152209493) internal successors, (1693), 1221 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:04,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1693 transitions. [2024-11-12 21:45:04,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1222 states and 1693 transitions. [2024-11-12 21:45:04,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-12 21:45:04,812 INFO L426 stractBuchiCegarLoop]: Abstraction has 1222 states and 1693 transitions. [2024-11-12 21:45:04,812 INFO L333 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-12 21:45:04,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1222 states and 1693 transitions. [2024-11-12 21:45:04,815 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1130 [2024-11-12 21:45:04,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:04,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:04,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:04,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:04,816 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:04,817 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:04,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:04,817 INFO L85 PathProgramCache]: Analyzing trace with hash 909741639, now seen corresponding path program 1 times [2024-11-12 21:45:04,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:04,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073322408] [2024-11-12 21:45:04,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:04,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:04,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073322408] [2024-11-12 21:45:04,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1073322408] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:04,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1090033552] [2024-11-12 21:45:04,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:04,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:04,868 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:04,873 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:04,876 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-12 21:45:04,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:04,993 INFO L256 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-12 21:45:04,994 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:05,017 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:05,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1090033552] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:05,024 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:05,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:45:05,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870112313] [2024-11-12 21:45:05,028 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:05,028 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:05,028 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:05,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1281750523, now seen corresponding path program 1 times [2024-11-12 21:45:05,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:05,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021061508] [2024-11-12 21:45:05,029 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:05,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:05,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:05,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:05,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021061508] [2024-11-12 21:45:05,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021061508] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:05,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [165047942] [2024-11-12 21:45:05,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:05,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:05,068 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:05,073 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:05,074 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-12 21:45:05,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:05,137 INFO L256 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:05,138 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:05,243 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:05,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [165047942] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:05,333 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:05,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:05,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695808337] [2024-11-12 21:45:05,334 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:05,334 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:05,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:05,334 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:45:05,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:45:05,334 INFO L87 Difference]: Start difference. First operand 1222 states and 1693 transitions. cyclomatic complexity: 473 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:05,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:05,543 INFO L93 Difference]: Finished difference Result 1276 states and 1747 transitions. [2024-11-12 21:45:05,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1276 states and 1747 transitions. [2024-11-12 21:45:05,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1181 [2024-11-12 21:45:05,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1276 states to 1276 states and 1747 transitions. [2024-11-12 21:45:05,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1276 [2024-11-12 21:45:05,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1276 [2024-11-12 21:45:05,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1276 states and 1747 transitions. [2024-11-12 21:45:05,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:05,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1276 states and 1747 transitions. [2024-11-12 21:45:05,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1276 states and 1747 transitions. [2024-11-12 21:45:05,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1276 to 1276. [2024-11-12 21:45:05,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1276 states, 1276 states have (on average 1.3691222570532915) internal successors, (1747), 1275 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:05,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1276 states to 1276 states and 1747 transitions. [2024-11-12 21:45:05,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1276 states and 1747 transitions. [2024-11-12 21:45:05,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:05,588 INFO L426 stractBuchiCegarLoop]: Abstraction has 1276 states and 1747 transitions. [2024-11-12 21:45:05,588 INFO L333 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-12 21:45:05,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1276 states and 1747 transitions. [2024-11-12 21:45:05,594 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1181 [2024-11-12 21:45:05,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:05,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:05,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:05,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:05,596 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:05,599 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:05,599 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:05,600 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2024-11-12 21:45:05,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:05,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219109569] [2024-11-12 21:45:05,600 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:05,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:05,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:05,641 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:05,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:05,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:05,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:05,696 INFO L85 PathProgramCache]: Analyzing trace with hash 678012350, now seen corresponding path program 1 times [2024-11-12 21:45:05,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:05,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808446969] [2024-11-12 21:45:05,696 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:05,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:05,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:05,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:05,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808446969] [2024-11-12 21:45:05,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808446969] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:05,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1882399094] [2024-11-12 21:45:05,742 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:05,742 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:05,742 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:05,745 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:05,746 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-12 21:45:05,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:05,852 INFO L256 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:05,854 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:06,020 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:06,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1882399094] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:06,218 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:06,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:06,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258448550] [2024-11-12 21:45:06,218 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:06,218 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:06,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:06,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:06,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:06,219 INFO L87 Difference]: Start difference. First operand 1276 states and 1747 transitions. cyclomatic complexity: 473 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:06,254 INFO L93 Difference]: Finished difference Result 1475 states and 2017 transitions. [2024-11-12 21:45:06,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1475 states and 2017 transitions. [2024-11-12 21:45:06,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1314 [2024-11-12 21:45:06,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1475 states to 1475 states and 2017 transitions. [2024-11-12 21:45:06,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1475 [2024-11-12 21:45:06,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1475 [2024-11-12 21:45:06,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1475 states and 2017 transitions. [2024-11-12 21:45:06,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:06,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1475 states and 2017 transitions. [2024-11-12 21:45:06,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1475 states and 2017 transitions. [2024-11-12 21:45:06,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1475 to 1475. [2024-11-12 21:45:06,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1475 states, 1475 states have (on average 1.367457627118644) internal successors, (2017), 1474 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1475 states to 1475 states and 2017 transitions. [2024-11-12 21:45:06,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1475 states and 2017 transitions. [2024-11-12 21:45:06,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:06,279 INFO L426 stractBuchiCegarLoop]: Abstraction has 1475 states and 2017 transitions. [2024-11-12 21:45:06,279 INFO L333 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-12 21:45:06,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1475 states and 2017 transitions. [2024-11-12 21:45:06,282 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1314 [2024-11-12 21:45:06,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:06,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:06,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,283 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:06,283 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:06,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,284 INFO L85 PathProgramCache]: Analyzing trace with hash -843787639, now seen corresponding path program 1 times [2024-11-12 21:45:06,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889671496] [2024-11-12 21:45:06,284 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:06,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:06,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889671496] [2024-11-12 21:45:06,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889671496] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:06,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1442421947] [2024-11-12 21:45:06,312 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:06,312 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:06,314 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:06,315 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-12 21:45:06,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,377 INFO L256 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:45:06,378 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:06,402 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:06,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1442421947] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:06,430 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:06,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-12 21:45:06,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577324321] [2024-11-12 21:45:06,430 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:06,431 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:06,431 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1276778683, now seen corresponding path program 1 times [2024-11-12 21:45:06,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188334109] [2024-11-12 21:45:06,431 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:06,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:06,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188334109] [2024-11-12 21:45:06,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188334109] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:06,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [625890196] [2024-11-12 21:45:06,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:06,474 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:06,476 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:06,477 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-12 21:45:06,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,545 INFO L256 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:45:06,546 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:06,560 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:06,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [625890196] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:06,573 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:06,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:45:06,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425570163] [2024-11-12 21:45:06,573 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:06,574 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:06,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:06,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-12 21:45:06,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-12 21:45:06,574 INFO L87 Difference]: Start difference. First operand 1475 states and 2017 transitions. cyclomatic complexity: 544 Second operand has 6 states, 6 states have (on average 20.333333333333332) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:06,636 INFO L93 Difference]: Finished difference Result 2324 states and 3164 transitions. [2024-11-12 21:45:06,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2324 states and 3164 transitions. [2024-11-12 21:45:06,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2227 [2024-11-12 21:45:06,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2324 states to 2324 states and 3164 transitions. [2024-11-12 21:45:06,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2324 [2024-11-12 21:45:06,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2324 [2024-11-12 21:45:06,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2324 states and 3164 transitions. [2024-11-12 21:45:06,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:06,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2324 states and 3164 transitions. [2024-11-12 21:45:06,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2324 states and 3164 transitions. [2024-11-12 21:45:06,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2324 to 2324. [2024-11-12 21:45:06,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2324 states, 2324 states have (on average 1.3614457831325302) internal successors, (3164), 2323 states have internal predecessors, (3164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 3164 transitions. [2024-11-12 21:45:06,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2324 states and 3164 transitions. [2024-11-12 21:45:06,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-12 21:45:06,683 INFO L426 stractBuchiCegarLoop]: Abstraction has 2324 states and 3164 transitions. [2024-11-12 21:45:06,683 INFO L333 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-12 21:45:06,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2324 states and 3164 transitions. [2024-11-12 21:45:06,688 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2227 [2024-11-12 21:45:06,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:06,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:06,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,689 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:06,689 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:06,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,689 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2024-11-12 21:45:06,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214437961] [2024-11-12 21:45:06,690 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:06,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:06,696 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:06,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:06,709 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:06,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,710 INFO L85 PathProgramCache]: Analyzing trace with hash -932890311, now seen corresponding path program 1 times [2024-11-12 21:45:06,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013052213] [2024-11-12 21:45:06,710 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:06,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:06,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013052213] [2024-11-12 21:45:06,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013052213] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:06,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [275126348] [2024-11-12 21:45:06,759 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:06,759 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:06,761 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:06,761 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-12 21:45:06,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:06,819 INFO L256 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:45:06,820 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:06,825 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:06,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [275126348] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:06,836 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:06,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:45:06,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207920159] [2024-11-12 21:45:06,837 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:06,837 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:06,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:06,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:45:06,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:45:06,838 INFO L87 Difference]: Start difference. First operand 2324 states and 3164 transitions. cyclomatic complexity: 844 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:06,890 INFO L93 Difference]: Finished difference Result 2352 states and 3192 transitions. [2024-11-12 21:45:06,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2352 states and 3192 transitions. [2024-11-12 21:45:06,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2255 [2024-11-12 21:45:06,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2352 states to 2352 states and 3192 transitions. [2024-11-12 21:45:06,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2352 [2024-11-12 21:45:06,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2352 [2024-11-12 21:45:06,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2352 states and 3192 transitions. [2024-11-12 21:45:06,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:06,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2352 states and 3192 transitions. [2024-11-12 21:45:06,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2352 states and 3192 transitions. [2024-11-12 21:45:06,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2352 to 2336. [2024-11-12 21:45:06,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2336 states, 2336 states have (on average 1.3595890410958904) internal successors, (3176), 2335 states have internal predecessors, (3176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:06,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2336 states to 2336 states and 3176 transitions. [2024-11-12 21:45:06,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2336 states and 3176 transitions. [2024-11-12 21:45:06,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:45:06,969 INFO L426 stractBuchiCegarLoop]: Abstraction has 2336 states and 3176 transitions. [2024-11-12 21:45:06,969 INFO L333 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-12 21:45:06,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2336 states and 3176 transitions. [2024-11-12 21:45:06,973 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2239 [2024-11-12 21:45:06,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:06,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:06,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:06,974 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:06,975 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:06,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,975 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2024-11-12 21:45:06,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466665422] [2024-11-12 21:45:06,975 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:06,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:06,981 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:06,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:06,994 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:06,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:06,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1093985992, now seen corresponding path program 1 times [2024-11-12 21:45:06,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:06,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360297907] [2024-11-12 21:45:06,995 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:06,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:07,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:07,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360297907] [2024-11-12 21:45:07,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360297907] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:07,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1486075432] [2024-11-12 21:45:07,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:07,056 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:07,057 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:07,061 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-12 21:45:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:07,124 INFO L256 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-12 21:45:07,125 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:07,141 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:07,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1486075432] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:07,147 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:07,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-12 21:45:07,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148917395] [2024-11-12 21:45:07,147 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:07,147 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:07,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:07,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-12 21:45:07,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-12 21:45:07,148 INFO L87 Difference]: Start difference. First operand 2336 states and 3176 transitions. cyclomatic complexity: 844 Second operand has 8 states, 8 states have (on average 17.5) internal successors, (140), 8 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:07,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:07,393 INFO L93 Difference]: Finished difference Result 2360 states and 3142 transitions. [2024-11-12 21:45:07,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2360 states and 3142 transitions. [2024-11-12 21:45:07,400 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2263 [2024-11-12 21:45:07,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2360 states to 2360 states and 3142 transitions. [2024-11-12 21:45:07,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2360 [2024-11-12 21:45:07,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2360 [2024-11-12 21:45:07,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2360 states and 3142 transitions. [2024-11-12 21:45:07,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:07,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2360 states and 3142 transitions. [2024-11-12 21:45:07,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2360 states and 3142 transitions. [2024-11-12 21:45:07,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2360 to 2360. [2024-11-12 21:45:07,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2360 states, 2360 states have (on average 1.3313559322033899) internal successors, (3142), 2359 states have internal predecessors, (3142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:07,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2360 states to 2360 states and 3142 transitions. [2024-11-12 21:45:07,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2360 states and 3142 transitions. [2024-11-12 21:45:07,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-12 21:45:07,432 INFO L426 stractBuchiCegarLoop]: Abstraction has 2360 states and 3142 transitions. [2024-11-12 21:45:07,432 INFO L333 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-12 21:45:07,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2360 states and 3142 transitions. [2024-11-12 21:45:07,437 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2263 [2024-11-12 21:45:07,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:07,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:07,437 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:07,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:07,438 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:45:07,438 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:45:07,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:07,439 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2024-11-12 21:45:07,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:07,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592005860] [2024-11-12 21:45:07,440 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,447 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:07,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,465 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:07,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:07,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1006924337, now seen corresponding path program 1 times [2024-11-12 21:45:07,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:07,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932010628] [2024-11-12 21:45:07,466 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:07,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:07,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932010628] [2024-11-12 21:45:07,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932010628] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:07,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1612981990] [2024-11-12 21:45:07,498 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,499 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:07,499 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:07,502 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:07,513 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-11-12 21:45:07,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:07,569 INFO L256 TraceCheckSpWp]: Trace formula consists of 192 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:07,570 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:07,646 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:07,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1612981990] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:07,726 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:07,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:07,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222140132] [2024-11-12 21:45:07,727 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:07,727 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:45:07,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:07,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:07,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:07,727 INFO L87 Difference]: Start difference. First operand 2360 states and 3142 transitions. cyclomatic complexity: 786 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:07,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:07,753 INFO L93 Difference]: Finished difference Result 3782 states and 4978 transitions. [2024-11-12 21:45:07,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3782 states and 4978 transitions. [2024-11-12 21:45:07,765 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3679 [2024-11-12 21:45:07,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3782 states to 3782 states and 4978 transitions. [2024-11-12 21:45:07,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3782 [2024-11-12 21:45:07,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3782 [2024-11-12 21:45:07,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3782 states and 4978 transitions. [2024-11-12 21:45:07,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:07,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3782 states and 4978 transitions. [2024-11-12 21:45:07,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3782 states and 4978 transitions. [2024-11-12 21:45:07,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3782 to 3782. [2024-11-12 21:45:07,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3782 states, 3782 states have (on average 1.316234796404019) internal successors, (4978), 3781 states have internal predecessors, (4978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:07,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3782 states to 3782 states and 4978 transitions. [2024-11-12 21:45:07,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3782 states and 4978 transitions. [2024-11-12 21:45:07,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:07,839 INFO L426 stractBuchiCegarLoop]: Abstraction has 3782 states and 4978 transitions. [2024-11-12 21:45:07,839 INFO L333 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-12 21:45:07,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3782 states and 4978 transitions. [2024-11-12 21:45:07,846 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3679 [2024-11-12 21:45:07,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:07,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:07,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:07,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:07,883 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:07,884 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:07,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:07,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2024-11-12 21:45:07,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:07,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684106041] [2024-11-12 21:45:07,887 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,901 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:07,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,925 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:07,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:07,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1779949543, now seen corresponding path program 1 times [2024-11-12 21:45:07,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:07,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775234153] [2024-11-12 21:45:07,929 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,933 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:07,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:07,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:07,938 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:07,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1784869629, now seen corresponding path program 1 times [2024-11-12 21:45:07,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:07,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531406774] [2024-11-12 21:45:07,938 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:07,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:07,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:07,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531406774] [2024-11-12 21:45:07,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531406774] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:07,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1303671517] [2024-11-12 21:45:07,980 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:07,980 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:07,981 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:07,983 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:07,984 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-11-12 21:45:08,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:08,079 INFO L256 TraceCheckSpWp]: Trace formula consists of 266 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:08,081 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:08,198 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:08,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1303671517] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:08,331 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:08,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:08,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334976112] [2024-11-12 21:45:08,331 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:08,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:08,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:08,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:08,427 INFO L87 Difference]: Start difference. First operand 3782 states and 4978 transitions. cyclomatic complexity: 1200 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:08,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:08,513 INFO L93 Difference]: Finished difference Result 7222 states and 9439 transitions. [2024-11-12 21:45:08,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7222 states and 9439 transitions. [2024-11-12 21:45:08,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7022 [2024-11-12 21:45:08,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7222 states to 7222 states and 9439 transitions. [2024-11-12 21:45:08,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7222 [2024-11-12 21:45:08,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7222 [2024-11-12 21:45:08,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7222 states and 9439 transitions. [2024-11-12 21:45:08,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:08,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7222 states and 9439 transitions. [2024-11-12 21:45:08,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7222 states and 9439 transitions. [2024-11-12 21:45:08,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7222 to 6890. [2024-11-12 21:45:08,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6890 states, 6890 states have (on average 1.3089985486211901) internal successors, (9019), 6889 states have internal predecessors, (9019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:08,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6890 states to 6890 states and 9019 transitions. [2024-11-12 21:45:08,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6890 states and 9019 transitions. [2024-11-12 21:45:08,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:08,711 INFO L426 stractBuchiCegarLoop]: Abstraction has 6890 states and 9019 transitions. [2024-11-12 21:45:08,711 INFO L333 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-12 21:45:08,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6890 states and 9019 transitions. [2024-11-12 21:45:08,728 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6690 [2024-11-12 21:45:08,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:08,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:08,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:08,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:08,729 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:08,730 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:08,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:08,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1481595819, now seen corresponding path program 1 times [2024-11-12 21:45:08,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:08,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895387909] [2024-11-12 21:45:08,730 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:08,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:08,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:08,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:08,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895387909] [2024-11-12 21:45:08,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895387909] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:08,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2065838829] [2024-11-12 21:45:08,753 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:08,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:08,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:08,758 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:08,759 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-12 21:45:08,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:08,839 INFO L256 TraceCheckSpWp]: Trace formula consists of 244 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:08,840 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:08,845 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:08,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2065838829] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:08,850 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:08,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:08,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103822344] [2024-11-12 21:45:08,850 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:08,851 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:45:08,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:08,851 INFO L85 PathProgramCache]: Analyzing trace with hash -1384180882, now seen corresponding path program 1 times [2024-11-12 21:45:08,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:08,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666222730] [2024-11-12 21:45:08,851 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:08,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:08,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:08,854 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:08,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:08,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:08,920 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:08,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:08,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:08,921 INFO L87 Difference]: Start difference. First operand 6890 states and 9019 transitions. cyclomatic complexity: 2133 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:08,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:08,949 INFO L93 Difference]: Finished difference Result 6801 states and 8902 transitions. [2024-11-12 21:45:08,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6801 states and 8902 transitions. [2024-11-12 21:45:08,969 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6690 [2024-11-12 21:45:08,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6801 states to 6801 states and 8902 transitions. [2024-11-12 21:45:08,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6801 [2024-11-12 21:45:08,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6801 [2024-11-12 21:45:08,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6801 states and 8902 transitions. [2024-11-12 21:45:08,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:08,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6801 states and 8902 transitions. [2024-11-12 21:45:08,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6801 states and 8902 transitions. [2024-11-12 21:45:09,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6801 to 6801. [2024-11-12 21:45:09,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6801 states, 6801 states have (on average 1.3089251580649905) internal successors, (8902), 6800 states have internal predecessors, (8902), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:09,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6801 states to 6801 states and 8902 transitions. [2024-11-12 21:45:09,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6801 states and 8902 transitions. [2024-11-12 21:45:09,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:09,070 INFO L426 stractBuchiCegarLoop]: Abstraction has 6801 states and 8902 transitions. [2024-11-12 21:45:09,070 INFO L333 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-12 21:45:09,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6801 states and 8902 transitions. [2024-11-12 21:45:09,087 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6690 [2024-11-12 21:45:09,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:09,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:09,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:09,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:09,089 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:09,089 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:09,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2024-11-12 21:45:09,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069958706] [2024-11-12 21:45:09,090 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,099 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:09,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:09,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1384180882, now seen corresponding path program 2 times [2024-11-12 21:45:09,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304434018] [2024-11-12 21:45:09,117 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,120 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:09,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:09,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,123 INFO L85 PathProgramCache]: Analyzing trace with hash -950945532, now seen corresponding path program 1 times [2024-11-12 21:45:09,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571105311] [2024-11-12 21:45:09,123 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:09,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:09,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571105311] [2024-11-12 21:45:09,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571105311] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:09,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [81250800] [2024-11-12 21:45:09,155 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,155 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:09,156 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:09,158 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:09,159 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-11-12 21:45:09,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:09,249 INFO L256 TraceCheckSpWp]: Trace formula consists of 270 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:09,250 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:09,354 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:09,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [81250800] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:09,496 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:09,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:09,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814093092] [2024-11-12 21:45:09,497 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:09,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:09,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:09,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:09,565 INFO L87 Difference]: Start difference. First operand 6801 states and 8902 transitions. cyclomatic complexity: 2105 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:09,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:09,644 INFO L93 Difference]: Finished difference Result 12871 states and 16756 transitions. [2024-11-12 21:45:09,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12871 states and 16756 transitions. [2024-11-12 21:45:09,691 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12744 [2024-11-12 21:45:09,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12871 states to 12871 states and 16756 transitions. [2024-11-12 21:45:09,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12871 [2024-11-12 21:45:09,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12871 [2024-11-12 21:45:09,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12871 states and 16756 transitions. [2024-11-12 21:45:09,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:09,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12871 states and 16756 transitions. [2024-11-12 21:45:09,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12871 states and 16756 transitions. [2024-11-12 21:45:09,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12871 to 12319. [2024-11-12 21:45:09,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12319 states, 12319 states have (on average 1.3049760532510757) internal successors, (16076), 12318 states have internal predecessors, (16076), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:09,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12319 states to 12319 states and 16076 transitions. [2024-11-12 21:45:09,907 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12319 states and 16076 transitions. [2024-11-12 21:45:09,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:09,908 INFO L426 stractBuchiCegarLoop]: Abstraction has 12319 states and 16076 transitions. [2024-11-12 21:45:09,908 INFO L333 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-12 21:45:09,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12319 states and 16076 transitions. [2024-11-12 21:45:09,941 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12192 [2024-11-12 21:45:09,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:09,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:09,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:09,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:09,943 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:09,943 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:09,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,943 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 3 times [2024-11-12 21:45:09,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29707565] [2024-11-12 21:45:09,944 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,952 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:09,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:09,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1160850791, now seen corresponding path program 1 times [2024-11-12 21:45:09,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922926361] [2024-11-12 21:45:09,970 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,973 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:09,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:09,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:09,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:09,976 INFO L85 PathProgramCache]: Analyzing trace with hash 888194429, now seen corresponding path program 1 times [2024-11-12 21:45:09,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:09,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10454977] [2024-11-12 21:45:09,976 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:09,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:09,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:10,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:10,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10454977] [2024-11-12 21:45:10,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10454977] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:10,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [33814722] [2024-11-12 21:45:10,012 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:10,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:10,013 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:10,015 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:10,017 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-11-12 21:45:10,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:10,094 INFO L256 TraceCheckSpWp]: Trace formula consists of 274 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:10,095 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:10,187 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:10,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [33814722] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:10,306 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:10,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:10,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419740655] [2024-11-12 21:45:10,306 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:10,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:10,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:10,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:10,385 INFO L87 Difference]: Start difference. First operand 12319 states and 16076 transitions. cyclomatic complexity: 3761 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:10,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:10,461 INFO L93 Difference]: Finished difference Result 14998 states and 19575 transitions. [2024-11-12 21:45:10,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14998 states and 19575 transitions. [2024-11-12 21:45:10,522 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14887 [2024-11-12 21:45:10,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14998 states to 14998 states and 19575 transitions. [2024-11-12 21:45:10,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14998 [2024-11-12 21:45:10,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14998 [2024-11-12 21:45:10,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14998 states and 19575 transitions. [2024-11-12 21:45:10,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:10,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14998 states and 19575 transitions. [2024-11-12 21:45:10,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14998 states and 19575 transitions. [2024-11-12 21:45:10,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14998 to 14550. [2024-11-12 21:45:10,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14550 states, 14550 states have (on average 1.306872852233677) internal successors, (19015), 14549 states have internal predecessors, (19015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:11,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14550 states to 14550 states and 19015 transitions. [2024-11-12 21:45:11,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14550 states and 19015 transitions. [2024-11-12 21:45:11,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:11,009 INFO L426 stractBuchiCegarLoop]: Abstraction has 14550 states and 19015 transitions. [2024-11-12 21:45:11,009 INFO L333 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-12 21:45:11,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14550 states and 19015 transitions. [2024-11-12 21:45:11,046 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14439 [2024-11-12 21:45:11,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:11,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:11,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:11,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:11,049 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:11,050 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:11,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:11,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 4 times [2024-11-12 21:45:11,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:11,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068527394] [2024-11-12 21:45:11,051 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:11,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:11,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:11,061 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:11,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:11,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:11,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:11,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1515958958, now seen corresponding path program 1 times [2024-11-12 21:45:11,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:11,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464360465] [2024-11-12 21:45:11,081 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:11,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:11,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:11,084 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:11,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:11,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:11,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:11,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1486200132, now seen corresponding path program 1 times [2024-11-12 21:45:11,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:11,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280224617] [2024-11-12 21:45:11,088 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:11,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:11,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:11,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:11,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280224617] [2024-11-12 21:45:11,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280224617] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:11,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [147878821] [2024-11-12 21:45:11,117 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:11,117 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:11,117 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:11,119 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:11,122 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-12 21:45:11,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:11,348 INFO L256 TraceCheckSpWp]: Trace formula consists of 278 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:11,350 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:11,432 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:11,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [147878821] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:11,524 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:11,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:11,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199554285] [2024-11-12 21:45:11,524 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:11,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:11,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:11,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:11,582 INFO L87 Difference]: Start difference. First operand 14550 states and 19015 transitions. cyclomatic complexity: 4468 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:11,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:11,665 INFO L93 Difference]: Finished difference Result 27179 states and 35389 transitions. [2024-11-12 21:45:11,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27179 states and 35389 transitions. [2024-11-12 21:45:11,754 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 27052 [2024-11-12 21:45:11,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27179 states to 27179 states and 35389 transitions. [2024-11-12 21:45:11,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27179 [2024-11-12 21:45:11,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27179 [2024-11-12 21:45:11,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27179 states and 35389 transitions. [2024-11-12 21:45:12,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:12,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27179 states and 35389 transitions. [2024-11-12 21:45:12,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27179 states and 35389 transitions. [2024-11-12 21:45:12,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27179 to 26339. [2024-11-12 21:45:12,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26339 states, 26339 states have (on average 1.3056304339572498) internal successors, (34389), 26338 states have internal predecessors, (34389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:12,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26339 states to 26339 states and 34389 transitions. [2024-11-12 21:45:12,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26339 states and 34389 transitions. [2024-11-12 21:45:12,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:12,386 INFO L426 stractBuchiCegarLoop]: Abstraction has 26339 states and 34389 transitions. [2024-11-12 21:45:12,386 INFO L333 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-12 21:45:12,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26339 states and 34389 transitions. [2024-11-12 21:45:12,658 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 26212 [2024-11-12 21:45:12,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:12,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:12,660 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:12,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:12,660 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:12,661 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume !(0 == ~t5_st~0);" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:12,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:12,661 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 5 times [2024-11-12 21:45:12,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:12,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415529922] [2024-11-12 21:45:12,661 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:12,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:12,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:12,669 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:12,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:12,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:12,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:12,686 INFO L85 PathProgramCache]: Analyzing trace with hash 650449639, now seen corresponding path program 1 times [2024-11-12 21:45:12,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:12,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504321266] [2024-11-12 21:45:12,686 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:12,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:12,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:12,690 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:12,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:12,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:12,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:12,693 INFO L85 PathProgramCache]: Analyzing trace with hash 2116988925, now seen corresponding path program 1 times [2024-11-12 21:45:12,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:12,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752948063] [2024-11-12 21:45:12,693 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:12,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:12,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:12,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:12,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752948063] [2024-11-12 21:45:12,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752948063] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:12,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1199689902] [2024-11-12 21:45:12,826 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:12,826 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:12,826 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:12,828 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:12,833 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-12 21:45:12,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:12,922 INFO L256 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:12,924 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:13,036 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:13,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1199689902] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:13,130 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:13,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:45:13,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351346962] [2024-11-12 21:45:13,130 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:13,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:13,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:13,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:13,187 INFO L87 Difference]: Start difference. First operand 26339 states and 34389 transitions. cyclomatic complexity: 8053 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:13,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:13,396 INFO L93 Difference]: Finished difference Result 48091 states and 62557 transitions. [2024-11-12 21:45:13,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48091 states and 62557 transitions. [2024-11-12 21:45:13,624 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 47932 [2024-11-12 21:45:13,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48091 states to 48091 states and 62557 transitions. [2024-11-12 21:45:13,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48091 [2024-11-12 21:45:13,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48091 [2024-11-12 21:45:13,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48091 states and 62557 transitions. [2024-11-12 21:45:13,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:13,975 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48091 states and 62557 transitions. [2024-11-12 21:45:13,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48091 states and 62557 transitions. [2024-11-12 21:45:14,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48091 to 46971. [2024-11-12 21:45:14,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46971 states, 46971 states have (on average 1.3028677268953184) internal successors, (61197), 46970 states have internal predecessors, (61197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:14,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46971 states to 46971 states and 61197 transitions. [2024-11-12 21:45:14,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46971 states and 61197 transitions. [2024-11-12 21:45:14,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:14,682 INFO L426 stractBuchiCegarLoop]: Abstraction has 46971 states and 61197 transitions. [2024-11-12 21:45:14,682 INFO L333 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-12 21:45:14,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46971 states and 61197 transitions. [2024-11-12 21:45:15,014 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 46812 [2024-11-12 21:45:15,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:15,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:15,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:15,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:15,017 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:15,018 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp_ndt_6~0#1);" "havoc eval_~tmp_ndt_6~0#1;" "assume !(0 == ~t6_st~0);" [2024-11-12 21:45:15,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:15,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 6 times [2024-11-12 21:45:15,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:15,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490640798] [2024-11-12 21:45:15,019 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:15,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:15,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:15,037 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:15,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:15,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:15,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:15,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1989256722, now seen corresponding path program 1 times [2024-11-12 21:45:15,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:15,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693633230] [2024-11-12 21:45:15,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:15,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:15,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:15,091 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:15,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:15,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:15,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:15,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1394275964, now seen corresponding path program 1 times [2024-11-12 21:45:15,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:15,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993410596] [2024-11-12 21:45:15,096 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:15,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:15,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:15,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:45:15,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993410596] [2024-11-12 21:45:15,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993410596] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:45:15,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1692202537] [2024-11-12 21:45:15,140 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:15,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:45:15,140 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:45:15,142 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:45:15,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-12 21:45:15,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:45:15,233 INFO L256 TraceCheckSpWp]: Trace formula consists of 286 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:45:15,237 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:45:15,352 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:45:15,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1692202537] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:45:15,489 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:45:15,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:45:15,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858152054] [2024-11-12 21:45:15,492 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:45:15,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:45:15,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:45:15,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:45:15,572 INFO L87 Difference]: Start difference. First operand 46971 states and 61197 transitions. cyclomatic complexity: 14229 Second operand has 3 states, 2 states have (on average 55.5) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:15,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:45:15,823 INFO L93 Difference]: Finished difference Result 79868 states and 103721 transitions. [2024-11-12 21:45:15,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79868 states and 103721 transitions. [2024-11-12 21:45:16,343 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 79645 [2024-11-12 21:45:16,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79868 states to 79868 states and 103721 transitions. [2024-11-12 21:45:16,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79868 [2024-11-12 21:45:16,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79868 [2024-11-12 21:45:16,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79868 states and 103721 transitions. [2024-11-12 21:45:16,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:45:16,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79868 states and 103721 transitions. [2024-11-12 21:45:16,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79868 states and 103721 transitions. [2024-11-12 21:45:17,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79868 to 79868. [2024-11-12 21:45:17,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79868 states, 79868 states have (on average 1.298655281214003) internal successors, (103721), 79867 states have internal predecessors, (103721), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:45:17,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79868 states to 79868 states and 103721 transitions. [2024-11-12 21:45:17,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79868 states and 103721 transitions. [2024-11-12 21:45:17,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:45:17,700 INFO L426 stractBuchiCegarLoop]: Abstraction has 79868 states and 103721 transitions. [2024-11-12 21:45:17,700 INFO L333 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-12 21:45:17,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79868 states and 103721 transitions. [2024-11-12 21:45:18,193 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 79645 [2024-11-12 21:45:18,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:45:18,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:45:18,195 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:18,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:45:18,195 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:45:18,195 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp_ndt_6~0#1);" "havoc eval_~tmp_ndt_6~0#1;" "assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1;" "assume !(0 != eval_~tmp_ndt_7~0#1);" "havoc eval_~tmp_ndt_7~0#1;" [2024-11-12 21:45:18,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:18,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 7 times [2024-11-12 21:45:18,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:18,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044348579] [2024-11-12 21:45:18,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:18,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:18,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,207 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:18,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,222 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:18,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:18,223 INFO L85 PathProgramCache]: Analyzing trace with hash -415395737, now seen corresponding path program 1 times [2024-11-12 21:45:18,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:18,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170148954] [2024-11-12 21:45:18,223 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:18,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:18,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,226 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:18,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:18,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:45:18,229 INFO L85 PathProgramCache]: Analyzing trace with hash 130462333, now seen corresponding path program 1 times [2024-11-12 21:45:18,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:45:18,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614722559] [2024-11-12 21:45:18,230 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:45:18,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:45:18,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,237 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:18,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:18,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:45:19,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:19,611 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:45:19,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:45:19,837 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 09:45:19 BoogieIcfgContainer [2024-11-12 21:45:19,838 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-12 21:45:19,844 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-12 21:45:19,844 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-12 21:45:19,844 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-12 21:45:19,845 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:45:00" (3/4) ... [2024-11-12 21:45:19,846 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-12 21:45:19,988 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-12 21:45:19,988 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-12 21:45:19,989 INFO L158 Benchmark]: Toolchain (without parser) took 20959.94ms. Allocated memory was 144.7MB in the beginning and 9.1GB in the end (delta: 8.9GB). Free memory was 73.1MB in the beginning and 8.0GB in the end (delta: -7.9GB). Peak memory consumption was 1.0GB. Max. memory is 16.1GB. [2024-11-12 21:45:19,989 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 144.7MB. Free memory was 108.0MB in the beginning and 107.8MB in the end (delta: 139.9kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-12 21:45:19,989 INFO L158 Benchmark]: CACSL2BoogieTranslator took 538.48ms. Allocated memory was 144.7MB in the beginning and 262.1MB in the end (delta: 117.4MB). Free memory was 72.9MB in the beginning and 219.7MB in the end (delta: -146.7MB). Peak memory consumption was 11.8MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,989 INFO L158 Benchmark]: Boogie Procedure Inliner took 82.26ms. Allocated memory is still 262.1MB. Free memory was 219.7MB in the beginning and 213.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,990 INFO L158 Benchmark]: Boogie Preprocessor took 114.68ms. Allocated memory is still 262.1MB. Free memory was 213.4MB in the beginning and 205.8MB in the end (delta: 7.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,990 INFO L158 Benchmark]: RCFGBuilder took 1170.28ms. Allocated memory is still 262.1MB. Free memory was 205.8MB in the beginning and 192.4MB in the end (delta: 13.4MB). Peak memory consumption was 77.6MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,990 INFO L158 Benchmark]: BuchiAutomizer took 18899.00ms. Allocated memory was 262.1MB in the beginning and 9.1GB in the end (delta: 8.8GB). Free memory was 192.4MB in the beginning and 8.0GB in the end (delta: -7.8GB). Peak memory consumption was 984.1MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,994 INFO L158 Benchmark]: Witness Printer took 144.33ms. Allocated memory is still 9.1GB. Free memory was 8.0GB in the beginning and 8.0GB in the end (delta: 17.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2024-11-12 21:45:19,995 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 144.7MB. Free memory was 108.0MB in the beginning and 107.8MB in the end (delta: 139.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 538.48ms. Allocated memory was 144.7MB in the beginning and 262.1MB in the end (delta: 117.4MB). Free memory was 72.9MB in the beginning and 219.7MB in the end (delta: -146.7MB). Peak memory consumption was 11.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 82.26ms. Allocated memory is still 262.1MB. Free memory was 219.7MB in the beginning and 213.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 114.68ms. Allocated memory is still 262.1MB. Free memory was 213.4MB in the beginning and 205.8MB in the end (delta: 7.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1170.28ms. Allocated memory is still 262.1MB. Free memory was 205.8MB in the beginning and 192.4MB in the end (delta: 13.4MB). Peak memory consumption was 77.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 18899.00ms. Allocated memory was 262.1MB in the beginning and 9.1GB in the end (delta: 8.8GB). Free memory was 192.4MB in the beginning and 8.0GB in the end (delta: -7.8GB). Peak memory consumption was 984.1MB. Max. memory is 16.1GB. * Witness Printer took 144.33ms. Allocated memory is still 9.1GB. Free memory was 8.0GB in the beginning and 8.0GB in the end (delta: 17.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (19 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.19 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 79868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 18.6s and 20 iterations. TraceHistogramMax:1. Analysis of lassos took 9.8s. Construction of modules took 0.7s. Büchi inclusion checks took 6.6s. Highest rank in rank-based complementation 0. Minimization of det autom 19. Minimization of nondet autom 0. Automata minimization 2.9s AutomataMinimizationTime, 19 MinimizatonAttempts, 3405 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 1.8s Buchi closure took 0.3s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 23772 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 23772 mSDsluCounter, 37592 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18995 mSDsCounter, 348 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 934 IncrementalHoareTripleChecker+Invalid, 1282 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 348 mSolverCounterUnsat, 18597 mSDtfsCounter, 934 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 565]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int t6_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int t6_st ; [L38] int m_i ; [L39] int t1_i ; [L40] int t2_i ; [L41] int t3_i ; [L42] int t4_i ; [L43] int t5_i ; [L44] int t6_i ; [L45] int M_E = 2; [L46] int T1_E = 2; [L47] int T2_E = 2; [L48] int T3_E = 2; [L49] int T4_E = 2; [L50] int T5_E = 2; [L51] int T6_E = 2; [L52] int E_M = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L67] int token ; [L69] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, token=0] [L1098] int __retres1 ; [L1102] CALL init_model() [L1008] m_i = 1 [L1009] t1_i = 1 [L1010] t2_i = 1 [L1011] t3_i = 1 [L1012] t4_i = 1 [L1013] t5_i = 1 [L1014] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1102] RET init_model() [L1103] CALL start_simulation() [L1039] int kernel_st ; [L1040] int tmp ; [L1041] int tmp___0 ; [L1045] kernel_st = 0 [L1046] FCALL update_channels() [L1047] CALL init_threads() [L475] COND TRUE m_i == 1 [L476] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L480] COND TRUE t1_i == 1 [L481] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L485] COND TRUE t2_i == 1 [L486] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L490] COND TRUE t3_i == 1 [L491] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L495] COND TRUE t4_i == 1 [L496] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L500] COND TRUE t5_i == 1 [L501] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L505] COND TRUE t6_i == 1 [L506] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1047] RET init_threads() [L1048] CALL fire_delta_events() [L684] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L689] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L694] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L699] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L704] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L709] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L714] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L719] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L724] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L729] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L734] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L739] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L744] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L749] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1048] RET fire_delta_events() [L1049] CALL activate_threads() [L837] int tmp ; [L838] int tmp___0 ; [L839] int tmp___1 ; [L840] int tmp___2 ; [L841] int tmp___3 ; [L842] int tmp___4 ; [L843] int tmp___5 ; [L847] CALL, EXPR is_master_triggered() [L331] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L334] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L344] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L346] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L847] RET, EXPR is_master_triggered() [L847] tmp = is_master_triggered() [L849] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] CALL, EXPR is_transmit1_triggered() [L350] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L353] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L363] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L365] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] RET, EXPR is_transmit1_triggered() [L855] tmp___0 = is_transmit1_triggered() [L857] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] CALL, EXPR is_transmit2_triggered() [L369] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L372] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L382] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L384] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] RET, EXPR is_transmit2_triggered() [L863] tmp___1 = is_transmit2_triggered() [L865] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] CALL, EXPR is_transmit3_triggered() [L388] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L391] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L401] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L403] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] RET, EXPR is_transmit3_triggered() [L871] tmp___2 = is_transmit3_triggered() [L873] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] CALL, EXPR is_transmit4_triggered() [L407] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L410] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L420] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L422] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] RET, EXPR is_transmit4_triggered() [L879] tmp___3 = is_transmit4_triggered() [L881] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] CALL, EXPR is_transmit5_triggered() [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L429] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L439] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L441] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] RET, EXPR is_transmit5_triggered() [L887] tmp___4 = is_transmit5_triggered() [L889] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] CALL, EXPR is_transmit6_triggered() [L445] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L448] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L458] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L460] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] RET, EXPR is_transmit6_triggered() [L895] tmp___5 = is_transmit6_triggered() [L897] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1049] RET activate_threads() [L1050] CALL reset_delta_events() [L762] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L767] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L772] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L777] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L782] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L787] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L792] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L797] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L802] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L807] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L812] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L817] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L822] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L827] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1050] RET reset_delta_events() [L1053] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1056] kernel_st = 1 [L1057] CALL eval() [L561] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] Loop: [L565] COND TRUE 1 [L568] CALL, EXPR exists_runnable_thread() [L515] int __retres1 ; [L518] COND TRUE m_st == 0 [L519] __retres1 = 1 [L556] return (__retres1); [L568] RET, EXPR exists_runnable_thread() [L568] tmp = exists_runnable_thread() [L570] COND TRUE \read(tmp) [L575] COND TRUE m_st == 0 [L576] int tmp_ndt_1; [L577] tmp_ndt_1 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_1)) [L589] COND TRUE t1_st == 0 [L590] int tmp_ndt_2; [L591] tmp_ndt_2 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_2)) [L603] COND TRUE t2_st == 0 [L604] int tmp_ndt_3; [L605] tmp_ndt_3 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_3)) [L617] COND TRUE t3_st == 0 [L618] int tmp_ndt_4; [L619] tmp_ndt_4 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_4)) [L631] COND TRUE t4_st == 0 [L632] int tmp_ndt_5; [L633] tmp_ndt_5 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_5)) [L645] COND TRUE t5_st == 0 [L646] int tmp_ndt_6; [L647] tmp_ndt_6 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_6)) [L659] COND TRUE t6_st == 0 [L660] int tmp_ndt_7; [L661] tmp_ndt_7 = __VERIFIER_nondet_int() [L662] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 565]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int t6_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int t6_st ; [L38] int m_i ; [L39] int t1_i ; [L40] int t2_i ; [L41] int t3_i ; [L42] int t4_i ; [L43] int t5_i ; [L44] int t6_i ; [L45] int M_E = 2; [L46] int T1_E = 2; [L47] int T2_E = 2; [L48] int T3_E = 2; [L49] int T4_E = 2; [L50] int T5_E = 2; [L51] int T6_E = 2; [L52] int E_M = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L67] int token ; [L69] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, token=0] [L1098] int __retres1 ; [L1102] CALL init_model() [L1008] m_i = 1 [L1009] t1_i = 1 [L1010] t2_i = 1 [L1011] t3_i = 1 [L1012] t4_i = 1 [L1013] t5_i = 1 [L1014] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1102] RET init_model() [L1103] CALL start_simulation() [L1039] int kernel_st ; [L1040] int tmp ; [L1041] int tmp___0 ; [L1045] kernel_st = 0 [L1046] FCALL update_channels() [L1047] CALL init_threads() [L475] COND TRUE m_i == 1 [L476] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L480] COND TRUE t1_i == 1 [L481] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L485] COND TRUE t2_i == 1 [L486] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L490] COND TRUE t3_i == 1 [L491] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L495] COND TRUE t4_i == 1 [L496] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L500] COND TRUE t5_i == 1 [L501] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L505] COND TRUE t6_i == 1 [L506] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1047] RET init_threads() [L1048] CALL fire_delta_events() [L684] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L689] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L694] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L699] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L704] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L709] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L714] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L719] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L724] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L729] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L734] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L739] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L744] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L749] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1048] RET fire_delta_events() [L1049] CALL activate_threads() [L837] int tmp ; [L838] int tmp___0 ; [L839] int tmp___1 ; [L840] int tmp___2 ; [L841] int tmp___3 ; [L842] int tmp___4 ; [L843] int tmp___5 ; [L847] CALL, EXPR is_master_triggered() [L331] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L334] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L344] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L346] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L847] RET, EXPR is_master_triggered() [L847] tmp = is_master_triggered() [L849] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] CALL, EXPR is_transmit1_triggered() [L350] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L353] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L363] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L365] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] RET, EXPR is_transmit1_triggered() [L855] tmp___0 = is_transmit1_triggered() [L857] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] CALL, EXPR is_transmit2_triggered() [L369] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L372] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L382] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L384] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] RET, EXPR is_transmit2_triggered() [L863] tmp___1 = is_transmit2_triggered() [L865] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] CALL, EXPR is_transmit3_triggered() [L388] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L391] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L401] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L403] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] RET, EXPR is_transmit3_triggered() [L871] tmp___2 = is_transmit3_triggered() [L873] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] CALL, EXPR is_transmit4_triggered() [L407] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L410] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L420] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L422] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] RET, EXPR is_transmit4_triggered() [L879] tmp___3 = is_transmit4_triggered() [L881] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] CALL, EXPR is_transmit5_triggered() [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L429] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L439] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L441] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] RET, EXPR is_transmit5_triggered() [L887] tmp___4 = is_transmit5_triggered() [L889] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] CALL, EXPR is_transmit6_triggered() [L445] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L448] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L458] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L460] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] RET, EXPR is_transmit6_triggered() [L895] tmp___5 = is_transmit6_triggered() [L897] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1049] RET activate_threads() [L1050] CALL reset_delta_events() [L762] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L767] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L772] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L777] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L782] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L787] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L792] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L797] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L802] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L807] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L812] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L817] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L822] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L827] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1050] RET reset_delta_events() [L1053] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1056] kernel_st = 1 [L1057] CALL eval() [L561] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] Loop: [L565] COND TRUE 1 [L568] CALL, EXPR exists_runnable_thread() [L515] int __retres1 ; [L518] COND TRUE m_st == 0 [L519] __retres1 = 1 [L556] return (__retres1); [L568] RET, EXPR exists_runnable_thread() [L568] tmp = exists_runnable_thread() [L570] COND TRUE \read(tmp) [L575] COND TRUE m_st == 0 [L576] int tmp_ndt_1; [L577] tmp_ndt_1 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_1)) [L589] COND TRUE t1_st == 0 [L590] int tmp_ndt_2; [L591] tmp_ndt_2 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_2)) [L603] COND TRUE t2_st == 0 [L604] int tmp_ndt_3; [L605] tmp_ndt_3 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_3)) [L617] COND TRUE t3_st == 0 [L618] int tmp_ndt_4; [L619] tmp_ndt_4 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_4)) [L631] COND TRUE t4_st == 0 [L632] int tmp_ndt_5; [L633] tmp_ndt_5 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_5)) [L645] COND TRUE t5_st == 0 [L646] int tmp_ndt_6; [L647] tmp_ndt_6 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_6)) [L659] COND TRUE t6_st == 0 [L660] int tmp_ndt_7; [L661] tmp_ndt_7 = __VERIFIER_nondet_int() [L662] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-12 21:45:20,028 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-11-12 21:45:20,229 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:20,427 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-11-12 21:45:20,631 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-11-12 21:45:20,832 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-11-12 21:45:21,037 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-11-12 21:45:21,242 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-11-12 21:45:21,439 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:21,639 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:21,842 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-11-12 21:45:22,041 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-11-12 21:45:22,240 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-11-12 21:45:22,443 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:22,645 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:22,844 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:23,049 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-12 21:45:23,253 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-12 21:45:23,448 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:23,652 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-12 21:45:23,860 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:24,056 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-12 21:45:24,258 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:24,457 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-12 21:45:24,658 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-11-12 21:45:24,857 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-12 21:45:25,058 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-12 21:45:25,268 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-12 21:45:25,669 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)