./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8be7027f Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.5-wip.dk.perfect-tracechecks-8be7027-m [2024-11-12 21:46:30,176 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-12 21:46:30,254 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-12 21:46:30,260 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-12 21:46:30,261 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-12 21:46:30,284 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-12 21:46:30,285 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-12 21:46:30,305 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-12 21:46:30,306 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-12 21:46:30,306 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-12 21:46:30,307 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-12 21:46:30,307 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-12 21:46:30,307 INFO L153 SettingsManager]: * Use SBE=true [2024-11-12 21:46:30,308 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-12 21:46:30,309 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-12 21:46:30,310 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-12 21:46:30,310 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-12 21:46:30,310 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-12 21:46:30,310 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-12 21:46:30,310 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-12 21:46:30,311 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-12 21:46:30,313 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-12 21:46:30,313 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-12 21:46:30,314 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-12 21:46:30,315 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-12 21:46:30,315 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-12 21:46:30,316 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-12 21:46:30,316 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-12 21:46:30,316 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-12 21:46:30,316 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2024-11-12 21:46:30,528 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-12 21:46:30,558 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-12 21:46:30,560 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-12 21:46:30,561 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-12 21:46:30,561 INFO L274 PluginConnector]: CDTParser initialized [2024-11-12 21:46:30,562 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2024-11-12 21:46:31,951 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-12 21:46:32,094 INFO L384 CDTParser]: Found 1 translation units. [2024-11-12 21:46:32,094 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2024-11-12 21:46:32,105 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ed3039f87/a0b46574b17e41b48aa0a2f4e8048aa2/FLAG5cfe130e0 [2024-11-12 21:46:32,501 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ed3039f87/a0b46574b17e41b48aa0a2f4e8048aa2 [2024-11-12 21:46:32,503 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-12 21:46:32,504 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-12 21:46:32,505 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-12 21:46:32,505 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-12 21:46:32,517 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-12 21:46:32,518 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,519 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@19c800fd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32, skipping insertion in model container [2024-11-12 21:46:32,519 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,544 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-12 21:46:32,781 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:46:32,796 INFO L200 MainTranslator]: Completed pre-run [2024-11-12 21:46:32,831 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-12 21:46:32,849 INFO L204 MainTranslator]: Completed translation [2024-11-12 21:46:32,849 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32 WrapperNode [2024-11-12 21:46:32,849 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-12 21:46:32,850 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-12 21:46:32,850 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-12 21:46:32,851 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-12 21:46:32,855 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,863 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,896 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 741 [2024-11-12 21:46:32,896 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-12 21:46:32,897 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-12 21:46:32,897 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-12 21:46:32,897 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-12 21:46:32,909 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,910 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,915 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,946 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-12 21:46:32,951 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,951 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,962 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,979 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,982 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,983 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,986 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-12 21:46:32,990 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-12 21:46:32,990 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-12 21:46:32,993 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-12 21:46:32,994 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (1/1) ... [2024-11-12 21:46:32,998 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:33,028 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:33,050 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:33,053 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-12 21:46:33,106 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-12 21:46:33,107 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-12 21:46:33,107 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-12 21:46:33,107 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-12 21:46:33,166 INFO L238 CfgBuilder]: Building ICFG [2024-11-12 21:46:33,168 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-12 21:46:33,746 INFO L? ?]: Removed 128 outVars from TransFormulas that were not future-live. [2024-11-12 21:46:33,747 INFO L287 CfgBuilder]: Performing block encoding [2024-11-12 21:46:33,763 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-12 21:46:33,766 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-12 21:46:33,767 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:46:33 BoogieIcfgContainer [2024-11-12 21:46:33,767 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-12 21:46:33,767 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-12 21:46:33,767 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-12 21:46:33,771 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-12 21:46:33,771 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:46:33,771 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 09:46:32" (1/3) ... [2024-11-12 21:46:33,772 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f648231 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:46:33, skipping insertion in model container [2024-11-12 21:46:33,772 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:46:33,772 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 09:46:32" (2/3) ... [2024-11-12 21:46:33,772 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f648231 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 09:46:33, skipping insertion in model container [2024-11-12 21:46:33,772 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-12 21:46:33,773 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:46:33" (3/3) ... [2024-11-12 21:46:33,774 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2024-11-12 21:46:33,816 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2024-11-12 21:46:33,816 INFO L302 stractBuchiCegarLoop]: Hoare is None [2024-11-12 21:46:33,816 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-12 21:46:33,817 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-12 21:46:33,817 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-12 21:46:33,817 INFO L306 stractBuchiCegarLoop]: Difference is false [2024-11-12 21:46:33,817 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-12 21:46:33,817 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-12 21:46:33,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:33,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-11-12 21:46:33,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:33,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:33,854 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:33,854 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:33,854 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-12 21:46:33,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:33,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2024-11-12 21:46:33,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:33,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:33,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:33,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:33,871 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:33,871 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume false;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:33,876 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:33,876 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2024-11-12 21:46:33,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:33,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495436337] [2024-11-12 21:46:33,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:33,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:33,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:34,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495436337] [2024-11-12 21:46:34,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495436337] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:34,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1816710911] [2024-11-12 21:46:34,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,057 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:34,057 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:34,059 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:34,060 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-12 21:46:34,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,173 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:34,181 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:34,234 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:34,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1816710911] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:34,287 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:34,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-12 21:46:34,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621267858] [2024-11-12 21:46:34,293 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:34,297 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:34,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:34,298 INFO L85 PathProgramCache]: Analyzing trace with hash -1698573144, now seen corresponding path program 1 times [2024-11-12 21:46:34,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:34,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639188330] [2024-11-12 21:46:34,299 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:34,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:34,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639188330] [2024-11-12 21:46:34,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639188330] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:34,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [570107202] [2024-11-12 21:46:34,347 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:34,347 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:34,349 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:34,351 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-12 21:46:34,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,422 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-12 21:46:34,454 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:34,459 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:34,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [570107202] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:34,465 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:34,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:46:34,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037197948] [2024-11-12 21:46:34,465 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:34,466 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:34,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:34,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:46:34,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:46:34,498 INFO L87 Difference]: Start difference. First operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:34,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:34,580 INFO L93 Difference]: Finished difference Result 294 states and 429 transitions. [2024-11-12 21:46:34,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 429 transitions. [2024-11-12 21:46:34,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-12 21:46:34,597 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 288 states and 423 transitions. [2024-11-12 21:46:34,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-12 21:46:34,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-12 21:46:34,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 423 transitions. [2024-11-12 21:46:34,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:34,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 423 transitions. [2024-11-12 21:46:34,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 423 transitions. [2024-11-12 21:46:34,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-12 21:46:34,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.46875) internal successors, (423), 287 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:34,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 423 transitions. [2024-11-12 21:46:34,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 423 transitions. [2024-11-12 21:46:34,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-12 21:46:34,642 INFO L426 stractBuchiCegarLoop]: Abstraction has 288 states and 423 transitions. [2024-11-12 21:46:34,642 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-12 21:46:34,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 423 transitions. [2024-11-12 21:46:34,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-12 21:46:34,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:34,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:34,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:34,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:34,649 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:34,649 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:34,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:34,650 INFO L85 PathProgramCache]: Analyzing trace with hash 598424500, now seen corresponding path program 1 times [2024-11-12 21:46:34,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:34,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469441523] [2024-11-12 21:46:34,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:34,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:34,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469441523] [2024-11-12 21:46:34,692 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469441523] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:34,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1660488690] [2024-11-12 21:46:34,692 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,692 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:34,693 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:34,694 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:34,696 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-12 21:46:34,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:34,750 INFO L256 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:34,752 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:34,857 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:34,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1660488690] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:34,915 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:34,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:46:34,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065565668] [2024-11-12 21:46:34,916 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:34,916 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:34,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:34,917 INFO L85 PathProgramCache]: Analyzing trace with hash -1557147238, now seen corresponding path program 1 times [2024-11-12 21:46:34,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:34,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681646198] [2024-11-12 21:46:34,917 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:34,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:34,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:35,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681646198] [2024-11-12 21:46:35,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681646198] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:35,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [760831211] [2024-11-12 21:46:35,086 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,086 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:35,086 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:35,095 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:35,097 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-12 21:46:35,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,153 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:35,154 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:35,242 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:35,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [760831211] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:35,275 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:35,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:35,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916762493] [2024-11-12 21:46:35,276 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:35,276 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:35,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:35,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:46:35,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:46:35,277 INFO L87 Difference]: Start difference. First operand 288 states and 423 transitions. cyclomatic complexity: 136 Second operand has 4 states, 4 states have (on average 18.5) internal successors, (74), 4 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:35,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:35,325 INFO L93 Difference]: Finished difference Result 288 states and 412 transitions. [2024-11-12 21:46:35,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 412 transitions. [2024-11-12 21:46:35,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-12 21:46:35,328 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 412 transitions. [2024-11-12 21:46:35,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2024-11-12 21:46:35,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2024-11-12 21:46:35,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 412 transitions. [2024-11-12 21:46:35,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:35,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 412 transitions. [2024-11-12 21:46:35,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 412 transitions. [2024-11-12 21:46:35,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2024-11-12 21:46:35,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4305555555555556) internal successors, (412), 287 states have internal predecessors, (412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:35,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 412 transitions. [2024-11-12 21:46:35,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 412 transitions. [2024-11-12 21:46:35,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:35,337 INFO L426 stractBuchiCegarLoop]: Abstraction has 288 states and 412 transitions. [2024-11-12 21:46:35,338 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-12 21:46:35,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 412 transitions. [2024-11-12 21:46:35,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2024-11-12 21:46:35,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:35,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:35,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:35,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:35,340 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:35,341 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:35,341 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:35,341 INFO L85 PathProgramCache]: Analyzing trace with hash 2134602257, now seen corresponding path program 1 times [2024-11-12 21:46:35,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:35,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384837082] [2024-11-12 21:46:35,342 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:35,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:35,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384837082] [2024-11-12 21:46:35,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384837082] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:35,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1384659967] [2024-11-12 21:46:35,368 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:35,369 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:35,370 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:35,372 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-12 21:46:35,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,467 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:35,468 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:35,527 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:35,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1384659967] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:35,580 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:35,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:46:35,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593703197] [2024-11-12 21:46:35,581 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:35,581 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:35,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:35,581 INFO L85 PathProgramCache]: Analyzing trace with hash 2072879770, now seen corresponding path program 1 times [2024-11-12 21:46:35,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:35,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579940260] [2024-11-12 21:46:35,582 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:35,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:35,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579940260] [2024-11-12 21:46:35,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579940260] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:35,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [283004374] [2024-11-12 21:46:35,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,646 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:35,646 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:35,648 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:35,652 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-12 21:46:35,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,704 INFO L256 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:35,706 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:35,737 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:35,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [283004374] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:35,775 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:35,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:35,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113693249] [2024-11-12 21:46:35,776 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:35,776 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:35,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:35,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:46:35,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:46:35,777 INFO L87 Difference]: Start difference. First operand 288 states and 412 transitions. cyclomatic complexity: 125 Second operand has 4 states, 4 states have (on average 21.25) internal successors, (85), 4 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:35,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:35,816 INFO L93 Difference]: Finished difference Result 516 states and 728 transitions. [2024-11-12 21:46:35,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 516 states and 728 transitions. [2024-11-12 21:46:35,819 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 462 [2024-11-12 21:46:35,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 516 states to 516 states and 728 transitions. [2024-11-12 21:46:35,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 516 [2024-11-12 21:46:35,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 516 [2024-11-12 21:46:35,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 516 states and 728 transitions. [2024-11-12 21:46:35,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:35,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 516 states and 728 transitions. [2024-11-12 21:46:35,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 516 states and 728 transitions. [2024-11-12 21:46:35,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 516 to 512. [2024-11-12 21:46:35,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 512 states, 512 states have (on average 1.412109375) internal successors, (723), 511 states have internal predecessors, (723), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:35,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 723 transitions. [2024-11-12 21:46:35,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 512 states and 723 transitions. [2024-11-12 21:46:35,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:35,838 INFO L426 stractBuchiCegarLoop]: Abstraction has 512 states and 723 transitions. [2024-11-12 21:46:35,838 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-12 21:46:35,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 512 states and 723 transitions. [2024-11-12 21:46:35,840 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 460 [2024-11-12 21:46:35,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:35,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:35,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:35,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:35,842 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:35,842 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:35,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:35,842 INFO L85 PathProgramCache]: Analyzing trace with hash 882094642, now seen corresponding path program 1 times [2024-11-12 21:46:35,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:35,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823550668] [2024-11-12 21:46:35,843 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:35,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:35,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823550668] [2024-11-12 21:46:35,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823550668] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:35,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1655683352] [2024-11-12 21:46:35,896 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:35,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:35,897 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:35,898 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:35,906 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-12 21:46:35,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:35,957 INFO L256 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:35,958 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:36,004 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:36,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1655683352] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:36,061 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:36,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 2, 2] total 6 [2024-11-12 21:46:36,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145555480] [2024-11-12 21:46:36,061 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:36,062 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:36,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:36,062 INFO L85 PathProgramCache]: Analyzing trace with hash -1583303047, now seen corresponding path program 1 times [2024-11-12 21:46:36,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:36,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903032877] [2024-11-12 21:46:36,062 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:36,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:36,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903032877] [2024-11-12 21:46:36,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903032877] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:36,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1864306437] [2024-11-12 21:46:36,109 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:36,109 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:36,111 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:36,112 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-12 21:46:36,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,170 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:36,171 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:36,217 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:36,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1864306437] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:36,258 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:36,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:36,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018739153] [2024-11-12 21:46:36,258 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:36,258 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:36,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:36,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-12 21:46:36,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-12 21:46:36,259 INFO L87 Difference]: Start difference. First operand 512 states and 723 transitions. cyclomatic complexity: 213 Second operand has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:36,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:36,422 INFO L93 Difference]: Finished difference Result 545 states and 748 transitions. [2024-11-12 21:46:36,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 545 states and 748 transitions. [2024-11-12 21:46:36,425 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 490 [2024-11-12 21:46:36,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 545 states to 545 states and 748 transitions. [2024-11-12 21:46:36,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 545 [2024-11-12 21:46:36,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 545 [2024-11-12 21:46:36,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 545 states and 748 transitions. [2024-11-12 21:46:36,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:36,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 545 states and 748 transitions. [2024-11-12 21:46:36,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states and 748 transitions. [2024-11-12 21:46:36,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 545. [2024-11-12 21:46:36,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 545 states, 545 states have (on average 1.3724770642201836) internal successors, (748), 544 states have internal predecessors, (748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:36,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 748 transitions. [2024-11-12 21:46:36,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 545 states and 748 transitions. [2024-11-12 21:46:36,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-12 21:46:36,449 INFO L426 stractBuchiCegarLoop]: Abstraction has 545 states and 748 transitions. [2024-11-12 21:46:36,453 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-12 21:46:36,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 545 states and 748 transitions. [2024-11-12 21:46:36,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 490 [2024-11-12 21:46:36,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:36,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:36,456 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:36,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:36,456 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:36,456 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:36,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:36,457 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2024-11-12 21:46:36,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:36,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224100333] [2024-11-12 21:46:36,460 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:36,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:36,473 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:36,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:36,500 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:36,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:36,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1107797629, now seen corresponding path program 1 times [2024-11-12 21:46:36,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:36,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188996056] [2024-11-12 21:46:36,501 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:36,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:36,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188996056] [2024-11-12 21:46:36,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188996056] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:36,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1120143515] [2024-11-12 21:46:36,529 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,529 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:36,529 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:36,531 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:36,532 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-12 21:46:36,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,600 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:36,601 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:36,634 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:36,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1120143515] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:36,674 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:36,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:36,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591455826] [2024-11-12 21:46:36,674 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:36,675 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:36,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:36,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:36,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:36,675 INFO L87 Difference]: Start difference. First operand 545 states and 748 transitions. cyclomatic complexity: 205 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:36,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:36,715 INFO L93 Difference]: Finished difference Result 920 states and 1247 transitions. [2024-11-12 21:46:36,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 920 states and 1247 transitions. [2024-11-12 21:46:36,720 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 827 [2024-11-12 21:46:36,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 920 states to 920 states and 1247 transitions. [2024-11-12 21:46:36,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 920 [2024-11-12 21:46:36,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 920 [2024-11-12 21:46:36,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 920 states and 1247 transitions. [2024-11-12 21:46:36,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:36,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 920 states and 1247 transitions. [2024-11-12 21:46:36,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 920 states and 1247 transitions. [2024-11-12 21:46:36,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 920 to 918. [2024-11-12 21:46:36,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 918 states, 918 states have (on average 1.3562091503267975) internal successors, (1245), 917 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:36,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 918 states to 918 states and 1245 transitions. [2024-11-12 21:46:36,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 918 states and 1245 transitions. [2024-11-12 21:46:36,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:36,738 INFO L426 stractBuchiCegarLoop]: Abstraction has 918 states and 1245 transitions. [2024-11-12 21:46:36,738 INFO L333 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-12 21:46:36,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 918 states and 1245 transitions. [2024-11-12 21:46:36,742 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 825 [2024-11-12 21:46:36,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:36,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:36,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:36,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:36,743 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:36,743 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:36,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:36,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2024-11-12 21:46:36,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:36,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104330770] [2024-11-12 21:46:36,744 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:36,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:36,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104330770] [2024-11-12 21:46:36,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104330770] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:36,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [119112685] [2024-11-12 21:46:36,781 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:36,781 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:36,787 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:36,789 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-12 21:46:36,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,836 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:36,838 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:36,855 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:36,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [119112685] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:36,881 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:36,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 3 [2024-11-12 21:46:36,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939451201] [2024-11-12 21:46:36,882 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:36,882 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:36,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:36,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1673683870, now seen corresponding path program 1 times [2024-11-12 21:46:36,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:36,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486241001] [2024-11-12 21:46:36,882 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:36,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:36,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486241001] [2024-11-12 21:46:36,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486241001] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:36,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [113157996] [2024-11-12 21:46:36,921 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:36,921 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:36,921 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:36,926 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:36,927 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-12 21:46:36,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:36,974 INFO L256 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:46:36,975 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:36,998 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:37,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [113157996] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:37,014 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:37,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:46:37,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054321470] [2024-11-12 21:46:37,015 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:37,015 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:37,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:37,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:46:37,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:46:37,015 INFO L87 Difference]: Start difference. First operand 918 states and 1245 transitions. cyclomatic complexity: 329 Second operand has 4 states, 4 states have (on average 16.0) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:37,044 INFO L93 Difference]: Finished difference Result 545 states and 729 transitions. [2024-11-12 21:46:37,044 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 545 states and 729 transitions. [2024-11-12 21:46:37,047 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 490 [2024-11-12 21:46:37,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 545 states to 545 states and 729 transitions. [2024-11-12 21:46:37,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 545 [2024-11-12 21:46:37,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 545 [2024-11-12 21:46:37,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 545 states and 729 transitions. [2024-11-12 21:46:37,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:37,050 INFO L218 hiAutomatonCegarLoop]: Abstraction has 545 states and 729 transitions. [2024-11-12 21:46:37,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states and 729 transitions. [2024-11-12 21:46:37,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 545. [2024-11-12 21:46:37,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 545 states, 545 states have (on average 1.3376146788990826) internal successors, (729), 544 states have internal predecessors, (729), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 729 transitions. [2024-11-12 21:46:37,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 545 states and 729 transitions. [2024-11-12 21:46:37,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-12 21:46:37,056 INFO L426 stractBuchiCegarLoop]: Abstraction has 545 states and 729 transitions. [2024-11-12 21:46:37,056 INFO L333 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-12 21:46:37,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 545 states and 729 transitions. [2024-11-12 21:46:37,058 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 490 [2024-11-12 21:46:37,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:37,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:37,059 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,059 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,060 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:37,060 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:37,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,060 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2024-11-12 21:46:37,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777247120] [2024-11-12 21:46:37,060 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,066 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:37,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:37,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1673683870, now seen corresponding path program 2 times [2024-11-12 21:46:37,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95765716] [2024-11-12 21:46:37,076 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:37,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95765716] [2024-11-12 21:46:37,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95765716] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:37,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1372514939] [2024-11-12 21:46:37,118 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-12 21:46:37,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:37,118 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:37,120 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:37,121 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-12 21:46:37,169 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2024-11-12 21:46:37,169 INFO L185 FreeRefinementEngine]: Found 0 perfect and 1 imperfect interpolant sequences. [2024-11-12 21:46:37,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2024-11-12 21:46:37,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336722395] [2024-11-12 21:46:37,169 INFO L85 oduleStraightlineAll]: Using 1 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:37,170 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:37,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:37,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:46:37,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:46:37,173 INFO L87 Difference]: Start difference. First operand 545 states and 729 transitions. cyclomatic complexity: 186 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:37,228 INFO L93 Difference]: Finished difference Result 559 states and 743 transitions. [2024-11-12 21:46:37,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 743 transitions. [2024-11-12 21:46:37,230 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 504 [2024-11-12 21:46:37,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 743 transitions. [2024-11-12 21:46:37,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2024-11-12 21:46:37,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2024-11-12 21:46:37,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 743 transitions. [2024-11-12 21:46:37,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:37,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 559 states and 743 transitions. [2024-11-12 21:46:37,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 743 transitions. [2024-11-12 21:46:37,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 551. [2024-11-12 21:46:37,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.3339382940108893) internal successors, (735), 550 states have internal predecessors, (735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 735 transitions. [2024-11-12 21:46:37,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 735 transitions. [2024-11-12 21:46:37,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:37,251 INFO L426 stractBuchiCegarLoop]: Abstraction has 551 states and 735 transitions. [2024-11-12 21:46:37,251 INFO L333 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-12 21:46:37,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 735 transitions. [2024-11-12 21:46:37,253 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2024-11-12 21:46:37,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:37,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:37,254 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,254 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,254 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:37,254 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:37,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,259 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2024-11-12 21:46:37,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962572409] [2024-11-12 21:46:37,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,273 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:37,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:37,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1443364504, now seen corresponding path program 1 times [2024-11-12 21:46:37,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745583984] [2024-11-12 21:46:37,298 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:37,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745583984] [2024-11-12 21:46:37,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745583984] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:37,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [923216998] [2024-11-12 21:46:37,380 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:37,380 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:37,382 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:37,384 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-12 21:46:37,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,434 INFO L256 TraceCheckSpWp]: Trace formula consists of 132 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:46:37,435 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:37,445 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:37,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [923216998] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:37,462 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:37,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:46:37,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780931943] [2024-11-12 21:46:37,462 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:37,463 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:37,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:37,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:46:37,463 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:46:37,463 INFO L87 Difference]: Start difference. First operand 551 states and 735 transitions. cyclomatic complexity: 186 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:37,512 INFO L93 Difference]: Finished difference Result 561 states and 745 transitions. [2024-11-12 21:46:37,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 561 states and 745 transitions. [2024-11-12 21:46:37,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2024-11-12 21:46:37,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 561 states to 561 states and 745 transitions. [2024-11-12 21:46:37,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 561 [2024-11-12 21:46:37,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 561 [2024-11-12 21:46:37,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 561 states and 745 transitions. [2024-11-12 21:46:37,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:37,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 561 states and 745 transitions. [2024-11-12 21:46:37,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states and 745 transitions. [2024-11-12 21:46:37,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 557. [2024-11-12 21:46:37,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.3303411131059246) internal successors, (741), 556 states have internal predecessors, (741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 741 transitions. [2024-11-12 21:46:37,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 741 transitions. [2024-11-12 21:46:37,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:37,529 INFO L426 stractBuchiCegarLoop]: Abstraction has 557 states and 741 transitions. [2024-11-12 21:46:37,529 INFO L333 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-12 21:46:37,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 741 transitions. [2024-11-12 21:46:37,531 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 502 [2024-11-12 21:46:37,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:37,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:37,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,532 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:37,532 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:37,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,533 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2024-11-12 21:46:37,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036877014] [2024-11-12 21:46:37,533 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,540 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:37,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:37,548 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1203605065, now seen corresponding path program 1 times [2024-11-12 21:46:37,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560508025] [2024-11-12 21:46:37,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:37,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1560508025] [2024-11-12 21:46:37,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1560508025] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:37,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [774865066] [2024-11-12 21:46:37,597 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:37,597 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:37,599 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:37,600 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-12 21:46:37,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,649 INFO L256 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:37,650 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:37,698 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:37,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [774865066] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:37,753 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:37,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:37,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745611202] [2024-11-12 21:46:37,754 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:37,754 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:37,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:37,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:37,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:37,755 INFO L87 Difference]: Start difference. First operand 557 states and 741 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:37,786 INFO L93 Difference]: Finished difference Result 961 states and 1260 transitions. [2024-11-12 21:46:37,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 961 states and 1260 transitions. [2024-11-12 21:46:37,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 906 [2024-11-12 21:46:37,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 961 states to 961 states and 1260 transitions. [2024-11-12 21:46:37,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 961 [2024-11-12 21:46:37,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 961 [2024-11-12 21:46:37,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 961 states and 1260 transitions. [2024-11-12 21:46:37,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:37,796 INFO L218 hiAutomatonCegarLoop]: Abstraction has 961 states and 1260 transitions. [2024-11-12 21:46:37,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 961 states and 1260 transitions. [2024-11-12 21:46:37,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 961 to 912. [2024-11-12 21:46:37,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 912 states, 912 states have (on average 1.3125) internal successors, (1197), 911 states have internal predecessors, (1197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:37,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 912 states to 912 states and 1197 transitions. [2024-11-12 21:46:37,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 912 states and 1197 transitions. [2024-11-12 21:46:37,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:37,809 INFO L426 stractBuchiCegarLoop]: Abstraction has 912 states and 1197 transitions. [2024-11-12 21:46:37,809 INFO L333 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-12 21:46:37,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 912 states and 1197 transitions. [2024-11-12 21:46:37,812 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 857 [2024-11-12 21:46:37,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:37,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:37,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:37,813 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:37,813 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:37,813 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,814 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2024-11-12 21:46:37,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586056114] [2024-11-12 21:46:37,814 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,819 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:37,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:37,825 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:37,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:37,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1443304922, now seen corresponding path program 1 times [2024-11-12 21:46:37,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:37,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376639855] [2024-11-12 21:46:37,826 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:37,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:37,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376639855] [2024-11-12 21:46:37,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376639855] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:37,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [976849395] [2024-11-12 21:46:37,867 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:37,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:37,867 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:37,871 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:37,875 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-12 21:46:37,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:37,928 INFO L256 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-12 21:46:37,929 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:37,950 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:37,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [976849395] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:37,956 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:37,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-12 21:46:37,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389156382] [2024-11-12 21:46:37,957 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:37,957 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:37,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:37,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-12 21:46:37,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-12 21:46:37,958 INFO L87 Difference]: Start difference. First operand 912 states and 1197 transitions. cyclomatic complexity: 287 Second operand has 8 states, 8 states have (on average 10.125) internal successors, (81), 8 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:38,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:38,190 INFO L93 Difference]: Finished difference Result 945 states and 1203 transitions. [2024-11-12 21:46:38,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 945 states and 1203 transitions. [2024-11-12 21:46:38,197 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2024-11-12 21:46:38,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 945 states to 945 states and 1203 transitions. [2024-11-12 21:46:38,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 945 [2024-11-12 21:46:38,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 945 [2024-11-12 21:46:38,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 945 states and 1203 transitions. [2024-11-12 21:46:38,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:38,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 945 states and 1203 transitions. [2024-11-12 21:46:38,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 945 states and 1203 transitions. [2024-11-12 21:46:38,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 945 to 945. [2024-11-12 21:46:38,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 945 states, 945 states have (on average 1.273015873015873) internal successors, (1203), 944 states have internal predecessors, (1203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:38,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 945 states to 945 states and 1203 transitions. [2024-11-12 21:46:38,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 945 states and 1203 transitions. [2024-11-12 21:46:38,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-12 21:46:38,223 INFO L426 stractBuchiCegarLoop]: Abstraction has 945 states and 1203 transitions. [2024-11-12 21:46:38,224 INFO L333 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-12 21:46:38,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 945 states and 1203 transitions. [2024-11-12 21:46:38,226 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2024-11-12 21:46:38,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:38,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:38,230 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:38,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:38,231 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:38,231 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:38,231 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:38,231 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2024-11-12 21:46:38,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:38,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433917404] [2024-11-12 21:46:38,232 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:38,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,243 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:38,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,252 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:38,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:38,253 INFO L85 PathProgramCache]: Analyzing trace with hash -581823658, now seen corresponding path program 1 times [2024-11-12 21:46:38,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:38,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262781634] [2024-11-12 21:46:38,253 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:38,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:38,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:38,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262781634] [2024-11-12 21:46:38,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262781634] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:38,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1795158362] [2024-11-12 21:46:38,313 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:38,313 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:38,317 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:38,327 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-12 21:46:38,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:38,374 INFO L256 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-12 21:46:38,374 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:38,381 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:38,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1795158362] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:38,394 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:38,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-12 21:46:38,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106886639] [2024-11-12 21:46:38,394 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:38,395 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-12 21:46:38,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:38,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-12 21:46:38,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-12 21:46:38,395 INFO L87 Difference]: Start difference. First operand 945 states and 1203 transitions. cyclomatic complexity: 260 Second operand has 5 states, 5 states have (on average 13.0) internal successors, (65), 5 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:38,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:38,496 INFO L93 Difference]: Finished difference Result 957 states and 1200 transitions. [2024-11-12 21:46:38,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 957 states and 1200 transitions. [2024-11-12 21:46:38,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 902 [2024-11-12 21:46:38,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 957 states to 957 states and 1200 transitions. [2024-11-12 21:46:38,502 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 957 [2024-11-12 21:46:38,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 957 [2024-11-12 21:46:38,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 957 states and 1200 transitions. [2024-11-12 21:46:38,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-12 21:46:38,503 INFO L218 hiAutomatonCegarLoop]: Abstraction has 957 states and 1200 transitions. [2024-11-12 21:46:38,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states and 1200 transitions. [2024-11-12 21:46:38,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 957. [2024-11-12 21:46:38,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 957 states have (on average 1.2539184952978057) internal successors, (1200), 956 states have internal predecessors, (1200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:38,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1200 transitions. [2024-11-12 21:46:38,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 957 states and 1200 transitions. [2024-11-12 21:46:38,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:38,513 INFO L426 stractBuchiCegarLoop]: Abstraction has 957 states and 1200 transitions. [2024-11-12 21:46:38,513 INFO L333 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-12 21:46:38,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 957 states and 1200 transitions. [2024-11-12 21:46:38,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 902 [2024-11-12 21:46:38,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:38,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:38,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:38,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:38,516 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-12 21:46:38,516 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-12 21:46:38,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:38,516 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2024-11-12 21:46:38,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:38,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828829324] [2024-11-12 21:46:38,517 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:38,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,521 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:38,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:38,527 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:38,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1091296748, now seen corresponding path program 1 times [2024-11-12 21:46:38,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:38,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169357555] [2024-11-12 21:46:38,527 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:38,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,533 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:38,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:38,573 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:38,573 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:38,573 INFO L85 PathProgramCache]: Analyzing trace with hash -778618813, now seen corresponding path program 1 times [2024-11-12 21:46:38,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:38,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743273193] [2024-11-12 21:46:38,574 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:38,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:38,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:38,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743273193] [2024-11-12 21:46:38,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743273193] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:38,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1519052827] [2024-11-12 21:46:38,600 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:38,600 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:38,600 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:38,602 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:38,603 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-12 21:46:38,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:38,677 INFO L256 TraceCheckSpWp]: Trace formula consists of 269 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:38,678 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:38,747 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:38,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1519052827] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:38,818 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:38,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-12 21:46:38,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461750433] [2024-11-12 21:46:38,818 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:39,234 INFO L204 LassoAnalysis]: Preferences: [2024-11-12 21:46:39,235 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-12 21:46:39,235 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-12 21:46:39,235 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-12 21:46:39,235 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-12 21:46:39,235 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,235 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-12 21:46:39,235 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-12 21:46:39,235 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration12_Loop [2024-11-12 21:46:39,235 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-12 21:46:39,236 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-12 21:46:39,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,269 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,272 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,282 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,309 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,313 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,321 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,323 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,326 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,330 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,333 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,336 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,338 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,349 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,351 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,618 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-12 21:46:39,619 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-12 21:46:39,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,621 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:39,624 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:39,626 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-12 21:46:39,627 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-12 21:46:39,627 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-12 21:46:39,645 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-12 21:46:39,645 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-12 21:46:39,666 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-12 21:46:39,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,667 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:39,668 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:39,672 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-12 21:46:39,678 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-12 21:46:39,678 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-12 21:46:39,692 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-12 21:46:39,693 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet6#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-12 21:46:39,708 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:39,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,709 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:39,710 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:39,711 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-12 21:46:39,716 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-12 21:46:39,717 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-12 21:46:39,736 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-12 21:46:39,737 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_2~0=-8} Honda state: {~E_2~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-12 21:46:39,752 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:39,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:39,754 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:39,760 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-12 21:46:39,761 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-12 21:46:39,761 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-12 21:46:39,784 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-12 21:46:39,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,785 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:39,789 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:39,824 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-12 21:46:39,826 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-12 21:46:39,826 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-12 21:46:39,839 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-12 21:46:39,851 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:39,851 INFO L204 LassoAnalysis]: Preferences: [2024-11-12 21:46:39,851 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-12 21:46:39,851 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-12 21:46:39,851 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-12 21:46:39,851 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-12 21:46:39,851 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:39,851 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-12 21:46:39,851 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-12 21:46:39,851 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration12_Loop [2024-11-12 21:46:39,851 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-12 21:46:39,852 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-12 21:46:39,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,903 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,914 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,974 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:39,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-12 21:46:40,245 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-12 21:46:40,254 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-12 21:46:40,255 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:40,255 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:40,257 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:40,258 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-12 21:46:40,263 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-12 21:46:40,273 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-12 21:46:40,274 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-12 21:46:40,274 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-12 21:46:40,274 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-12 21:46:40,274 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-12 21:46:40,276 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-12 21:46:40,276 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-12 21:46:40,278 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-12 21:46:40,289 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-12 21:46:40,290 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:40,290 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:40,291 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:40,292 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-12 21:46:40,293 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-12 21:46:40,303 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-12 21:46:40,303 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-12 21:46:40,303 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-12 21:46:40,303 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-12 21:46:40,303 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-12 21:46:40,305 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-12 21:46:40,305 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-12 21:46:40,309 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-12 21:46:40,312 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-12 21:46:40,312 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-12 21:46:40,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-12 21:46:40,314 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:40,315 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-12 21:46:40,316 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-12 21:46:40,318 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-12 21:46:40,318 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-12 21:46:40,318 INFO L474 LassoAnalysis]: Proved termination. [2024-11-12 21:46:40,319 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-12 21:46:40,330 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-12 21:46:40,332 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-12 21:46:40,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:40,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:40,423 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-12 21:46:40,424 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:40,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:40,537 INFO L256 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-12 21:46:40,538 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:40,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-12 21:46:40,761 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-12 21:46:40,762 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 957 states and 1200 transitions. cyclomatic complexity: 245 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:40,871 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 957 states and 1200 transitions. cyclomatic complexity: 245. Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 2447 states and 3085 transitions. Complement of second has 5 states. [2024-11-12 21:46:40,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-12 21:46:40,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:40,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 337 transitions. [2024-11-12 21:46:40,875 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 337 transitions. Stem has 49 letters. Loop has 65 letters. [2024-11-12 21:46:40,878 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-12 21:46:40,878 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 337 transitions. Stem has 114 letters. Loop has 65 letters. [2024-11-12 21:46:40,878 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-12 21:46:40,879 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 337 transitions. Stem has 49 letters. Loop has 130 letters. [2024-11-12 21:46:40,882 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-12 21:46:40,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2447 states and 3085 transitions. [2024-11-12 21:46:40,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1640 [2024-11-12 21:46:40,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2447 states to 2447 states and 3085 transitions. [2024-11-12 21:46:40,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1696 [2024-11-12 21:46:40,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1703 [2024-11-12 21:46:40,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2447 states and 3085 transitions. [2024-11-12 21:46:40,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:40,928 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2447 states and 3085 transitions. [2024-11-12 21:46:40,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2447 states and 3085 transitions. [2024-11-12 21:46:40,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2447 to 2440. [2024-11-12 21:46:40,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2440 states, 2440 states have (on average 1.2614754098360657) internal successors, (3078), 2439 states have internal predecessors, (3078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:40,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2440 states to 2440 states and 3078 transitions. [2024-11-12 21:46:40,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2440 states and 3078 transitions. [2024-11-12 21:46:40,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:40,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-12 21:46:40,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-12 21:46:40,990 INFO L87 Difference]: Start difference. First operand 2440 states and 3078 transitions. Second operand has 4 states, 4 states have (on average 46.25) internal successors, (185), 4 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:41,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:41,087 INFO L93 Difference]: Finished difference Result 3210 states and 3969 transitions. [2024-11-12 21:46:41,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3210 states and 3969 transitions. [2024-11-12 21:46:41,114 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2087 [2024-11-12 21:46:41,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3210 states to 3210 states and 3969 transitions. [2024-11-12 21:46:41,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2144 [2024-11-12 21:46:41,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2144 [2024-11-12 21:46:41,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3210 states and 3969 transitions. [2024-11-12 21:46:41,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:41,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3210 states and 3969 transitions. [2024-11-12 21:46:41,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3210 states and 3969 transitions. [2024-11-12 21:46:41,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3210 to 2838. [2024-11-12 21:46:41,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2838 states, 2838 states have (on average 1.244186046511628) internal successors, (3531), 2837 states have internal predecessors, (3531), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:41,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2838 states to 2838 states and 3531 transitions. [2024-11-12 21:46:41,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2838 states and 3531 transitions. [2024-11-12 21:46:41,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-12 21:46:41,219 INFO L426 stractBuchiCegarLoop]: Abstraction has 2838 states and 3531 transitions. [2024-11-12 21:46:41,219 INFO L333 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-12 21:46:41,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2838 states and 3531 transitions. [2024-11-12 21:46:41,234 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1839 [2024-11-12 21:46:41,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:41,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:41,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:41,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:41,238 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:46:41,238 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:46:41,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:41,239 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2024-11-12 21:46:41,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:41,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801872694] [2024-11-12 21:46:41,240 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:41,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:41,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:41,257 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:41,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:41,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:41,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:41,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 1 times [2024-11-12 21:46:41,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:41,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651720266] [2024-11-12 21:46:41,273 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:41,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:41,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:41,280 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:41,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:41,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:41,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:41,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1338864530, now seen corresponding path program 1 times [2024-11-12 21:46:41,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:41,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077501292] [2024-11-12 21:46:41,287 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:41,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:41,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:41,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:41,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077501292] [2024-11-12 21:46:41,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077501292] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:41,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1336501237] [2024-11-12 21:46:41,335 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:41,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:41,335 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:41,337 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:41,343 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-12 21:46:41,442 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:41,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:41,474 INFO L256 TraceCheckSpWp]: Trace formula consists of 165 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:41,475 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:41,570 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:41,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1336501237] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:41,667 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:41,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:41,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214144929] [2024-11-12 21:46:41,668 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:41,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:41,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:41,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:41,716 INFO L87 Difference]: Start difference. First operand 2838 states and 3531 transitions. cyclomatic complexity: 703 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:41,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:41,774 INFO L93 Difference]: Finished difference Result 4338 states and 5349 transitions. [2024-11-12 21:46:41,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4338 states and 5349 transitions. [2024-11-12 21:46:41,808 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2820 [2024-11-12 21:46:41,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4338 states to 4338 states and 5349 transitions. [2024-11-12 21:46:41,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2928 [2024-11-12 21:46:41,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2928 [2024-11-12 21:46:41,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4338 states and 5349 transitions. [2024-11-12 21:46:41,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:41,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4338 states and 5349 transitions. [2024-11-12 21:46:41,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4338 states and 5349 transitions. [2024-11-12 21:46:41,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4338 to 4338. [2024-11-12 21:46:41,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4338 states, 4338 states have (on average 1.2330567081604427) internal successors, (5349), 4337 states have internal predecessors, (5349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:42,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4338 states to 4338 states and 5349 transitions. [2024-11-12 21:46:42,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4338 states and 5349 transitions. [2024-11-12 21:46:42,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:42,013 INFO L426 stractBuchiCegarLoop]: Abstraction has 4338 states and 5349 transitions. [2024-11-12 21:46:42,013 INFO L333 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-12 21:46:42,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4338 states and 5349 transitions. [2024-11-12 21:46:42,040 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2820 [2024-11-12 21:46:42,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:42,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:42,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:42,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:42,044 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:46:42,044 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:46:42,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:42,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1015345778, now seen corresponding path program 1 times [2024-11-12 21:46:42,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:42,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779518078] [2024-11-12 21:46:42,049 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:42,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:42,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:42,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779518078] [2024-11-12 21:46:42,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779518078] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:42,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1964875449] [2024-11-12 21:46:42,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:42,083 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:42,086 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:42,090 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-12 21:46:42,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:42,138 INFO L256 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:42,139 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:42,150 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:42,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1964875449] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:42,156 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:42,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:42,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715482104] [2024-11-12 21:46:42,156 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:42,156 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-12 21:46:42,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:42,156 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 2 times [2024-11-12 21:46:42,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:42,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729259742] [2024-11-12 21:46:42,157 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:42,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,159 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:42,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:42,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:42,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:42,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:42,232 INFO L87 Difference]: Start difference. First operand 4338 states and 5349 transitions. cyclomatic complexity: 1021 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:42,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:42,262 INFO L93 Difference]: Finished difference Result 4290 states and 5291 transitions. [2024-11-12 21:46:42,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4290 states and 5291 transitions. [2024-11-12 21:46:42,287 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2820 [2024-11-12 21:46:42,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4290 states to 4290 states and 5291 transitions. [2024-11-12 21:46:42,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2881 [2024-11-12 21:46:42,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2881 [2024-11-12 21:46:42,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4290 states and 5291 transitions. [2024-11-12 21:46:42,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:42,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4290 states and 5291 transitions. [2024-11-12 21:46:42,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4290 states and 5291 transitions. [2024-11-12 21:46:42,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4290 to 4290. [2024-11-12 21:46:42,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4290 states, 4290 states have (on average 1.2333333333333334) internal successors, (5291), 4289 states have internal predecessors, (5291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:42,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4290 states to 4290 states and 5291 transitions. [2024-11-12 21:46:42,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4290 states and 5291 transitions. [2024-11-12 21:46:42,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:42,445 INFO L426 stractBuchiCegarLoop]: Abstraction has 4290 states and 5291 transitions. [2024-11-12 21:46:42,445 INFO L333 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-12 21:46:42,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4290 states and 5291 transitions. [2024-11-12 21:46:42,464 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2820 [2024-11-12 21:46:42,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:42,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:42,469 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:42,469 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:42,469 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:46:42,469 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2024-11-12 21:46:42,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:42,470 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2024-11-12 21:46:42,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:42,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487487321] [2024-11-12 21:46:42,470 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:42,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,482 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:42,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,498 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:42,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:42,499 INFO L85 PathProgramCache]: Analyzing trace with hash 2096165373, now seen corresponding path program 1 times [2024-11-12 21:46:42,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:42,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645796277] [2024-11-12 21:46:42,499 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:42,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,505 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:42,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:42,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:42,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:42,507 INFO L85 PathProgramCache]: Analyzing trace with hash -1967606800, now seen corresponding path program 1 times [2024-11-12 21:46:42,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:42,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395589041] [2024-11-12 21:46:42,507 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:42,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:42,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:42,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395589041] [2024-11-12 21:46:42,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395589041] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:42,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [559537093] [2024-11-12 21:46:42,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:42,549 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:42,550 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:42,551 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:42,552 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-12 21:46:42,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:42,604 INFO L256 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:42,604 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:42,688 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:42,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [559537093] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:42,771 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:42,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-12 21:46:42,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801751833] [2024-11-12 21:46:42,771 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:42,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:42,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:42,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:42,827 INFO L87 Difference]: Start difference. First operand 4290 states and 5291 transitions. cyclomatic complexity: 1011 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:42,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:42,905 INFO L93 Difference]: Finished difference Result 6430 states and 7885 transitions. [2024-11-12 21:46:42,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6430 states and 7885 transitions. [2024-11-12 21:46:42,921 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4240 [2024-11-12 21:46:42,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6430 states to 6430 states and 7885 transitions. [2024-11-12 21:46:42,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4309 [2024-11-12 21:46:42,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4309 [2024-11-12 21:46:42,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6430 states and 7885 transitions. [2024-11-12 21:46:42,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:42,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6430 states and 7885 transitions. [2024-11-12 21:46:42,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6430 states and 7885 transitions. [2024-11-12 21:46:43,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6430 to 6430. [2024-11-12 21:46:43,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6430 states, 6430 states have (on average 1.2262830482115086) internal successors, (7885), 6429 states have internal predecessors, (7885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:43,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6430 states to 6430 states and 7885 transitions. [2024-11-12 21:46:43,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6430 states and 7885 transitions. [2024-11-12 21:46:43,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:43,060 INFO L426 stractBuchiCegarLoop]: Abstraction has 6430 states and 7885 transitions. [2024-11-12 21:46:43,060 INFO L333 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-12 21:46:43,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6430 states and 7885 transitions. [2024-11-12 21:46:43,096 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4240 [2024-11-12 21:46:43,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:43,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:43,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:43,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:43,099 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:46:43,099 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2024-11-12 21:46:43,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,102 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2024-11-12 21:46:43,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530101458] [2024-11-12 21:46:43,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,111 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:43,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:43,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,127 INFO L85 PathProgramCache]: Analyzing trace with hash 71302111, now seen corresponding path program 1 times [2024-11-12 21:46:43,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560787445] [2024-11-12 21:46:43,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,132 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:43,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,134 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:43,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,137 INFO L85 PathProgramCache]: Analyzing trace with hash -1088484078, now seen corresponding path program 1 times [2024-11-12 21:46:43,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357670475] [2024-11-12 21:46:43,137 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:43,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-12 21:46:43,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357670475] [2024-11-12 21:46:43,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357670475] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-12 21:46:43,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1870439305] [2024-11-12 21:46:43,177 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,178 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-12 21:46:43,178 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-12 21:46:43,179 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-12 21:46:43,186 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-12 21:46:43,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-12 21:46:43,243 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-12 21:46:43,244 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-12 21:46:43,349 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-12 21:46:43,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1870439305] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-12 21:46:43,453 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-12 21:46:43,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-12 21:46:43,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699128244] [2024-11-12 21:46:43,453 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-12 21:46:43,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-12 21:46:43,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-12 21:46:43,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-12 21:46:43,510 INFO L87 Difference]: Start difference. First operand 6430 states and 7885 transitions. cyclomatic complexity: 1465 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:43,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-12 21:46:43,563 INFO L93 Difference]: Finished difference Result 8058 states and 9882 transitions. [2024-11-12 21:46:43,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8058 states and 9882 transitions. [2024-11-12 21:46:43,592 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5043 [2024-11-12 21:46:43,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8058 states to 8058 states and 9882 transitions. [2024-11-12 21:46:43,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5120 [2024-11-12 21:46:43,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5120 [2024-11-12 21:46:43,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8058 states and 9882 transitions. [2024-11-12 21:46:43,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-12 21:46:43,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8058 states and 9882 transitions. [2024-11-12 21:46:43,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8058 states and 9882 transitions. [2024-11-12 21:46:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8058 to 8058. [2024-11-12 21:46:43,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8058 states, 8058 states have (on average 1.2263588979895756) internal successors, (9882), 8057 states have internal predecessors, (9882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-12 21:46:43,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8058 states to 8058 states and 9882 transitions. [2024-11-12 21:46:43,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8058 states and 9882 transitions. [2024-11-12 21:46:43,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-12 21:46:43,703 INFO L426 stractBuchiCegarLoop]: Abstraction has 8058 states and 9882 transitions. [2024-11-12 21:46:43,704 INFO L333 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-12 21:46:43,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8058 states and 9882 transitions. [2024-11-12 21:46:43,761 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5043 [2024-11-12 21:46:43,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-12 21:46:43,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-12 21:46:43,761 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:43,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-12 21:46:43,762 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume !false;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-12 21:46:43,762 INFO L749 eck$LassoCheckResult]: Loop: "assume !false;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" [2024-11-12 21:46:43,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,766 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2024-11-12 21:46:43,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812815948] [2024-11-12 21:46:43,766 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,773 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:43,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:43,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,782 INFO L85 PathProgramCache]: Analyzing trace with hash -198166090, now seen corresponding path program 1 times [2024-11-12 21:46:43,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916375018] [2024-11-12 21:46:43,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,788 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:43,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:43,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-12 21:46:43,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1938803241, now seen corresponding path program 1 times [2024-11-12 21:46:43,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-12 21:46:43,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707646621] [2024-11-12 21:46:43,790 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-12 21:46:43,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-12 21:46:43,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,796 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:43,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:43,803 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-12 21:46:44,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:44,686 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-12 21:46:44,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-12 21:46:44,812 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 09:46:44 BoogieIcfgContainer [2024-11-12 21:46:44,812 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-12 21:46:44,812 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-12 21:46:44,812 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-12 21:46:44,813 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-12 21:46:44,813 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 09:46:33" (3/4) ... [2024-11-12 21:46:44,816 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-12 21:46:44,879 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-12 21:46:44,879 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-12 21:46:44,879 INFO L158 Benchmark]: Toolchain (without parser) took 12375.27ms. Allocated memory was 211.8MB in the beginning and 337.6MB in the end (delta: 125.8MB). Free memory was 143.2MB in the beginning and 144.8MB in the end (delta: -1.6MB). Peak memory consumption was 127.1MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,879 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 76.6MB in the beginning and 76.5MB in the end (delta: 118.9kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-12 21:46:44,880 INFO L158 Benchmark]: CACSL2BoogieTranslator took 344.90ms. Allocated memory is still 211.8MB. Free memory was 143.2MB in the beginning and 126.8MB in the end (delta: 16.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,880 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.71ms. Allocated memory is still 211.8MB. Free memory was 126.8MB in the beginning and 123.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,880 INFO L158 Benchmark]: Boogie Preprocessor took 89.89ms. Allocated memory is still 211.8MB. Free memory was 123.2MB in the beginning and 180.5MB in the end (delta: -57.3MB). Peak memory consumption was 9.1MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,880 INFO L158 Benchmark]: RCFGBuilder took 776.71ms. Allocated memory is still 211.8MB. Free memory was 180.5MB in the beginning and 138.6MB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,880 INFO L158 Benchmark]: BuchiAutomizer took 11044.69ms. Allocated memory was 211.8MB in the beginning and 337.6MB in the end (delta: 125.8MB). Free memory was 138.6MB in the beginning and 152.2MB in the end (delta: -13.6MB). Peak memory consumption was 113.8MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,881 INFO L158 Benchmark]: Witness Printer took 66.42ms. Allocated memory is still 337.6MB. Free memory was 152.2MB in the beginning and 144.8MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-12 21:46:44,882 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 76.6MB in the beginning and 76.5MB in the end (delta: 118.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 344.90ms. Allocated memory is still 211.8MB. Free memory was 143.2MB in the beginning and 126.8MB in the end (delta: 16.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.71ms. Allocated memory is still 211.8MB. Free memory was 126.8MB in the beginning and 123.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 89.89ms. Allocated memory is still 211.8MB. Free memory was 123.2MB in the beginning and 180.5MB in the end (delta: -57.3MB). Peak memory consumption was 9.1MB. Max. memory is 16.1GB. * RCFGBuilder took 776.71ms. Allocated memory is still 211.8MB. Free memory was 180.5MB in the beginning and 138.6MB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 11044.69ms. Allocated memory was 211.8MB in the beginning and 337.6MB in the end (delta: 125.8MB). Free memory was 138.6MB in the beginning and 152.2MB in the end (delta: -13.6MB). Peak memory consumption was 113.8MB. Max. memory is 16.1GB. * Witness Printer took 66.42ms. Allocated memory is still 337.6MB. Free memory was 152.2MB in the beginning and 144.8MB in the end (delta: 7.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (16 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 16 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 8058 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.9s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 7.6s. Construction of modules took 0.6s. Büchi inclusion checks took 2.1s. Highest rank in rank-based complementation 3. Minimization of det autom 11. Minimization of nondet autom 6. Automata minimization 0.7s AutomataMinimizationTime, 17 MinimizatonAttempts, 446 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6238 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6237 mSDsluCounter, 16758 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 9669 mSDsCounter, 215 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 818 IncrementalHoareTripleChecker+Invalid, 1033 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 215 mSolverCounterUnsat, 7089 mSDtfsCounter, 818 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc3 concLT1 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital86 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 23ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 3 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-12 21:46:44,907 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-11-12 21:46:45,107 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:45,307 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:45,510 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:45,711 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:45,911 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-11-12 21:46:46,116 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:46,317 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-12 21:46:46,520 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:46,721 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:46,924 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-12 21:46:47,126 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:47,328 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:47,528 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:47,724 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-12 21:46:47,924 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:48,125 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:48,328 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:48,528 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-12 21:46:48,729 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-12 21:46:48,935 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-12 21:46:49,133 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)