./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:12:34,328 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:12:34,404 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-11-13 13:12:34,409 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:12:34,409 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:12:34,448 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:12:34,449 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:12:34,450 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:12:34,450 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:12:34,451 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:12:34,451 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:12:34,452 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:12:34,452 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:12:34,453 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:12:34,453 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:12:34,453 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:12:34,454 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:12:34,454 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:12:34,455 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:12:34,455 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:12:34,456 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:12:34,456 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:12:34,456 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:12:34,456 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:12:34,457 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2024-11-13 13:12:34,788 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:12:34,802 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:12:34,805 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:12:34,807 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:12:34,807 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:12:34,808 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c Unable to find full path for "g++" [2024-11-13 13:12:36,738 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:12:36,969 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:12:36,970 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2024-11-13 13:12:36,977 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/data/ae97d4061/47b98b30c9d54acea1a8a56be96f70bf/FLAG5382b5011 [2024-11-13 13:12:37,008 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/data/ae97d4061/47b98b30c9d54acea1a8a56be96f70bf [2024-11-13 13:12:37,011 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:12:37,014 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:12:37,017 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:12:37,017 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:12:37,023 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:12:37,025 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,028 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@21fda86d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37, skipping insertion in model container [2024-11-13 13:12:37,029 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,045 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:12:37,232 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:12:37,239 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:12:37,252 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:12:37,270 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:12:37,270 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37 WrapperNode [2024-11-13 13:12:37,271 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:12:37,272 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:12:37,272 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:12:37,273 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:12:37,283 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,287 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,303 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 18 [2024-11-13 13:12:37,305 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:12:37,306 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:12:37,307 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:12:37,307 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:12:37,316 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,317 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,318 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,324 INFO L175 MemorySlicer]: No memory access in input program. [2024-11-13 13:12:37,324 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,324 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,327 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,332 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,333 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,334 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,339 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:12:37,340 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:12:37,340 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:12:37,340 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:12:37,341 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (1/1) ... [2024-11-13 13:12:37,351 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:37,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:37,389 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:37,391 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:12:37,414 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:12:37,414 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:12:37,480 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:12:37,483 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:12:37,552 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2024-11-13 13:12:37,552 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:12:37,561 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:12:37,562 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-13 13:12:37,562 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:12:37 BoogieIcfgContainer [2024-11-13 13:12:37,562 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:12:37,563 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:12:37,564 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:12:37,569 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:12:37,571 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:12:37,572 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:12:37" (1/3) ... [2024-11-13 13:12:37,573 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@410d2374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:12:37, skipping insertion in model container [2024-11-13 13:12:37,573 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:12:37,573 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:12:37" (2/3) ... [2024-11-13 13:12:37,573 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@410d2374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:12:37, skipping insertion in model container [2024-11-13 13:12:37,573 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:12:37,574 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:12:37" (3/3) ... [2024-11-13 13:12:37,576 INFO L333 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2024-11-13 13:12:37,662 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:12:37,662 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:12:37,662 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:12:37,663 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:12:37,663 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:12:37,663 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:12:37,664 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:12:37,664 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:12:37,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:37,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-13 13:12:37,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:37,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:37,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-13 13:12:37,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:37,698 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:12:37,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:37,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-13 13:12:37,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:37,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:37,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-13 13:12:37,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:37,710 INFO L745 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2024-11-13 13:12:37,711 INFO L747 eck$LassoCheckResult]: Loop: 3#L12-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2024-11-13 13:12:37,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:37,718 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-11-13 13:12:37,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:37,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818279295] [2024-11-13 13:12:37,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:37,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:37,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:37,821 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:37,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:37,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:37,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:37,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 1 times [2024-11-13 13:12:37,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:37,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279354213] [2024-11-13 13:12:37,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:37,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:37,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:37,866 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:37,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:37,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:37,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:37,879 INFO L85 PathProgramCache]: Analyzing trace with hash 925774, now seen corresponding path program 1 times [2024-11-13 13:12:37,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:37,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85363481] [2024-11-13 13:12:37,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:37,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:37,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:38,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:38,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:38,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85363481] [2024-11-13 13:12:38,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85363481] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:12:38,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:12:38,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:12:38,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79326178] [2024-11-13 13:12:38,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:12:38,093 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:38,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:12:38,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:12:38,133 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:38,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:38,194 INFO L93 Difference]: Finished difference Result 12 states and 16 transitions. [2024-11-13 13:12:38,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 16 transitions. [2024-11-13 13:12:38,196 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:38,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 8 states and 11 transitions. [2024-11-13 13:12:38,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-13 13:12:38,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-13 13:12:38,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 11 transitions. [2024-11-13 13:12:38,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:12:38,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-11-13 13:12:38,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 11 transitions. [2024-11-13 13:12:38,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2024-11-13 13:12:38,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.375) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:38,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 11 transitions. [2024-11-13 13:12:38,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-11-13 13:12:38,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:12:38,242 INFO L424 stractBuchiCegarLoop]: Abstraction has 8 states and 11 transitions. [2024-11-13 13:12:38,242 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:12:38,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 11 transitions. [2024-11-13 13:12:38,243 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:38,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:38,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:38,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-13 13:12:38,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-13 13:12:38,244 INFO L745 eck$LassoCheckResult]: Stem: 35#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 36#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 37#L12-1 [2024-11-13 13:12:38,244 INFO L747 eck$LassoCheckResult]: Loop: 37#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 38#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 39#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 37#L12-1 [2024-11-13 13:12:38,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:38,245 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2024-11-13 13:12:38,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:38,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320424585] [2024-11-13 13:12:38,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:38,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:38,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,250 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:38,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:38,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:38,253 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 1 times [2024-11-13 13:12:38,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:38,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748092214] [2024-11-13 13:12:38,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:38,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:38,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,262 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:38,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,268 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:38,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:38,271 INFO L85 PathProgramCache]: Analyzing trace with hash 28698764, now seen corresponding path program 1 times [2024-11-13 13:12:38,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:38,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206162853] [2024-11-13 13:12:38,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:38,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:38,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,289 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:38,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:38,296 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:38,371 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:38,371 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:38,371 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:38,372 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:38,372 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:12:38,372 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,372 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:38,372 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:38,372 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-11-13 13:12:38,372 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:38,373 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:38,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,574 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:38,575 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:12:38,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:38,583 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:38,586 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 13:12:38,587 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:38,587 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:38,618 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:12:38,619 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:12:38,638 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 13:12:38,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:38,640 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:38,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 13:12:38,644 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:38,644 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:38,669 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:12:38,669 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:12:38,687 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:38,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,687 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:38,689 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:38,691 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 13:12:38,692 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:38,693 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:38,735 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 13:12:38,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,735 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:38,738 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:38,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 13:12:38,741 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:12:38,742 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:38,824 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:12:38,828 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 13:12:38,828 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:38,828 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:38,829 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:38,829 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:38,829 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:12:38,829 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,829 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:38,829 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:38,829 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-11-13 13:12:38,829 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:38,829 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:38,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:38,993 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:38,998 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:12:38,999 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:38,999 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:39,001 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:39,003 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 13:12:39,005 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:39,021 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:39,021 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:39,022 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:39,022 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:39,029 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-13 13:12:39,030 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-13 13:12:39,036 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:12:39,054 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:39,054 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:39,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:39,057 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:39,059 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 13:12:39,060 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:39,074 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:39,075 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:39,075 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:39,075 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:39,078 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-13 13:12:39,078 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-13 13:12:39,085 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:12:39,103 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 13:12:39,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:39,103 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:39,105 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:39,107 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 13:12:39,108 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:39,123 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:39,123 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:12:39,123 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:39,123 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:39,123 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:39,125 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:12:39,125 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:12:39,129 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:12:39,133 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:12:39,136 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:12:39,137 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:39,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:39,140 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:39,142 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 13:12:39,142 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:12:39,143 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:12:39,143 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:12:39,143 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-11-13 13:12:39,162 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:39,166 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:12:39,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:39,209 INFO L255 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:39,210 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:39,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:39,223 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-13 13:12:39,223 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:39,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:39,269 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-13 13:12:39,270 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:39,338 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 15 transitions. Complement of second has 5 states. [2024-11-13 13:12:39,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:39,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:39,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 5 transitions. [2024-11-13 13:12:39,349 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 3 letters. [2024-11-13 13:12:39,350 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:39,350 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 5 letters. Loop has 3 letters. [2024-11-13 13:12:39,351 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:39,351 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 6 letters. [2024-11-13 13:12:39,351 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:39,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 15 transitions. [2024-11-13 13:12:39,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-13 13:12:39,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 15 transitions. [2024-11-13 13:12:39,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-11-13 13:12:39,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-13 13:12:39,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 15 transitions. [2024-11-13 13:12:39,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:39,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-11-13 13:12:39,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 15 transitions. [2024-11-13 13:12:39,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2024-11-13 13:12:39,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:39,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2024-11-13 13:12:39,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-11-13 13:12:39,358 INFO L424 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2024-11-13 13:12:39,358 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:12:39,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2024-11-13 13:12:39,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-13 13:12:39,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:39,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:39,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2024-11-13 13:12:39,359 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:39,360 INFO L745 eck$LassoCheckResult]: Stem: 93#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 94#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 95#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 90#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 91#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 86#L12-1 [2024-11-13 13:12:39,360 INFO L747 eck$LassoCheckResult]: Loop: 86#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 87#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 86#L12-1 [2024-11-13 13:12:39,360 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,360 INFO L85 PathProgramCache]: Analyzing trace with hash 28698762, now seen corresponding path program 1 times [2024-11-13 13:12:39,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619410084] [2024-11-13 13:12:39,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,368 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:39,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,373 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:39,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 2 times [2024-11-13 13:12:39,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463270446] [2024-11-13 13:12:39,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,378 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:39,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:39,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1809706837, now seen corresponding path program 1 times [2024-11-13 13:12:39,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580304362] [2024-11-13 13:12:39,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:39,483 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:39,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:39,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580304362] [2024-11-13 13:12:39,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580304362] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:39,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [905594775] [2024-11-13 13:12:39,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,484 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:39,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:39,486 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:39,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-13 13:12:39,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:39,543 INFO L255 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 13:12:39,544 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:39,643 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:39,643 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:39,680 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:39,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [905594775] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:39,681 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:39,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-13 13:12:39,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753600669] [2024-11-13 13:12:39,681 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:39,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:39,707 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-13 13:12:39,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-11-13 13:12:39,707 INFO L87 Difference]: Start difference. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:39,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:39,775 INFO L93 Difference]: Finished difference Result 23 states and 28 transitions. [2024-11-13 13:12:39,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 28 transitions. [2024-11-13 13:12:39,776 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:39,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 28 transitions. [2024-11-13 13:12:39,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2024-11-13 13:12:39,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2024-11-13 13:12:39,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 28 transitions. [2024-11-13 13:12:39,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:39,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-11-13 13:12:39,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 28 transitions. [2024-11-13 13:12:39,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2024-11-13 13:12:39,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 22 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:39,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 28 transitions. [2024-11-13 13:12:39,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-11-13 13:12:39,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-13 13:12:39,784 INFO L424 stractBuchiCegarLoop]: Abstraction has 23 states and 28 transitions. [2024-11-13 13:12:39,785 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:12:39,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 28 transitions. [2024-11-13 13:12:39,785 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:39,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:39,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:39,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1] [2024-11-13 13:12:39,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-13 13:12:39,786 INFO L745 eck$LassoCheckResult]: Stem: 178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 181#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 170#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 171#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 184#L12-1 [2024-11-13 13:12:39,786 INFO L747 eck$LassoCheckResult]: Loop: 184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 189#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 184#L12-1 [2024-11-13 13:12:39,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1637078698, now seen corresponding path program 1 times [2024-11-13 13:12:39,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044539076] [2024-11-13 13:12:39,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:39,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,825 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:39,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,826 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 2 times [2024-11-13 13:12:39,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848958827] [2024-11-13 13:12:39,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,837 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:39,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:39,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:39,846 INFO L85 PathProgramCache]: Analyzing trace with hash 857856069, now seen corresponding path program 2 times [2024-11-13 13:12:39,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:39,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023156149] [2024-11-13 13:12:39,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:39,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:39,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,867 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:39,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:39,880 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:39,941 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:39,941 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:39,941 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:39,941 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:39,941 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:12:39,941 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:39,941 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:39,942 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:39,942 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-11-13 13:12:39,942 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:39,942 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:39,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:39,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:39,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,034 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:40,034 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:12:40,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,034 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,038 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,039 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 13:12:40,041 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:40,041 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,068 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:12:40,068 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:12:40,086 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 13:12:40,086 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,086 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,089 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 13:12:40,092 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:40,092 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,117 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:12:40,117 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:12:40,135 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 13:12:40,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,136 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,138 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,140 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 13:12:40,144 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:40,144 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,180 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 13:12:40,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,183 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 13:12:40,185 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:12:40,186 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,258 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:12:40,263 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-13 13:12:40,264 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:40,264 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:40,264 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:40,264 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:40,264 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:12:40,264 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,264 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:40,264 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:40,264 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-11-13 13:12:40,264 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:40,264 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:40,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,359 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:40,359 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:12:40,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,359 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,361 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,363 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 13:12:40,364 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:40,378 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:40,378 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:40,378 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:40,379 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:40,382 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-13 13:12:40,382 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-13 13:12:40,388 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 13:12:40,406 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:40,406 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,406 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,408 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 13:12:40,411 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:40,424 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:40,424 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:12:40,424 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:40,424 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:40,424 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:40,425 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:12:40,425 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:12:40,428 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:12:40,433 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:12:40,433 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 13:12:40,433 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,436 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 13:12:40,441 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:12:40,441 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:12:40,441 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:12:40,441 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-11-13 13:12:40,454 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:40,456 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:12:40,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:40,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:40,493 INFO L255 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:40,494 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:40,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:40,516 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-13 13:12:40,517 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:40,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:40,543 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-13 13:12:40,543 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:40,570 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 50 transitions. Complement of second has 5 states. [2024-11-13 13:12:40,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:40,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:40,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-11-13 13:12:40,572 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 3 letters. [2024-11-13 13:12:40,572 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:40,573 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-11-13 13:12:40,573 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:40,573 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 6 letters. [2024-11-13 13:12:40,573 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:40,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 50 transitions. [2024-11-13 13:12:40,575 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:40,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 38 states and 44 transitions. [2024-11-13 13:12:40,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-13 13:12:40,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2024-11-13 13:12:40,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 44 transitions. [2024-11-13 13:12:40,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:40,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 44 transitions. [2024-11-13 13:12:40,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 44 transitions. [2024-11-13 13:12:40,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2024-11-13 13:12:40,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:40,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2024-11-13 13:12:40,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2024-11-13 13:12:40,580 INFO L424 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2024-11-13 13:12:40,580 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:12:40,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2024-11-13 13:12:40,581 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-13 13:12:40,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:40,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:40,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1] [2024-11-13 13:12:40,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-13 13:12:40,583 INFO L745 eck$LassoCheckResult]: Stem: 308#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 309#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 310#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 311#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 299#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 305#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 321#L12-1 [2024-11-13 13:12:40,583 INFO L747 eck$LassoCheckResult]: Loop: 321#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 326#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 321#L12-1 [2024-11-13 13:12:40,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:40,583 INFO L85 PathProgramCache]: Analyzing trace with hash -1310178303, now seen corresponding path program 3 times [2024-11-13 13:12:40,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:40,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586711595] [2024-11-13 13:12:40,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:40,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:40,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,595 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:40,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:40,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:40,605 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 3 times [2024-11-13 13:12:40,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:40,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171787211] [2024-11-13 13:12:40,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:40,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:40,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:40,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:40,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:40,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1140971406, now seen corresponding path program 4 times [2024-11-13 13:12:40,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:40,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899545312] [2024-11-13 13:12:40,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:40,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:40,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:40,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:40,639 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:40,697 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:40,697 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:40,697 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:40,697 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:40,697 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:12:40,697 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,697 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:40,697 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:40,698 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-11-13 13:12:40,698 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:40,698 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:40,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:40,795 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:40,835 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 13:12:40,860 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:40,860 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:12:40,860 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,860 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,864 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,866 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 13:12:40,867 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:40,867 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,889 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 13:12:40,889 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 13:12:40,901 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 13:12:40,902 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,902 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,904 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,905 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 13:12:40,906 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:40,906 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:40,933 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 13:12:40,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:40,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:40,935 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:40,936 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 13:12:40,937 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:12:40,937 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:41,012 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:12:41,015 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 13:12:41,015 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:41,015 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:41,016 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:41,016 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:41,016 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:12:41,016 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:41,016 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:41,016 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:41,016 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-11-13 13:12:41,016 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:41,016 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:41,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:41,031 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:41,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:41,101 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:41,101 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:12:41,102 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:41,102 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:41,104 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:41,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 13:12:41,107 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:41,122 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:41,123 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:12:41,123 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:41,123 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:41,123 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:41,124 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:12:41,124 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:12:41,127 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:12:41,132 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:12:41,132 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-11-13 13:12:41,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:41,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:41,138 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:41,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 13:12:41,145 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:12:41,145 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:12:41,145 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:12:41,145 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-11-13 13:12:41,162 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2024-11-13 13:12:41,164 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:12:41,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:41,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,201 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,202 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,243 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,244 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,270 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-13 13:12:41,270 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,295 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2024-11-13 13:12:41,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:41,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-11-13 13:12:41,300 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-11-13 13:12:41,300 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:41,300 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-11-13 13:12:41,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:41,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,340 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,341 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,375 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,376 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,403 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-13 13:12:41,404 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,431 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2024-11-13 13:12:41,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:41,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2024-11-13 13:12:41,433 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2024-11-13 13:12:41,433 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:41,433 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-11-13 13:12:41,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:41,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,459 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,460 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,489 WARN L253 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,489 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,514 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-13 13:12:41,515 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,546 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 69 transitions. Complement of second has 4 states. [2024-11-13 13:12:41,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:41,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2024-11-13 13:12:41,548 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 3 letters. [2024-11-13 13:12:41,548 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:41,548 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 17 letters. Loop has 3 letters. [2024-11-13 13:12:41,548 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:41,549 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 6 letters. [2024-11-13 13:12:41,549 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:41,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2024-11-13 13:12:41,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2024-11-13 13:12:41,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 47 states and 58 transitions. [2024-11-13 13:12:41,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-13 13:12:41,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2024-11-13 13:12:41,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2024-11-13 13:12:41,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:41,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2024-11-13 13:12:41,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2024-11-13 13:12:41,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 31. [2024-11-13 13:12:41,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:41,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2024-11-13 13:12:41,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2024-11-13 13:12:41,555 INFO L424 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2024-11-13 13:12:41,555 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:12:41,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2024-11-13 13:12:41,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2024-11-13 13:12:41,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:41,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:41,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1, 1] [2024-11-13 13:12:41,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2024-11-13 13:12:41,557 INFO L745 eck$LassoCheckResult]: Stem: 669#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 671#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 664#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 690#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 660#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 661#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 665#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 666#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 668#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 688#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 684#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 681#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 680#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 678#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 676#L12-1 [2024-11-13 13:12:41,557 INFO L747 eck$LassoCheckResult]: Loop: 676#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 677#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 686#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 683#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 685#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 682#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 676#L12-1 [2024-11-13 13:12:41,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:41,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1334690828, now seen corresponding path program 5 times [2024-11-13 13:12:41,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:41,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124061555] [2024-11-13 13:12:41,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:41,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:41,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:41,663 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:41,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124061555] [2024-11-13 13:12:41,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124061555] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:41,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [560172998] [2024-11-13 13:12:41,663 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-13 13:12:41,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:41,664 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:41,666 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:41,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-13 13:12:41,719 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-11-13 13:12:41,720 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:41,724 INFO L255 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-13 13:12:41,725 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:41,823 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,823 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:41,904 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:41,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [560172998] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:41,904 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:41,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-11-13 13:12:41,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178080426] [2024-11-13 13:12:41,904 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:41,905 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:41,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:41,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1186287651, now seen corresponding path program 1 times [2024-11-13 13:12:41,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:41,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284813341] [2024-11-13 13:12:41,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:41,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:41,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:41,921 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:41,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:41,929 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:42,002 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:42,002 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:42,002 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:42,002 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:42,002 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 13:12:42,003 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,003 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:42,003 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:42,003 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-11-13 13:12:42,003 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:42,003 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:42,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,116 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:42,116 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 13:12:42,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,116 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:42,120 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:42,123 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 13:12:42,124 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:42,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 13:12:42,158 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-13 13:12:42,158 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,158 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:42,161 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:42,163 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 13:12:42,164 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 13:12:42,164 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 13:12:42,235 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 13:12:42,294 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 13:12:42,297 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 13:12:42,297 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 13:12:42,297 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 13:12:42,298 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 13:12:42,298 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 13:12:42,298 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 13:12:42,298 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,298 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 13:12:42,298 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 13:12:42,298 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-11-13 13:12:42,298 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 13:12:42,298 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 13:12:42,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,316 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 13:12:42,411 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 13:12:42,411 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 13:12:42,411 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:42,414 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:42,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 13:12:42,416 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 13:12:42,433 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 13:12:42,433 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 13:12:42,434 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 13:12:42,434 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 13:12:42,434 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 13:12:42,439 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 13:12:42,440 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 13:12:42,444 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 13:12:42,448 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 13:12:42,448 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-11-13 13:12:42,449 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:12:42,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:42,451 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:12:42,454 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 13:12:42,455 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 13:12:42,455 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 13:12:42,455 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 13:12:42,456 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-11-13 13:12:42,474 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-13 13:12:42,475 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 13:12:42,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:42,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:42,510 INFO L255 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 13:12:42,510 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:42,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:42,551 INFO L255 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-13 13:12:42,552 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:42,614 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:12:42,614 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 13:12:42,615 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:42,652 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 72 states and 96 transitions. Complement of second has 6 states. [2024-11-13 13:12:42,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2024-11-13 13:12:42,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:42,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 15 transitions. [2024-11-13 13:12:42,657 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 6 letters. [2024-11-13 13:12:42,657 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:42,657 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 23 letters. Loop has 6 letters. [2024-11-13 13:12:42,657 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:42,657 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 15 transitions. Stem has 17 letters. Loop has 12 letters. [2024-11-13 13:12:42,657 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 13:12:42,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 96 transitions. [2024-11-13 13:12:42,662 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:42,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 55 states and 73 transitions. [2024-11-13 13:12:42,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2024-11-13 13:12:42,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2024-11-13 13:12:42,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 73 transitions. [2024-11-13 13:12:42,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:42,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 73 transitions. [2024-11-13 13:12:42,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 73 transitions. [2024-11-13 13:12:42,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 47. [2024-11-13 13:12:42,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.3404255319148937) internal successors, (63), 46 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:42,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 63 transitions. [2024-11-13 13:12:42,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 63 transitions. [2024-11-13 13:12:42,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:42,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-13 13:12:42,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2024-11-13 13:12:42,676 INFO L87 Difference]: Start difference. First operand 47 states and 63 transitions. Second operand has 13 states, 13 states have (on average 3.076923076923077) internal successors, (40), 13 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:42,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:42,801 INFO L93 Difference]: Finished difference Result 89 states and 105 transitions. [2024-11-13 13:12:42,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 105 transitions. [2024-11-13 13:12:42,802 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:42,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 75 states and 91 transitions. [2024-11-13 13:12:42,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-11-13 13:12:42,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-11-13 13:12:42,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 91 transitions. [2024-11-13 13:12:42,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:42,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 91 transitions. [2024-11-13 13:12:42,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 91 transitions. [2024-11-13 13:12:42,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 71. [2024-11-13 13:12:42,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.2253521126760563) internal successors, (87), 70 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:42,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 87 transitions. [2024-11-13 13:12:42,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71 states and 87 transitions. [2024-11-13 13:12:42,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-13 13:12:42,810 INFO L424 stractBuchiCegarLoop]: Abstraction has 71 states and 87 transitions. [2024-11-13 13:12:42,810 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:12:42,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 87 transitions. [2024-11-13 13:12:42,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:42,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:42,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:42,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1, 1] [2024-11-13 13:12:42,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:42,815 INFO L745 eck$LassoCheckResult]: Stem: 1109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1144#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1142#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1117#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1158#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1154#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1153#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1152#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1150#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1149#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1148#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1139#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1138#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1137#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1162#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1121#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1120#L12 [2024-11-13 13:12:42,815 INFO L747 eck$LassoCheckResult]: Loop: 1120#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1119#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1120#L12 [2024-11-13 13:12:42,815 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:42,817 INFO L85 PathProgramCache]: Analyzing trace with hash 950657182, now seen corresponding path program 6 times [2024-11-13 13:12:42,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:42,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858143036] [2024-11-13 13:12:42,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:42,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:42,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:43,143 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-13 13:12:43,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:43,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858143036] [2024-11-13 13:12:43,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858143036] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:43,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2107577444] [2024-11-13 13:12:43,144 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-13 13:12:43,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:43,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:43,147 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:43,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-13 13:12:43,209 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2024-11-13 13:12:43,209 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:43,210 INFO L255 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-11-13 13:12:43,212 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:43,438 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 13:12:43,469 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-13 13:12:43,470 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:43,694 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-13 13:12:43,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2107577444] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:43,696 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:43,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2024-11-13 13:12:43,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122418465] [2024-11-13 13:12:43,696 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:43,697 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:43,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:43,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 3 times [2024-11-13 13:12:43,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:43,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891881191] [2024-11-13 13:12:43,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:43,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:43,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:43,706 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:43,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:43,710 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:43,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:43,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-13 13:12:43,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2024-11-13 13:12:43,733 INFO L87 Difference]: Start difference. First operand 71 states and 87 transitions. cyclomatic complexity: 22 Second operand has 25 states, 25 states have (on average 3.04) internal successors, (76), 25 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:44,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:44,024 INFO L93 Difference]: Finished difference Result 151 states and 167 transitions. [2024-11-13 13:12:44,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 167 transitions. [2024-11-13 13:12:44,027 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:44,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 123 states and 139 transitions. [2024-11-13 13:12:44,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-11-13 13:12:44,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-11-13 13:12:44,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 139 transitions. [2024-11-13 13:12:44,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:44,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 139 transitions. [2024-11-13 13:12:44,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 139 transitions. [2024-11-13 13:12:44,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2024-11-13 13:12:44,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 119 states have (on average 1.134453781512605) internal successors, (135), 118 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:44,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 135 transitions. [2024-11-13 13:12:44,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119 states and 135 transitions. [2024-11-13 13:12:44,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-11-13 13:12:44,047 INFO L424 stractBuchiCegarLoop]: Abstraction has 119 states and 135 transitions. [2024-11-13 13:12:44,047 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:12:44,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 135 transitions. [2024-11-13 13:12:44,048 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:44,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:44,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:44,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 21, 2, 1, 1] [2024-11-13 13:12:44,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:44,051 INFO L745 eck$LassoCheckResult]: Stem: 1583#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1584#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1580#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1581#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1634#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1670#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1669#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1668#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1666#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1664#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1663#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1662#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1661#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1660#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1659#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1658#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1657#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1656#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1655#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1654#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1653#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1652#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1651#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1650#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1649#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1648#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1647#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1646#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1645#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1644#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1643#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1642#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1641#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1640#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1639#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1638#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1637#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1636#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1610#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1608#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1607#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1589#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1633#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1632#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1631#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1630#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1629#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1628#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1627#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1625#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1624#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1623#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1622#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1621#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1620#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1618#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1619#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1615#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1612#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1592#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1593#L12 [2024-11-13 13:12:44,051 INFO L747 eck$LassoCheckResult]: Loop: 1593#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1595#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1593#L12 [2024-11-13 13:12:44,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:44,051 INFO L85 PathProgramCache]: Analyzing trace with hash -582136098, now seen corresponding path program 7 times [2024-11-13 13:12:44,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:44,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108748125] [2024-11-13 13:12:44,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:44,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:44,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:44,748 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-11-13 13:12:44,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:44,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108748125] [2024-11-13 13:12:44,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108748125] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:44,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1473679528] [2024-11-13 13:12:44,749 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-13 13:12:44,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:44,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:44,752 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:44,755 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-13 13:12:44,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:44,827 INFO L255 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-13 13:12:44,830 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:45,341 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-11-13 13:12:45,341 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:45,766 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-11-13 13:12:45,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1473679528] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:45,767 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:45,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2024-11-13 13:12:45,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316225166] [2024-11-13 13:12:45,767 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:45,768 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:45,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:45,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 4 times [2024-11-13 13:12:45,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:45,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407086457] [2024-11-13 13:12:45,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:45,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:45,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:45,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:45,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:45,779 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:45,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:45,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-11-13 13:12:45,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2024-11-13 13:12:45,811 INFO L87 Difference]: Start difference. First operand 119 states and 135 transitions. cyclomatic complexity: 22 Second operand has 38 states, 38 states have (on average 3.0526315789473686) internal successors, (116), 38 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:46,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:46,147 INFO L93 Difference]: Finished difference Result 220 states and 236 transitions. [2024-11-13 13:12:46,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220 states and 236 transitions. [2024-11-13 13:12:46,149 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:46,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220 states to 186 states and 202 transitions. [2024-11-13 13:12:46,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2024-11-13 13:12:46,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2024-11-13 13:12:46,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 202 transitions. [2024-11-13 13:12:46,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:46,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 202 transitions. [2024-11-13 13:12:46,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 202 transitions. [2024-11-13 13:12:46,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 182. [2024-11-13 13:12:46,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.0879120879120878) internal successors, (198), 181 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:46,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 198 transitions. [2024-11-13 13:12:46,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 198 transitions. [2024-11-13 13:12:46,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-11-13 13:12:46,169 INFO L424 stractBuchiCegarLoop]: Abstraction has 182 states and 198 transitions. [2024-11-13 13:12:46,169 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:12:46,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 198 transitions. [2024-11-13 13:12:46,171 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2024-11-13 13:12:46,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:46,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:46,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 34, 2, 1, 1] [2024-11-13 13:12:46,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:46,174 INFO L745 eck$LassoCheckResult]: Stem: 2397#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2524#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2395#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2514#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2492#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2491#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2479#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2473#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2424#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2422#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2403#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2456#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2451#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2406#L12 [2024-11-13 13:12:46,175 INFO L747 eck$LassoCheckResult]: Loop: 2406#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2406#L12 [2024-11-13 13:12:46,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:46,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1682834915, now seen corresponding path program 8 times [2024-11-13 13:12:46,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:46,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465325261] [2024-11-13 13:12:46,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:46,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:46,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:46,213 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:46,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:46,255 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:46,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:46,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 5 times [2024-11-13 13:12:46,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:46,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424413502] [2024-11-13 13:12:46,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:46,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:46,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:46,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:46,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:46,264 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:46,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:46,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1998316616, now seen corresponding path program 1 times [2024-11-13 13:12:46,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:46,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827913506] [2024-11-13 13:12:46,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:46,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:46,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:46,363 INFO L134 CoverageAnalysis]: Checked inductivity of 1999 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 1820 trivial. 0 not checked. [2024-11-13 13:12:46,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:46,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827913506] [2024-11-13 13:12:46,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827913506] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:12:46,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:12:46,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:12:46,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817585724] [2024-11-13 13:12:46,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:12:46,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:46,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:12:46,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:12:46,384 INFO L87 Difference]: Start difference. First operand 182 states and 198 transitions. cyclomatic complexity: 22 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:46,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:46,404 INFO L93 Difference]: Finished difference Result 180 states and 192 transitions. [2024-11-13 13:12:46,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 192 transitions. [2024-11-13 13:12:46,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:46,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 132 states and 140 transitions. [2024-11-13 13:12:46,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2024-11-13 13:12:46,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-11-13 13:12:46,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 140 transitions. [2024-11-13 13:12:46,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:46,407 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 140 transitions. [2024-11-13 13:12:46,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 140 transitions. [2024-11-13 13:12:46,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 129. [2024-11-13 13:12:46,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.062015503875969) internal successors, (137), 128 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:46,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 137 transitions. [2024-11-13 13:12:46,413 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 137 transitions. [2024-11-13 13:12:46,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:12:46,414 INFO L424 stractBuchiCegarLoop]: Abstraction has 129 states and 137 transitions. [2024-11-13 13:12:46,414 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:12:46,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 137 transitions. [2024-11-13 13:12:46,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:46,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:46,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:46,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 37, 34, 3, 1, 1, 1] [2024-11-13 13:12:46,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:46,418 INFO L745 eck$LassoCheckResult]: Stem: 2767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2769#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2772#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2773#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2784#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2785#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2765#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2761#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2762#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2888#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2887#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2886#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2885#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2884#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2882#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2881#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2879#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2878#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2877#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2876#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2875#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2874#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2873#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2872#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2870#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2869#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2867#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2866#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2865#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2863#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2861#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2860#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2859#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2858#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2857#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2856#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2855#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2854#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2853#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2852#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2851#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2849#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2848#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2847#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2845#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2844#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2843#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2842#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2841#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2839#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2837#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2838#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2836#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2835#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2834#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2833#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2832#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2831#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2830#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2829#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2828#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2827#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2826#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2825#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2824#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2823#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2822#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2821#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2820#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2819#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2818#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2817#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2816#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2815#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2814#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2813#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2812#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2811#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2810#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2809#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2808#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2807#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2806#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2805#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2804#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2803#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2802#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2801#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2800#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2799#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2798#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2797#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2796#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2795#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2794#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2793#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2792#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2791#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2790#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2789#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2788#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2783#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2782#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2778#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2774#L12-1 [2024-11-13 13:12:46,418 INFO L747 eck$LassoCheckResult]: Loop: 2774#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2775#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2774#L12-1 [2024-11-13 13:12:46,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:46,419 INFO L85 PathProgramCache]: Analyzing trace with hash -532118895, now seen corresponding path program 2 times [2024-11-13 13:12:46,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:46,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915945707] [2024-11-13 13:12:46,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:46,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:46,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:47,061 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-11-13 13:12:47,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:47,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915945707] [2024-11-13 13:12:47,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915945707] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:47,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [492027239] [2024-11-13 13:12:47,062 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-13 13:12:47,062 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:47,062 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:47,066 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:47,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-13 13:12:47,139 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-13 13:12:47,139 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:47,144 INFO L255 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-13 13:12:47,147 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:47,802 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-11-13 13:12:47,802 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:48,358 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2024-11-13 13:12:48,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [492027239] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:48,358 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:48,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2024-11-13 13:12:48,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139917086] [2024-11-13 13:12:48,359 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:48,361 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:48,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:48,361 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 6 times [2024-11-13 13:12:48,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:48,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134157581] [2024-11-13 13:12:48,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:48,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:48,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:48,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:48,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:48,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:48,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:48,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2024-11-13 13:12:48,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2024-11-13 13:12:48,389 INFO L87 Difference]: Start difference. First operand 129 states and 137 transitions. cyclomatic complexity: 12 Second operand has 40 states, 40 states have (on average 3.075) internal successors, (123), 40 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:49,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:49,689 INFO L93 Difference]: Finished difference Result 319 states and 329 transitions. [2024-11-13 13:12:49,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 329 transitions. [2024-11-13 13:12:49,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:49,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 251 states and 261 transitions. [2024-11-13 13:12:49,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2024-11-13 13:12:49,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-11-13 13:12:49,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 251 states and 261 transitions. [2024-11-13 13:12:49,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:49,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 251 states and 261 transitions. [2024-11-13 13:12:49,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states and 261 transitions. [2024-11-13 13:12:49,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 243. [2024-11-13 13:12:49,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 243 states, 243 states have (on average 1.0411522633744856) internal successors, (253), 242 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:49,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 253 transitions. [2024-11-13 13:12:49,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 243 states and 253 transitions. [2024-11-13 13:12:49,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2024-11-13 13:12:49,706 INFO L424 stractBuchiCegarLoop]: Abstraction has 243 states and 253 transitions. [2024-11-13 13:12:49,706 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:12:49,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243 states and 253 transitions. [2024-11-13 13:12:49,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:49,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:49,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:49,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 75, 70, 5, 1, 1, 1] [2024-11-13 13:12:49,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:49,712 INFO L745 eck$LassoCheckResult]: Stem: 4018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 4019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 4020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4024#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4037#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4016#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4012#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4220#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4208#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4199#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4142#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4112#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4109#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4098#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4097#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4093#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4092#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4089#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4088#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4087#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4085#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4084#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4076#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4075#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4073#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4072#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4069#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4065#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4064#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4063#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4062#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4061#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4060#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4057#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4054#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4053#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4051#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4050#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4049#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4048#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4045#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4042#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4039#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4035#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4034#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4029#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4025#L12-1 [2024-11-13 13:12:49,712 INFO L747 eck$LassoCheckResult]: Loop: 4025#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4026#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4025#L12-1 [2024-11-13 13:12:49,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:49,713 INFO L85 PathProgramCache]: Analyzing trace with hash -1435741323, now seen corresponding path program 3 times [2024-11-13 13:12:49,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:49,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761701805] [2024-11-13 13:12:49,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:49,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:49,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:50,135 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 0 proven. 6525 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2024-11-13 13:12:50,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:50,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761701805] [2024-11-13 13:12:50,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761701805] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:50,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2013193710] [2024-11-13 13:12:50,136 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-13 13:12:50,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:50,136 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:50,138 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:50,143 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-11-13 13:12:50,210 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-11-13 13:12:50,210 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:50,211 INFO L255 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-13 13:12:50,218 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:50,289 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2024-11-13 13:12:50,290 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:50,356 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2024-11-13 13:12:50,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2013193710] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:50,356 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:50,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2024-11-13 13:12:50,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724133233] [2024-11-13 13:12:50,357 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:50,358 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:50,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:50,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 7 times [2024-11-13 13:12:50,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:50,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729293935] [2024-11-13 13:12:50,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:50,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:50,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:50,361 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:50,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:50,364 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:50,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:50,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-13 13:12:50,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2024-11-13 13:12:50,382 INFO L87 Difference]: Start difference. First operand 243 states and 253 transitions. cyclomatic complexity: 16 Second operand has 12 states, 11 states have (on average 3.5454545454545454) internal successors, (39), 12 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:50,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:50,696 INFO L93 Difference]: Finished difference Result 267 states and 282 transitions. [2024-11-13 13:12:50,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 282 transitions. [2024-11-13 13:12:50,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:50,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 282 transitions. [2024-11-13 13:12:50,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2024-11-13 13:12:50,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2024-11-13 13:12:50,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 282 transitions. [2024-11-13 13:12:50,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:50,700 INFO L218 hiAutomatonCegarLoop]: Abstraction has 267 states and 282 transitions. [2024-11-13 13:12:50,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 282 transitions. [2024-11-13 13:12:50,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 256. [2024-11-13 13:12:50,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 256 states, 256 states have (on average 1.046875) internal successors, (268), 255 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:50,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 268 transitions. [2024-11-13 13:12:50,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 256 states and 268 transitions. [2024-11-13 13:12:50,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-13 13:12:50,715 INFO L424 stractBuchiCegarLoop]: Abstraction has 256 states and 268 transitions. [2024-11-13 13:12:50,715 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:12:50,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 256 states and 268 transitions. [2024-11-13 13:12:50,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:50,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:50,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:50,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [78, 77, 71, 6, 1, 1, 1] [2024-11-13 13:12:50,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:50,722 INFO L745 eck$LassoCheckResult]: Stem: 5949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 5950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 5951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5965#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5961#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5956#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5947#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5943#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6142#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6112#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6109#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6098#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6097#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6093#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6092#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6089#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6087#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6085#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6084#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6076#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6075#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6073#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6072#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6069#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6065#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6064#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6063#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6062#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6061#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6060#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6057#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6054#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6053#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6051#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6050#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6049#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6048#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6045#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6042#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6041#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6039#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6038#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6037#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6034#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6035#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6032#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6031#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6030#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6029#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6028#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6027#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6026#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6025#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6024#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6022#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6021#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6020#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6019#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6018#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6017#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6016#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6015#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6014#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6013#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6012#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6011#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6010#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6009#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6008#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6007#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6006#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6005#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6004#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6003#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6002#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6001#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6000#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5999#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5998#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5997#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5996#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5995#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5994#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5993#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5992#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5991#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5990#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5989#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5988#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5987#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5985#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5984#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5982#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5981#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5980#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5979#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5973#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5967#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5962#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5959#L12-1 [2024-11-13 13:12:50,722 INFO L747 eck$LassoCheckResult]: Loop: 5959#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5960#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5959#L12-1 [2024-11-13 13:12:50,723 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:50,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1945344531, now seen corresponding path program 4 times [2024-11-13 13:12:50,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:50,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213259283] [2024-11-13 13:12:50,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:50,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:50,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:51,129 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 154 proven. 6828 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2024-11-13 13:12:51,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:51,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213259283] [2024-11-13 13:12:51,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213259283] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:51,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [502030859] [2024-11-13 13:12:51,130 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-13 13:12:51,130 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:51,130 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:51,133 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:51,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-11-13 13:12:51,260 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-13 13:12:51,260 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:51,263 INFO L255 TraceCheckSpWp]: Trace formula consists of 489 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-11-13 13:12:51,268 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:52,143 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2024-11-13 13:12:52,144 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:53,006 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2024-11-13 13:12:53,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [502030859] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:53,007 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:53,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 28, 28] total 50 [2024-11-13 13:12:53,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561645475] [2024-11-13 13:12:53,008 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:53,008 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:53,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:53,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 8 times [2024-11-13 13:12:53,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:53,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597040176] [2024-11-13 13:12:53,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:53,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:53,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:53,014 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:53,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:53,016 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:53,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:53,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-11-13 13:12:53,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=1767, Unknown=0, NotChecked=0, Total=2450 [2024-11-13 13:12:53,036 INFO L87 Difference]: Start difference. First operand 256 states and 268 transitions. cyclomatic complexity: 19 Second operand has 50 states, 50 states have (on average 3.18) internal successors, (159), 50 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:56,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:12:56,182 INFO L93 Difference]: Finished difference Result 1034 states and 1149 transitions. [2024-11-13 13:12:56,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1034 states and 1149 transitions. [2024-11-13 13:12:56,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:56,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1034 states to 986 states and 1101 transitions. [2024-11-13 13:12:56,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2024-11-13 13:12:56,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2024-11-13 13:12:56,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 986 states and 1101 transitions. [2024-11-13 13:12:56,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:12:56,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 986 states and 1101 transitions. [2024-11-13 13:12:56,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 986 states and 1101 transitions. [2024-11-13 13:12:56,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 986 to 693. [2024-11-13 13:12:56,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.1096681096681096) internal successors, (769), 692 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:12:56,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 769 transitions. [2024-11-13 13:12:56,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 769 transitions. [2024-11-13 13:12:56,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2024-11-13 13:12:56,220 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 769 transitions. [2024-11-13 13:12:56,220 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:12:56,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 769 transitions. [2024-11-13 13:12:56,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:12:56,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:12:56,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:12:56,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 83, 11, 1, 1, 1] [2024-11-13 13:12:56,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:12:56,234 INFO L745 eck$LassoCheckResult]: Stem: 9116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 9117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 9118#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9113#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9109#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9525#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9524#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9520#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9519#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9513#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9512#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9509#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9507#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9506#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9504#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9503#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9502#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9501#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9500#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9497#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9496#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9495#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9494#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9490#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9489#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9488#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9486#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9484#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9482#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9481#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9480#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9478#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9476#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9474#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9470#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9468#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9467#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9466#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9463#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9462#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9461#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9458#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9457#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9456#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9455#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9454#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9452#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9450#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9449#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9448#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9447#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9446#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9445#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9444#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9443#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9440#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9439#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9438#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9436#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9435#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9431#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9430#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9427#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9426#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9425#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9412#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9398#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9397#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9395#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9393#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9392#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9387#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9385#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9383#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9382#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9381#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9379#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9375#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9373#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9369#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9359#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9358#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9357#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9356#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9355#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9353#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9351#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9350#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9347#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9346#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9345#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9344#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9342#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9341#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9338#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9334#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9326#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9324#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9322#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9318#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9316#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9312#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9308#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9281#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9300#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9296#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9274#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9269#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9285#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9262#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9261#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9260#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9259#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9258#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9209#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9186#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9181#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9172#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9166#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9158#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9157#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9146#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9144#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9143#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9142#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9139#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9138#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9137#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9136#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 9132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9129#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 9128#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9125#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9124#L12-1 [2024-11-13 13:12:56,234 INFO L747 eck$LassoCheckResult]: Loop: 9124#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9123#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 9124#L12-1 [2024-11-13 13:12:56,234 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:56,234 INFO L85 PathProgramCache]: Analyzing trace with hash -220878292, now seen corresponding path program 5 times [2024-11-13 13:12:56,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:56,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362095897] [2024-11-13 13:12:56,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:56,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:56,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:12:57,244 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 5787 proven. 5686 refuted. 0 times theorem prover too weak. 1828 trivial. 0 not checked. [2024-11-13 13:12:57,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:12:57,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362095897] [2024-11-13 13:12:57,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362095897] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:12:57,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [237810553] [2024-11-13 13:12:57,244 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-13 13:12:57,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:12:57,245 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:12:57,247 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:12:57,251 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-11-13 13:12:57,536 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2024-11-13 13:12:57,536 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:12:57,539 INFO L255 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 29 conjuncts are in the unsatisfiable core [2024-11-13 13:12:57,544 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:12:58,257 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2024-11-13 13:12:58,257 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:12:58,869 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7733 proven. 3749 refuted. 0 times theorem prover too weak. 1819 trivial. 0 not checked. [2024-11-13 13:12:58,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [237810553] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:12:58,869 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:12:58,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 29, 29] total 48 [2024-11-13 13:12:58,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280762408] [2024-11-13 13:12:58,870 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:12:58,870 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:12:58,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:12:58,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 9 times [2024-11-13 13:12:58,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:12:58,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663365536] [2024-11-13 13:12:58,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:12:58,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:12:58,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:58,873 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:12:58,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:12:58,874 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:12:58,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:12:58,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2024-11-13 13:12:58,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=585, Invalid=1671, Unknown=0, NotChecked=0, Total=2256 [2024-11-13 13:12:58,896 INFO L87 Difference]: Start difference. First operand 693 states and 769 transitions. cyclomatic complexity: 82 Second operand has 48 states, 48 states have (on average 3.2291666666666665) internal successors, (155), 48 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:01,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:13:01,698 INFO L93 Difference]: Finished difference Result 1368 states and 1470 transitions. [2024-11-13 13:13:01,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1368 states and 1470 transitions. [2024-11-13 13:13:01,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:01,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1368 states to 1240 states and 1342 transitions. [2024-11-13 13:13:01,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2024-11-13 13:13:01,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2024-11-13 13:13:01,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1240 states and 1342 transitions. [2024-11-13 13:13:01,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:13:01,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1240 states and 1342 transitions. [2024-11-13 13:13:01,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1240 states and 1342 transitions. [2024-11-13 13:13:01,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1240 to 609. [2024-11-13 13:13:01,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 609 states, 609 states have (on average 1.083743842364532) internal successors, (660), 608 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:01,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 660 transitions. [2024-11-13 13:13:01,737 INFO L240 hiAutomatonCegarLoop]: Abstraction has 609 states and 660 transitions. [2024-11-13 13:13:01,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 135 states. [2024-11-13 13:13:01,738 INFO L424 stractBuchiCegarLoop]: Abstraction has 609 states and 660 transitions. [2024-11-13 13:13:01,740 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:13:01,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 609 states and 660 transitions. [2024-11-13 13:13:01,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:01,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:13:01,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:13:01,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [131, 130, 115, 15, 1, 1, 1] [2024-11-13 13:13:01,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:13:01,750 INFO L745 eck$LassoCheckResult]: Stem: 13188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 13189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 13190#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13185#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13181#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13677#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13676#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13675#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13674#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13673#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13669#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13668#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13667#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13666#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13665#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13664#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13662#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13661#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13660#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13659#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13658#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13657#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13656#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13655#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13654#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13653#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13652#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13651#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13650#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13649#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13648#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13647#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13646#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13645#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13644#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13643#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13642#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13641#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13640#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13639#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13638#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13637#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13634#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13633#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13632#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13631#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13630#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13629#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13628#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13627#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13625#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13624#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13623#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13622#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13621#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13620#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13619#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13618#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13617#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13616#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13615#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13613#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13612#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13611#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13610#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13608#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13607#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13606#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13605#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13604#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13603#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13602#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13601#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13600#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13599#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13598#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13597#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13596#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13595#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13594#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13593#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13592#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13589#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13588#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13587#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13586#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13585#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13584#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13583#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13582#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13581#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13580#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13578#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13577#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13576#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13575#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13574#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13573#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13572#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13571#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13568#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13566#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13559#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13558#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13556#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13553#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13552#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13551#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13550#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13549#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13548#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13547#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13544#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13539#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13538#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13533#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13530#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13528#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13511#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13510#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13506#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13505#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13494#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13493#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13491#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13487#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13485#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13481#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13473#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13467#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13457#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13430#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13413#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13394#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13370#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13366#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13365#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13364#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13363#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13341#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13340#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13335#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13334#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13331#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13329#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13328#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13327#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13319#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13317#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13315#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13314#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13312#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13313#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13309#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13308#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13305#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13304#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13299#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13296#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13292#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13290#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13288#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13289#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13284#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13283#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13281#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13280#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13279#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13278#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13277#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13276#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13274#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13273#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13272#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13268#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13264#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13263#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13262#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13261#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13260#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13259#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13258#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13257#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13256#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13255#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13254#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13253#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13252#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13251#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13250#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13249#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13247#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13246#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13245#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13244#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13243#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13242#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13241#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13240#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13239#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13238#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13237#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13236#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13235#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13232#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13230#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13229#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13228#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13227#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13226#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13225#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13223#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13220#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13218#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13217#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13216#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13214#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13211#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13210#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13209#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13208#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13207#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 13204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13201#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 13200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13195#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13196#L12-1 [2024-11-13 13:13:01,751 INFO L747 eck$LassoCheckResult]: Loop: 13196#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 13199#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 13196#L12-1 [2024-11-13 13:13:01,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:01,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1167427228, now seen corresponding path program 6 times [2024-11-13 13:13:01,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:01,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024606864] [2024-11-13 13:13:01,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:01,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:01,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:13:03,110 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 12928 proven. 8663 refuted. 0 times theorem prover too weak. 3824 trivial. 0 not checked. [2024-11-13 13:13:03,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:13:03,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024606864] [2024-11-13 13:13:03,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024606864] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:13:03,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [67074157] [2024-11-13 13:13:03,110 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-13 13:13:03,111 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:13:03,111 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:13:03,115 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:13:03,117 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-11-13 13:13:03,385 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 81 check-sat command(s) [2024-11-13 13:13:03,385 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:13:03,387 INFO L255 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-13 13:13:03,392 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:13:03,775 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2024-11-13 13:13:03,775 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:13:04,132 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2024-11-13 13:13:04,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [67074157] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:13:04,132 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:13:04,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14, 14] total 37 [2024-11-13 13:13:04,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891496216] [2024-11-13 13:13:04,132 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:13:04,133 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:13:04,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:04,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 10 times [2024-11-13 13:13:04,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:04,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306992065] [2024-11-13 13:13:04,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:04,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:04,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:04,137 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:04,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:04,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:13:04,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:13:04,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2024-11-13 13:13:04,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=1140, Unknown=0, NotChecked=0, Total=1332 [2024-11-13 13:13:04,162 INFO L87 Difference]: Start difference. First operand 609 states and 660 transitions. cyclomatic complexity: 57 Second operand has 37 states, 37 states have (on average 3.324324324324324) internal successors, (123), 37 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:06,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:13:06,140 INFO L93 Difference]: Finished difference Result 811 states and 861 transitions. [2024-11-13 13:13:06,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 811 states and 861 transitions. [2024-11-13 13:13:06,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:06,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 811 states to 765 states and 813 transitions. [2024-11-13 13:13:06,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2024-11-13 13:13:06,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68 [2024-11-13 13:13:06,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 765 states and 813 transitions. [2024-11-13 13:13:06,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:13:06,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 765 states and 813 transitions. [2024-11-13 13:13:06,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states and 813 transitions. [2024-11-13 13:13:06,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 589. [2024-11-13 13:13:06,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 589 states, 589 states have (on average 1.0475382003395586) internal successors, (617), 588 states have internal predecessors, (617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:06,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 589 states to 589 states and 617 transitions. [2024-11-13 13:13:06,164 INFO L240 hiAutomatonCegarLoop]: Abstraction has 589 states and 617 transitions. [2024-11-13 13:13:06,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2024-11-13 13:13:06,164 INFO L424 stractBuchiCegarLoop]: Abstraction has 589 states and 617 transitions. [2024-11-13 13:13:06,164 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:13:06,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 589 states and 617 transitions. [2024-11-13 13:13:06,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:06,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:13:06,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:13:06,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [140, 140, 125, 15, 1, 1] [2024-11-13 13:13:06,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:13:06,175 INFO L745 eck$LassoCheckResult]: Stem: 17181#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 17182#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 17183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17324#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17322#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17318#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17315#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17173#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17174#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17613#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17612#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17610#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17609#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17608#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17607#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17606#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17605#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17604#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17603#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17602#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17601#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17600#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17599#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17598#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17597#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17596#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17595#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17594#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17593#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17592#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17591#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17590#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17589#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17588#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17587#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17586#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17584#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17583#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17582#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17581#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17580#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17579#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17578#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17573#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17572#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17571#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17570#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17568#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17567#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17566#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17564#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17561#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17560#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17559#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17558#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17557#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17555#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17554#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17552#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17551#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17550#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17541#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17540#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17536#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17535#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17534#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17533#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17532#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17531#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17529#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17528#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17525#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17524#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17523#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17522#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17521#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17520#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17519#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17518#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17517#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17516#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17515#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17514#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17511#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17510#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17502#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17494#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17493#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17492#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17490#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17489#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17488#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17487#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17486#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17484#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17483#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17482#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17481#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17480#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17477#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17476#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17474#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17472#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17456#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17451#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17448#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17433#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17432#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17429#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17428#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17423#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17422#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17420#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17419#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17418#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17417#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17416#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17415#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17400#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17399#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17388#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17387#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17385#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17383#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17382#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17381#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17379#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17375#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17373#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17369#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17312#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17280#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17311#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17309#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17308#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17307#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17306#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17301#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17300#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17299#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17298#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17297#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17296#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17295#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17294#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17293#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17292#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17291#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17290#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17289#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17288#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17287#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17286#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17285#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17284#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17283#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17282#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17253#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17281#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17279#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17278#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17277#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17276#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17275#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17267#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17265#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17254#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17250#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17230#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17226#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17220#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17189#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17209#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17205#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17203#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17202#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17186#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17178#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17179#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17360#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17359#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17358#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17357#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17356#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17355#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17353#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17351#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17350#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17348#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17347#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17346#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17345#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17344#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17342#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17341#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17338#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17337#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17336#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17335#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17334#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17333#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17330#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17329#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17328#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17327#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17325#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17323#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17321#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17319#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17317#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17313#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17314#L12-1 [2024-11-13 13:13:06,175 INFO L747 eck$LassoCheckResult]: Loop: 17314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17316#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17314#L12-1 [2024-11-13 13:13:06,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:06,175 INFO L85 PathProgramCache]: Analyzing trace with hash 146618817, now seen corresponding path program 9 times [2024-11-13 13:13:06,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:06,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767384565] [2024-11-13 13:13:06,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:06,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:06,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:13:07,108 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 13932 proven. 9015 refuted. 0 times theorem prover too weak. 6243 trivial. 0 not checked. [2024-11-13 13:13:07,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:13:07,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767384565] [2024-11-13 13:13:07,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767384565] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:13:07,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [657364972] [2024-11-13 13:13:07,109 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-13 13:13:07,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:13:07,109 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:13:07,111 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:13:07,113 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-11-13 13:13:07,617 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 117 check-sat command(s) [2024-11-13 13:13:07,617 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:13:07,622 INFO L255 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-13 13:13:07,628 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:13:08,442 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2024-11-13 13:13:08,442 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:13:09,306 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2024-11-13 13:13:09,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [657364972] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:13:09,307 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:13:09,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 25, 25] total 44 [2024-11-13 13:13:09,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880025095] [2024-11-13 13:13:09,307 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:13:09,308 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:13:09,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:09,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 11 times [2024-11-13 13:13:09,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:09,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731624594] [2024-11-13 13:13:09,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:09,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:09,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:09,311 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:09,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:09,313 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:13:09,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:13:09,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2024-11-13 13:13:09,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=1556, Unknown=0, NotChecked=0, Total=1892 [2024-11-13 13:13:09,336 INFO L87 Difference]: Start difference. First operand 589 states and 617 transitions. cyclomatic complexity: 34 Second operand has 44 states, 44 states have (on average 3.4318181818181817) internal successors, (151), 44 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:14,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:13:14,649 INFO L93 Difference]: Finished difference Result 1054 states and 1109 transitions. [2024-11-13 13:13:14,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1054 states and 1109 transitions. [2024-11-13 13:13:14,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:14,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1054 states to 1011 states and 1066 transitions. [2024-11-13 13:13:14,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2024-11-13 13:13:14,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2024-11-13 13:13:14,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1011 states and 1066 transitions. [2024-11-13 13:13:14,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:13:14,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1011 states and 1066 transitions. [2024-11-13 13:13:14,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1011 states and 1066 transitions. [2024-11-13 13:13:14,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1011 to 760. [2024-11-13 13:13:14,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.0460526315789473) internal successors, (795), 759 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:14,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 795 transitions. [2024-11-13 13:13:14,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 760 states and 795 transitions. [2024-11-13 13:13:14,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 177 states. [2024-11-13 13:13:14,675 INFO L424 stractBuchiCegarLoop]: Abstraction has 760 states and 795 transitions. [2024-11-13 13:13:14,675 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:13:14,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 795 transitions. [2024-11-13 13:13:14,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:14,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:13:14,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:13:14,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [161, 161, 144, 17, 1, 1] [2024-11-13 13:13:14,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:13:14,689 INFO L745 eck$LassoCheckResult]: Stem: 21739#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 21740#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 21741#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21775#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21774#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21773#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21771#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21768#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21731#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21732#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22387#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22385#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22383#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22382#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22381#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22379#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22375#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22373#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22369#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22360#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22359#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22358#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22357#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22356#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22355#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22354#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22353#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22352#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22351#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22350#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22349#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22348#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22347#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22346#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22345#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22344#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22343#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22342#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22339#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22337#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22336#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22335#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22334#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22333#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22332#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22330#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22329#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22327#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22326#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22325#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22324#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22323#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22322#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22321#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22318#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22317#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22316#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22315#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22314#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22313#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22312#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22311#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22309#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22308#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22307#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22306#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22301#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22300#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22299#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22298#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22297#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22296#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22295#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22294#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22293#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22292#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22291#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22290#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22289#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22288#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22287#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22286#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22285#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22283#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22284#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22282#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22281#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22280#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22279#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22278#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22277#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22276#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22275#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22267#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22265#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22254#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22230#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22226#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22220#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22208#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22203#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22202#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22178#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22177#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22171#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22170#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22169#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22168#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22165#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22163#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22162#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22161#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22160#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22159#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22158#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22157#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22156#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22155#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22154#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22153#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22149#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22148#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22147#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22146#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22144#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22143#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22142#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22137#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22131#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22129#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22125#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22123#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22140#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21994#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21993#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21992#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21991#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21990#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21989#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21988#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21987#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21986#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21985#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21984#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21983#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21982#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21981#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21980#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21979#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21978#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21977#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21975#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21974#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21973#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21972#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21971#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21970#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21969#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21968#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21967#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21966#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21965#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21964#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21963#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21961#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21960#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21959#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21958#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21957#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21956#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21955#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21954#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21953#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21952#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21951#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21950#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21949#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21948#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21947#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21946#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21945#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21944#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21943#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21942#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21941#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21940#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21939#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21938#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21937#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21936#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21935#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21934#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21933#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21932#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21930#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21929#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21928#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21927#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21926#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21925#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21924#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21923#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21922#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21921#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21920#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21919#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21918#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21917#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21916#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21915#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21914#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21913#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21912#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21911#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21910#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21909#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21908#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21907#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21906#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21905#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21904#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21903#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21902#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21901#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21900#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21898#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21897#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21896#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21895#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21894#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21893#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21892#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21891#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21890#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21889#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21888#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21887#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21886#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21885#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21884#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21883#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21880#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21878#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21876#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21874#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21872#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21870#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21868#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21866#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21862#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21860#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21858#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21856#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21854#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21852#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21850#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21848#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21844#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21842#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21839#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21838#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21837#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21836#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21831#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21830#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21829#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21828#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21827#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21826#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21825#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21824#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21823#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21822#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21821#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21820#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21819#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21818#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21817#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21816#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21815#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21814#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21746#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21813#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21764#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21763#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21762#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21761#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21760#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21759#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21758#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21757#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21756#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21755#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21754#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21753#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21752#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21751#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21750#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21749#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21748#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21747#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21745#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21743#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21736#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21737#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21744#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21812#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21811#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21810#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21809#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21808#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21807#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21806#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21805#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21804#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21803#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21802#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21801#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21800#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21799#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21798#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21797#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21796#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21795#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21794#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21793#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21792#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21791#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21790#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21789#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21788#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21787#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21785#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21784#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21783#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21782#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21781#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21780#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21779#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21778#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21777#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21776#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21772#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21770#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21766#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21767#L12-1 [2024-11-13 13:13:14,689 INFO L747 eck$LassoCheckResult]: Loop: 21767#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21769#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21767#L12-1 [2024-11-13 13:13:14,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:14,690 INFO L85 PathProgramCache]: Analyzing trace with hash 704422726, now seen corresponding path program 10 times [2024-11-13 13:13:14,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:14,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571281474] [2024-11-13 13:13:14,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:14,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:14,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:13:15,699 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 18300 proven. 12627 refuted. 0 times theorem prover too weak. 7713 trivial. 0 not checked. [2024-11-13 13:13:15,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:13:15,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571281474] [2024-11-13 13:13:15,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571281474] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:13:15,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1801166174] [2024-11-13 13:13:15,700 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-13 13:13:15,700 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:13:15,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:13:15,704 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:13:15,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-11-13 13:13:15,905 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-13 13:13:15,905 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:13:15,910 INFO L255 TraceCheckSpWp]: Trace formula consists of 1020 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-11-13 13:13:15,920 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:13:17,031 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2024-11-13 13:13:17,031 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:13:17,996 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2024-11-13 13:13:17,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1801166174] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-13 13:13:17,997 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-13 13:13:17,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 40, 40] total 57 [2024-11-13 13:13:17,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690445898] [2024-11-13 13:13:17,997 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-13 13:13:17,998 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:13:17,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:17,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 12 times [2024-11-13 13:13:17,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:17,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505513821] [2024-11-13 13:13:17,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:17,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:18,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:18,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:18,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:18,003 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:13:18,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:13:18,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2024-11-13 13:13:18,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=2542, Unknown=0, NotChecked=0, Total=3192 [2024-11-13 13:13:18,030 INFO L87 Difference]: Start difference. First operand 760 states and 795 transitions. cyclomatic complexity: 42 Second operand has 57 states, 57 states have (on average 3.192982456140351) internal successors, (182), 57 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:25,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:13:25,173 INFO L93 Difference]: Finished difference Result 1366 states and 1422 transitions. [2024-11-13 13:13:25,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 1422 transitions. [2024-11-13 13:13:25,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:25,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1286 states and 1342 transitions. [2024-11-13 13:13:25,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74 [2024-11-13 13:13:25,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74 [2024-11-13 13:13:25,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1286 states and 1342 transitions. [2024-11-13 13:13:25,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 13:13:25,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1286 states and 1342 transitions. [2024-11-13 13:13:25,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1286 states and 1342 transitions. [2024-11-13 13:13:25,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1286 to 643. [2024-11-13 13:13:25,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 643 states, 643 states have (on average 1.026438569206843) internal successors, (660), 642 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:13:25,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 660 transitions. [2024-11-13 13:13:25,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 643 states and 660 transitions. [2024-11-13 13:13:25,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 238 states. [2024-11-13 13:13:25,199 INFO L424 stractBuchiCegarLoop]: Abstraction has 643 states and 660 transitions. [2024-11-13 13:13:25,199 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:13:25,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states and 660 transitions. [2024-11-13 13:13:25,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2024-11-13 13:13:25,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:13:25,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:13:25,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [210, 210, 190, 20, 1, 1] [2024-11-13 13:13:25,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-13 13:13:25,207 INFO L745 eck$LassoCheckResult]: Stem: 27481#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 27482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 27483#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27518#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27515#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27473#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28111#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28110#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28109#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28108#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28107#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28106#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28105#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28104#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28101#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28100#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28099#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28098#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28097#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28096#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28095#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28094#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28093#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28092#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28090#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28089#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28087#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28086#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28085#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28084#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28083#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28082#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28081#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28080#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28077#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28074#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28073#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28072#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28071#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28070#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28069#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28068#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28065#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28063#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28062#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28061#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28060#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28058#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 28057#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28054#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28053#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28051#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28050#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28049#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28048#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28045#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28042#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28041#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28039#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28038#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28037#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28035#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28034#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28032#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28031#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28030#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28029#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28028#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28027#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28026#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28025#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28024#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28022#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28021#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28020#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28019#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28018#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28017#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28016#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28015#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28014#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28013#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28012#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28011#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28010#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28009#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28008#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28007#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28006#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28005#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 28003#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 28002#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 28001#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 28000#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27999#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27998#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27997#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27996#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27995#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27994#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27993#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27992#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27991#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27990#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27989#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27988#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27987#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27985#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27984#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27983#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27982#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27981#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27980#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27979#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27977#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27976#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27975#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27974#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27973#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27972#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27971#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27970#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27969#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27968#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27967#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27966#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27965#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27964#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27963#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27962#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27961#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27960#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27959#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27958#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27957#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27956#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27955#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27954#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27953#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27952#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27951#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27949#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27948#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27947#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27946#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27945#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27944#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27943#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27942#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27941#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27940#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27939#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27938#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27937#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27936#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27935#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27934#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27933#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27932#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27931#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27930#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27929#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27928#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27927#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27926#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27925#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27924#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27923#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27922#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27921#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27920#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27919#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27918#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27917#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27916#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27915#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27914#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27913#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27912#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27911#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27910#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27909#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27908#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27907#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27906#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27905#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27904#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27903#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27902#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27901#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27851#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27900#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27898#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27897#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27896#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27895#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27894#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27893#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27892#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27891#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27890#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27889#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27888#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27887#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27886#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27885#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27884#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27883#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27882#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27881#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27880#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27879#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27878#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27877#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27876#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27875#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27874#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27873#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27872#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27871#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27870#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27869#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27868#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27867#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27866#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27865#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27864#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27863#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27862#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27861#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27860#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27859#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27858#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27857#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27856#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27855#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27854#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27853#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27806#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27852#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27850#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27849#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27848#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27847#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27846#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27845#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27844#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27843#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27842#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27841#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27840#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27839#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27838#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27837#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27836#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27835#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27834#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27833#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27832#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27831#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27830#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27829#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27828#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27827#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27826#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27825#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27824#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27823#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27822#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27821#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27820#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27819#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27818#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27817#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27816#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27815#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27814#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27813#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27812#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27811#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27810#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27809#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27808#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27764#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27807#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27805#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27804#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27803#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27802#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27801#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27800#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27799#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27798#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27797#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27796#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27795#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27794#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27793#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27792#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27791#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27790#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27789#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27788#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27787#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27785#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27784#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27783#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27782#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27781#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27780#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27779#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27778#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27777#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27776#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27775#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27774#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27773#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27772#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27771#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27770#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27769#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27768#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27767#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27766#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27725#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27765#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27763#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27762#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27761#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27760#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27759#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27758#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27757#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27756#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27755#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27754#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27753#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27752#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27751#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27750#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27749#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27748#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27747#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27746#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27745#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27744#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27743#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27742#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27741#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27740#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27739#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27738#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27737#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27736#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27735#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27734#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27733#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27732#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27731#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27730#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27729#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27728#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27727#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27689#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27726#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27724#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27723#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27722#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27721#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27720#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27719#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27718#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27717#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27716#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27715#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27714#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27713#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27712#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27711#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27710#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27709#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27708#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27707#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27706#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27705#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27704#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27703#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27702#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27701#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27700#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27699#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27698#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27697#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27696#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27695#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27694#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27693#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27692#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27691#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27656#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27690#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27688#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27687#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27686#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27685#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27684#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27683#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27682#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27681#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27680#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27679#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27678#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27677#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27676#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27675#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27674#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27673#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27669#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27668#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27667#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27666#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27665#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27664#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27662#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27661#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27660#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27659#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27658#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27657#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27655#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27654#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27653#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27652#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27651#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27650#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27649#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27648#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27647#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27646#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27645#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27644#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27643#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27642#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27641#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27640#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27639#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27638#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27637#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27634#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27633#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27632#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27631#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27630#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27629#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27628#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27599#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27627#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27625#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27624#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27623#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27622#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27621#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27620#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27619#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27618#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27617#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27616#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27615#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27614#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27613#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27612#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27611#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27610#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27608#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27607#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27606#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27605#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27604#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27603#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27602#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27601#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27600#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27598#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27597#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27596#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27595#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27594#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27593#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27592#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27589#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27588#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27587#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27586#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27585#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27584#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27583#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27582#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27581#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27580#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27578#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27577#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27576#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27574#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27573#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27572#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27571#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27570#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27569#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27568#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27566#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27559#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27558#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27556#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27506#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27505#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27494#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27493#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27492#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27490#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27486#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27488#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27555#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27489#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27479#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27554#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27552#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27551#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27550#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27544#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27541#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27540#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27536#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27535#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27534#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27533#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27532#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27531#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27529#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27528#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27525#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27524#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27523#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27522#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27521#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27520#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 27516#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27510#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 27511#L12-1 [2024-11-13 13:13:25,208 INFO L747 eck$LassoCheckResult]: Loop: 27511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 27513#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 27511#L12-1 [2024-11-13 13:13:25,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:25,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1512831709, now seen corresponding path program 11 times [2024-11-13 13:13:25,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:25,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112362186] [2024-11-13 13:13:25,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:25,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:25,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:25,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:13:25,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:25,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 13 times [2024-11-13 13:13:25,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:25,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091367364] [2024-11-13 13:13:25,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:25,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:25,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,585 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:25,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:13:25,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:13:25,587 INFO L85 PathProgramCache]: Analyzing trace with hash -2132325970, now seen corresponding path program 7 times [2024-11-13 13:13:25,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:13:25,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92269312] [2024-11-13 13:13:25,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:13:25,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:13:25,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,754 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:13:25,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:13:25,937 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:14:15,266 WARN L286 SmtUtils]: Spent 48.97s on a formula simplification. DAG size of input: 2128 DAG size of output: 662 (called from [L 276] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2024-11-13 13:14:17,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:14:17,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:14:17,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:14:18,204 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 01:14:18 BoogieIcfgContainer [2024-11-13 13:14:18,204 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 13:14:18,205 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:14:18,205 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:14:18,205 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:14:18,206 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:12:37" (3/4) ... [2024-11-13 13:14:18,207 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 13:14:18,326 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 13:14:18,327 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:14:18,328 INFO L158 Benchmark]: Toolchain (without parser) took 101313.82ms. Allocated memory was 117.4MB in the beginning and 394.3MB in the end (delta: 276.8MB). Free memory was 92.5MB in the beginning and 268.4MB in the end (delta: -176.0MB). Peak memory consumption was 95.9MB. Max. memory is 16.1GB. [2024-11-13 13:14:18,328 INFO L158 Benchmark]: CDTParser took 0.94ms. Allocated memory is still 83.9MB. Free memory is still 41.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:14:18,328 INFO L158 Benchmark]: CACSL2BoogieTranslator took 254.14ms. Allocated memory is still 117.4MB. Free memory was 92.0MB in the beginning and 82.1MB in the end (delta: 9.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:14:18,328 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.74ms. Allocated memory is still 117.4MB. Free memory was 82.1MB in the beginning and 81.2MB in the end (delta: 873.2kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:14:18,329 INFO L158 Benchmark]: Boogie Preprocessor took 32.77ms. Allocated memory is still 117.4MB. Free memory was 81.2MB in the beginning and 80.3MB in the end (delta: 887.3kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:14:18,329 INFO L158 Benchmark]: RCFGBuilder took 222.56ms. Allocated memory is still 117.4MB. Free memory was 80.3MB in the beginning and 71.7MB in the end (delta: 8.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:14:18,329 INFO L158 Benchmark]: BuchiAutomizer took 100640.48ms. Allocated memory was 117.4MB in the beginning and 394.3MB in the end (delta: 276.8MB). Free memory was 71.7MB in the beginning and 289.4MB in the end (delta: -217.7MB). Peak memory consumption was 62.3MB. Max. memory is 16.1GB. [2024-11-13 13:14:18,330 INFO L158 Benchmark]: Witness Printer took 122.24ms. Allocated memory is still 394.3MB. Free memory was 289.4MB in the beginning and 268.4MB in the end (delta: 21.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 13:14:18,331 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.94ms. Allocated memory is still 83.9MB. Free memory is still 41.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 254.14ms. Allocated memory is still 117.4MB. Free memory was 92.0MB in the beginning and 82.1MB in the end (delta: 9.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.74ms. Allocated memory is still 117.4MB. Free memory was 82.1MB in the beginning and 81.2MB in the end (delta: 873.2kB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 32.77ms. Allocated memory is still 117.4MB. Free memory was 81.2MB in the beginning and 80.3MB in the end (delta: 887.3kB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 222.56ms. Allocated memory is still 117.4MB. Free memory was 80.3MB in the beginning and 71.7MB in the end (delta: 8.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 100640.48ms. Allocated memory was 117.4MB in the beginning and 394.3MB in the end (delta: 276.8MB). Free memory was 71.7MB in the beginning and 289.4MB in the end (delta: -217.7MB). Peak memory consumption was 62.3MB. Max. memory is 16.1GB. * Witness Printer took 122.24ms. Allocated memory is still 394.3MB. Free memory was 289.4MB in the beginning and 268.4MB in the end (delta: 21.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (13 trivial, 3 deterministic, 1 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. One deterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. One deterministic module has affine ranking function range and consists of 4 locations. One nondeterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. 13 modules have a trivial ranking function, the largest among these consists of 57 locations. The remainder module has 643 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 100.3s and 17 iterations. TraceHistogramMax:210. Analysis of lassos took 76.0s. Construction of modules took 4.6s. Büchi inclusion checks took 19.4s. Highest rank in rank-based complementation 3. Minimization of det autom 1. Minimization of nondet autom 16. Automata minimization 0.2s AutomataMinimizationTime, 17 MinimizatonAttempts, 2056 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [3, 0, 1, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 3/3 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 286 SdHoareTripleChecker+Valid, 5.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 280 mSDsluCounter, 149 SdHoareTripleChecker+Invalid, 4.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 80 mSDsCounter, 1221 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 6403 IncrementalHoareTripleChecker+Invalid, 7624 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1221 mSolverCounterUnsat, 69 mSDtfsCounter, 6403 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT3 conc3 concLT0 SILN9 SILU0 SILI0 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital17 mio100 ax167 hnf100 lsp59 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq166 hnf95 smp71 dnf100 smp100 tf110 neg100 sie109 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 37ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 5 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.7s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 11]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 VAL [range=20] [L11] COND TRUE 0 <= i && i <= range VAL [i=20, range=20] [L12] COND TRUE !(0 == i && i == range) VAL [i=20, range=20] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=19, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=19, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=19, range=19] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=18] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=17] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=16] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=15] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=14] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=13] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=12] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=11] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=10] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=9] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=8] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=7] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=6] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=5] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=4] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=3] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=2] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=1] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=1] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=0] Loop: [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 11]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 VAL [range=20] [L11] COND TRUE 0 <= i && i <= range VAL [i=20, range=20] [L12] COND TRUE !(0 == i && i == range) VAL [i=20, range=20] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=19, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=19, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=19, range=19] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=18] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=17] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=16] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=15] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=14] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=13] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=12] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=11] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=10] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=9] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=8] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=7] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=6] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=5] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=4] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=3] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=2] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=1] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=1] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=0] Loop: [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 13:14:18,391 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2024-11-13 13:14:18,568 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2024-11-13 13:14:18,768 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2024-11-13 13:14:18,968 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-11-13 13:14:19,168 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2024-11-13 13:14:19,368 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-11-13 13:14:19,584 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-11-13 13:14:19,775 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-11-13 13:14:19,973 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 0 [2024-11-13 13:14:20,177 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-11-13 13:14:20,373 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-13 13:14:20,576 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f1f3dc9-ca9c-46ee-aef2-4e0a38da0fd7/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)