./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/bist_cell.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:36:14,585 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:36:14,672 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:36:14,678 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:36:14,678 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:36:14,708 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:36:14,709 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:36:14,710 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:36:14,710 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:36:14,710 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:36:14,711 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:36:14,711 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:36:14,711 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:36:14,711 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:36:14,711 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:36:14,712 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:36:14,712 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:36:14,712 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:36:14,712 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:36:14,712 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:36:14,713 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:36:14,714 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:36:14,715 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:36:14,715 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:36:14,715 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:36:14,715 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:36:14,715 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:36:14,716 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:36:14,716 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:36:14,716 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2024-11-13 15:36:15,086 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:36:15,101 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:36:15,106 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:36:15,107 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:36:15,108 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:36:15,110 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/bist_cell.cil.c Unable to find full path for "g++" [2024-11-13 15:36:17,285 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:36:17,585 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:36:17,586 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/sv-benchmarks/c/systemc/bist_cell.cil.c [2024-11-13 15:36:17,597 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/data/aa725963d/5e6a3dbf99034927876e60f7b9e22cdc/FLAG7bf1d793e [2024-11-13 15:36:17,619 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/data/aa725963d/5e6a3dbf99034927876e60f7b9e22cdc [2024-11-13 15:36:17,622 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:36:17,625 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:36:17,626 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:36:17,628 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:36:17,633 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:36:17,635 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:36:17" (1/1) ... [2024-11-13 15:36:17,636 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@441b4a29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:17, skipping insertion in model container [2024-11-13 15:36:17,638 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:36:17" (1/1) ... [2024-11-13 15:36:17,669 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:36:17,966 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:36:17,987 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:36:18,065 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:36:18,094 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:36:18,097 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18 WrapperNode [2024-11-13 15:36:18,098 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:36:18,099 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:36:18,099 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:36:18,099 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:36:18,113 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,121 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,166 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 343 [2024-11-13 15:36:18,166 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:36:18,168 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:36:18,168 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:36:18,168 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:36:18,181 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,182 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,185 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,217 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:36:18,218 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,218 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,228 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,242 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,247 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,249 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,256 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:36:18,257 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:36:18,260 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:36:18,260 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:36:18,261 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (1/1) ... [2024-11-13 15:36:18,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:18,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:18,310 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:18,314 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:36:18,350 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:36:18,351 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:36:18,351 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:36:18,351 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:36:18,467 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:36:18,470 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:36:19,062 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2024-11-13 15:36:19,062 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:36:19,090 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:36:19,092 INFO L316 CfgBuilder]: Removed 2 assume(true) statements. [2024-11-13 15:36:19,094 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:36:19 BoogieIcfgContainer [2024-11-13 15:36:19,094 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:36:19,095 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:36:19,095 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:36:19,102 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:36:19,103 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:36:19,103 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:36:17" (1/3) ... [2024-11-13 15:36:19,104 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28d10be0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:36:19, skipping insertion in model container [2024-11-13 15:36:19,104 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:36:19,104 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:36:18" (2/3) ... [2024-11-13 15:36:19,105 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28d10be0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:36:19, skipping insertion in model container [2024-11-13 15:36:19,105 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:36:19,105 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:36:19" (3/3) ... [2024-11-13 15:36:19,107 INFO L333 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2024-11-13 15:36:19,174 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:36:19,174 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:36:19,174 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:36:19,175 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:36:19,175 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:36:19,175 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:36:19,175 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:36:19,175 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:36:19,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:19,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:19,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:19,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:19,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,232 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:36:19,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:19,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:19,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:19,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:19,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,263 INFO L745 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 41#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 118#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70#L212true assume !(1 == ~b0_req_up~0); 122#L212-2true assume !(1 == ~b1_req_up~0); 78#L219-1true assume !(1 == ~d0_req_up~0); 42#L226-1true assume !(1 == ~d1_req_up~0); 61#L233-1true assume !(1 == ~z_req_up~0); 105#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 115#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62#L321true assume !(0 == ~b0_ev~0); 77#L321-2true assume !(0 == ~b1_ev~0); 22#L326-1true assume !(0 == ~d0_ev~0); 25#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 5#L336-1true assume !(0 == ~z_ev~0); 120#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 116#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 104#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 75#is_method1_triggered_returnLabel#1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 87#L390true assume !(0 != activate_threads_~tmp~1#1); 110#L390-2true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53#L354true assume !(1 == ~b0_ev~0); 38#L354-2true assume !(1 == ~b1_ev~0); 85#L359-1true assume !(1 == ~d0_ev~0); 40#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 45#L369-1true assume !(1 == ~z_ev~0); 92#L374-1true assume { :end_inline_reset_delta_events } true; 33#L432-2true [2024-11-13 15:36:19,265 INFO L747 eck$LassoCheckResult]: Loop: 33#L432-2true assume !false; 64#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 4#L295true assume !true; 84#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79#L212-3true assume !(1 == ~b0_req_up~0); 107#L212-5true assume !(1 == ~b1_req_up~0); 83#L219-3true assume !(1 == ~d0_req_up~0); 3#L226-3true assume !(1 == ~d1_req_up~0); 36#L233-3true assume !(1 == ~z_req_up~0); 14#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 60#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 89#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 48#L331-3true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 9#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 15#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 112#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 43#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 113#is_method1_triggered_returnLabel#2true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 21#L390-5true havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 97#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 95#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 76#L364-3true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 73#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 47#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 66#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 117#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 90#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 11#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123#stop_simulation_returnLabel#1true start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 67#L449true assume !(0 != start_simulation_~tmp~3#1); 33#L432-2true [2024-11-13 15:36:19,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:19,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2024-11-13 15:36:19,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:19,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674244649] [2024-11-13 15:36:19,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:19,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:19,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:19,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:19,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:19,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674244649] [2024-11-13 15:36:19,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1674244649] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:19,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:19,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:19,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47920046] [2024-11-13 15:36:19,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:19,722 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:19,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:19,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1475371125, now seen corresponding path program 1 times [2024-11-13 15:36:19,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:19,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260097556] [2024-11-13 15:36:19,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:19,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:19,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:19,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:19,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:19,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260097556] [2024-11-13 15:36:19,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260097556] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:19,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:19,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:36:19,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281395209] [2024-11-13 15:36:19,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:19,755 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:19,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:19,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:19,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:19,799 INFO L87 Difference]: Start difference. First operand has 126 states, 125 states have (on average 1.584) internal successors, (198), 125 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:19,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:19,846 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2024-11-13 15:36:19,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2024-11-13 15:36:19,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:19,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2024-11-13 15:36:19,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:19,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:19,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2024-11-13 15:36:19,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:19,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-11-13 15:36:19,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2024-11-13 15:36:19,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:19,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:19,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2024-11-13 15:36:19,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-11-13 15:36:19,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:19,920 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2024-11-13 15:36:19,920 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:36:19,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2024-11-13 15:36:19,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:19,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:19,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:19,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:19,928 INFO L745 eck$LassoCheckResult]: Stem: 302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 355#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 343#L137 assume !(~b0_val~0 != ~b0_val_t~0); 344#L137-2 ~b0_req_up~0 := 0; 371#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 375#L212-2 assume !(1 == ~b1_req_up~0); 278#L219-1 assume !(1 == ~d0_req_up~0); 325#L226-1 assume !(1 == ~d1_req_up~0); 327#L233-1 assume !(1 == ~z_req_up~0); 348#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 280#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 349#L321 assume !(0 == ~b0_ev~0); 350#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 264#L336-1 assume !(0 == ~z_ev~0); 265#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 358#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 359#L390 assume !(0 != activate_threads_~tmp~1#1); 364#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336#L354 assume !(1 == ~b0_ev~0); 318#L354-2 assume !(1 == ~b1_ev~0); 319#L359-1 assume !(1 == ~d0_ev~0); 322#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 323#L369-1 assume !(1 == ~z_ev~0); 329#L374-1 assume { :end_inline_reset_delta_events } true; 310#L432-2 [2024-11-13 15:36:19,931 INFO L747 eck$LassoCheckResult]: Loop: 310#L432-2 assume !false; 311#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 262#L295 assume !false; 263#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 273#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 274#L290 assume !(0 != eval_~tmp___0~0#1); 363#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 361#L212-3 assume !(1 == ~b0_req_up~0); 314#L212-5 assume !(1 == ~b1_req_up~0); 321#L219-3 assume !(1 == ~d0_req_up~0); 259#L226-3 assume !(1 == ~d1_req_up~0); 260#L233-3 assume !(1 == ~z_req_up~0); 281#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 345#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 346#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 332#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 271#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 272#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 283#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 301#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 328#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 266#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 267#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 307#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 360#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 357#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 330#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 331#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 351#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 365#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 275#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 373#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 352#L449 assume !(0 != start_simulation_~tmp~3#1); 310#L432-2 [2024-11-13 15:36:19,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:19,933 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2024-11-13 15:36:19,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:19,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736071785] [2024-11-13 15:36:19,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:19,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:19,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736071785] [2024-11-13 15:36:20,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736071785] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:20,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831675527] [2024-11-13 15:36:20,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,093 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:20,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,094 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 1 times [2024-11-13 15:36:20,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426719155] [2024-11-13 15:36:20,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426719155] [2024-11-13 15:36:20,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426719155] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:20,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318588126] [2024-11-13 15:36:20,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,231 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:20,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:20,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:20,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:20,233 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:20,283 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2024-11-13 15:36:20,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2024-11-13 15:36:20,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2024-11-13 15:36:20,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:20,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:20,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2024-11-13 15:36:20,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:20,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-11-13 15:36:20,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2024-11-13 15:36:20,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:20,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2024-11-13 15:36:20,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-11-13 15:36:20,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:20,309 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2024-11-13 15:36:20,309 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:36:20,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2024-11-13 15:36:20,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:20,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:20,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,319 INFO L745 eck$LassoCheckResult]: Stem: 545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 598#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 586#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 587#L137-2 ~b0_req_up~0 := 0; 614#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 618#L212-2 assume !(1 == ~b1_req_up~0); 521#L219-1 assume !(1 == ~d0_req_up~0); 568#L226-1 assume !(1 == ~d1_req_up~0); 570#L233-1 assume !(1 == ~z_req_up~0); 591#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 522#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 523#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 592#L321 assume !(0 == ~b0_ev~0); 593#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 507#L336-1 assume !(0 == ~z_ev~0); 508#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 601#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 602#L390 assume !(0 != activate_threads_~tmp~1#1); 607#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579#L354 assume !(1 == ~b0_ev~0); 561#L354-2 assume !(1 == ~b1_ev~0); 562#L359-1 assume !(1 == ~d0_ev~0); 565#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 566#L369-1 assume !(1 == ~z_ev~0); 572#L374-1 assume { :end_inline_reset_delta_events } true; 553#L432-2 [2024-11-13 15:36:20,319 INFO L747 eck$LassoCheckResult]: Loop: 553#L432-2 assume !false; 554#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 505#L295 assume !false; 506#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 516#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 517#L290 assume !(0 != eval_~tmp___0~0#1); 606#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 604#L212-3 assume !(1 == ~b0_req_up~0); 557#L212-5 assume !(1 == ~b1_req_up~0); 564#L219-3 assume !(1 == ~d0_req_up~0); 502#L226-3 assume !(1 == ~d1_req_up~0); 503#L233-3 assume !(1 == ~z_req_up~0); 524#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 588#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 589#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 575#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 514#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 515#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 526#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 544#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 571#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 509#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 510#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 550#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 603#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 600#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 573#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 574#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 594#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 608#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 518#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 616#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 595#L449 assume !(0 != start_simulation_~tmp~3#1); 553#L432-2 [2024-11-13 15:36:20,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,320 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2024-11-13 15:36:20,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219529950] [2024-11-13 15:36:20,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219529950] [2024-11-13 15:36:20,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219529950] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:20,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142068613] [2024-11-13 15:36:20,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,421 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:20,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,422 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 2 times [2024-11-13 15:36:20,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142898224] [2024-11-13 15:36:20,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142898224] [2024-11-13 15:36:20,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142898224] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,507 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,507 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:20,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710094859] [2024-11-13 15:36:20,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,508 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:20,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:20,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:20,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:20,510 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:20,540 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2024-11-13 15:36:20,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2024-11-13 15:36:20,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2024-11-13 15:36:20,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:20,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:20,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2024-11-13 15:36:20,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:20,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-11-13 15:36:20,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2024-11-13 15:36:20,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:20,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2024-11-13 15:36:20,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-11-13 15:36:20,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:20,565 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2024-11-13 15:36:20,565 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:36:20,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2024-11-13 15:36:20,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:20,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:20,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,570 INFO L745 eck$LassoCheckResult]: Stem: 788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 810#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 841#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 829#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 830#L137-2 ~b0_req_up~0 := 0; 857#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 861#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 790#L152 assume !(~b1_val~0 != ~b1_val_t~0); 791#L152-2 ~b1_req_up~0 := 0; 763#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 764#L219-1 assume !(1 == ~d0_req_up~0); 811#L226-1 assume !(1 == ~d1_req_up~0); 813#L233-1 assume !(1 == ~z_req_up~0); 834#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 765#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 766#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 835#L321 assume !(0 == ~b0_ev~0); 836#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 750#L336-1 assume !(0 == ~z_ev~0); 751#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 844#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 845#L390 assume !(0 != activate_threads_~tmp~1#1); 850#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822#L354 assume !(1 == ~b0_ev~0); 804#L354-2 assume !(1 == ~b1_ev~0); 805#L359-1 assume !(1 == ~d0_ev~0); 808#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 809#L369-1 assume !(1 == ~z_ev~0); 815#L374-1 assume { :end_inline_reset_delta_events } true; 796#L432-2 [2024-11-13 15:36:20,571 INFO L747 eck$LassoCheckResult]: Loop: 796#L432-2 assume !false; 797#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 748#L295 assume !false; 749#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 759#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 760#L290 assume !(0 != eval_~tmp___0~0#1); 849#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 847#L212-3 assume !(1 == ~b0_req_up~0); 800#L212-5 assume !(1 == ~b1_req_up~0); 807#L219-3 assume !(1 == ~d0_req_up~0); 745#L226-3 assume !(1 == ~d1_req_up~0); 746#L233-3 assume !(1 == ~z_req_up~0); 767#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 768#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 831#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 832#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 818#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 757#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 758#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 769#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 787#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 814#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 752#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 753#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 793#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 846#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 843#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 816#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 817#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 837#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 851#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 761#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 762#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 859#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 838#L449 assume !(0 != start_simulation_~tmp~3#1); 796#L432-2 [2024-11-13 15:36:20,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2024-11-13 15:36:20,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942143103] [2024-11-13 15:36:20,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942143103] [2024-11-13 15:36:20,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942143103] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:36:20,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763994282] [2024-11-13 15:36:20,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,717 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:20,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,717 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 3 times [2024-11-13 15:36:20,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346631330] [2024-11-13 15:36:20,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:20,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:20,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:20,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346631330] [2024-11-13 15:36:20,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346631330] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:20,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:20,843 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:20,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340618843] [2024-11-13 15:36:20,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:20,844 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:20,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:20,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:36:20,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:36:20,845 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:20,922 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2024-11-13 15:36:20,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2024-11-13 15:36:20,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2024-11-13 15:36:20,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:20,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:20,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2024-11-13 15:36:20,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:20,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-11-13 15:36:20,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2024-11-13 15:36:20,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:20,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:20,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2024-11-13 15:36:20,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-11-13 15:36:20,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:36:20,945 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2024-11-13 15:36:20,945 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:36:20,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2024-11-13 15:36:20,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:20,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:20,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:20,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:20,948 INFO L745 eck$LassoCheckResult]: Stem: 1034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1056#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1087#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1075#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1076#L137-2 ~b0_req_up~0 := 0; 1103#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1107#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1036#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1037#L152-2 ~b1_req_up~0 := 0; 1009#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1010#L219-1 assume !(1 == ~d0_req_up~0); 1057#L226-1 assume !(1 == ~d1_req_up~0); 1059#L233-1 assume !(1 == ~z_req_up~0); 1080#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1011#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1012#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1081#L321 assume !(0 == ~b0_ev~0); 1082#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 996#L336-1 assume !(0 == ~z_ev~0); 997#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1090#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1091#L390 assume !(0 != activate_threads_~tmp~1#1); 1096#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1068#L354 assume !(1 == ~b0_ev~0); 1050#L354-2 assume !(1 == ~b1_ev~0); 1051#L359-1 assume !(1 == ~d0_ev~0); 1054#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1055#L369-1 assume !(1 == ~z_ev~0); 1061#L374-1 assume { :end_inline_reset_delta_events } true; 1042#L432-2 [2024-11-13 15:36:20,949 INFO L747 eck$LassoCheckResult]: Loop: 1042#L432-2 assume !false; 1043#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 994#L295 assume !false; 995#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1005#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1006#L290 assume !(0 != eval_~tmp___0~0#1); 1095#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1093#L212-3 assume !(1 == ~b0_req_up~0); 1046#L212-5 assume !(1 == ~b1_req_up~0); 1053#L219-3 assume !(1 == ~d0_req_up~0); 991#L226-3 assume !(1 == ~d1_req_up~0); 992#L233-3 assume !(1 == ~z_req_up~0); 1013#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1014#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1077#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1078#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1064#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1003#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1004#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1015#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1033#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1060#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 998#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 999#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1039#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1092#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1089#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1062#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1063#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1083#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1097#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1007#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1008#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1105#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1084#L449 assume !(0 != start_simulation_~tmp~3#1); 1042#L432-2 [2024-11-13 15:36:20,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:20,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2024-11-13 15:36:20,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:20,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931521931] [2024-11-13 15:36:20,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:20,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:20,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931521931] [2024-11-13 15:36:21,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931521931] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:21,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067498535] [2024-11-13 15:36:21,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,033 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:21,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,034 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 4 times [2024-11-13 15:36:21,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885533067] [2024-11-13 15:36:21,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885533067] [2024-11-13 15:36:21,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885533067] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:21,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996634376] [2024-11-13 15:36:21,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,130 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:21,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:21,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:21,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:21,131 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:21,156 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2024-11-13 15:36:21,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2024-11-13 15:36:21,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2024-11-13 15:36:21,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:21,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:21,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2024-11-13 15:36:21,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:21,161 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-11-13 15:36:21,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2024-11-13 15:36:21,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:21,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2024-11-13 15:36:21,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-11-13 15:36:21,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:21,168 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2024-11-13 15:36:21,168 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:36:21,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2024-11-13 15:36:21,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:21,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:21,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,171 INFO L745 eck$LassoCheckResult]: Stem: 1277#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1299#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1330#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1318#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1319#L137-2 ~b0_req_up~0 := 0; 1346#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1350#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1279#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1280#L152-2 ~b1_req_up~0 := 0; 1252#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1253#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1259#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1260#L167-2 ~d0_req_up~0 := 0; 1274#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1300#L226-1 assume !(1 == ~d1_req_up~0); 1302#L233-1 assume !(1 == ~z_req_up~0); 1323#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1254#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1255#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1324#L321 assume !(0 == ~b0_ev~0); 1325#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1239#L336-1 assume !(0 == ~z_ev~0); 1240#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1333#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1334#L390 assume !(0 != activate_threads_~tmp~1#1); 1339#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1311#L354 assume !(1 == ~b0_ev~0); 1293#L354-2 assume !(1 == ~b1_ev~0); 1294#L359-1 assume !(1 == ~d0_ev~0); 1297#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1298#L369-1 assume !(1 == ~z_ev~0); 1304#L374-1 assume { :end_inline_reset_delta_events } true; 1285#L432-2 [2024-11-13 15:36:21,171 INFO L747 eck$LassoCheckResult]: Loop: 1285#L432-2 assume !false; 1286#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1237#L295 assume !false; 1238#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1248#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1249#L290 assume !(0 != eval_~tmp___0~0#1); 1338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1336#L212-3 assume !(1 == ~b0_req_up~0); 1289#L212-5 assume !(1 == ~b1_req_up~0); 1296#L219-3 assume !(1 == ~d0_req_up~0); 1234#L226-3 assume !(1 == ~d1_req_up~0); 1235#L233-3 assume !(1 == ~z_req_up~0); 1256#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1257#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1320#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1321#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1307#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1246#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1247#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1258#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1276#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1303#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1241#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1242#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1282#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1335#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1332#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1305#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1306#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1326#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1340#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1250#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1348#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1327#L449 assume !(0 != start_simulation_~tmp~3#1); 1285#L432-2 [2024-11-13 15:36:21,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,172 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2024-11-13 15:36:21,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245461962] [2024-11-13 15:36:21,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245461962] [2024-11-13 15:36:21,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245461962] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:36:21,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004541668] [2024-11-13 15:36:21,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,269 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:21,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,269 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 5 times [2024-11-13 15:36:21,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804451802] [2024-11-13 15:36:21,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804451802] [2024-11-13 15:36:21,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804451802] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:21,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103203909] [2024-11-13 15:36:21,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,334 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:21,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:21,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:36:21,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:36:21,335 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:21,404 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2024-11-13 15:36:21,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2024-11-13 15:36:21,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2024-11-13 15:36:21,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:21,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:21,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2024-11-13 15:36:21,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:21,411 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-11-13 15:36:21,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2024-11-13 15:36:21,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:21,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2024-11-13 15:36:21,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-11-13 15:36:21,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:36:21,418 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2024-11-13 15:36:21,418 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:36:21,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2024-11-13 15:36:21,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:21,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:21,420 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,421 INFO L745 eck$LassoCheckResult]: Stem: 1523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1576#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1564#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1565#L137-2 ~b0_req_up~0 := 0; 1592#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1596#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1525#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1526#L152-2 ~b1_req_up~0 := 0; 1498#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1499#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1505#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1506#L167-2 ~d0_req_up~0 := 0; 1520#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1546#L226-1 assume !(1 == ~d1_req_up~0); 1548#L233-1 assume !(1 == ~z_req_up~0); 1569#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1500#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1501#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570#L321 assume !(0 == ~b0_ev~0); 1571#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1485#L336-1 assume !(0 == ~z_ev~0); 1486#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1579#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1580#L390 assume !(0 != activate_threads_~tmp~1#1); 1585#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1557#L354 assume !(1 == ~b0_ev~0); 1539#L354-2 assume !(1 == ~b1_ev~0); 1540#L359-1 assume !(1 == ~d0_ev~0); 1543#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1544#L369-1 assume !(1 == ~z_ev~0); 1550#L374-1 assume { :end_inline_reset_delta_events } true; 1531#L432-2 [2024-11-13 15:36:21,421 INFO L747 eck$LassoCheckResult]: Loop: 1531#L432-2 assume !false; 1532#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1483#L295 assume !false; 1484#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1495#L290 assume !(0 != eval_~tmp___0~0#1); 1584#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1582#L212-3 assume !(1 == ~b0_req_up~0); 1535#L212-5 assume !(1 == ~b1_req_up~0); 1542#L219-3 assume !(1 == ~d0_req_up~0); 1480#L226-3 assume !(1 == ~d1_req_up~0); 1481#L233-3 assume !(1 == ~z_req_up~0); 1502#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1503#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1566#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1567#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1553#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1492#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1493#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1504#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1522#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1549#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1487#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1488#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1528#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1581#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1578#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1551#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1552#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1572#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1586#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1496#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1497#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1594#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1573#L449 assume !(0 != start_simulation_~tmp~3#1); 1531#L432-2 [2024-11-13 15:36:21,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,422 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2024-11-13 15:36:21,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307618690] [2024-11-13 15:36:21,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307618690] [2024-11-13 15:36:21,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307618690] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:21,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546116530] [2024-11-13 15:36:21,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:21,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,468 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 6 times [2024-11-13 15:36:21,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175678634] [2024-11-13 15:36:21,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175678634] [2024-11-13 15:36:21,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175678634] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:21,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185713044] [2024-11-13 15:36:21,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,545 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:21,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:21,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:21,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:21,546 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:21,564 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2024-11-13 15:36:21,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2024-11-13 15:36:21,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2024-11-13 15:36:21,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2024-11-13 15:36:21,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2024-11-13 15:36:21,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2024-11-13 15:36:21,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:21,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-11-13 15:36:21,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2024-11-13 15:36:21,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2024-11-13 15:36:21,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2024-11-13 15:36:21,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-11-13 15:36:21,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:21,578 INFO L424 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2024-11-13 15:36:21,578 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:36:21,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2024-11-13 15:36:21,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-13 15:36:21,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:21,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:21,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,581 INFO L745 eck$LassoCheckResult]: Stem: 1766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1788#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1819#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1806#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1807#L137-2 ~b0_req_up~0 := 0; 1835#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 1839#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1768#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1769#L152-2 ~b1_req_up~0 := 0; 1741#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1742#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1748#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1749#L167-2 ~d0_req_up~0 := 0; 1763#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 1789#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1790#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 1810#L233-1 assume !(1 == ~z_req_up~0); 1812#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1743#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1744#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813#L321 assume !(0 == ~b0_ev~0); 1814#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1728#L336-1 assume !(0 == ~z_ev~0); 1729#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1822#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1823#L390 assume !(0 != activate_threads_~tmp~1#1); 1828#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1799#L354 assume !(1 == ~b0_ev~0); 1782#L354-2 assume !(1 == ~b1_ev~0); 1783#L359-1 assume !(1 == ~d0_ev~0); 1786#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1787#L369-1 assume !(1 == ~z_ev~0); 1792#L374-1 assume { :end_inline_reset_delta_events } true; 1774#L432-2 [2024-11-13 15:36:21,581 INFO L747 eck$LassoCheckResult]: Loop: 1774#L432-2 assume !false; 1775#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1726#L295 assume !false; 1727#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1737#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1738#L290 assume !(0 != eval_~tmp___0~0#1); 1827#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1825#L212-3 assume !(1 == ~b0_req_up~0); 1778#L212-5 assume !(1 == ~b1_req_up~0); 1785#L219-3 assume !(1 == ~d0_req_up~0); 1723#L226-3 assume !(1 == ~d1_req_up~0); 1724#L233-3 assume !(1 == ~z_req_up~0); 1745#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1746#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1808#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1809#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1795#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1735#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1736#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1747#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1765#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1791#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1730#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1731#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1771#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1824#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1821#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1793#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1794#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1815#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1829#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1739#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1740#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1837#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1816#L449 assume !(0 != start_simulation_~tmp~3#1); 1774#L432-2 [2024-11-13 15:36:21,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,582 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2024-11-13 15:36:21,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631304547] [2024-11-13 15:36:21,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631304547] [2024-11-13 15:36:21,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631304547] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:36:21,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074129680] [2024-11-13 15:36:21,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,731 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:21,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,731 INFO L85 PathProgramCache]: Analyzing trace with hash -220677599, now seen corresponding path program 7 times [2024-11-13 15:36:21,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973545636] [2024-11-13 15:36:21,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:21,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:21,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:21,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973545636] [2024-11-13 15:36:21,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973545636] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:21,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:21,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:21,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427856034] [2024-11-13 15:36:21,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:21,809 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:21,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:21,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:36:21,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:36:21,810 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:21,865 INFO L93 Difference]: Finished difference Result 122 states and 182 transitions. [2024-11-13 15:36:21,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 182 transitions. [2024-11-13 15:36:21,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2024-11-13 15:36:21,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 122 states and 182 transitions. [2024-11-13 15:36:21,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2024-11-13 15:36:21,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2024-11-13 15:36:21,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 182 transitions. [2024-11-13 15:36:21,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:36:21,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122 states and 182 transitions. [2024-11-13 15:36:21,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 182 transitions. [2024-11-13 15:36:21,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 120. [2024-11-13 15:36:21,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:21,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2024-11-13 15:36:21,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2024-11-13 15:36:21,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:36:21,879 INFO L424 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2024-11-13 15:36:21,879 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:36:21,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2024-11-13 15:36:21,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2024-11-13 15:36:21,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:21,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:21,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:21,882 INFO L745 eck$LassoCheckResult]: Stem: 2016#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2069#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2056#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2057#L137-2 ~b0_req_up~0 := 0; 2085#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 2089#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2018#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2019#L152-2 ~b1_req_up~0 := 0; 1990#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 1991#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1997#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1998#L167-2 ~d0_req_up~0 := 0; 2013#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 2039#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2040#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2003#L182-2 ~d1_req_up~0 := 0; 2004#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 2060#L233-1 assume !(1 == ~z_req_up~0); 2062#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1992#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1993#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2063#L321 assume !(0 == ~b0_ev~0); 2064#L321-2 assume !(0 == ~b1_ev~0); 2009#L326-1 assume !(0 == ~d0_ev~0); 2010#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1977#L336-1 assume !(0 == ~z_ev~0); 1978#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2088#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2001#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2072#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2073#L390 assume !(0 != activate_threads_~tmp~1#1); 2078#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2049#L354 assume !(1 == ~b0_ev~0); 2032#L354-2 assume !(1 == ~b1_ev~0); 2033#L359-1 assume !(1 == ~d0_ev~0); 2036#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2037#L369-1 assume !(1 == ~z_ev~0); 2042#L374-1 assume { :end_inline_reset_delta_events } true; 2024#L432-2 [2024-11-13 15:36:21,882 INFO L747 eck$LassoCheckResult]: Loop: 2024#L432-2 assume !false; 2025#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1975#L295 assume !false; 1976#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2005#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2007#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2091#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2090#L290 assume !(0 != eval_~tmp___0~0#1); 2077#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2075#L212-3 assume !(1 == ~b0_req_up~0); 2028#L212-5 assume !(1 == ~b1_req_up~0); 2035#L219-3 assume !(1 == ~d0_req_up~0); 1972#L226-3 assume !(1 == ~d1_req_up~0); 1973#L233-3 assume !(1 == ~z_req_up~0); 1994#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1995#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2058#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2059#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2045#L331-3 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1984#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1985#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1996#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2015#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2041#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1979#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1980#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2008#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2021#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2082#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2074#L364-3 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2071#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2043#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2044#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2065#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2079#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1988#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1989#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2087#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2066#L449 assume !(0 != start_simulation_~tmp~3#1); 2024#L432-2 [2024-11-13 15:36:21,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:21,886 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2024-11-13 15:36:21,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:21,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727331588] [2024-11-13 15:36:21,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:21,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:21,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:22,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:22,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:22,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727331588] [2024-11-13 15:36:22,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727331588] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:22,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:22,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:36:22,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977727932] [2024-11-13 15:36:22,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:22,007 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:22,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:22,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1064683101, now seen corresponding path program 1 times [2024-11-13 15:36:22,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:22,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323696933] [2024-11-13 15:36:22,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:22,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:22,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:22,031 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:22,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:22,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:22,751 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:36:22,752 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:36:22,752 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:36:22,752 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:36:22,752 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 15:36:22,752 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:22,753 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:36:22,753 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:36:22,753 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-11-13 15:36:22,753 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:36:22,753 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:36:22,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:22,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,260 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:36:23,261 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 15:36:23,264 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,264 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:23,269 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:23,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 15:36:23,273 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:36:23,273 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:36:23,301 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:36:23,301 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:36:23,325 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 15:36:23,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,326 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:23,329 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:23,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 15:36:23,337 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:36:23,337 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:36:23,386 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 15:36:23,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,386 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:23,388 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:23,390 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 15:36:23,391 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 15:36:23,391 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:36:23,411 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 15:36:23,434 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 15:36:23,435 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:36:23,435 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:36:23,435 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:36:23,435 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:36:23,435 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 15:36:23,435 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,435 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:36:23,435 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:36:23,435 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-11-13 15:36:23,435 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:36:23,435 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:36:23,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,467 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,531 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,543 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,553 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,558 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,578 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:23,912 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:36:23,919 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 15:36:23,920 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,920 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:23,923 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:23,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 15:36:23,928 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:23,948 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:23,948 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:23,949 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:23,949 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:23,949 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:23,961 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:23,961 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:23,967 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:36:23,989 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-13 15:36:23,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:23,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:23,993 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:23,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 15:36:23,997 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:24,015 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:24,015 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:24,015 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:24,016 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:24,016 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:24,017 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:24,017 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:24,021 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:36:24,043 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 15:36:24,043 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:24,043 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:24,046 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:24,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 15:36:24,050 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:24,068 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:24,068 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:24,068 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:24,068 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:24,068 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:24,069 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:24,069 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:24,071 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:36:24,094 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 15:36:24,094 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:24,095 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:24,097 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:24,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 15:36:24,101 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:24,119 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:24,119 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:24,119 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:24,119 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:24,119 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:24,121 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:24,121 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:24,126 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 15:36:24,133 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 15:36:24,136 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 15:36:24,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:24,139 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:24,142 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:24,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 15:36:24,144 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 15:36:24,145 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 15:36:24,145 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 15:36:24,145 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2024-11-13 15:36:24,171 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 15:36:24,174 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 15:36:24,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:24,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:24,279 INFO L255 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 15:36:24,281 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:36:24,354 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 15:36:24,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:24,448 INFO L255 TraceCheckSpWp]: Trace formula consists of 96 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 15:36:24,449 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:36:24,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:24,636 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 15:36:24,638 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:24,758 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 420 transitions. Complement of second has 5 states. [2024-11-13 15:36:24,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 15:36:24,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:24,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2024-11-13 15:36:24,772 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2024-11-13 15:36:24,774 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:24,774 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2024-11-13 15:36:24,779 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:24,779 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2024-11-13 15:36:24,782 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:24,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 420 transitions. [2024-11-13 15:36:24,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-11-13 15:36:24,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 420 transitions. [2024-11-13 15:36:24,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2024-11-13 15:36:24,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2024-11-13 15:36:24,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 420 transitions. [2024-11-13 15:36:24,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:24,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 420 transitions. [2024-11-13 15:36:24,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 420 transitions. [2024-11-13 15:36:24,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2024-11-13 15:36:24,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:24,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2024-11-13 15:36:24,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2024-11-13 15:36:24,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:24,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:36:24,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:36:24,810 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:24,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:24,862 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2024-11-13 15:36:24,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2024-11-13 15:36:24,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-11-13 15:36:24,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2024-11-13 15:36:24,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2024-11-13 15:36:24,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2024-11-13 15:36:24,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2024-11-13 15:36:24,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:24,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-11-13 15:36:24,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2024-11-13 15:36:24,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2024-11-13 15:36:24,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:24,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2024-11-13 15:36:24,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-11-13 15:36:24,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:36:24,890 INFO L424 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2024-11-13 15:36:24,890 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:36:24,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2024-11-13 15:36:24,892 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2024-11-13 15:36:24,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:24,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:24,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:24,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:24,898 INFO L745 eck$LassoCheckResult]: Stem: 3242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3279#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3332#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3311#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3312#L137-2 ~b0_req_up~0 := 0; 3368#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 3374#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3244#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3245#L152-2 ~b1_req_up~0 := 0; 3204#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 3205#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3216#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3217#L167-2 ~d0_req_up~0 := 0; 3237#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 3282#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3283#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3227#L182-2 ~d1_req_up~0 := 0; 3228#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 3317#L233-1 assume !(1 == ~z_req_up~0); 3319#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3206#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3207#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3320#L321 assume !(0 == ~b0_ev~0); 3321#L321-2 assume !(0 == ~b1_ev~0); 3235#L326-1 assume !(0 == ~d0_ev~0); 3236#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3182#L336-1 assume !(0 == ~z_ev~0); 3183#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3373#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3219#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3341#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3342#L390 assume !(0 != activate_threads_~tmp~1#1); 3351#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3299#L354 assume !(1 == ~b0_ev~0); 3275#L354-2 assume !(1 == ~b1_ev~0); 3276#L359-1 assume !(1 == ~d0_ev~0); 3277#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3278#L369-1 assume !(1 == ~z_ev~0); 3284#L374-1 assume { :end_inline_reset_delta_events } true; 3357#L432-2 assume !false; 3255#L433 [2024-11-13 15:36:24,898 INFO L747 eck$LassoCheckResult]: Loop: 3255#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3174#L295 assume !false; 3175#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3221#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3223#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3379#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3378#L290 assume !(0 != eval_~tmp___0~0#1); 3349#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3343#L212-3 assume !(1 == ~b0_req_up~0); 3261#L212-5 assume !(1 == ~b1_req_up~0); 3347#L219-3 assume !(1 == ~d0_req_up~0); 3348#L226-3 assume !(1 == ~d1_req_up~0); 3383#L233-3 assume !(1 == ~z_req_up~0); 3208#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3209#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3337#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3381#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3289#L331-3 assume !(0 == ~d1_ev~0); 3192#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 3193#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3212#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3239#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3280#is_method1_triggered_returnLabel#2 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3178#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3179#L390-5 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3229#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3246#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3358#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3338#L364-3 assume !(1 == ~d1_ev~0); 3335#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3285#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3286#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3322#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3353#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3200#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3201#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3371#stop_simulation_returnLabel#1 start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3324#L449 assume !(0 != start_simulation_~tmp~3#1); 3254#L432-2 assume !false; 3255#L433 [2024-11-13 15:36:24,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:24,899 INFO L85 PathProgramCache]: Analyzing trace with hash 750743387, now seen corresponding path program 1 times [2024-11-13 15:36:24,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:24,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798632863] [2024-11-13 15:36:24,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:24,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:24,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:24,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:24,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:24,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798632863] [2024-11-13 15:36:24,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798632863] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:24,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:24,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:24,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408742713] [2024-11-13 15:36:24,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:24,975 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:24,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:24,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1535310851, now seen corresponding path program 1 times [2024-11-13 15:36:24,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:24,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807644899] [2024-11-13 15:36:24,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:24,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:24,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:24,985 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:24,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:24,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:25,491 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:36:25,491 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:36:25,491 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:36:25,491 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:36:25,491 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 15:36:25,491 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:25,492 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:36:25,492 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:36:25,492 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2024-11-13 15:36:25,492 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:36:25,492 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:36:25,494 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,505 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,522 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,526 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,557 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,585 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,880 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:36:25,880 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 15:36:25,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:25,881 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:25,883 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:25,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 15:36:25,895 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:36:25,895 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:36:25,931 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-13 15:36:25,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:25,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:25,934 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:25,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 15:36:25,937 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 15:36:25,937 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:36:25,962 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 15:36:25,984 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-13 15:36:25,984 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:36:25,985 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:36:25,985 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:36:25,985 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:36:25,985 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 15:36:25,985 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:25,985 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:36:25,985 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:36:25,985 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2024-11-13 15:36:25,985 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:36:25,985 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:36:25,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:25,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,031 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,041 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,045 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,050 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,054 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,060 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,066 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,097 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:36:26,371 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:36:26,372 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 15:36:26,372 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:26,372 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:26,374 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:26,378 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 15:36:26,379 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:26,397 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:26,397 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:26,397 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:26,398 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:26,398 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:26,399 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:26,399 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:26,404 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:36:26,423 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-13 15:36:26,424 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:26,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:26,426 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:26,428 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 15:36:26,428 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:36:26,442 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:36:26,442 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:36:26,442 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:36:26,442 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:36:26,442 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:36:26,443 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:36:26,443 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:36:26,446 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 15:36:26,451 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 15:36:26,451 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 15:36:26,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:36:26,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:36:26,454 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:36:26,455 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 15:36:26,456 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 15:36:26,456 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 15:36:26,456 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 15:36:26,456 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2024-11-13 15:36:26,476 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 15:36:26,477 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 15:36:26,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:26,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:26,546 INFO L255 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 15:36:26,547 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:36:26,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:26,649 INFO L255 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 15:36:26,650 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:36:26,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:26,809 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 15:36:26,809 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:26,887 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148. Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 734 states and 1142 transitions. Complement of second has 5 states. [2024-11-13 15:36:26,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 15:36:26,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:26,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2024-11-13 15:36:26,889 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 39 letters. [2024-11-13 15:36:26,890 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:26,890 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 80 letters. Loop has 39 letters. [2024-11-13 15:36:26,890 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:26,890 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 78 letters. [2024-11-13 15:36:26,891 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:36:26,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 734 states and 1142 transitions. [2024-11-13 15:36:26,898 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2024-11-13 15:36:26,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 734 states to 734 states and 1142 transitions. [2024-11-13 15:36:26,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346 [2024-11-13 15:36:26,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2024-11-13 15:36:26,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 734 states and 1142 transitions. [2024-11-13 15:36:26,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:26,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 734 states and 1142 transitions. [2024-11-13 15:36:26,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 734 states and 1142 transitions. [2024-11-13 15:36:26,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 734 to 729. [2024-11-13 15:36:26,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.5541838134430728) internal successors, (1133), 728 states have internal predecessors, (1133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:26,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1133 transitions. [2024-11-13 15:36:26,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1133 transitions. [2024-11-13 15:36:26,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:26,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:26,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:26,933 INFO L87 Difference]: Start difference. First operand 729 states and 1133 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:26,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:26,979 INFO L93 Difference]: Finished difference Result 909 states and 1378 transitions. [2024-11-13 15:36:26,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 909 states and 1378 transitions. [2024-11-13 15:36:26,991 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2024-11-13 15:36:26,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 909 states to 909 states and 1378 transitions. [2024-11-13 15:36:26,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2024-11-13 15:36:26,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2024-11-13 15:36:26,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 909 states and 1378 transitions. [2024-11-13 15:36:27,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:27,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2024-11-13 15:36:27,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1378 transitions. [2024-11-13 15:36:27,053 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-13 15:36:27,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 909. [2024-11-13 15:36:27,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.515951595159516) internal successors, (1378), 908 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1378 transitions. [2024-11-13 15:36:27,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2024-11-13 15:36:27,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:27,067 INFO L424 stractBuchiCegarLoop]: Abstraction has 909 states and 1378 transitions. [2024-11-13 15:36:27,067 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:36:27,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1378 transitions. [2024-11-13 15:36:27,074 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2024-11-13 15:36:27,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:27,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:27,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,075 INFO L745 eck$LassoCheckResult]: Stem: 6145#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 6146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 6181#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6239#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 6217#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 6218#L137-2 ~b0_req_up~0 := 0; 6283#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 6292#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 6147#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 6148#L152-2 ~b1_req_up~0 := 0; 6106#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 6107#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6116#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6117#L167-2 ~d0_req_up~0 := 0; 6140#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 6182#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 6183#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6124#L182-2 ~d1_req_up~0 := 0; 6125#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 6223#L233-1 assume !(1 == ~z_req_up~0); 6225#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6108#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6109#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6226#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 6227#L321-2 assume !(0 == ~b1_ev~0); 6134#L326-1 assume !(0 == ~d0_ev~0); 6135#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 6081#L336-1 assume !(0 == ~z_ev~0); 6082#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 6289#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 6122#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 6245#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6246#L390 assume !(0 != activate_threads_~tmp~1#1); 6260#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6203#L354 assume !(1 == ~b0_ev~0); 6173#L354-2 assume !(1 == ~b1_ev~0); 6174#L359-1 assume !(1 == ~d0_ev~0); 6179#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 6180#L369-1 assume !(1 == ~z_ev~0); 6186#L374-1 assume { :end_inline_reset_delta_events } true; 6266#L432-2 assume !false; 6524#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 6119#L295 [2024-11-13 15:36:27,075 INFO L747 eck$LassoCheckResult]: Loop: 6119#L295 assume !false; 6374#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 6375#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 6369#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 6370#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6365#L290 assume 0 != eval_~tmp___0~0#1; 6284#L290-1 assume !(0 == ~comp_m1_st~0); 6119#L295 [2024-11-13 15:36:27,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,076 INFO L85 PathProgramCache]: Analyzing trace with hash -807814842, now seen corresponding path program 1 times [2024-11-13 15:36:27,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346358621] [2024-11-13 15:36:27,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346358621] [2024-11-13 15:36:27,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346358621] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,134 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:27,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334464362] [2024-11-13 15:36:27,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,135 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:27,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1003059716, now seen corresponding path program 1 times [2024-11-13 15:36:27,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147633745] [2024-11-13 15:36:27,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147633745] [2024-11-13 15:36:27,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147633745] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:36:27,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815914909] [2024-11-13 15:36:27,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,199 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:27,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:27,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:36:27,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:36:27,200 INFO L87 Difference]: Start difference. First operand 909 states and 1378 transitions. cyclomatic complexity: 478 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:27,255 INFO L93 Difference]: Finished difference Result 927 states and 1387 transitions. [2024-11-13 15:36:27,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 927 states and 1387 transitions. [2024-11-13 15:36:27,264 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2024-11-13 15:36:27,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 927 states to 927 states and 1387 transitions. [2024-11-13 15:36:27,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 434 [2024-11-13 15:36:27,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 434 [2024-11-13 15:36:27,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 927 states and 1387 transitions. [2024-11-13 15:36:27,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:27,275 INFO L218 hiAutomatonCegarLoop]: Abstraction has 927 states and 1387 transitions. [2024-11-13 15:36:27,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states and 1387 transitions. [2024-11-13 15:36:27,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 909. [2024-11-13 15:36:27,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.506050605060506) internal successors, (1369), 908 states have internal predecessors, (1369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1369 transitions. [2024-11-13 15:36:27,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1369 transitions. [2024-11-13 15:36:27,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:36:27,306 INFO L424 stractBuchiCegarLoop]: Abstraction has 909 states and 1369 transitions. [2024-11-13 15:36:27,306 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:36:27,306 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1369 transitions. [2024-11-13 15:36:27,312 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2024-11-13 15:36:27,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:27,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:27,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,315 INFO L745 eck$LassoCheckResult]: Stem: 7991#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 7992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 8028#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8086#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 8064#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 8065#L137-2 ~b0_req_up~0 := 0; 8131#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 8141#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 7993#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 7994#L152-2 ~b1_req_up~0 := 0; 7951#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 7952#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 7962#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 7963#L167-2 ~d0_req_up~0 := 0; 7986#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 8029#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 8030#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 7970#L182-2 ~d1_req_up~0 := 0; 7971#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 8070#L233-1 assume !(1 == ~z_req_up~0); 8072#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7953#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 7954#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8073#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 8074#L321-2 assume !(0 == ~b1_ev~0); 7980#L326-1 assume !(0 == ~d0_ev~0); 7981#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 7926#L336-1 assume !(0 == ~z_ev~0); 7927#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 8137#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 7968#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 8093#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 8094#L390 assume !(0 != activate_threads_~tmp~1#1); 8108#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8050#L354 assume !(1 == ~b0_ev~0); 8020#L354-2 assume !(1 == ~b1_ev~0); 8021#L359-1 assume !(1 == ~d0_ev~0); 8026#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 8027#L369-1 assume !(1 == ~z_ev~0); 8033#L374-1 assume { :end_inline_reset_delta_events } true; 8114#L432-2 assume !false; 8355#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 7965#L295 [2024-11-13 15:36:27,315 INFO L747 eck$LassoCheckResult]: Loop: 7965#L295 assume !false; 8210#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 8208#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 8209#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 8232#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8229#L290 assume 0 != eval_~tmp___0~0#1; 8132#L290-1 assume !(0 == ~comp_m1_st~0); 7965#L295 [2024-11-13 15:36:27,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,316 INFO L85 PathProgramCache]: Analyzing trace with hash -807814842, now seen corresponding path program 2 times [2024-11-13 15:36:27,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596728825] [2024-11-13 15:36:27,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596728825] [2024-11-13 15:36:27,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596728825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:27,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115077823] [2024-11-13 15:36:27,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,383 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:27,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1004906758, now seen corresponding path program 1 times [2024-11-13 15:36:27,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72552220] [2024-11-13 15:36:27,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72552220] [2024-11-13 15:36:27,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72552220] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:36:27,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515613894] [2024-11-13 15:36:27,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,400 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:36:27,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:27,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:27,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:27,400 INFO L87 Difference]: Start difference. First operand 909 states and 1369 transitions. cyclomatic complexity: 469 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:27,445 INFO L93 Difference]: Finished difference Result 1111 states and 1643 transitions. [2024-11-13 15:36:27,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1111 states and 1643 transitions. [2024-11-13 15:36:27,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-13 15:36:27,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1111 states to 1111 states and 1643 transitions. [2024-11-13 15:36:27,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 526 [2024-11-13 15:36:27,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 526 [2024-11-13 15:36:27,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1111 states and 1643 transitions. [2024-11-13 15:36:27,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:27,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2024-11-13 15:36:27,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1111 states and 1643 transitions. [2024-11-13 15:36:27,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1111 to 1111. [2024-11-13 15:36:27,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1111 states, 1111 states have (on average 1.478847884788479) internal successors, (1643), 1110 states have internal predecessors, (1643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1111 states to 1111 states and 1643 transitions. [2024-11-13 15:36:27,498 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2024-11-13 15:36:27,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:27,500 INFO L424 stractBuchiCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2024-11-13 15:36:27,500 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:36:27,500 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1111 states and 1643 transitions. [2024-11-13 15:36:27,507 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-13 15:36:27,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:27,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:27,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,509 INFO L745 eck$LassoCheckResult]: Stem: 10021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 10022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 10059#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10119#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 10097#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 10098#L137-2 ~b0_req_up~0 := 0; 10170#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 10184#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 10023#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 10024#L152-2 ~b1_req_up~0 := 0; 9979#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 9980#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 9990#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 9991#L167-2 ~d0_req_up~0 := 0; 10014#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 10060#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 10061#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 9999#L182-2 ~d1_req_up~0 := 0; 10000#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 10103#L233-1 assume !(1 == ~z_req_up~0); 10105#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9981#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 9982#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10106#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 10107#L321-2 assume !(0 == ~b1_ev~0); 10008#L326-1 assume !(0 == ~d0_ev~0); 10009#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 9953#L336-1 assume !(0 == ~z_ev~0); 9954#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 10179#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9997#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 10125#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 10126#L390 assume !(0 != activate_threads_~tmp~1#1); 10145#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10173#L354 assume !(1 == ~b0_ev~0); 10051#L354-2 assume !(1 == ~b1_ev~0); 10052#L359-1 assume !(1 == ~d0_ev~0); 10057#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 10058#L369-1 assume !(1 == ~z_ev~0); 10151#L374-1 assume { :end_inline_reset_delta_events } true; 10152#L432-2 assume !false; 10783#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 10283#L295 [2024-11-13 15:36:27,510 INFO L747 eck$LassoCheckResult]: Loop: 10283#L295 assume !false; 10137#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 10001#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 10002#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 10300#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10294#L290 assume 0 != eval_~tmp___0~0#1; 10284#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10282#L299 assume !(0 != eval_~tmp~0#1); 10283#L295 [2024-11-13 15:36:27,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1230516668, now seen corresponding path program 1 times [2024-11-13 15:36:27,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389428203] [2024-11-13 15:36:27,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389428203] [2024-11-13 15:36:27,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389428203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:36:27,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857422383] [2024-11-13 15:36:27,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,592 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:27,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,592 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 1 times [2024-11-13 15:36:27,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8674726] [2024-11-13 15:36:27,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:27,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:27,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:27,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:27,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:27,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:36:27,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:36:27,640 INFO L87 Difference]: Start difference. First operand 1111 states and 1643 transitions. cyclomatic complexity: 541 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:27,684 INFO L93 Difference]: Finished difference Result 1097 states and 1619 transitions. [2024-11-13 15:36:27,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1097 states and 1619 transitions. [2024-11-13 15:36:27,714 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-13 15:36:27,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1097 states to 1097 states and 1619 transitions. [2024-11-13 15:36:27,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2024-11-13 15:36:27,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2024-11-13 15:36:27,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1097 states and 1619 transitions. [2024-11-13 15:36:27,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:27,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2024-11-13 15:36:27,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1097 states and 1619 transitions. [2024-11-13 15:36:27,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1097 to 1097. [2024-11-13 15:36:27,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1097 states, 1097 states have (on average 1.4758432087511395) internal successors, (1619), 1096 states have internal predecessors, (1619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1097 states to 1097 states and 1619 transitions. [2024-11-13 15:36:27,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2024-11-13 15:36:27,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:36:27,756 INFO L424 stractBuchiCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2024-11-13 15:36:27,756 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:36:27,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1097 states and 1619 transitions. [2024-11-13 15:36:27,764 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2024-11-13 15:36:27,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:27,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:27,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,765 INFO L745 eck$LassoCheckResult]: Stem: 12233#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 12234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 12273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12333#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 12309#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 12310#L137-2 ~b0_req_up~0 := 0; 12393#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 12403#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 12235#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 12236#L152-2 ~b1_req_up~0 := 0; 12196#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 12197#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 12206#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 12207#L167-2 ~d0_req_up~0 := 0; 12228#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 12274#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 12275#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 12213#L182-2 ~d1_req_up~0 := 0; 12214#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 12315#L233-1 assume !(1 == ~z_req_up~0); 12317#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12198#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 12199#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12318#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 12319#L321-2 assume !(0 == ~b1_ev~0); 12222#L326-1 assume !(0 == ~d0_ev~0); 12223#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 12170#L336-1 assume !(0 == ~z_ev~0); 12171#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 12399#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 12211#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 12342#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 12343#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 12362#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12396#L354 assume !(1 == ~b0_ev~0); 12265#L354-2 assume !(1 == ~b1_ev~0); 12266#L359-1 assume !(1 == ~d0_ev~0); 12271#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 12272#L369-1 assume !(1 == ~z_ev~0); 12371#L374-1 assume { :end_inline_reset_delta_events } true; 12372#L432-2 assume !false; 12737#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 12738#L295 [2024-11-13 15:36:27,765 INFO L747 eck$LassoCheckResult]: Loop: 12738#L295 assume !false; 12850#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 12849#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 12813#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 12848#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12847#L290 assume 0 != eval_~tmp___0~0#1; 12846#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12845#L299 assume !(0 != eval_~tmp~0#1); 12738#L295 [2024-11-13 15:36:27,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,766 INFO L85 PathProgramCache]: Analyzing trace with hash -414787832, now seen corresponding path program 1 times [2024-11-13 15:36:27,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147876180] [2024-11-13 15:36:27,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:27,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:27,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:27,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147876180] [2024-11-13 15:36:27,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147876180] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:27,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:27,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:27,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365853481] [2024-11-13 15:36:27,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:27,803 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:27,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 2 times [2024-11-13 15:36:27,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666143722] [2024-11-13 15:36:27,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:27,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:27,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:27,812 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:27,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:27,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:27,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:27,844 INFO L87 Difference]: Start difference. First operand 1097 states and 1619 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:27,899 INFO L93 Difference]: Finished difference Result 1394 states and 2020 transitions. [2024-11-13 15:36:27,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1394 states and 2020 transitions. [2024-11-13 15:36:27,911 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2024-11-13 15:36:27,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1394 states to 1394 states and 2020 transitions. [2024-11-13 15:36:27,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 644 [2024-11-13 15:36:27,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 644 [2024-11-13 15:36:27,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1394 states and 2020 transitions. [2024-11-13 15:36:27,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:27,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2024-11-13 15:36:27,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1394 states and 2020 transitions. [2024-11-13 15:36:27,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1394 to 1394. [2024-11-13 15:36:27,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1394 states, 1394 states have (on average 1.449067431850789) internal successors, (2020), 1393 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:27,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1394 states to 1394 states and 2020 transitions. [2024-11-13 15:36:27,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2024-11-13 15:36:27,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:27,963 INFO L424 stractBuchiCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2024-11-13 15:36:27,964 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:36:27,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1394 states and 2020 transitions. [2024-11-13 15:36:27,973 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2024-11-13 15:36:27,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:27,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:27,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:27,976 INFO L745 eck$LassoCheckResult]: Stem: 14730#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 14731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 14769#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14831#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 14806#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 14807#L137-2 ~b0_req_up~0 := 0; 14883#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 14893#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 14732#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 14733#L152-2 ~b1_req_up~0 := 0; 14693#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 14694#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 14706#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 14707#L167-2 ~d0_req_up~0 := 0; 14725#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 14770#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 14771#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 14715#L182-2 ~d1_req_up~0 := 0; 14716#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 14812#L233-1 assume !(1 == ~z_req_up~0); 14814#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14695#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 14696#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14815#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 14816#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 14723#L326-1 assume !(0 == ~d0_ev~0); 14724#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 14667#L336-1 assume !(0 == ~z_ev~0); 14668#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 14891#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 14709#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 14837#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 14838#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 14854#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14886#L354 assume !(1 == ~b0_ev~0); 14765#L354-2 assume !(1 == ~b1_ev~0); 14766#L359-1 assume !(1 == ~d0_ev~0); 14767#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 14768#L369-1 assume !(1 == ~z_ev~0); 14864#L374-1 assume { :end_inline_reset_delta_events } true; 14865#L432-2 assume !false; 15485#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 15486#L295 [2024-11-13 15:36:27,976 INFO L747 eck$LassoCheckResult]: Loop: 15486#L295 assume !false; 15806#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 15805#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 15025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 15804#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15803#L290 assume 0 != eval_~tmp___0~0#1; 15802#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 15801#L299 assume !(0 != eval_~tmp~0#1); 15486#L295 [2024-11-13 15:36:27,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:27,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1579356874, now seen corresponding path program 1 times [2024-11-13 15:36:27,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:27,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648316484] [2024-11-13 15:36:27,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:27,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:27,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:28,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:28,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:28,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648316484] [2024-11-13 15:36:28,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648316484] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:28,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:28,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:28,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402147399] [2024-11-13 15:36:28,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:28,011 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:28,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,011 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 3 times [2024-11-13 15:36:28,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380609578] [2024-11-13 15:36:28,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,015 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,019 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:28,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:28,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:28,054 INFO L87 Difference]: Start difference. First operand 1394 states and 2020 transitions. cyclomatic complexity: 635 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:28,099 INFO L93 Difference]: Finished difference Result 1547 states and 2225 transitions. [2024-11-13 15:36:28,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1547 states and 2225 transitions. [2024-11-13 15:36:28,112 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2024-11-13 15:36:28,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1547 states to 1547 states and 2225 transitions. [2024-11-13 15:36:28,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2024-11-13 15:36:28,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2024-11-13 15:36:28,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1547 states and 2225 transitions. [2024-11-13 15:36:28,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:28,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2024-11-13 15:36:28,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1547 states and 2225 transitions. [2024-11-13 15:36:28,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1547 to 1547. [2024-11-13 15:36:28,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1547 states, 1547 states have (on average 1.438267614738203) internal successors, (2225), 1546 states have internal predecessors, (2225), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1547 states to 1547 states and 2225 transitions. [2024-11-13 15:36:28,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2024-11-13 15:36:28,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:28,163 INFO L424 stractBuchiCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2024-11-13 15:36:28,163 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:36:28,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1547 states and 2225 transitions. [2024-11-13 15:36:28,173 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2024-11-13 15:36:28,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:28,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:28,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,174 INFO L745 eck$LassoCheckResult]: Stem: 17676#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 17677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 17717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17775#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 17753#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 17754#L137-2 ~b0_req_up~0 := 0; 17831#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 17845#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 17678#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 17679#L152-2 ~b1_req_up~0 := 0; 17640#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 17641#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 17652#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 17653#L167-2 ~d0_req_up~0 := 0; 17671#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 17720#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 17721#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 17661#L182-2 ~d1_req_up~0 := 0; 17662#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 17759#L233-1 assume !(1 == ~z_req_up~0); 17761#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17646#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 17647#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17762#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 17763#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 17669#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 17670#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 17620#L336-1 assume !(0 == ~z_ev~0); 17621#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 17839#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 17655#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 17784#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 17785#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 17801#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17834#L354 assume !(1 == ~b0_ev~0); 17713#L354-2 assume !(1 == ~b1_ev~0); 17714#L359-1 assume !(1 == ~d0_ev~0); 17715#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 17716#L369-1 assume !(1 == ~z_ev~0); 17809#L374-1 assume { :end_inline_reset_delta_events } true; 17810#L432-2 assume !false; 18636#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 17704#L295 [2024-11-13 15:36:28,174 INFO L747 eck$LassoCheckResult]: Loop: 17704#L295 assume !false; 19140#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 17657#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 17658#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 17632#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17633#L290 assume 0 != eval_~tmp___0~0#1; 17832#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 17703#L299 assume !(0 != eval_~tmp~0#1); 17704#L295 [2024-11-13 15:36:28,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1127262520, now seen corresponding path program 1 times [2024-11-13 15:36:28,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894035160] [2024-11-13 15:36:28,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:28,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:28,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:28,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894035160] [2024-11-13 15:36:28,206 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894035160] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:28,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:28,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:28,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116205637] [2024-11-13 15:36:28,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:28,207 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:28,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 4 times [2024-11-13 15:36:28,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399188394] [2024-11-13 15:36:28,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:28,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:28,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:28,248 INFO L87 Difference]: Start difference. First operand 1547 states and 2225 transitions. cyclomatic complexity: 687 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:28,296 INFO L93 Difference]: Finished difference Result 1686 states and 2416 transitions. [2024-11-13 15:36:28,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1686 states and 2416 transitions. [2024-11-13 15:36:28,329 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 748 [2024-11-13 15:36:28,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1686 states to 1686 states and 2416 transitions. [2024-11-13 15:36:28,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2024-11-13 15:36:28,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2024-11-13 15:36:28,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1686 states and 2416 transitions. [2024-11-13 15:36:28,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:28,342 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1686 states and 2416 transitions. [2024-11-13 15:36:28,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1686 states and 2416 transitions. [2024-11-13 15:36:28,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1686 to 1686. [2024-11-13 15:36:28,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1686 states, 1686 states have (on average 1.4329774614472124) internal successors, (2416), 1685 states have internal predecessors, (2416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1686 states to 1686 states and 2416 transitions. [2024-11-13 15:36:28,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1686 states and 2416 transitions. [2024-11-13 15:36:28,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:28,385 INFO L424 stractBuchiCegarLoop]: Abstraction has 1686 states and 2416 transitions. [2024-11-13 15:36:28,385 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:36:28,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1686 states and 2416 transitions. [2024-11-13 15:36:28,394 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 748 [2024-11-13 15:36:28,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:28,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:28,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,395 INFO L745 eck$LassoCheckResult]: Stem: 20917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 20918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 20961#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21022#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 20998#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 20999#L137-2 ~b0_req_up~0 := 0; 21083#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 21096#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 20919#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 20920#L152-2 ~b1_req_up~0 := 0; 20880#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 20881#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 20894#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 20895#L167-2 ~d0_req_up~0 := 0; 20912#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 20962#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 20963#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 20896#L182-2 ~d1_req_up~0 := 0; 20897#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 21004#L233-1 assume !(1 == ~z_req_up~0); 21006#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20886#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 20887#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21007#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 21008#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 20910#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 20911#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 20853#L336-1 assume !(0 == ~z_ev~0); 20854#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 21093#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 21079#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 21031#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 21032#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 21051#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21357#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 21356#L354-2 assume !(1 == ~b1_ev~0); 21050#L359-1 assume !(1 == ~d0_ev~0); 20959#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 20960#L369-1 assume !(1 == ~z_ev~0); 21312#L374-1 assume { :end_inline_reset_delta_events } true; 21308#L432-2 assume !false; 21310#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 21011#L295 [2024-11-13 15:36:28,396 INFO L747 eck$LassoCheckResult]: Loop: 21011#L295 assume !false; 22363#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 22361#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 22089#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 22305#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21102#L290 assume 0 != eval_~tmp___0~0#1; 21103#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 22115#L299 assume !(0 != eval_~tmp~0#1); 21011#L295 [2024-11-13 15:36:28,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,396 INFO L85 PathProgramCache]: Analyzing trace with hash -317915894, now seen corresponding path program 1 times [2024-11-13 15:36:28,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199351976] [2024-11-13 15:36:28,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:28,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:28,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:28,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199351976] [2024-11-13 15:36:28,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199351976] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:28,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:28,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:28,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746912363] [2024-11-13 15:36:28,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:28,430 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:28,431 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 5 times [2024-11-13 15:36:28,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721837803] [2024-11-13 15:36:28,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,435 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:28,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:28,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:28,469 INFO L87 Difference]: Start difference. First operand 1686 states and 2416 transitions. cyclomatic complexity: 739 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:28,512 INFO L93 Difference]: Finished difference Result 1949 states and 2796 transitions. [2024-11-13 15:36:28,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1949 states and 2796 transitions. [2024-11-13 15:36:28,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 860 [2024-11-13 15:36:28,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1949 states to 1949 states and 2796 transitions. [2024-11-13 15:36:28,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 920 [2024-11-13 15:36:28,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 920 [2024-11-13 15:36:28,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1949 states and 2796 transitions. [2024-11-13 15:36:28,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:28,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1949 states and 2796 transitions. [2024-11-13 15:36:28,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1949 states and 2796 transitions. [2024-11-13 15:36:28,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1949 to 1949. [2024-11-13 15:36:28,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1949 states, 1949 states have (on average 1.4345818368394048) internal successors, (2796), 1948 states have internal predecessors, (2796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1949 states to 1949 states and 2796 transitions. [2024-11-13 15:36:28,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1949 states and 2796 transitions. [2024-11-13 15:36:28,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:28,591 INFO L424 stractBuchiCegarLoop]: Abstraction has 1949 states and 2796 transitions. [2024-11-13 15:36:28,591 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:36:28,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1949 states and 2796 transitions. [2024-11-13 15:36:28,602 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 860 [2024-11-13 15:36:28,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:28,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:28,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,603 INFO L745 eck$LassoCheckResult]: Stem: 24556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 24557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 24596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24657#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 24635#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 24636#L137-2 ~b0_req_up~0 := 0; 24715#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 24725#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 24558#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 24559#L152-2 ~b1_req_up~0 := 0; 24520#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 24521#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 24530#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 24531#L167-2 ~d0_req_up~0 := 0; 24551#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 24597#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 24598#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 24536#L182-2 ~d1_req_up~0 := 0; 24537#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 24641#L233-1 assume !(1 == ~z_req_up~0); 24643#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24522#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 24523#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24644#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 24645#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 24545#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 24546#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 24494#L336-1 assume !(0 == ~z_ev~0); 24495#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 24724#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 24709#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 24664#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 24665#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 24680#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24718#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 24935#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 24679#L359-1 assume !(1 == ~d0_ev~0); 24594#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 24595#L369-1 assume !(1 == ~z_ev~0); 24895#L374-1 assume { :end_inline_reset_delta_events } true; 24885#L432-2 assume !false; 24887#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 24581#L295 [2024-11-13 15:36:28,603 INFO L747 eck$LassoCheckResult]: Loop: 24581#L295 assume !false; 26372#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 26371#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 25757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 24730#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24728#L290 assume 0 != eval_~tmp___0~0#1; 24716#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24580#L299 assume !(0 != eval_~tmp~0#1); 24581#L295 [2024-11-13 15:36:28,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,604 INFO L85 PathProgramCache]: Analyzing trace with hash -2092923256, now seen corresponding path program 1 times [2024-11-13 15:36:28,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466506400] [2024-11-13 15:36:28,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:36:28,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:36:28,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:36:28,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466506400] [2024-11-13 15:36:28,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466506400] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:36:28,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:36:28,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:36:28,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069501046] [2024-11-13 15:36:28,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:36:28,642 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:36:28,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 6 times [2024-11-13 15:36:28,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037900879] [2024-11-13 15:36:28,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,647 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:36:28,686 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:36:28,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:36:28,687 INFO L87 Difference]: Start difference. First operand 1949 states and 2796 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:36:28,732 INFO L93 Difference]: Finished difference Result 2418 states and 3454 transitions. [2024-11-13 15:36:28,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2418 states and 3454 transitions. [2024-11-13 15:36:28,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 966 [2024-11-13 15:36:28,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2418 states to 2267 states and 3223 transitions. [2024-11-13 15:36:28,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1030 [2024-11-13 15:36:28,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1030 [2024-11-13 15:36:28,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2267 states and 3223 transitions. [2024-11-13 15:36:28,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:36:28,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2267 states and 3223 transitions. [2024-11-13 15:36:28,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2267 states and 3223 transitions. [2024-11-13 15:36:28,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2267 to 2267. [2024-11-13 15:36:28,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2267 states, 2267 states have (on average 1.4217026907807675) internal successors, (3223), 2266 states have internal predecessors, (3223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:36:28,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 3223 transitions. [2024-11-13 15:36:28,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2267 states and 3223 transitions. [2024-11-13 15:36:28,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:36:28,851 INFO L424 stractBuchiCegarLoop]: Abstraction has 2267 states and 3223 transitions. [2024-11-13 15:36:28,852 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:36:28,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2267 states and 3223 transitions. [2024-11-13 15:36:28,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 966 [2024-11-13 15:36:28,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:36:28,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:36:28,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:36:28,868 INFO L745 eck$LassoCheckResult]: Stem: 28931#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 28932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 28972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29036#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 29015#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 29016#L137-2 ~b0_req_up~0 := 0; 29099#update_b0_returnLabel#1 assume { :end_inline_update_b0 } true; 29109#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 28933#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 28934#L152-2 ~b1_req_up~0 := 0; 28894#update_b1_returnLabel#1 assume { :end_inline_update_b1 } true; 28895#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 28905#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 28906#L167-2 ~d0_req_up~0 := 0; 28926#update_d0_returnLabel#1 assume { :end_inline_update_d0 } true; 28976#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 28977#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 28910#L182-2 ~d1_req_up~0 := 0; 28911#update_d1_returnLabel#1 assume { :end_inline_update_d1 } true; 29021#L233-1 assume !(1 == ~z_req_up~0); 29023#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28900#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 28901#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29024#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 29025#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 28920#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 28921#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 28873#L336-1 assume !(0 == ~z_ev~0); 28874#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 29106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 29093#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 29045#is_method1_triggered_returnLabel#1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 29046#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 29063#L390-2 havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29102#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 28964#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 28965#L359-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 28970#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 28971#L369-1 assume !(1 == ~z_ev~0); 29069#L374-1 assume { :end_inline_reset_delta_events } true; 29070#L432-2 assume !false; 29253#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 30144#L295 [2024-11-13 15:36:28,868 INFO L747 eck$LassoCheckResult]: Loop: 30144#L295 assume !false; 30785#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 30760#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 30473#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 30748#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30745#L290 assume 0 != eval_~tmp___0~0#1; 30740#L290-1 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 30702#L299 assume !(0 != eval_~tmp~0#1); 30144#L295 [2024-11-13 15:36:28,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,869 INFO L85 PathProgramCache]: Analyzing trace with hash 2144785738, now seen corresponding path program 1 times [2024-11-13 15:36:28,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043628108] [2024-11-13 15:36:28,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,883 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1087340276, now seen corresponding path program 7 times [2024-11-13 15:36:28,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779605326] [2024-11-13 15:36:28,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:28,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:36:28,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1088814421, now seen corresponding path program 1 times [2024-11-13 15:36:28,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:36:28,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920183080] [2024-11-13 15:36:28,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:36:28,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:36:28,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:28,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:28,958 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:36:30,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:30,596 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:36:30,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:36:30,778 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 03:36:30 BoogieIcfgContainer [2024-11-13 15:36:30,781 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 15:36:30,782 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 15:36:30,782 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 15:36:30,782 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 15:36:30,783 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:36:19" (3/4) ... [2024-11-13 15:36:30,790 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 15:36:30,914 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 15:36:30,914 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 15:36:30,915 INFO L158 Benchmark]: Toolchain (without parser) took 13291.27ms. Allocated memory was 117.4MB in the beginning and 184.5MB in the end (delta: 67.1MB). Free memory was 91.9MB in the beginning and 126.0MB in the end (delta: -34.0MB). Peak memory consumption was 33.5MB. Max. memory is 16.1GB. [2024-11-13 15:36:30,917 INFO L158 Benchmark]: CDTParser took 1.14ms. Allocated memory is still 83.9MB. Free memory is still 40.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:36:30,918 INFO L158 Benchmark]: CACSL2BoogieTranslator took 471.90ms. Allocated memory is still 117.4MB. Free memory was 91.3MB in the beginning and 78.2MB in the end (delta: 13.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 15:36:30,918 INFO L158 Benchmark]: Boogie Procedure Inliner took 68.02ms. Allocated memory is still 117.4MB. Free memory was 78.2MB in the beginning and 76.5MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:36:30,918 INFO L158 Benchmark]: Boogie Preprocessor took 88.32ms. Allocated memory is still 117.4MB. Free memory was 76.5MB in the beginning and 74.1MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:36:30,919 INFO L158 Benchmark]: RCFGBuilder took 837.60ms. Allocated memory is still 117.4MB. Free memory was 74.1MB in the beginning and 51.3MB in the end (delta: 22.8MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 15:36:30,919 INFO L158 Benchmark]: BuchiAutomizer took 11685.85ms. Allocated memory was 117.4MB in the beginning and 184.5MB in the end (delta: 67.1MB). Free memory was 51.3MB in the beginning and 132.7MB in the end (delta: -81.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:36:30,919 INFO L158 Benchmark]: Witness Printer took 132.59ms. Allocated memory is still 184.5MB. Free memory was 132.7MB in the beginning and 126.0MB in the end (delta: 6.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:36:30,925 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.14ms. Allocated memory is still 83.9MB. Free memory is still 40.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 471.90ms. Allocated memory is still 117.4MB. Free memory was 91.3MB in the beginning and 78.2MB in the end (delta: 13.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 68.02ms. Allocated memory is still 117.4MB. Free memory was 78.2MB in the beginning and 76.5MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 88.32ms. Allocated memory is still 117.4MB. Free memory was 76.5MB in the beginning and 74.1MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 837.60ms. Allocated memory is still 117.4MB. Free memory was 74.1MB in the beginning and 51.3MB in the end (delta: 22.8MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 11685.85ms. Allocated memory was 117.4MB in the beginning and 184.5MB in the end (delta: 67.1MB). Free memory was 51.3MB in the beginning and 132.7MB in the end (delta: -81.4MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 132.59ms. Allocated memory is still 184.5MB. Free memory was 132.7MB in the beginning and 126.0MB in the end (delta: 6.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (18 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * d0_ev) + 1) and consists of 3 locations. 18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2267 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 11.4s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 8.3s. Construction of modules took 0.4s. Büchi inclusion checks took 2.3s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 12. Automata minimization 0.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 28 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 758 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 756 mSDsluCounter, 7873 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4353 mSDsCounter, 50 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 276 IncrementalHoareTripleChecker+Invalid, 326 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 50 mSolverCounterUnsat, 3520 mSDtfsCounter, 276 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN6 SILU0 SILI10 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital60 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq184 hnf97 smp100 dnf152 smp86 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 47ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 15:36:30,976 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73ed1c50-c526-4724-a329-12a9f96f1ae6/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)