./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu1.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 14:33:44,611 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 14:33:44,681 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 14:33:44,691 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 14:33:44,691 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 14:33:44,714 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 14:33:44,714 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 14:33:44,715 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 14:33:44,715 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 14:33:44,715 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 14:33:44,716 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 14:33:44,716 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 14:33:44,716 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 14:33:44,716 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 14:33:44,716 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 14:33:44,716 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 14:33:44,717 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 14:33:44,717 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 14:33:44,717 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 14:33:44,717 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 14:33:44,717 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 14:33:44,718 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 14:33:44,719 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 14:33:44,719 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 14:33:44,720 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 14:33:44,720 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 14:33:44,720 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 14:33:44,720 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 [2024-11-13 14:33:45,007 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 14:33:45,016 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 14:33:45,018 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 14:33:45,019 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 14:33:45,020 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 14:33:45,021 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/kundu1.cil.c Unable to find full path for "g++" [2024-11-13 14:33:46,987 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 14:33:47,266 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 14:33:47,271 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/sv-benchmarks/c/systemc/kundu1.cil.c [2024-11-13 14:33:47,289 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/data/938f2d474/ae74ac4ae4be49ab84bcd243fdf7f6dc/FLAG65e263107 [2024-11-13 14:33:47,307 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/data/938f2d474/ae74ac4ae4be49ab84bcd243fdf7f6dc [2024-11-13 14:33:47,310 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 14:33:47,311 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 14:33:47,313 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 14:33:47,313 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 14:33:47,317 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 14:33:47,318 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,319 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@b898c40 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47, skipping insertion in model container [2024-11-13 14:33:47,319 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,352 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 14:33:47,559 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:33:47,571 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 14:33:47,619 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:33:47,635 INFO L204 MainTranslator]: Completed translation [2024-11-13 14:33:47,635 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47 WrapperNode [2024-11-13 14:33:47,635 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 14:33:47,636 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 14:33:47,636 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 14:33:47,636 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 14:33:47,643 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,650 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,676 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 37, statements flattened = 371 [2024-11-13 14:33:47,676 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 14:33:47,676 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 14:33:47,677 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 14:33:47,677 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 14:33:47,685 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,685 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,687 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,699 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 14:33:47,700 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,700 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,705 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,715 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,720 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,721 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,728 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 14:33:47,729 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 14:33:47,729 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 14:33:47,729 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 14:33:47,730 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (1/1) ... [2024-11-13 14:33:47,736 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:33:47,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:33:47,762 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:33:47,766 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 14:33:47,795 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 14:33:47,795 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 14:33:47,795 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 14:33:47,795 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 14:33:47,904 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 14:33:47,906 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 14:33:48,301 INFO L? ?]: Removed 68 outVars from TransFormulas that were not future-live. [2024-11-13 14:33:48,301 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 14:33:48,319 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 14:33:48,319 INFO L316 CfgBuilder]: Removed 4 assume(true) statements. [2024-11-13 14:33:48,319 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:33:48 BoogieIcfgContainer [2024-11-13 14:33:48,319 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 14:33:48,320 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 14:33:48,321 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 14:33:48,326 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 14:33:48,326 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:33:48,327 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 02:33:47" (1/3) ... [2024-11-13 14:33:48,328 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7746a248 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:33:48, skipping insertion in model container [2024-11-13 14:33:48,328 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:33:48,328 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:33:47" (2/3) ... [2024-11-13 14:33:48,328 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7746a248 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:33:48, skipping insertion in model container [2024-11-13 14:33:48,328 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:33:48,329 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:33:48" (3/3) ... [2024-11-13 14:33:48,330 INFO L333 chiAutomizerObserver]: Analyzing ICFG kundu1.cil.c [2024-11-13 14:33:48,393 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 14:33:48,393 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 14:33:48,394 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 14:33:48,394 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 14:33:48,394 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 14:33:48,394 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 14:33:48,395 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 14:33:48,395 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 14:33:48,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:48,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-13 14:33:48,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:48,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:48,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,447 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 14:33:48,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:48,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-13 14:33:48,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:48,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:48,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,470 INFO L745 eck$LassoCheckResult]: Stem: 30#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 43#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 122#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65#L236true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 64#L236-2true assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 124#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6#L117true assume !(1 == ~P_1_pc~0); 21#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 59#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 51#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 56#L383true assume !(0 != activate_threads_~tmp~1#1); 22#L383-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 55#L199true assume 1 == ~C_1_pc~0; 102#L200true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 68#L220true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 119#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 79#L391true assume !(0 != activate_threads_~tmp___1~1#1); 3#L391-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 80#L445-2true [2024-11-13 14:33:48,474 INFO L747 eck$LassoCheckResult]: Loop: 80#L445-2true assume !false; 105#L446true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 97#L304true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4#L117-3true assume 1 == ~P_1_pc~0; 60#L118-1true assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 83#L128-1true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 69#is_P_1_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34#L383-3true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 15#L383-5true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 118#L199-3true assume 1 == ~C_1_pc~0; 19#L200-1true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 109#L220-1true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 57#is_C_1_triggered_returnLabel#2true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 129#L391-3true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 36#L391-5true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11#L254-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 40#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 95#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 106#L464true assume !(0 == start_simulation_~tmp~3#1); 23#L464-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26#L254-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 84#L267-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 38#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 5#L419true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 111#L426true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 125#stop_simulation_returnLabel#1true start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 27#L477true assume !(0 != start_simulation_~tmp___0~2#1); 80#L445-2true [2024-11-13 14:33:48,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:48,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1103808071, now seen corresponding path program 1 times [2024-11-13 14:33:48,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:48,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552661117] [2024-11-13 14:33:48,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:48,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:48,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:48,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:48,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:48,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552661117] [2024-11-13 14:33:48,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552661117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:48,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:48,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:33:48,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723088186] [2024-11-13 14:33:48,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:48,746 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:33:48,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:48,747 INFO L85 PathProgramCache]: Analyzing trace with hash 1064352430, now seen corresponding path program 1 times [2024-11-13 14:33:48,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:48,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293644103] [2024-11-13 14:33:48,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:48,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:48,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:48,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:48,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:48,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293644103] [2024-11-13 14:33:48,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293644103] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:48,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:48,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:33:48,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092824746] [2024-11-13 14:33:48,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:48,818 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:48,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:48,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:33:48,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:33:48,846 INFO L87 Difference]: Start difference. First operand has 128 states, 127 states have (on average 1.4803149606299213) internal successors, (188), 127 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:48,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:48,881 INFO L93 Difference]: Finished difference Result 122 states and 172 transitions. [2024-11-13 14:33:48,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 172 transitions. [2024-11-13 14:33:48,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2024-11-13 14:33:48,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 115 states and 165 transitions. [2024-11-13 14:33:48,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2024-11-13 14:33:48,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2024-11-13 14:33:48,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 165 transitions. [2024-11-13 14:33:48,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:48,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2024-11-13 14:33:48,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 165 transitions. [2024-11-13 14:33:48,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2024-11-13 14:33:48,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.434782608695652) internal successors, (165), 114 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:48,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 165 transitions. [2024-11-13 14:33:48,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2024-11-13 14:33:48,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:33:48,949 INFO L424 stractBuchiCegarLoop]: Abstraction has 115 states and 165 transitions. [2024-11-13 14:33:48,950 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 14:33:48,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 165 transitions. [2024-11-13 14:33:48,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2024-11-13 14:33:48,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:48,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:48,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:48,956 INFO L745 eck$LassoCheckResult]: Stem: 313#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 329#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 354#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 355#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 266#L117 assume !(1 == ~P_1_pc~0); 267#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 299#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 341#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 342#L383 assume !(0 != activate_threads_~tmp~1#1); 300#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 301#L199 assume 1 == ~C_1_pc~0; 347#L200 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 278#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 357#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 361#L391 assume !(0 != activate_threads_~tmp___1~1#1); 259#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 309#L445-2 [2024-11-13 14:33:48,956 INFO L747 eck$LassoCheckResult]: Loop: 309#L445-2 assume !false; 362#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 283#L304 assume !false; 366#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 351#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 303#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 285#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 286#L284 assume !(0 != eval_~tmp___2~0#1); 356#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 328#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 261#L117-3 assume 1 == ~P_1_pc~0; 262#L118-1 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 352#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 358#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 316#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 287#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 288#L199-3 assume 1 == ~C_1_pc~0; 294#L200-1 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 295#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 349#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 350#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 318#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 279#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 280#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 325#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 367#L464 assume !(0 == start_simulation_~tmp~3#1); 273#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 302#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 306#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 323#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 264#L419 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 265#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 373#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 308#L477 assume !(0 != start_simulation_~tmp___0~2#1); 309#L445-2 [2024-11-13 14:33:48,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:48,957 INFO L85 PathProgramCache]: Analyzing trace with hash 484539831, now seen corresponding path program 1 times [2024-11-13 14:33:48,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:48,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931326745] [2024-11-13 14:33:48,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:48,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:48,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:49,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:49,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:49,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931326745] [2024-11-13 14:33:49,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931326745] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:49,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:49,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 14:33:49,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469769240] [2024-11-13 14:33:49,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:49,122 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:33:49,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:49,123 INFO L85 PathProgramCache]: Analyzing trace with hash 996091042, now seen corresponding path program 1 times [2024-11-13 14:33:49,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:49,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051547339] [2024-11-13 14:33:49,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:49,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:49,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:49,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:49,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:49,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051547339] [2024-11-13 14:33:49,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051547339] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:49,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:49,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:33:49,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882132014] [2024-11-13 14:33:49,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:49,217 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:49,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:49,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:33:49,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:33:49,218 INFO L87 Difference]: Start difference. First operand 115 states and 165 transitions. cyclomatic complexity: 51 Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:49,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:49,446 INFO L93 Difference]: Finished difference Result 281 states and 389 transitions. [2024-11-13 14:33:49,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 389 transitions. [2024-11-13 14:33:49,449 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2024-11-13 14:33:49,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 389 transitions. [2024-11-13 14:33:49,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2024-11-13 14:33:49,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2024-11-13 14:33:49,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 389 transitions. [2024-11-13 14:33:49,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:49,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 389 transitions. [2024-11-13 14:33:49,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 389 transitions. [2024-11-13 14:33:49,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 262. [2024-11-13 14:33:49,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 262 states, 262 states have (on average 1.3969465648854962) internal successors, (366), 261 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:49,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 366 transitions. [2024-11-13 14:33:49,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 262 states and 366 transitions. [2024-11-13 14:33:49,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:33:49,476 INFO L424 stractBuchiCegarLoop]: Abstraction has 262 states and 366 transitions. [2024-11-13 14:33:49,477 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 14:33:49,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 262 states and 366 transitions. [2024-11-13 14:33:49,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 239 [2024-11-13 14:33:49,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:49,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:49,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:49,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:49,481 INFO L745 eck$LassoCheckResult]: Stem: 723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 736#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 737#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 765#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 766#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 780#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 674#L117 assume !(1 == ~P_1_pc~0); 675#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 707#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 751#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 752#L383 assume !(0 != activate_threads_~tmp~1#1); 709#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 710#L199 assume !(1 == ~C_1_pc~0); 757#L199-2 assume !(2 == ~C_1_pc~0); 687#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 688#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 768#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 774#L391 assume !(0 != activate_threads_~tmp___1~1#1); 670#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 671#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 718#L445-2 [2024-11-13 14:33:49,481 INFO L747 eck$LassoCheckResult]: Loop: 718#L445-2 assume !false; 777#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 690#L304 assume !false; 781#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 760#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 711#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 692#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 693#L284 assume !(0 != eval_~tmp___2~0#1); 767#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 778#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 738#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 668#L117-3 assume !(1 == ~P_1_pc~0); 669#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 773#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 769#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 726#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 694#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 695#L199-3 assume !(1 == ~C_1_pc~0); 793#L199-5 assume 2 == ~C_1_pc~0; 720#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 721#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 758#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 759#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 727#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 683#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 684#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 735#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 782#L464 assume !(0 == start_simulation_~tmp~3#1); 792#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 714#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 715#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 672#L419 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 673#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 794#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 717#L477 assume !(0 != start_simulation_~tmp___0~2#1); 718#L445-2 [2024-11-13 14:33:49,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:49,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 1 times [2024-11-13 14:33:49,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:49,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190405625] [2024-11-13 14:33:49,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:49,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:49,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:49,496 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:49,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:49,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:49,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:49,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1284153179, now seen corresponding path program 1 times [2024-11-13 14:33:49,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:49,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430401846] [2024-11-13 14:33:49,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:49,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:49,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:49,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:49,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:49,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430401846] [2024-11-13 14:33:49,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430401846] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:49,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:49,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:33:49,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666673031] [2024-11-13 14:33:49,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:49,639 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:49,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:49,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:33:49,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:33:49,640 INFO L87 Difference]: Start difference. First operand 262 states and 366 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:49,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:49,719 INFO L93 Difference]: Finished difference Result 283 states and 387 transitions. [2024-11-13 14:33:49,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283 states and 387 transitions. [2024-11-13 14:33:49,722 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 260 [2024-11-13 14:33:49,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283 states to 283 states and 387 transitions. [2024-11-13 14:33:49,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283 [2024-11-13 14:33:49,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283 [2024-11-13 14:33:49,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283 states and 387 transitions. [2024-11-13 14:33:49,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:49,726 INFO L218 hiAutomatonCegarLoop]: Abstraction has 283 states and 387 transitions. [2024-11-13 14:33:49,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283 states and 387 transitions. [2024-11-13 14:33:49,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283 to 271. [2024-11-13 14:33:49,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.3837638376383763) internal successors, (375), 270 states have internal predecessors, (375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:49,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 375 transitions. [2024-11-13 14:33:49,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 375 transitions. [2024-11-13 14:33:49,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:33:49,748 INFO L424 stractBuchiCegarLoop]: Abstraction has 271 states and 375 transitions. [2024-11-13 14:33:49,748 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 14:33:49,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 375 transitions. [2024-11-13 14:33:49,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 248 [2024-11-13 14:33:49,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:49,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:49,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:49,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:49,752 INFO L745 eck$LassoCheckResult]: Stem: 1276#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 1293#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1291#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1322#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1323#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1338#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1227#L117 assume !(1 == ~P_1_pc~0); 1228#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1259#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1305#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1306#L383 assume !(0 != activate_threads_~tmp~1#1); 1262#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1263#L199 assume !(1 == ~C_1_pc~0); 1311#L199-2 assume !(2 == ~C_1_pc~0); 1240#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 1241#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1325#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1329#L391 assume !(0 != activate_threads_~tmp___1~1#1); 1223#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1224#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1271#L445-2 [2024-11-13 14:33:49,752 INFO L747 eck$LassoCheckResult]: Loop: 1271#L445-2 assume !false; 1333#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1439#L304 assume !false; 1438#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1437#L254 assume !(0 == ~P_1_st~0); 1435#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1434#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1433#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1431#L284 assume !(0 != eval_~tmp___2~0#1); 1430#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1429#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1292#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1221#L117-3 assume !(1 == ~P_1_pc~0); 1222#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 1328#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1326#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1281#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1247#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1248#L199-3 assume !(1 == ~C_1_pc~0); 1350#L199-5 assume 2 == ~C_1_pc~0; 1273#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 1274#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1491#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1490#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1489#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1488#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1236#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1237#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1289#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1341#L464 assume !(0 == start_simulation_~tmp~3#1); 1235#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1462#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1461#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1287#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1225#L419 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1226#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1351#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1270#L477 assume !(0 != start_simulation_~tmp___0~2#1); 1271#L445-2 [2024-11-13 14:33:49,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:49,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 2 times [2024-11-13 14:33:49,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:49,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25799540] [2024-11-13 14:33:49,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:49,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:49,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:49,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:49,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:49,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:49,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:49,799 INFO L85 PathProgramCache]: Analyzing trace with hash 616819713, now seen corresponding path program 1 times [2024-11-13 14:33:49,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:49,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507144024] [2024-11-13 14:33:49,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:49,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:49,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:49,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:49,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:49,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507144024] [2024-11-13 14:33:49,908 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507144024] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:49,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:49,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:33:49,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320928861] [2024-11-13 14:33:49,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:49,908 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:49,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:49,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:33:49,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:33:49,909 INFO L87 Difference]: Start difference. First operand 271 states and 375 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:49,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:49,990 INFO L93 Difference]: Finished difference Result 286 states and 390 transitions. [2024-11-13 14:33:49,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286 states and 390 transitions. [2024-11-13 14:33:49,995 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 263 [2024-11-13 14:33:49,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286 states to 286 states and 390 transitions. [2024-11-13 14:33:49,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 286 [2024-11-13 14:33:50,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 286 [2024-11-13 14:33:50,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 286 states and 390 transitions. [2024-11-13 14:33:50,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:50,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 286 states and 390 transitions. [2024-11-13 14:33:50,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states and 390 transitions. [2024-11-13 14:33:50,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 280. [2024-11-13 14:33:50,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280 states, 280 states have (on average 1.3714285714285714) internal successors, (384), 279 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 384 transitions. [2024-11-13 14:33:50,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 280 states and 384 transitions. [2024-11-13 14:33:50,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:33:50,031 INFO L424 stractBuchiCegarLoop]: Abstraction has 280 states and 384 transitions. [2024-11-13 14:33:50,031 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 14:33:50,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 280 states and 384 transitions. [2024-11-13 14:33:50,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 257 [2024-11-13 14:33:50,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:50,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:50,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,039 INFO L745 eck$LassoCheckResult]: Stem: 1841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 1857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1854#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1855#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1887#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1888#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1902#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1793#L117 assume !(1 == ~P_1_pc~0); 1794#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1825#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1870#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1871#L383 assume !(0 != activate_threads_~tmp~1#1); 1827#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1828#L199 assume !(1 == ~C_1_pc~0); 1876#L199-2 assume !(2 == ~C_1_pc~0); 1806#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 1807#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1889#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1893#L391 assume !(0 != activate_threads_~tmp___1~1#1); 1789#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1916#L445-2 [2024-11-13 14:33:50,039 INFO L747 eck$LassoCheckResult]: Loop: 1916#L445-2 assume !false; 2020#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2016#L304 assume !false; 2015#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2014#L254 assume !(0 == ~P_1_st~0); 1843#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1844#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2061#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2060#L284 assume !(0 != eval_~tmp___2~0#1); 1898#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1919#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2007#L117-3 assume !(1 == ~P_1_pc~0); 2006#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 1900#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1890#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1845#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1813#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1814#L199-3 assume !(1 == ~C_1_pc~0); 1917#L199-5 assume !(2 == ~C_1_pc~0); 1840#L209-3 is_C_1_triggered_~__retres1~1#1 := 0; 1839#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1915#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2065#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2064#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1904#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1905#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2062#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1906#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1907#L464 assume !(0 == start_simulation_~tmp~3#1); 1914#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2037#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2035#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2033#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2032#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2030#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2022#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2021#L477 assume !(0 != start_simulation_~tmp___0~2#1); 1916#L445-2 [2024-11-13 14:33:50,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 3 times [2024-11-13 14:33:50,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380966322] [2024-11-13 14:33:50,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,060 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1607924804, now seen corresponding path program 1 times [2024-11-13 14:33:50,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447497064] [2024-11-13 14:33:50,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:50,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:50,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:50,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447497064] [2024-11-13 14:33:50,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447497064] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:50,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:50,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:33:50,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100069392] [2024-11-13 14:33:50,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:50,202 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:50,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:50,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:33:50,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:33:50,203 INFO L87 Difference]: Start difference. First operand 280 states and 384 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:50,277 INFO L93 Difference]: Finished difference Result 292 states and 393 transitions. [2024-11-13 14:33:50,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 292 states and 393 transitions. [2024-11-13 14:33:50,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2024-11-13 14:33:50,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 292 states to 292 states and 393 transitions. [2024-11-13 14:33:50,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 292 [2024-11-13 14:33:50,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 292 [2024-11-13 14:33:50,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292 states and 393 transitions. [2024-11-13 14:33:50,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:50,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 292 states and 393 transitions. [2024-11-13 14:33:50,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states and 393 transitions. [2024-11-13 14:33:50,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 292. [2024-11-13 14:33:50,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292 states, 292 states have (on average 1.345890410958904) internal successors, (393), 291 states have internal predecessors, (393), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292 states to 292 states and 393 transitions. [2024-11-13 14:33:50,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 292 states and 393 transitions. [2024-11-13 14:33:50,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:33:50,297 INFO L424 stractBuchiCegarLoop]: Abstraction has 292 states and 393 transitions. [2024-11-13 14:33:50,297 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 14:33:50,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 292 states and 393 transitions. [2024-11-13 14:33:50,300 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 269 [2024-11-13 14:33:50,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:50,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:50,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,301 INFO L745 eck$LassoCheckResult]: Stem: 2421#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 2438#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2436#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2465#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2466#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2484#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2373#L117 assume !(1 == ~P_1_pc~0); 2374#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2405#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2450#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2451#L383 assume !(0 != activate_threads_~tmp~1#1); 2406#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2407#L199 assume !(1 == ~C_1_pc~0); 2456#L199-2 assume !(2 == ~C_1_pc~0); 2383#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 2384#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2467#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2472#L391 assume !(0 != activate_threads_~tmp___1~1#1); 2366#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2367#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2473#L445-2 [2024-11-13 14:33:50,302 INFO L747 eck$LassoCheckResult]: Loop: 2473#L445-2 assume !false; 2474#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2389#L304 assume !false; 2485#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2459#L254 assume !(0 == ~P_1_st~0); 2423#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2424#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2595#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2586#L284 assume !(0 != eval_~tmp___2~0#1); 2587#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2637#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2636#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2635#L117-3 assume !(1 == ~P_1_pc~0); 2634#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 2633#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2632#is_P_1_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2631#L383-3 assume !(0 != activate_threads_~tmp~1#1); 2630#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2498#L199-3 assume !(1 == ~C_1_pc~0); 2493#L199-5 assume 2 == ~C_1_pc~0; 2418#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 2419#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2457#is_C_1_triggered_returnLabel#2 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2458#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2427#L391-5 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2428#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2385#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2386#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2486#L464 assume !(0 == start_simulation_~tmp~3#1); 2381#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2408#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2412#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2371#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2372#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2641#stop_simulation_returnLabel#1 start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2638#L477 assume !(0 != start_simulation_~tmp___0~2#1); 2473#L445-2 [2024-11-13 14:33:50,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 4 times [2024-11-13 14:33:50,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743113204] [2024-11-13 14:33:50,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,313 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,323 INFO L85 PathProgramCache]: Analyzing trace with hash 835614849, now seen corresponding path program 1 times [2024-11-13 14:33:50,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694430296] [2024-11-13 14:33:50,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:50,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:50,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:50,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694430296] [2024-11-13 14:33:50,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694430296] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:50,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:50,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:33:50,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772343287] [2024-11-13 14:33:50,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:50,360 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:33:50,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:50,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:33:50,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:33:50,360 INFO L87 Difference]: Start difference. First operand 292 states and 393 transitions. cyclomatic complexity: 103 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:50,414 INFO L93 Difference]: Finished difference Result 436 states and 577 transitions. [2024-11-13 14:33:50,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 577 transitions. [2024-11-13 14:33:50,417 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 406 [2024-11-13 14:33:50,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 436 states and 577 transitions. [2024-11-13 14:33:50,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 436 [2024-11-13 14:33:50,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 436 [2024-11-13 14:33:50,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 436 states and 577 transitions. [2024-11-13 14:33:50,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:50,422 INFO L218 hiAutomatonCegarLoop]: Abstraction has 436 states and 577 transitions. [2024-11-13 14:33:50,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 436 states and 577 transitions. [2024-11-13 14:33:50,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 436 to 436. [2024-11-13 14:33:50,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.323394495412844) internal successors, (577), 435 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 577 transitions. [2024-11-13 14:33:50,436 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 577 transitions. [2024-11-13 14:33:50,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:33:50,438 INFO L424 stractBuchiCegarLoop]: Abstraction has 436 states and 577 transitions. [2024-11-13 14:33:50,439 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 14:33:50,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 577 transitions. [2024-11-13 14:33:50,445 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 406 [2024-11-13 14:33:50,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:50,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:50,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,446 INFO L745 eck$LassoCheckResult]: Stem: 3157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 3177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3173#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3174#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3205#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3206#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3226#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3106#L117 assume !(1 == ~P_1_pc~0); 3107#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3139#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3190#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3191#L383 assume !(0 != activate_threads_~tmp~1#1); 3140#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 3141#L199 assume !(1 == ~C_1_pc~0); 3196#L199-2 assume !(2 == ~C_1_pc~0); 3116#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 3117#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 3209#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3216#L391 assume !(0 != activate_threads_~tmp___1~1#1); 3100#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3101#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3240#L445-2 assume !false; 3415#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3411#L304 [2024-11-13 14:33:50,446 INFO L747 eck$LassoCheckResult]: Loop: 3411#L304 assume !false; 3434#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3431#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3429#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3426#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3424#L284 assume 0 != eval_~tmp___2~0#1; 3422#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3418#L293 assume !(0 != eval_~tmp~0#1); 3414#L289 assume !(0 == ~C_1_st~0); 3411#L304 [2024-11-13 14:33:50,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,447 INFO L85 PathProgramCache]: Analyzing trace with hash 6828105, now seen corresponding path program 1 times [2024-11-13 14:33:50,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458385631] [2024-11-13 14:33:50,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,460 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,480 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1102176986, now seen corresponding path program 1 times [2024-11-13 14:33:50,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942861093] [2024-11-13 14:33:50,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,489 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,500 INFO L85 PathProgramCache]: Analyzing trace with hash 751025630, now seen corresponding path program 1 times [2024-11-13 14:33:50,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217744399] [2024-11-13 14:33:50,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:50,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:50,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:50,569 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217744399] [2024-11-13 14:33:50,569 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217744399] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:50,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:50,570 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:33:50,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058845258] [2024-11-13 14:33:50,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:50,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:50,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:33:50,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:33:50,636 INFO L87 Difference]: Start difference. First operand 436 states and 577 transitions. cyclomatic complexity: 144 Second operand has 3 states, 2 states have (on average 16.5) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:50,695 INFO L93 Difference]: Finished difference Result 706 states and 917 transitions. [2024-11-13 14:33:50,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 706 states and 917 transitions. [2024-11-13 14:33:50,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2024-11-13 14:33:50,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 706 states to 706 states and 917 transitions. [2024-11-13 14:33:50,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 706 [2024-11-13 14:33:50,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 706 [2024-11-13 14:33:50,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 706 states and 917 transitions. [2024-11-13 14:33:50,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:50,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 706 states and 917 transitions. [2024-11-13 14:33:50,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states and 917 transitions. [2024-11-13 14:33:50,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 706. [2024-11-13 14:33:50,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 706 states, 706 states have (on average 1.2988668555240792) internal successors, (917), 705 states have internal predecessors, (917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 917 transitions. [2024-11-13 14:33:50,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 706 states and 917 transitions. [2024-11-13 14:33:50,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:33:50,733 INFO L424 stractBuchiCegarLoop]: Abstraction has 706 states and 917 transitions. [2024-11-13 14:33:50,733 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 14:33:50,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 706 states and 917 transitions. [2024-11-13 14:33:50,741 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2024-11-13 14:33:50,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:50,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:50,741 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,741 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,742 INFO L745 eck$LassoCheckResult]: Stem: 4305#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 4306#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 4324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4320#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4321#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 4352#L236-2 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 4353#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4724#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4723#L117 assume !(1 == ~P_1_pc~0); 4722#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 4721#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4720#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4719#L383 assume !(0 != activate_threads_~tmp~1#1); 4718#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 4717#L199 assume !(1 == ~C_1_pc~0); 4716#L199-2 assume !(2 == ~C_1_pc~0); 4505#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 4503#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 4501#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4495#L391 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4250#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4251#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 4384#L445-2 assume !false; 4550#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4527#L304 [2024-11-13 14:33:50,743 INFO L747 eck$LassoCheckResult]: Loop: 4527#L304 assume !false; 4545#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4542#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4540#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4538#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4536#L284 assume 0 != eval_~tmp___2~0#1; 4534#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4531#L293 assume !(0 != eval_~tmp~0#1); 4529#L289 assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4487#L308 assume !(0 != eval_~tmp___1~0#1); 4527#L304 [2024-11-13 14:33:50,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,744 INFO L85 PathProgramCache]: Analyzing trace with hash -1683962679, now seen corresponding path program 1 times [2024-11-13 14:33:50,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051429923] [2024-11-13 14:33:50,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:33:50,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:33:50,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:33:50,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051429923] [2024-11-13 14:33:50,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051429923] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:33:50,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:33:50,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:33:50,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109036336] [2024-11-13 14:33:50,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:33:50,783 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:33:50,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,783 INFO L85 PathProgramCache]: Analyzing trace with hash 192249553, now seen corresponding path program 1 times [2024-11-13 14:33:50,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607341636] [2024-11-13 14:33:50,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,791 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,798 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:33:50,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:33:50,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:33:50,852 INFO L87 Difference]: Start difference. First operand 706 states and 917 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:33:50,864 INFO L93 Difference]: Finished difference Result 687 states and 894 transitions. [2024-11-13 14:33:50,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 894 transitions. [2024-11-13 14:33:50,869 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2024-11-13 14:33:50,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 687 states and 894 transitions. [2024-11-13 14:33:50,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 687 [2024-11-13 14:33:50,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 687 [2024-11-13 14:33:50,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 687 states and 894 transitions. [2024-11-13 14:33:50,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:33:50,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 687 states and 894 transitions. [2024-11-13 14:33:50,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 687 states and 894 transitions. [2024-11-13 14:33:50,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 687 to 687. [2024-11-13 14:33:50,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 687 states, 687 states have (on average 1.3013100436681222) internal successors, (894), 686 states have internal predecessors, (894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:33:50,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 687 states to 687 states and 894 transitions. [2024-11-13 14:33:50,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 687 states and 894 transitions. [2024-11-13 14:33:50,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:33:50,899 INFO L424 stractBuchiCegarLoop]: Abstraction has 687 states and 894 transitions. [2024-11-13 14:33:50,899 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 14:33:50,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 687 states and 894 transitions. [2024-11-13 14:33:50,903 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2024-11-13 14:33:50,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:33:50,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:33:50,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:33:50,906 INFO L745 eck$LassoCheckResult]: Stem: 5702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 5703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 5720#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5717#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5718#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 5749#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 5750#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5768#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 5655#L117 assume !(1 == ~P_1_pc~0); 5656#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 5687#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 5734#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5735#L383 assume !(0 != activate_threads_~tmp~1#1); 5689#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 5690#L199 assume !(1 == ~C_1_pc~0); 5740#L199-2 assume !(2 == ~C_1_pc~0); 5667#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 5668#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 5751#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5758#L391 assume !(0 != activate_threads_~tmp___1~1#1); 5651#L391-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5652#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 5780#L445-2 assume !false; 6006#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 5974#L304 [2024-11-13 14:33:50,906 INFO L747 eck$LassoCheckResult]: Loop: 5974#L304 assume !false; 6003#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5999#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5995#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5993#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5991#L284 assume 0 != eval_~tmp___2~0#1; 5988#L284-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5985#L293 assume !(0 != eval_~tmp~0#1); 5981#L289 assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5952#L308 assume !(0 != eval_~tmp___1~0#1); 5974#L304 [2024-11-13 14:33:50,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,907 INFO L85 PathProgramCache]: Analyzing trace with hash 6828105, now seen corresponding path program 2 times [2024-11-13 14:33:50,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137929033] [2024-11-13 14:33:50,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,920 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,933 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,933 INFO L85 PathProgramCache]: Analyzing trace with hash 192249553, now seen corresponding path program 2 times [2024-11-13 14:33:50,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132558391] [2024-11-13 14:33:50,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,940 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,947 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:50,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:33:50,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1806955801, now seen corresponding path program 1 times [2024-11-13 14:33:50,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:33:50,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650770306] [2024-11-13 14:33:50,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:33:50,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:33:50,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,964 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:50,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:50,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:33:51,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:51,839 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:33:51,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:33:51,969 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 02:33:51 BoogieIcfgContainer [2024-11-13 14:33:51,972 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 14:33:51,973 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 14:33:51,977 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 14:33:51,977 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 14:33:51,977 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:33:48" (3/4) ... [2024-11-13 14:33:51,979 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 14:33:52,045 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 14:33:52,045 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 14:33:52,049 INFO L158 Benchmark]: Toolchain (without parser) took 4735.12ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 93.8MB in the beginning and 152.9MB in the end (delta: -59.1MB). Peak memory consumption was 175.2MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,049 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory is still 105.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:33:52,050 INFO L158 Benchmark]: CACSL2BoogieTranslator took 323.11ms. Allocated memory is still 117.4MB. Free memory was 93.4MB in the beginning and 80.4MB in the end (delta: 13.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,050 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.90ms. Allocated memory is still 117.4MB. Free memory was 80.4MB in the beginning and 78.3MB in the end (delta: 2.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,050 INFO L158 Benchmark]: Boogie Preprocessor took 51.45ms. Allocated memory is still 117.4MB. Free memory was 78.3MB in the beginning and 76.2MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:33:52,050 INFO L158 Benchmark]: RCFGBuilder took 590.92ms. Allocated memory is still 117.4MB. Free memory was 76.2MB in the beginning and 54.9MB in the end (delta: 21.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,051 INFO L158 Benchmark]: BuchiAutomizer took 3652.06ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 54.6MB in the beginning and 157.2MB in the end (delta: -102.6MB). Peak memory consumption was 124.9MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,051 INFO L158 Benchmark]: Witness Printer took 72.34ms. Allocated memory is still 352.3MB. Free memory was 157.2MB in the beginning and 152.9MB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:33:52,053 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory is still 105.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 323.11ms. Allocated memory is still 117.4MB. Free memory was 93.4MB in the beginning and 80.4MB in the end (delta: 13.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 39.90ms. Allocated memory is still 117.4MB. Free memory was 80.4MB in the beginning and 78.3MB in the end (delta: 2.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 51.45ms. Allocated memory is still 117.4MB. Free memory was 78.3MB in the beginning and 76.2MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 590.92ms. Allocated memory is still 117.4MB. Free memory was 76.2MB in the beginning and 54.9MB in the end (delta: 21.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 3652.06ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 54.6MB in the beginning and 157.2MB in the end (delta: -102.6MB). Peak memory consumption was 124.9MB. Max. memory is 16.1GB. * Witness Printer took 72.34ms. Allocated memory is still 352.3MB. Free memory was 157.2MB in the beginning and 152.9MB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 8 terminating modules (8 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.8 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 687 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.5s and 9 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.3s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 8. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 8 MinimizatonAttempts, 37 StatesRemovedByMinimization, 3 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 881 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 881 mSDsluCounter, 3117 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1845 mSDsCounter, 65 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 222 IncrementalHoareTripleChecker+Invalid, 287 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 65 mSolverCounterUnsat, 1272 mSDtfsCounter, 222 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 279]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 279]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 14:33:52,087 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_156b28bb-3615-4def-a8da-cfe7239b79a8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)