./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu2.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 14:52:04,477 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 14:52:04,565 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 14:52:04,570 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 14:52:04,570 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 14:52:04,595 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 14:52:04,596 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 14:52:04,596 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 14:52:04,596 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 14:52:04,596 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 14:52:04,597 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 14:52:04,597 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 14:52:04,597 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 14:52:04,597 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 14:52:04,597 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 14:52:04,597 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 14:52:04,597 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 14:52:04,598 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 14:52:04,598 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 14:52:04,599 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 14:52:04,600 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 14:52:04,600 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 14:52:04,600 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 14:52:04,600 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 14:52:04,600 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 14:52:04,600 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2024-11-13 14:52:04,908 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 14:52:04,920 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 14:52:04,924 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 14:52:04,926 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 14:52:04,926 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 14:52:04,928 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/kundu2.cil.c Unable to find full path for "g++" [2024-11-13 14:52:06,717 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 14:52:07,039 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 14:52:07,039 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/sv-benchmarks/c/systemc/kundu2.cil.c [2024-11-13 14:52:07,066 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/data/1973e9d0f/b0b478bc69c547acb1146eb0ee6ff3f1/FLAG1f032a0d8 [2024-11-13 14:52:07,297 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/data/1973e9d0f/b0b478bc69c547acb1146eb0ee6ff3f1 [2024-11-13 14:52:07,299 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 14:52:07,303 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 14:52:07,306 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 14:52:07,306 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 14:52:07,311 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 14:52:07,312 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,313 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3304f2d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07, skipping insertion in model container [2024-11-13 14:52:07,313 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,359 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 14:52:07,620 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:52:07,636 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 14:52:07,705 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:52:07,728 INFO L204 MainTranslator]: Completed translation [2024-11-13 14:52:07,728 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07 WrapperNode [2024-11-13 14:52:07,728 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 14:52:07,729 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 14:52:07,730 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 14:52:07,730 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 14:52:07,737 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,747 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,789 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 530 [2024-11-13 14:52:07,792 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 14:52:07,793 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 14:52:07,793 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 14:52:07,793 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 14:52:07,805 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,805 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,808 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,828 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 14:52:07,828 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,828 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,835 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,842 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,844 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,845 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,848 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 14:52:07,849 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 14:52:07,849 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 14:52:07,849 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 14:52:07,851 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (1/1) ... [2024-11-13 14:52:07,857 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:52:07,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:52:07,887 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:52:07,890 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 14:52:07,916 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 14:52:07,917 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 14:52:07,917 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 14:52:07,917 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 14:52:08,028 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 14:52:08,030 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 14:52:08,651 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live. [2024-11-13 14:52:08,651 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 14:52:08,665 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 14:52:08,665 INFO L316 CfgBuilder]: Removed 5 assume(true) statements. [2024-11-13 14:52:08,665 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:52:08 BoogieIcfgContainer [2024-11-13 14:52:08,665 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 14:52:08,666 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 14:52:08,666 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 14:52:08,671 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 14:52:08,672 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:52:08,672 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 02:52:07" (1/3) ... [2024-11-13 14:52:08,673 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@710642f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:52:08, skipping insertion in model container [2024-11-13 14:52:08,673 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:52:08,673 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:52:07" (2/3) ... [2024-11-13 14:52:08,673 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@710642f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:52:08, skipping insertion in model container [2024-11-13 14:52:08,674 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:52:08,674 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:52:08" (3/3) ... [2024-11-13 14:52:08,675 INFO L333 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2024-11-13 14:52:08,728 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 14:52:08,728 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 14:52:08,728 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 14:52:08,729 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 14:52:08,729 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 14:52:08,729 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 14:52:08,729 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 14:52:08,729 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 14:52:08,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:08,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2024-11-13 14:52:08,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:08,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:08,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:08,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:08,786 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 14:52:08,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:08,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2024-11-13 14:52:08,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:08,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:08,802 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:08,802 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:08,813 INFO L745 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 137#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 189#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 79#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 15#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 148#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4#L117true assume !(1 == ~P_1_pc~0); 19#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 147#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 43#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 128#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 166#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 84#L185true assume 1 == ~P_2_pc~0; 53#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 54#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 93#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 80#L485true assume !(0 != activate_threads_~tmp___0~1#1); 108#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 123#L267true assume 1 == ~C_1_pc~0; 122#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 23#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 188#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116#L493true assume !(0 != activate_threads_~tmp___1~1#1); 149#L493-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 145#L547-2true [2024-11-13 14:52:08,814 INFO L747 eck$LassoCheckResult]: Loop: 145#L547-2true assume !false; 151#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 73#L396true assume !true; 70#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 30#L117-6true assume !(1 == ~P_1_pc~0); 35#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 194#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 56#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 36#L185-6true assume !(1 == ~P_2_pc~0); 51#L185-8true is_P_2_triggered_~__retres1~1#1 := 0; 187#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 191#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 141#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 98#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 69#L267-6true assume 1 == ~C_1_pc~0; 179#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 142#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 27#L493-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 183#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 90#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 175#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 91#L566true assume !(0 == start_simulation_~tmp~3#1); 41#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 161#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 78#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 112#L579true assume !(0 != start_simulation_~tmp___0~2#1); 145#L547-2true [2024-11-13 14:52:08,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:08,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2024-11-13 14:52:08,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:08,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353490159] [2024-11-13 14:52:08,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:08,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:08,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353490159] [2024-11-13 14:52:09,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353490159] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:09,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193732309] [2024-11-13 14:52:09,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,088 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:09,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:09,090 INFO L85 PathProgramCache]: Analyzing trace with hash 357423619, now seen corresponding path program 1 times [2024-11-13 14:52:09,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:09,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049660281] [2024-11-13 14:52:09,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:09,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:09,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049660281] [2024-11-13 14:52:09,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049660281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:52:09,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63772483] [2024-11-13 14:52:09,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,120 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:09,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:09,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:09,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:09,155 INFO L87 Difference]: Start difference. First operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:09,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:09,203 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2024-11-13 14:52:09,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2024-11-13 14:52:09,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-13 14:52:09,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2024-11-13 14:52:09,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2024-11-13 14:52:09,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2024-11-13 14:52:09,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2024-11-13 14:52:09,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:09,246 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-13 14:52:09,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2024-11-13 14:52:09,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2024-11-13 14:52:09,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:09,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2024-11-13 14:52:09,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-13 14:52:09,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:09,299 INFO L424 stractBuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2024-11-13 14:52:09,300 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 14:52:09,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2024-11-13 14:52:09,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-13 14:52:09,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:09,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:09,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:09,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:09,309 INFO L745 eck$LassoCheckResult]: Stem: 479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 499#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 559#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 448#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 449#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 529#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 398#L117 assume !(1 == ~P_1_pc~0); 399#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 461#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 520#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 476#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 477#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 553#L185 assume 1 == ~P_2_pc~0; 535#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 512#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 536#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 560#L485 assume !(0 != activate_threads_~tmp___0~1#1); 403#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 404#L267 assume 1 == ~C_1_pc~0; 457#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 458#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 475#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 438#L493 assume !(0 != activate_threads_~tmp___1~1#1); 439#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 530#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 422#L547-2 [2024-11-13 14:52:09,309 INFO L747 eck$LassoCheckResult]: Loop: 422#L547-2 assume !false; 523#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 532#L396 assume !false; 527#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 451#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 412#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 429#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 430#L361 assume !(0 != eval_~tmp___2~0#1); 549#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 556#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 502#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 488#L117-6 assume !(1 == ~P_1_pc~0); 489#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 504#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 507#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 462#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 463#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 505#L185-6 assume 1 == ~P_2_pc~0; 408#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 409#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 566#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 517#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 518#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 554#L267-6 assume 1 == ~C_1_pc~0; 555#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 390#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 519#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 521#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 482#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 558#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 472#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 562#L566 assume !(0 == start_simulation_~tmp~3#1); 513#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 491#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 485#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 493#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 494#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 510#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 421#L579 assume !(0 != start_simulation_~tmp___0~2#1); 422#L547-2 [2024-11-13 14:52:09,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:09,310 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2024-11-13 14:52:09,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:09,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970602703] [2024-11-13 14:52:09,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:09,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:09,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970602703] [2024-11-13 14:52:09,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970602703] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:09,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214514889] [2024-11-13 14:52:09,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,400 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:09,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:09,400 INFO L85 PathProgramCache]: Analyzing trace with hash 688046042, now seen corresponding path program 1 times [2024-11-13 14:52:09,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:09,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876327497] [2024-11-13 14:52:09,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:09,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:09,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876327497] [2024-11-13 14:52:09,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876327497] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:09,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580366349] [2024-11-13 14:52:09,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,545 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:09,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:09,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:09,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:09,546 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:09,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:09,576 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2024-11-13 14:52:09,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2024-11-13 14:52:09,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-13 14:52:09,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2024-11-13 14:52:09,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2024-11-13 14:52:09,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2024-11-13 14:52:09,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2024-11-13 14:52:09,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:09,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-13 14:52:09,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2024-11-13 14:52:09,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2024-11-13 14:52:09,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:09,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2024-11-13 14:52:09,590 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-13 14:52:09,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:09,591 INFO L424 stractBuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2024-11-13 14:52:09,591 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 14:52:09,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2024-11-13 14:52:09,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2024-11-13 14:52:09,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:09,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:09,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:09,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:09,595 INFO L745 eck$LassoCheckResult]: Stem: 844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 864#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 923#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 811#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 812#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 894#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 763#L117 assume !(1 == ~P_1_pc~0); 764#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 826#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 885#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 841#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 842#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 918#L185 assume 1 == ~P_2_pc~0; 899#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 877#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 900#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 924#L485 assume !(0 != activate_threads_~tmp___0~1#1); 766#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 767#L267 assume 1 == ~C_1_pc~0; 822#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 823#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 835#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 803#L493 assume !(0 != activate_threads_~tmp___1~1#1); 804#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 895#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 787#L547-2 [2024-11-13 14:52:09,595 INFO L747 eck$LassoCheckResult]: Loop: 787#L547-2 assume !false; 887#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 897#L396 assume !false; 892#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 815#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 777#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 794#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 795#L361 assume !(0 != eval_~tmp___2~0#1); 913#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 867#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 853#L117-6 assume !(1 == ~P_1_pc~0); 854#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 869#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 872#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 827#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 828#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 870#L185-6 assume 1 == ~P_2_pc~0; 773#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 774#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 931#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 882#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 883#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 919#L267-6 assume 1 == ~C_1_pc~0; 920#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 755#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 884#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 886#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 847#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 848#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 925#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 838#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 927#L566 assume !(0 == start_simulation_~tmp~3#1); 878#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 856#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 850#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 859#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 874#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 875#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 786#L579 assume !(0 != start_simulation_~tmp___0~2#1); 787#L547-2 [2024-11-13 14:52:09,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:09,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2024-11-13 14:52:09,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:09,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984897828] [2024-11-13 14:52:09,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:09,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:09,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984897828] [2024-11-13 14:52:09,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984897828] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:09,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008314551] [2024-11-13 14:52:09,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,717 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:09,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:09,718 INFO L85 PathProgramCache]: Analyzing trace with hash 688046042, now seen corresponding path program 2 times [2024-11-13 14:52:09,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:09,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771042515] [2024-11-13 14:52:09,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:09,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:09,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:09,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:09,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:09,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771042515] [2024-11-13 14:52:09,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771042515] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:09,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:09,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:09,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035584058] [2024-11-13 14:52:09,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:09,846 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:09,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:09,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:52:09,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:52:09,847 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:09,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:09,990 INFO L93 Difference]: Finished difference Result 190 states and 271 transitions. [2024-11-13 14:52:09,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190 states and 271 transitions. [2024-11-13 14:52:09,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2024-11-13 14:52:09,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190 states to 190 states and 271 transitions. [2024-11-13 14:52:09,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190 [2024-11-13 14:52:09,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190 [2024-11-13 14:52:09,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190 states and 271 transitions. [2024-11-13 14:52:09,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:09,996 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-13 14:52:09,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states and 271 transitions. [2024-11-13 14:52:10,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 190. [2024-11-13 14:52:10,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:10,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2024-11-13 14:52:10,004 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-13 14:52:10,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:52:10,005 INFO L424 stractBuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2024-11-13 14:52:10,005 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 14:52:10,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2024-11-13 14:52:10,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2024-11-13 14:52:10,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:10,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:10,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,008 INFO L745 eck$LassoCheckResult]: Stem: 1223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1247#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1243#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1307#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1190#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1191#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1273#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1142#L117 assume !(1 == ~P_1_pc~0); 1143#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1205#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1264#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1220#L477 assume !(0 != activate_threads_~tmp~1#1); 1221#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1299#L185 assume 1 == ~P_2_pc~0; 1280#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1256#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1281#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1308#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1147#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1148#L267 assume 1 == ~C_1_pc~0; 1201#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1202#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1219#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1182#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1183#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1275#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1166#L547-2 [2024-11-13 14:52:10,008 INFO L747 eck$LassoCheckResult]: Loop: 1166#L547-2 assume !false; 1267#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1277#L396 assume !false; 1271#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1195#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1156#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1173#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1174#L361 assume !(0 != eval_~tmp___2~0#1); 1293#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1246#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1236#L117-6 assume !(1 == ~P_1_pc~0); 1237#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 1249#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1251#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1206#L477-6 assume !(0 != activate_threads_~tmp~1#1); 1207#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1248#L185-6 assume 1 == ~P_2_pc~0; 1152#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1153#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1314#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1261#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1262#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1300#L267-6 assume 1 == ~C_1_pc~0; 1301#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1134#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1263#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1265#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1225#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1226#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1306#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1216#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1310#L566 assume !(0 == start_simulation_~tmp~3#1); 1257#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1232#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1229#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1235#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1252#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1253#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1165#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1166#L547-2 [2024-11-13 14:52:10,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,009 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2024-11-13 14:52:10,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836254413] [2024-11-13 14:52:10,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836254413] [2024-11-13 14:52:10,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836254413] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 14:52:10,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896506533] [2024-11-13 14:52:10,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,066 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:10,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1683693220, now seen corresponding path program 1 times [2024-11-13 14:52:10,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100880576] [2024-11-13 14:52:10,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100880576] [2024-11-13 14:52:10,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100880576] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:10,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297296324] [2024-11-13 14:52:10,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,167 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:10,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:10,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:52:10,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:52:10,168 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:10,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:10,310 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2024-11-13 14:52:10,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2024-11-13 14:52:10,317 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2024-11-13 14:52:10,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2024-11-13 14:52:10,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2024-11-13 14:52:10,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2024-11-13 14:52:10,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2024-11-13 14:52:10,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:10,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 665 transitions. [2024-11-13 14:52:10,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2024-11-13 14:52:10,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2024-11-13 14:52:10,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:10,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2024-11-13 14:52:10,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 610 transitions. [2024-11-13 14:52:10,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:52:10,386 INFO L424 stractBuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2024-11-13 14:52:10,386 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 14:52:10,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2024-11-13 14:52:10,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2024-11-13 14:52:10,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:10,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:10,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,397 INFO L745 eck$LassoCheckResult]: Stem: 1900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1918#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1919#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1995#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1867#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1868#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1957#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1818#L117 assume !(1 == ~P_1_pc~0); 1819#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1882#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1944#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1897#L477 assume !(0 != activate_threads_~tmp~1#1); 1898#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1985#L185 assume !(1 == ~P_2_pc~0); 1934#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 1935#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1965#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1996#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1820#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1821#L267 assume 1 == ~C_1_pc~0; 1878#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1879#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1891#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1856#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1857#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1960#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2007#L547-2 [2024-11-13 14:52:10,397 INFO L747 eck$LassoCheckResult]: Loop: 2007#L547-2 assume !false; 2188#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2186#L396 assume !false; 2182#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2178#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2174#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2173#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2172#L361 assume !(0 != eval_~tmp___2~0#1); 1989#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1923#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1909#L117-6 assume !(1 == ~P_1_pc~0); 1910#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 2239#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2238#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2237#L477-6 assume !(0 != activate_threads_~tmp~1#1); 2236#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2235#L185-6 assume !(1 == ~P_2_pc~0); 2234#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 2233#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2203#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2202#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2008#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1986#L267-6 assume 1 == ~C_1_pc~0; 1988#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2180#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2175#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2166#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2165#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2164#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2159#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2156#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2153#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2006#L566 assume !(0 == start_simulation_~tmp~3#1); 1936#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1937#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1980#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1913#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1914#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1932#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1933#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2194#L579 assume !(0 != start_simulation_~tmp___0~2#1); 2007#L547-2 [2024-11-13 14:52:10,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2024-11-13 14:52:10,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473045161] [2024-11-13 14:52:10,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473045161] [2024-11-13 14:52:10,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473045161] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 14:52:10,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687591971] [2024-11-13 14:52:10,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,475 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:10,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,475 INFO L85 PathProgramCache]: Analyzing trace with hash 553670045, now seen corresponding path program 1 times [2024-11-13 14:52:10,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508451298] [2024-11-13 14:52:10,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,561 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508451298] [2024-11-13 14:52:10,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508451298] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:10,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924523522] [2024-11-13 14:52:10,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:10,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:10,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:52:10,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:52:10,564 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:10,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:10,735 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2024-11-13 14:52:10,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2024-11-13 14:52:10,745 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2024-11-13 14:52:10,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2024-11-13 14:52:10,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2024-11-13 14:52:10,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2024-11-13 14:52:10,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2024-11-13 14:52:10,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:10,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2024-11-13 14:52:10,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2024-11-13 14:52:10,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2024-11-13 14:52:10,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:10,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2024-11-13 14:52:10,800 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2024-11-13 14:52:10,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:52:10,806 INFO L424 stractBuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2024-11-13 14:52:10,806 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 14:52:10,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2024-11-13 14:52:10,814 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2024-11-13 14:52:10,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:10,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:10,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:10,817 INFO L745 eck$LassoCheckResult]: Stem: 3528#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3550#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3551#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3659#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3493#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3494#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3596#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3443#L117 assume !(1 == ~P_1_pc~0); 3444#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3506#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3578#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3524#L477 assume !(0 != activate_threads_~tmp~1#1); 3525#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3643#L185 assume !(1 == ~P_2_pc~0); 3567#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3568#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3606#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3660#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3445#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3446#L267 assume !(1 == ~C_1_pc~0); 3507#L267-2 assume 2 == ~C_1_pc~0; 3648#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3517#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3518#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3482#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3483#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3600#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3467#L547-2 [2024-11-13 14:52:10,817 INFO L747 eck$LassoCheckResult]: Loop: 3467#L547-2 assume !false; 3603#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3604#L396 assume !false; 3590#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3591#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3530#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3531#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3630#L361 assume !(0 != eval_~tmp___2~0#1); 3632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4546#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4545#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4544#L117-6 assume !(1 == ~P_1_pc~0); 4543#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 4542#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4541#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4540#L477-6 assume !(0 != activate_threads_~tmp~1#1); 3608#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3609#L185-6 assume !(1 == ~P_2_pc~0); 4538#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 4536#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4535#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4534#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 3680#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3681#L267-6 assume !(1 == ~C_1_pc~0); 3615#L267-8 assume 2 == ~C_1_pc~0; 3616#L278-2 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3576#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3577#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3579#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 3580#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4525#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3676#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3520#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3664#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3665#L566 assume !(0 == start_simulation_~tmp~3#1); 4516#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4513#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3634#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3635#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3657#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3658#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4511#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3466#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3467#L547-2 [2024-11-13 14:52:10,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,819 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2024-11-13 14:52:10,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706117319] [2024-11-13 14:52:10,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706117319] [2024-11-13 14:52:10,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706117319] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:10,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887632329] [2024-11-13 14:52:10,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,896 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:10,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:10,896 INFO L85 PathProgramCache]: Analyzing trace with hash 432967031, now seen corresponding path program 1 times [2024-11-13 14:52:10,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:10,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011792945] [2024-11-13 14:52:10,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:10,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:10,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:10,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:10,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:10,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011792945] [2024-11-13 14:52:10,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011792945] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:10,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:10,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:10,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464804048] [2024-11-13 14:52:10,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:10,970 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:10,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:10,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:10,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:10,971 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:11,038 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2024-11-13 14:52:11,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2024-11-13 14:52:11,051 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2024-11-13 14:52:11,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2024-11-13 14:52:11,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2024-11-13 14:52:11,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2024-11-13 14:52:11,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2024-11-13 14:52:11,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:11,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2024-11-13 14:52:11,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2024-11-13 14:52:11,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2024-11-13 14:52:11,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2024-11-13 14:52:11,129 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2024-11-13 14:52:11,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:11,131 INFO L424 stractBuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2024-11-13 14:52:11,131 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 14:52:11,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2024-11-13 14:52:11,143 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2024-11-13 14:52:11,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:11,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:11,144 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,144 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,144 INFO L745 eck$LassoCheckResult]: Stem: 6139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6166#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6160#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6161#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6243#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6108#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6109#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6200#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6060#L117 assume !(1 == ~P_1_pc~0); 6061#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6119#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6187#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6135#L477 assume !(0 != activate_threads_~tmp~1#1); 6136#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6235#L185 assume !(1 == ~P_2_pc~0); 6176#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6177#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6209#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6244#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6062#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6063#L267 assume !(1 == ~C_1_pc~0); 6120#L267-2 assume !(2 == ~C_1_pc~0); 6208#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6129#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6130#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6097#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6098#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6204#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6264#L547-2 [2024-11-13 14:52:11,144 INFO L747 eck$LassoCheckResult]: Loop: 6264#L547-2 assume !false; 7391#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6241#L396 assume !false; 6242#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7378#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7375#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7372#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7368#L361 assume !(0 != eval_~tmp___2~0#1); 7369#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7508#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7507#L117-6 assume !(1 == ~P_1_pc~0); 7506#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 7505#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7504#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7503#L477-6 assume !(0 != activate_threads_~tmp~1#1); 7502#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7501#L185-6 assume !(1 == ~P_2_pc~0); 7500#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 7499#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7498#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7497#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7496#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7495#L267-6 assume !(1 == ~C_1_pc~0); 7494#L267-8 assume !(2 == ~C_1_pc~0); 7493#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 7492#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7491#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7490#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6142#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6143#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7472#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7471#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7429#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7424#L566 assume !(0 == start_simulation_~tmp~3#1); 7420#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7416#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7415#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7409#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7407#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7404#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7402#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6264#L547-2 [2024-11-13 14:52:11,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2024-11-13 14:52:11,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169266209] [2024-11-13 14:52:11,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,155 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:11,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:11,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,184 INFO L85 PathProgramCache]: Analyzing trace with hash 1424131704, now seen corresponding path program 1 times [2024-11-13 14:52:11,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545217254] [2024-11-13 14:52:11,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:11,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:11,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:11,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545217254] [2024-11-13 14:52:11,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545217254] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:11,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:11,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:52:11,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794474340] [2024-11-13 14:52:11,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:11,234 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:11,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:11,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:52:11,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:52:11,235 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:11,301 INFO L93 Difference]: Finished difference Result 1548 states and 2085 transitions. [2024-11-13 14:52:11,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1548 states and 2085 transitions. [2024-11-13 14:52:11,314 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1501 [2024-11-13 14:52:11,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1548 states to 1548 states and 2085 transitions. [2024-11-13 14:52:11,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1548 [2024-11-13 14:52:11,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1548 [2024-11-13 14:52:11,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1548 states and 2085 transitions. [2024-11-13 14:52:11,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:11,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1548 states and 2085 transitions. [2024-11-13 14:52:11,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1548 states and 2085 transitions. [2024-11-13 14:52:11,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1548 to 1500. [2024-11-13 14:52:11,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2024-11-13 14:52:11,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2024-11-13 14:52:11,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:52:11,361 INFO L424 stractBuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2024-11-13 14:52:11,361 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 14:52:11,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2024-11-13 14:52:11,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2024-11-13 14:52:11,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:11,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:11,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,371 INFO L745 eck$LassoCheckResult]: Stem: 9162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 9163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 9187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9180#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9181#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 9266#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 9132#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 9133#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9223#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 9080#L117 assume !(1 == ~P_1_pc~0); 9081#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 9141#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 9207#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9158#L477 assume !(0 != activate_threads_~tmp~1#1); 9159#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 9257#L185 assume !(1 == ~P_2_pc~0); 9198#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 9199#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 9231#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9267#L485 assume !(0 != activate_threads_~tmp___0~1#1); 9085#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 9086#L267 assume !(1 == ~C_1_pc~0); 9145#L267-2 assume !(2 == ~C_1_pc~0); 9229#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 9156#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 9157#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9119#L493 assume !(0 != activate_threads_~tmp___1~1#1); 9120#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9224#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 9285#L547-2 [2024-11-13 14:52:11,373 INFO L747 eck$LassoCheckResult]: Loop: 9285#L547-2 assume !false; 10272#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10142#L396 assume !false; 10268#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10254#L327 assume !(0 == ~P_1_st~0); 10255#L331 assume !(0 == ~P_2_st~0); 10252#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10253#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10243#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10244#L361 assume !(0 != eval_~tmp___2~0#1); 10374#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10373#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10372#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10371#L117-6 assume !(1 == ~P_1_pc~0); 10370#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 10369#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10368#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10366#L477-6 assume !(0 != activate_threads_~tmp~1#1); 10364#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10362#L185-6 assume !(1 == ~P_2_pc~0); 10360#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 10358#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10356#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10354#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10352#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10350#L267-6 assume !(1 == ~C_1_pc~0); 10348#L267-8 assume !(2 == ~C_1_pc~0); 10346#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10344#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10342#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10340#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10338#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10336#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10330#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10328#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10326#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10323#L566 assume !(0 == start_simulation_~tmp~3#1); 10321#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10318#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10317#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10299#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10296#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10294#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10291#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10288#L579 assume !(0 != start_simulation_~tmp___0~2#1); 9285#L547-2 [2024-11-13 14:52:11,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2024-11-13 14:52:11,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948491557] [2024-11-13 14:52:11,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:11,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,393 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:11,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,394 INFO L85 PathProgramCache]: Analyzing trace with hash 939554335, now seen corresponding path program 1 times [2024-11-13 14:52:11,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254912467] [2024-11-13 14:52:11,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:11,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:11,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:11,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254912467] [2024-11-13 14:52:11,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254912467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:11,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:11,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:11,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136958296] [2024-11-13 14:52:11,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:11,424 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:52:11,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:11,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:11,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:11,424 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:11,479 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2024-11-13 14:52:11,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2024-11-13 14:52:11,496 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2024-11-13 14:52:11,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2024-11-13 14:52:11,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2024-11-13 14:52:11,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2024-11-13 14:52:11,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2024-11-13 14:52:11,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:11,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-13 14:52:11,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2024-11-13 14:52:11,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2024-11-13 14:52:11,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2024-11-13 14:52:11,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-13 14:52:11,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:11,609 INFO L424 stractBuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2024-11-13 14:52:11,611 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 14:52:11,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2024-11-13 14:52:11,624 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2024-11-13 14:52:11,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:11,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:11,626 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,626 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:11,626 INFO L745 eck$LassoCheckResult]: Stem: 12994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 12995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 13024#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13018#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 13111#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 12961#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 12962#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13058#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 12911#L117 assume !(1 == ~P_1_pc~0); 12912#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 12973#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 13044#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12990#L477 assume !(0 != activate_threads_~tmp~1#1); 12991#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 13098#L185 assume !(1 == ~P_2_pc~0); 13033#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 13034#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 13068#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13112#L485 assume !(0 != activate_threads_~tmp___0~1#1); 12913#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 12914#L267 assume !(1 == ~C_1_pc~0); 12975#L267-2 assume !(2 == ~C_1_pc~0); 13067#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 12988#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 12989#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12949#L493 assume !(0 != activate_threads_~tmp___1~1#1); 12950#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13062#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 13135#L547-2 assume !false; 15021#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 13897#L396 [2024-11-13 14:52:11,626 INFO L747 eck$LassoCheckResult]: Loop: 13897#L396 assume !false; 14409#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14364#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14365#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14337#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14338#L361 assume 0 != eval_~tmp___2~0#1; 14884#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14883#L370 assume !(0 != eval_~tmp~0#1); 14882#L366 assume !(0 == ~P_2_st~0); 13905#L381 assume !(0 == ~C_1_st~0); 13897#L396 [2024-11-13 14:52:11,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,632 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 1 times [2024-11-13 14:52:11,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728431148] [2024-11-13 14:52:11,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,645 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:11,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,659 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:11,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1970158275, now seen corresponding path program 1 times [2024-11-13 14:52:11,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084369550] [2024-11-13 14:52:11,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:11,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:11,674 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:11,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:11,676 INFO L85 PathProgramCache]: Analyzing trace with hash -860559990, now seen corresponding path program 1 times [2024-11-13 14:52:11,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:11,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046865837] [2024-11-13 14:52:11,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:11,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:11,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:11,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:11,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:11,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046865837] [2024-11-13 14:52:11,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046865837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:11,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:11,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:11,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488998514] [2024-11-13 14:52:11,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:11,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:11,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:11,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:11,809 INFO L87 Difference]: Start difference. First operand 2325 states and 3118 transitions. cyclomatic complexity: 800 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:11,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:11,883 INFO L93 Difference]: Finished difference Result 3877 states and 5120 transitions. [2024-11-13 14:52:11,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3877 states and 5120 transitions. [2024-11-13 14:52:11,908 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3725 [2024-11-13 14:52:11,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3877 states to 3877 states and 5120 transitions. [2024-11-13 14:52:11,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3877 [2024-11-13 14:52:11,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3877 [2024-11-13 14:52:11,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3877 states and 5120 transitions. [2024-11-13 14:52:11,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:11,939 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3877 states and 5120 transitions. [2024-11-13 14:52:11,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3877 states and 5120 transitions. [2024-11-13 14:52:11,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3877 to 3793. [2024-11-13 14:52:11,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3229633535460057) internal successors, (5018), 3792 states have internal predecessors, (5018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:12,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5018 transitions. [2024-11-13 14:52:12,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2024-11-13 14:52:12,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:12,046 INFO L424 stractBuchiCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2024-11-13 14:52:12,046 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 14:52:12,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5018 transitions. [2024-11-13 14:52:12,061 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-13 14:52:12,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:12,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:12,063 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:12,063 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:12,063 INFO L745 eck$LassoCheckResult]: Stem: 19206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 19207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 19233#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19227#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19228#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 19322#L304-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 19323#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 21810#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21809#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 21808#L117 assume !(1 == ~P_1_pc~0); 21807#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 21806#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 21805#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21804#L477 assume !(0 != activate_threads_~tmp~1#1); 21803#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 21802#L185 assume !(1 == ~P_2_pc~0); 21801#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 21800#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 21799#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19324#L485 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 19125#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 19126#L267 assume !(1 == ~C_1_pc~0); 19313#L267-2 assume !(2 == ~C_1_pc~0); 19314#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 19199#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 19200#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19157#L493 assume !(0 != activate_threads_~tmp___1~1#1); 19158#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19348#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 19349#L547-2 assume !false; 21788#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 21727#L396 [2024-11-13 14:52:12,063 INFO L747 eck$LassoCheckResult]: Loop: 21727#L396 assume !false; 21728#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21551#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21552#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21547#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21548#L361 assume 0 != eval_~tmp___2~0#1; 21539#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 21540#L370 assume !(0 != eval_~tmp~0#1); 21519#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 21512#L385 assume !(0 != eval_~tmp___0~0#1); 21513#L381 assume !(0 == ~C_1_st~0); 21727#L396 [2024-11-13 14:52:12,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:12,064 INFO L85 PathProgramCache]: Analyzing trace with hash -131921906, now seen corresponding path program 1 times [2024-11-13 14:52:12,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:12,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230277266] [2024-11-13 14:52:12,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:12,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:12,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:12,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:12,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:12,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230277266] [2024-11-13 14:52:12,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230277266] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:12,098 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:12,098 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:52:12,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635435856] [2024-11-13 14:52:12,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:12,099 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:52:12,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:12,099 INFO L85 PathProgramCache]: Analyzing trace with hash -945506006, now seen corresponding path program 1 times [2024-11-13 14:52:12,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:12,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975795305] [2024-11-13 14:52:12,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:12,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:12,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,106 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:12,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:12,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:12,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:12,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:12,170 INFO L87 Difference]: Start difference. First operand 3793 states and 5018 transitions. cyclomatic complexity: 1232 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:12,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:12,193 INFO L93 Difference]: Finished difference Result 3768 states and 4990 transitions. [2024-11-13 14:52:12,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3768 states and 4990 transitions. [2024-11-13 14:52:12,213 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-13 14:52:12,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3768 states to 3768 states and 4990 transitions. [2024-11-13 14:52:12,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3768 [2024-11-13 14:52:12,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3768 [2024-11-13 14:52:12,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3768 states and 4990 transitions. [2024-11-13 14:52:12,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:12,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-13 14:52:12,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3768 states and 4990 transitions. [2024-11-13 14:52:12,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3768 to 3768. [2024-11-13 14:52:12,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3768 states, 3768 states have (on average 1.3243099787685775) internal successors, (4990), 3767 states have internal predecessors, (4990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:12,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 4990 transitions. [2024-11-13 14:52:12,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-13 14:52:12,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:12,368 INFO L424 stractBuchiCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2024-11-13 14:52:12,368 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 14:52:12,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3768 states and 4990 transitions. [2024-11-13 14:52:12,385 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2024-11-13 14:52:12,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:12,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:12,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:12,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:12,386 INFO L745 eck$LassoCheckResult]: Stem: 26771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 26772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 26799#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26792#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26793#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 26876#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 26738#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 26739#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26832#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 26688#L117 assume !(1 == ~P_1_pc~0); 26689#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 26747#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 26819#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26767#L477 assume !(0 != activate_threads_~tmp~1#1); 26768#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 26867#L185 assume !(1 == ~P_2_pc~0); 26808#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 26809#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 26842#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26877#L485 assume !(0 != activate_threads_~tmp___0~1#1); 26692#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 26693#L267 assume !(1 == ~C_1_pc~0); 26753#L267-2 assume !(2 == ~C_1_pc~0); 26840#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 26765#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 26766#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26724#L493 assume !(0 != activate_threads_~tmp___1~1#1); 26725#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26836#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 26900#L547-2 assume !false; 29830#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29826#L396 [2024-11-13 14:52:12,387 INFO L747 eck$LassoCheckResult]: Loop: 29826#L396 assume !false; 29823#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29819#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29817#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29814#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29810#L361 assume 0 != eval_~tmp___2~0#1; 29805#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 26694#L370 assume !(0 != eval_~tmp~0#1); 26696#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 26721#L385 assume !(0 != eval_~tmp___0~0#1); 26722#L381 assume !(0 == ~C_1_st~0); 29826#L396 [2024-11-13 14:52:12,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:12,387 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 2 times [2024-11-13 14:52:12,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:12,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065962203] [2024-11-13 14:52:12,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:12,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:12,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:12,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,414 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:12,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:12,416 INFO L85 PathProgramCache]: Analyzing trace with hash -945506006, now seen corresponding path program 2 times [2024-11-13 14:52:12,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:12,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039873383] [2024-11-13 14:52:12,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:12,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:12,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,423 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:12,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:12,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:12,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:12,433 INFO L85 PathProgramCache]: Analyzing trace with hash -907697539, now seen corresponding path program 1 times [2024-11-13 14:52:12,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:12,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870442113] [2024-11-13 14:52:12,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:12,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:12,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:52:12,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:52:12,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:52:12,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870442113] [2024-11-13 14:52:12,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870442113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:52:12,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:52:12,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:52:12,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453107392] [2024-11-13 14:52:12,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:52:12,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:52:12,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:52:12,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:52:12,567 INFO L87 Difference]: Start difference. First operand 3768 states and 4990 transitions. cyclomatic complexity: 1229 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:12,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:52:12,657 INFO L93 Difference]: Finished difference Result 6578 states and 8632 transitions. [2024-11-13 14:52:12,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6578 states and 8632 transitions. [2024-11-13 14:52:12,696 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2024-11-13 14:52:12,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6578 states to 6578 states and 8632 transitions. [2024-11-13 14:52:12,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6578 [2024-11-13 14:52:12,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6578 [2024-11-13 14:52:12,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6578 states and 8632 transitions. [2024-11-13 14:52:12,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:52:12,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-13 14:52:12,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6578 states and 8632 transitions. [2024-11-13 14:52:12,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6578 to 6578. [2024-11-13 14:52:12,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6578 states, 6578 states have (on average 1.3122529644268774) internal successors, (8632), 6577 states have internal predecessors, (8632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:52:12,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6578 states to 6578 states and 8632 transitions. [2024-11-13 14:52:12,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-13 14:52:12,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:52:12,903 INFO L424 stractBuchiCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2024-11-13 14:52:12,903 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 14:52:12,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6578 states and 8632 transitions. [2024-11-13 14:52:13,011 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2024-11-13 14:52:13,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:52:13,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:52:13,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:13,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:52:13,012 INFO L745 eck$LassoCheckResult]: Stem: 37126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 37127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 37156#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37148#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37149#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 37244#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 37092#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 37093#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37191#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 37042#L117 assume !(1 == ~P_1_pc~0); 37043#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 37105#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 37178#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 37121#L477 assume !(0 != activate_threads_~tmp~1#1); 37122#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 37233#L185 assume !(1 == ~P_2_pc~0); 37167#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 37168#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 37201#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37245#L485 assume !(0 != activate_threads_~tmp___0~1#1); 37046#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 37047#L267 assume !(1 == ~C_1_pc~0); 37108#L267-2 assume !(2 == ~C_1_pc~0); 37199#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 37119#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 37120#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37078#L493 assume !(0 != activate_threads_~tmp___1~1#1); 37079#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37195#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 37263#L547-2 assume !false; 38072#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 38066#L396 [2024-11-13 14:52:13,012 INFO L747 eck$LassoCheckResult]: Loop: 38066#L396 assume !false; 38067#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 38052#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 38053#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 38040#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38041#L361 assume 0 != eval_~tmp___2~0#1; 38027#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 38028#L370 assume !(0 != eval_~tmp~0#1); 38014#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 38015#L385 assume !(0 != eval_~tmp___0~0#1); 40587#L381 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40585#L400 assume !(0 != eval_~tmp___1~0#1); 38066#L396 [2024-11-13 14:52:13,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:13,013 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 3 times [2024-11-13 14:52:13,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:13,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721562650] [2024-11-13 14:52:13,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:13,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:13,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:13,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:13,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:13,039 INFO L85 PathProgramCache]: Analyzing trace with hash 754082820, now seen corresponding path program 1 times [2024-11-13 14:52:13,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:13,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589747542] [2024-11-13 14:52:13,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:13,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:13,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,046 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:13,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:13,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:52:13,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1926145297, now seen corresponding path program 1 times [2024-11-13 14:52:13,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:52:13,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466987941] [2024-11-13 14:52:13,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:52:13,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:52:13,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:13,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:13,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:52:14,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:14,106 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:52:14,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:52:14,223 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 02:52:14 BoogieIcfgContainer [2024-11-13 14:52:14,223 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 14:52:14,224 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 14:52:14,224 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 14:52:14,224 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 14:52:14,224 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:52:08" (3/4) ... [2024-11-13 14:52:14,226 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 14:52:14,297 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 14:52:14,297 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 14:52:14,299 INFO L158 Benchmark]: Toolchain (without parser) took 6994.85ms. Allocated memory was 142.6MB in the beginning and 218.1MB in the end (delta: 75.5MB). Free memory was 118.6MB in the beginning and 101.6MB in the end (delta: 17.1MB). Peak memory consumption was 87.1MB. Max. memory is 16.1GB. [2024-11-13 14:52:14,300 INFO L158 Benchmark]: CDTParser took 1.03ms. Allocated memory is still 142.6MB. Free memory is still 80.3MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:52:14,300 INFO L158 Benchmark]: CACSL2BoogieTranslator took 422.89ms. Allocated memory is still 142.6MB. Free memory was 118.4MB in the beginning and 104.5MB in the end (delta: 13.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 14:52:14,301 INFO L158 Benchmark]: Boogie Procedure Inliner took 63.06ms. Allocated memory is still 142.6MB. Free memory was 104.5MB in the beginning and 102.1MB in the end (delta: 2.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:52:14,301 INFO L158 Benchmark]: Boogie Preprocessor took 55.56ms. Allocated memory is still 142.6MB. Free memory was 102.1MB in the beginning and 99.4MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:52:14,302 INFO L158 Benchmark]: RCFGBuilder took 816.19ms. Allocated memory is still 142.6MB. Free memory was 99.4MB in the beginning and 69.4MB in the end (delta: 30.0MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-11-13 14:52:14,303 INFO L158 Benchmark]: BuchiAutomizer took 5556.74ms. Allocated memory was 142.6MB in the beginning and 218.1MB in the end (delta: 75.5MB). Free memory was 69.1MB in the beginning and 106.4MB in the end (delta: -37.3MB). Peak memory consumption was 36.8MB. Max. memory is 16.1GB. [2024-11-13 14:52:14,303 INFO L158 Benchmark]: Witness Printer took 73.69ms. Allocated memory is still 218.1MB. Free memory was 106.4MB in the beginning and 101.6MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:52:14,305 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.03ms. Allocated memory is still 142.6MB. Free memory is still 80.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 422.89ms. Allocated memory is still 142.6MB. Free memory was 118.4MB in the beginning and 104.5MB in the end (delta: 13.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 63.06ms. Allocated memory is still 142.6MB. Free memory was 104.5MB in the beginning and 102.1MB in the end (delta: 2.4MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 55.56ms. Allocated memory is still 142.6MB. Free memory was 102.1MB in the beginning and 99.4MB in the end (delta: 2.7MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 816.19ms. Allocated memory is still 142.6MB. Free memory was 99.4MB in the beginning and 69.4MB in the end (delta: 30.0MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 5556.74ms. Allocated memory was 142.6MB in the beginning and 218.1MB in the end (delta: 75.5MB). Free memory was 69.1MB in the beginning and 106.4MB in the end (delta: -37.3MB). Peak memory consumption was 36.8MB. Max. memory is 16.1GB. * Witness Printer took 73.69ms. Allocated memory is still 218.1MB. Free memory was 106.4MB in the beginning and 101.6MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6578 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.4s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.0s. Construction of modules took 0.4s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 11 MinimizatonAttempts, 257 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2677 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2677 mSDsluCounter, 5835 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3091 mSDsCounter, 111 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 302 IncrementalHoareTripleChecker+Invalid, 413 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 111 mSolverCounterUnsat, 2744 mSDtfsCounter, 302 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 14:52:14,338 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5277eeac-bad3-4b5e-9962-4178c910d211/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)