./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:10:39,977 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:10:40,068 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:10:40,081 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:10:40,081 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:10:40,106 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:10:40,107 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:10:40,107 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:10:40,108 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:10:40,108 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:10:40,108 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:10:40,108 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:10:40,108 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:10:40,109 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:10:40,109 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:10:40,109 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:10:40,109 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:10:40,109 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:10:40,112 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:10:40,112 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:10:40,112 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:10:40,112 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:10:40,112 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:10:40,112 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:10:40,113 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:10:40,114 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:10:40,114 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:10:40,114 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:10:40,114 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:10:40,114 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:10:40,115 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:10:40,115 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2024-11-13 15:10:40,469 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:10:40,482 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:10:40,488 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:10:40,489 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:10:40,490 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:10:40,492 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c Unable to find full path for "g++" [2024-11-13 15:10:42,392 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:10:42,670 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:10:42,672 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2024-11-13 15:10:42,698 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/data/5ceab9364/b9d8207c022f44968f6445ada469b687/FLAGd6e550498 [2024-11-13 15:10:42,717 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/data/5ceab9364/b9d8207c022f44968f6445ada469b687 [2024-11-13 15:10:42,720 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:10:42,726 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:10:42,727 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:10:42,727 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:10:42,731 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:10:42,731 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:10:42" (1/1) ... [2024-11-13 15:10:42,732 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5404f2c9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:42, skipping insertion in model container [2024-11-13 15:10:42,732 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:10:42" (1/1) ... [2024-11-13 15:10:42,754 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:10:42,964 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:10:42,985 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:10:43,046 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:10:43,068 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:10:43,069 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43 WrapperNode [2024-11-13 15:10:43,069 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:10:43,070 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:10:43,070 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:10:43,070 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:10:43,078 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,084 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,110 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 303 [2024-11-13 15:10:43,110 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:10:43,111 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:10:43,111 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:10:43,111 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:10:43,120 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,121 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,123 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,145 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:10:43,146 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,146 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,154 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,159 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,161 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,162 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,165 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:10:43,166 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:10:43,166 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:10:43,166 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:10:43,167 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (1/1) ... [2024-11-13 15:10:43,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:10:43,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:10:43,209 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:10:43,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:10:43,247 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:10:43,247 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:10:43,247 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:10:43,247 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:10:43,350 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:10:43,353 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:10:43,744 INFO L? ?]: Removed 41 outVars from TransFormulas that were not future-live. [2024-11-13 15:10:43,744 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:10:43,756 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:10:43,757 INFO L316 CfgBuilder]: Removed 4 assume(true) statements. [2024-11-13 15:10:43,757 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:10:43 BoogieIcfgContainer [2024-11-13 15:10:43,757 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:10:43,758 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:10:43,758 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:10:43,763 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:10:43,764 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:10:43,764 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:10:42" (1/3) ... [2024-11-13 15:10:43,765 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2bcaadae and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:10:43, skipping insertion in model container [2024-11-13 15:10:43,766 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:10:43,766 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:10:43" (2/3) ... [2024-11-13 15:10:43,766 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2bcaadae and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:10:43, skipping insertion in model container [2024-11-13 15:10:43,766 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:10:43,766 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:10:43" (3/3) ... [2024-11-13 15:10:43,768 INFO L333 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2024-11-13 15:10:43,829 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:10:43,830 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:10:43,830 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:10:43,830 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:10:43,830 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:10:43,830 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:10:43,831 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:10:43,832 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:10:43,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:43,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-13 15:10:43,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:43,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:43,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:43,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:43,871 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:10:43,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:43,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-13 15:10:43,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:43,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:43,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:43,884 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:43,891 INFO L745 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 101#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 39#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 106#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 56#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 74#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 36#L315true assume !(0 != activate_threads_~tmp~1#1); 62#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 96#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 68#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 37#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2024-11-13 15:10:43,892 INFO L747 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 102#L364true assume false; 65#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 41#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 54#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 55#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 59#L84-3true assume 1 == ~c_dr_pc~0; 44#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 104#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume !(1 == ~q_write_ev~0); 53#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 75#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2024-11-13 15:10:43,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:43,897 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2024-11-13 15:10:43,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:43,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819838049] [2024-11-13 15:10:43,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:43,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:44,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:44,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:44,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:44,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819838049] [2024-11-13 15:10:44,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1819838049] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:44,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:44,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:44,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830280637] [2024-11-13 15:10:44,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:44,171 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:44,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:44,173 INFO L85 PathProgramCache]: Analyzing trace with hash -973468315, now seen corresponding path program 1 times [2024-11-13 15:10:44,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:44,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32608385] [2024-11-13 15:10:44,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:44,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:44,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:44,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:44,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:44,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32608385] [2024-11-13 15:10:44,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32608385] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:44,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:44,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:10:44,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873487815] [2024-11-13 15:10:44,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:44,223 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:44,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:44,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:10:44,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:10:44,257 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:44,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:44,320 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2024-11-13 15:10:44,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2024-11-13 15:10:44,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2024-11-13 15:10:44,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2024-11-13 15:10:44,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2024-11-13 15:10:44,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2024-11-13 15:10:44,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2024-11-13 15:10:44,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:44,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-13 15:10:44,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2024-11-13 15:10:44,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2024-11-13 15:10:44,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:44,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2024-11-13 15:10:44,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-13 15:10:44,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:10:44,394 INFO L424 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2024-11-13 15:10:44,396 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:10:44,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2024-11-13 15:10:44,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2024-11-13 15:10:44,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:44,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:44,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:44,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:44,403 INFO L745 eck$LassoCheckResult]: Stem: 272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 239#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 280#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 301#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299#L275 assume !(0 == ~q_read_ev~0); 300#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 283#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 282#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315 assume !(0 != activate_threads_~tmp~1#1); 245#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 246#L84 assume 1 == ~c_dr_pc~0; 292#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 259#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 260#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 222#L323 assume !(0 != activate_threads_~tmp___0~1#1); 223#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 308#L293 assume !(1 == ~q_read_ev~0); 215#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 216#L298-1 assume { :end_inline_reset_delta_events } true; 241#L419-2 [2024-11-13 15:10:44,403 INFO L747 eck$LassoCheckResult]: Loop: 241#L419-2 assume !false; 242#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 257#L364 assume !false; 288#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 252#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 237#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 238#L344 assume !(0 != eval_~tmp___1~0#1); 253#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254#L222-3 assume !(1 == ~q_req_up~0); 285#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 279#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 306#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 228#L65-3 assume !(1 == ~p_dw_pc~0); 229#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 263#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 307#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 295#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 276#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 277#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 294#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 274#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 226#L293-5 assume !(1 == ~q_write_ev~0); 227#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 289#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 290#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 247#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 233#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 234#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 293#L436 assume !(0 != start_simulation_~tmp~4#1); 241#L419-2 [2024-11-13 15:10:44,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:44,404 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2024-11-13 15:10:44,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:44,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995729005] [2024-11-13 15:10:44,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:44,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:44,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:44,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:44,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:44,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995729005] [2024-11-13 15:10:44,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995729005] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:44,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:44,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:10:44,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855154235] [2024-11-13 15:10:44,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:44,588 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:44,588 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:44,588 INFO L85 PathProgramCache]: Analyzing trace with hash -966857865, now seen corresponding path program 1 times [2024-11-13 15:10:44,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:44,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593851584] [2024-11-13 15:10:44,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:44,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:44,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:44,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:44,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:44,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593851584] [2024-11-13 15:10:44,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593851584] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:44,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:44,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:44,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045658781] [2024-11-13 15:10:44,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:44,709 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:44,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:44,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:10:44,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:10:44,710 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:44,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:44,869 INFO L93 Difference]: Finished difference Result 211 states and 299 transitions. [2024-11-13 15:10:44,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 299 transitions. [2024-11-13 15:10:44,874 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 177 [2024-11-13 15:10:44,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 299 transitions. [2024-11-13 15:10:44,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2024-11-13 15:10:44,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2024-11-13 15:10:44,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 299 transitions. [2024-11-13 15:10:44,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:44,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 211 states and 299 transitions. [2024-11-13 15:10:44,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 299 transitions. [2024-11-13 15:10:44,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2024-11-13 15:10:44,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.4285714285714286) internal successors, (280), 195 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:44,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 280 transitions. [2024-11-13 15:10:44,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 280 transitions. [2024-11-13 15:10:44,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:10:44,906 INFO L424 stractBuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2024-11-13 15:10:44,906 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:10:44,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 280 transitions. [2024-11-13 15:10:44,908 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 164 [2024-11-13 15:10:44,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:44,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:44,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:44,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:44,912 INFO L745 eck$LassoCheckResult]: Stem: 587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 611#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 565#L222 assume !(1 == ~q_req_up~0); 552#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 553#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 597#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 616#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 614#L275 assume !(0 == ~q_read_ev~0); 615#L275-2 assume !(0 == ~q_write_ev~0); 600#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 601#L65 assume !(1 == ~p_dw_pc~0); 608#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 609#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 585#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 586#L315 assume !(0 != activate_threads_~tmp~1#1); 560#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 561#L84 assume !(1 == ~c_dr_pc~0); 581#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 575#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 576#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 538#L323 assume !(0 != activate_threads_~tmp___0~1#1); 539#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 624#L293 assume !(1 == ~q_read_ev~0); 532#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 533#L298-1 assume { :end_inline_reset_delta_events } true; 619#L419-2 [2024-11-13 15:10:44,913 INFO L747 eck$LassoCheckResult]: Loop: 619#L419-2 assume !false; 696#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 692#L364 assume !false; 690#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 688#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 686#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 684#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 680#L344 assume !(0 != eval_~tmp___1~0#1); 677#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 663#L222-3 assume !(1 == ~q_req_up~0); 658#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 652#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 651#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 631#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 544#L65-3 assume !(1 == ~p_dw_pc~0); 545#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 726#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 725#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 724#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 723#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 722#L84-3 assume !(1 == ~c_dr_pc~0); 721#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 720#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 719#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 718#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 717#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 715#L293-5 assume !(1 == ~q_write_ev~0); 713#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 711#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 709#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 707#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 705#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 703#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 701#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 699#L436 assume !(0 != start_simulation_~tmp~4#1); 619#L419-2 [2024-11-13 15:10:44,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:44,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2024-11-13 15:10:44,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:44,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139734937] [2024-11-13 15:10:44,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:44,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:44,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139734937] [2024-11-13 15:10:45,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139734937] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:10:45,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988995474] [2024-11-13 15:10:45,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,015 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:45,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,015 INFO L85 PathProgramCache]: Analyzing trace with hash 209746454, now seen corresponding path program 1 times [2024-11-13 15:10:45,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288515226] [2024-11-13 15:10:45,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288515226] [2024-11-13 15:10:45,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288515226] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:45,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853983115] [2024-11-13 15:10:45,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,096 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:45,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:45,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:10:45,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:10:45,097 INFO L87 Difference]: Start difference. First operand 196 states and 280 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:45,258 INFO L93 Difference]: Finished difference Result 449 states and 621 transitions. [2024-11-13 15:10:45,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 621 transitions. [2024-11-13 15:10:45,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2024-11-13 15:10:45,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 621 transitions. [2024-11-13 15:10:45,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-13 15:10:45,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-13 15:10:45,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 621 transitions. [2024-11-13 15:10:45,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:45,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-13 15:10:45,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 621 transitions. [2024-11-13 15:10:45,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-13 15:10:45,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3830734966592428) internal successors, (621), 448 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 621 transitions. [2024-11-13 15:10:45,311 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-13 15:10:45,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:10:45,312 INFO L424 stractBuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2024-11-13 15:10:45,312 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:10:45,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 621 transitions. [2024-11-13 15:10:45,319 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2024-11-13 15:10:45,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:45,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:45,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,324 INFO L745 eck$LassoCheckResult]: Stem: 1250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1222#L222 assume !(1 == ~q_req_up~0); 1224#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1262#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1263#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1298#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1299#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1287#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1302#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1357#L65 assume !(1 == ~p_dw_pc~0); 1356#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1355#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1354#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1353#L315 assume !(0 != activate_threads_~tmp~1#1); 1352#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1351#L84 assume !(1 == ~c_dr_pc~0); 1350#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1349#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1348#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1347#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1346#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1345#L293 assume !(1 == ~q_read_ev~0); 1344#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1189#L298-1 assume { :end_inline_reset_delta_events } true; 1536#L419-2 [2024-11-13 15:10:45,324 INFO L747 eck$LassoCheckResult]: Loop: 1536#L419-2 assume !false; 1534#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1400#L364 assume !false; 1532#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1530#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1527#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1525#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1522#L344 assume !(0 != eval_~tmp___1~0#1); 1523#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1609#L222-3 assume !(1 == ~q_req_up~0); 1607#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1605#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1304#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1200#L65-3 assume !(1 == ~p_dw_pc~0); 1201#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1237#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1300#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1307#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1279#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1280#L84-3 assume !(1 == ~c_dr_pc~0); 1626#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1256#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1257#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1619#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1618#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1617#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1615#L293-5 assume !(1 == ~q_write_ev~0); 1197#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1455#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1439#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1415#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1413#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1410#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1327#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1328#L436 assume !(0 != start_simulation_~tmp~4#1); 1536#L419-2 [2024-11-13 15:10:45,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2024-11-13 15:10:45,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698074314] [2024-11-13 15:10:45,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698074314] [2024-11-13 15:10:45,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698074314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:45,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020968289] [2024-11-13 15:10:45,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,412 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:45,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,412 INFO L85 PathProgramCache]: Analyzing trace with hash 209746454, now seen corresponding path program 2 times [2024-11-13 15:10:45,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216567943] [2024-11-13 15:10:45,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216567943] [2024-11-13 15:10:45,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [216567943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:45,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950430841] [2024-11-13 15:10:45,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,468 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:45,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:45,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:10:45,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:10:45,469 INFO L87 Difference]: Start difference. First operand 449 states and 621 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:45,517 INFO L93 Difference]: Finished difference Result 701 states and 951 transitions. [2024-11-13 15:10:45,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 951 transitions. [2024-11-13 15:10:45,526 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 586 [2024-11-13 15:10:45,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 951 transitions. [2024-11-13 15:10:45,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2024-11-13 15:10:45,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2024-11-13 15:10:45,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 951 transitions. [2024-11-13 15:10:45,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:45,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 701 states and 951 transitions. [2024-11-13 15:10:45,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 951 transitions. [2024-11-13 15:10:45,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2024-11-13 15:10:45,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3588235294117648) internal successors, (693), 509 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 693 transitions. [2024-11-13 15:10:45,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 510 states and 693 transitions. [2024-11-13 15:10:45,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:10:45,573 INFO L424 stractBuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2024-11-13 15:10:45,573 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:10:45,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 693 transitions. [2024-11-13 15:10:45,579 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2024-11-13 15:10:45,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:45,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:45,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,582 INFO L745 eck$LassoCheckResult]: Stem: 2403#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2429#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2379#L222 assume !(1 == ~q_req_up~0); 2365#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2366#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2412#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2435#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2431#L275 assume !(0 == ~q_read_ev~0); 2432#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2443#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2486#L65 assume !(1 == ~p_dw_pc~0); 2484#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2482#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2480#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2478#L315 assume !(0 != activate_threads_~tmp~1#1); 2476#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2474#L84 assume !(1 == ~c_dr_pc~0); 2472#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2470#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2468#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2466#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2464#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2462#L293 assume !(1 == ~q_read_ev~0); 2459#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2346#L298-1 assume { :end_inline_reset_delta_events } true; 2441#L419-2 [2024-11-13 15:10:45,583 INFO L747 eck$LassoCheckResult]: Loop: 2441#L419-2 assume !false; 2776#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2774#L364 assume !false; 2773#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2772#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2766#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2367#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2368#L344 assume !(0 != eval_~tmp___1~0#1); 2382#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2383#L222-3 assume !(1 == ~q_req_up~0); 2422#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2826#L275-3 assume !(0 == ~q_read_ev~0); 2824#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2823#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2822#L65-3 assume !(1 == ~p_dw_pc~0); 2821#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2820#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2819#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2818#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2817#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2816#L84-3 assume !(1 == ~c_dr_pc~0); 2815#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2814#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2813#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2812#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2811#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2810#L293-3 assume !(1 == ~q_read_ev~0); 2687#L293-5 assume !(1 == ~q_write_ev~0); 2808#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2789#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2421#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2398#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2399#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2779#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2778#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2777#L436 assume !(0 != start_simulation_~tmp~4#1); 2441#L419-2 [2024-11-13 15:10:45,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,583 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2024-11-13 15:10:45,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557489859] [2024-11-13 15:10:45,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557489859] [2024-11-13 15:10:45,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557489859] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 15:10:45,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713928807] [2024-11-13 15:10:45,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,671 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:45,671 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,671 INFO L85 PathProgramCache]: Analyzing trace with hash -42731946, now seen corresponding path program 1 times [2024-11-13 15:10:45,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041794110] [2024-11-13 15:10:45,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:45,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:45,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:45,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1041794110] [2024-11-13 15:10:45,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1041794110] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:45,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:45,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:45,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514905127] [2024-11-13 15:10:45,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:45,729 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:45,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:45,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:10:45,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:10:45,730 INFO L87 Difference]: Start difference. First operand 510 states and 693 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:45,831 INFO L93 Difference]: Finished difference Result 745 states and 1002 transitions. [2024-11-13 15:10:45,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 1002 transitions. [2024-11-13 15:10:45,839 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 622 [2024-11-13 15:10:45,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 1002 transitions. [2024-11-13 15:10:45,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2024-11-13 15:10:45,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2024-11-13 15:10:45,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 1002 transitions. [2024-11-13 15:10:45,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:45,849 INFO L218 hiAutomatonCegarLoop]: Abstraction has 745 states and 1002 transitions. [2024-11-13 15:10:45,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 1002 transitions. [2024-11-13 15:10:45,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2024-11-13 15:10:45,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:45,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2024-11-13 15:10:45,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 563 states and 759 transitions. [2024-11-13 15:10:45,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:10:45,884 INFO L424 stractBuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2024-11-13 15:10:45,885 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:10:45,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2024-11-13 15:10:45,890 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2024-11-13 15:10:45,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:45,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:45,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:45,893 INFO L745 eck$LassoCheckResult]: Stem: 3670#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3697#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3645#L222 assume !(1 == ~q_req_up~0); 3633#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3634#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3772#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3708#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3699#L275 assume !(0 == ~q_read_ev~0); 3700#L275-2 assume !(0 == ~q_write_ev~0); 3683#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3684#L65 assume !(1 == ~p_dw_pc~0); 3693#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3694#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3665#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3666#L315 assume !(0 != activate_threads_~tmp~1#1); 3639#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3640#L84 assume !(1 == ~c_dr_pc~0); 3660#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3655#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3656#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3616#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3617#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3713#L293 assume !(1 == ~q_read_ev~0); 3610#L293-2 assume !(1 == ~q_write_ev~0); 3611#L298-1 assume { :end_inline_reset_delta_events } true; 3637#L419-2 [2024-11-13 15:10:45,894 INFO L747 eck$LassoCheckResult]: Loop: 3637#L419-2 assume !false; 3638#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3721#L364 assume !false; 3682#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3647#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3613#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3631#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3632#L344 assume !(0 != eval_~tmp___1~0#1); 3815#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4150#L222-3 assume !(1 == ~q_req_up~0); 3681#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3676#L275-3 assume !(0 == ~q_read_ev~0); 3677#L275-5 assume !(0 == ~q_write_ev~0); 3710#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3622#L65-3 assume !(1 == ~p_dw_pc~0); 3623#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3659#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3709#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3711#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3695#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3614#L84-3 assume !(1 == ~c_dr_pc~0); 3615#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4160#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4158#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4156#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4154#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4152#L293-3 assume !(1 == ~q_read_ev~0); 3620#L293-5 assume !(1 == ~q_write_ev~0); 3621#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3685#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3686#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3664#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3641#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3626#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3627#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3691#L436 assume !(0 != start_simulation_~tmp~4#1); 3637#L419-2 [2024-11-13 15:10:45,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,894 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2024-11-13 15:10:45,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558358865] [2024-11-13 15:10:45,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:45,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:45,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:45,951 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:45,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:45,952 INFO L85 PathProgramCache]: Analyzing trace with hash -176745452, now seen corresponding path program 1 times [2024-11-13 15:10:45,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:45,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002393976] [2024-11-13 15:10:45,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:45,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:45,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002393976] [2024-11-13 15:10:46,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002393976] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:10:46,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031391342] [2024-11-13 15:10:46,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,041 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:46,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:46,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:10:46,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:10:46,042 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:46,097 INFO L93 Difference]: Finished difference Result 593 states and 789 transitions. [2024-11-13 15:10:46,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 593 states and 789 transitions. [2024-11-13 15:10:46,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2024-11-13 15:10:46,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 593 states to 593 states and 789 transitions. [2024-11-13 15:10:46,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 593 [2024-11-13 15:10:46,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 593 [2024-11-13 15:10:46,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 593 states and 789 transitions. [2024-11-13 15:10:46,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:46,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 593 states and 789 transitions. [2024-11-13 15:10:46,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 593 states and 789 transitions. [2024-11-13 15:10:46,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 593 to 581. [2024-11-13 15:10:46,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3373493975903614) internal successors, (777), 580 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 777 transitions. [2024-11-13 15:10:46,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 581 states and 777 transitions. [2024-11-13 15:10:46,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:10:46,139 INFO L424 stractBuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2024-11-13 15:10:46,139 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:10:46,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 777 transitions. [2024-11-13 15:10:46,144 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2024-11-13 15:10:46,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:46,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:46,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,145 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,145 INFO L745 eck$LassoCheckResult]: Stem: 4834#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4863#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4810#L222 assume !(1 == ~q_req_up~0); 4812#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4945#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4943#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4941#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4939#L275 assume !(0 == ~q_read_ev~0); 4879#L275-2 assume !(0 == ~q_write_ev~0); 4880#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4935#L65 assume !(1 == ~p_dw_pc~0); 4933#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4931#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4929#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4927#L315 assume !(0 != activate_threads_~tmp~1#1); 4925#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4923#L84 assume !(1 == ~c_dr_pc~0); 4921#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4919#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4917#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4915#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4913#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4911#L293 assume !(1 == ~q_read_ev~0); 4910#L293-2 assume !(1 == ~q_write_ev~0); 4875#L298-1 assume { :end_inline_reset_delta_events } true; 4800#L419-2 [2024-11-13 15:10:46,146 INFO L747 eck$LassoCheckResult]: Loop: 4800#L419-2 assume !false; 4801#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4816#L364 assume !false; 4852#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4813#L255 assume !(0 == ~p_dw_st~0); 4776#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4778#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4825#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5131#L344 assume !(0 != eval_~tmp___1~0#1); 5274#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5338#L222-3 assume !(1 == ~q_req_up~0); 4874#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4844#L275-3 assume !(0 == ~q_read_ev~0); 4845#L275-5 assume !(0 == ~q_write_ev~0); 5325#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5354#L65-3 assume !(1 == ~p_dw_pc~0); 5353#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5352#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5351#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5350#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5346#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5345#L84-3 assume !(1 == ~c_dr_pc~0); 4870#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4842#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4843#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4859#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4839#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4840#L293-3 assume !(1 == ~q_read_ev~0); 4877#L293-5 assume !(1 == ~q_write_ev~0); 5293#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5291#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5288#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5284#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5282#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5280#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5277#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5276#L436 assume !(0 != start_simulation_~tmp~4#1); 4800#L419-2 [2024-11-13 15:10:46,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,146 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2024-11-13 15:10:46,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381363706] [2024-11-13 15:10:46,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,165 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:46,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,182 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:46,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1871138352, now seen corresponding path program 1 times [2024-11-13 15:10:46,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856037311] [2024-11-13 15:10:46,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856037311] [2024-11-13 15:10:46,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856037311] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,288 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:10:46,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565337125] [2024-11-13 15:10:46,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,289 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:46,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:46,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:10:46,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:10:46,289 INFO L87 Difference]: Start difference. First operand 581 states and 777 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:46,344 INFO L93 Difference]: Finished difference Result 593 states and 777 transitions. [2024-11-13 15:10:46,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 593 states and 777 transitions. [2024-11-13 15:10:46,350 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2024-11-13 15:10:46,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 593 states to 593 states and 777 transitions. [2024-11-13 15:10:46,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 593 [2024-11-13 15:10:46,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 593 [2024-11-13 15:10:46,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 593 states and 777 transitions. [2024-11-13 15:10:46,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:46,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 593 states and 777 transitions. [2024-11-13 15:10:46,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 593 states and 777 transitions. [2024-11-13 15:10:46,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 593 to 593. [2024-11-13 15:10:46,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 593 states, 593 states have (on average 1.3102866779089377) internal successors, (777), 592 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 593 states to 593 states and 777 transitions. [2024-11-13 15:10:46,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 593 states and 777 transitions. [2024-11-13 15:10:46,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:10:46,387 INFO L424 stractBuchiCegarLoop]: Abstraction has 593 states and 777 transitions. [2024-11-13 15:10:46,387 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:10:46,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 593 states and 777 transitions. [2024-11-13 15:10:46,391 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2024-11-13 15:10:46,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:46,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:46,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,393 INFO L745 eck$LassoCheckResult]: Stem: 6018#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5992#L222 assume !(1 == ~q_req_up~0); 5994#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6136#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6134#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6132#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6130#L275 assume !(0 == ~q_read_ev~0); 6065#L275-2 assume !(0 == ~q_write_ev~0); 6066#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6126#L65 assume !(1 == ~p_dw_pc~0); 6124#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6122#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6120#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6118#L315 assume !(0 != activate_threads_~tmp~1#1); 6116#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6114#L84 assume !(1 == ~c_dr_pc~0); 6112#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6110#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6108#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6106#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6104#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6102#L293 assume !(1 == ~q_read_ev~0); 5956#L293-2 assume !(1 == ~q_write_ev~0); 5957#L298-1 assume { :end_inline_reset_delta_events } true; 6385#L419-2 [2024-11-13 15:10:46,393 INFO L747 eck$LassoCheckResult]: Loop: 6385#L419-2 assume !false; 6382#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6087#L364 assume !false; 6088#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5995#L255 assume !(0 == ~p_dw_st~0); 5958#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5960#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6007#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6354#L344 assume !(0 != eval_~tmp___1~0#1); 6536#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6534#L222-3 assume !(1 == ~q_req_up~0); 6033#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6028#L275-3 assume !(0 == ~q_read_ev~0); 6029#L275-5 assume !(0 == ~q_write_ev~0); 6069#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6544#L65-3 assume !(1 == ~p_dw_pc~0); 6543#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6067#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6068#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6542#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6541#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6540#L84-3 assume !(1 == ~c_dr_pc~0); 6539#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6026#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6027#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6045#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6023#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6024#L293-3 assume !(1 == ~q_read_ev~0); 6063#L293-5 assume !(1 == ~q_write_ev~0); 6417#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6410#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6405#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6400#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6395#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6392#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6389#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6388#L436 assume !(0 != start_simulation_~tmp~4#1); 6385#L419-2 [2024-11-13 15:10:46,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2024-11-13 15:10:46,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942845865] [2024-11-13 15:10:46,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:46,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:46,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,430 INFO L85 PathProgramCache]: Analyzing trace with hash 429684238, now seen corresponding path program 1 times [2024-11-13 15:10:46,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993138967] [2024-11-13 15:10:46,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993138967] [2024-11-13 15:10:46,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993138967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:46,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923134973] [2024-11-13 15:10:46,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,476 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:46,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:46,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:10:46,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:10:46,477 INFO L87 Difference]: Start difference. First operand 593 states and 777 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:46,514 INFO L93 Difference]: Finished difference Result 832 states and 1065 transitions. [2024-11-13 15:10:46,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 832 states and 1065 transitions. [2024-11-13 15:10:46,521 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-13 15:10:46,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 832 states to 832 states and 1065 transitions. [2024-11-13 15:10:46,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 832 [2024-11-13 15:10:46,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 832 [2024-11-13 15:10:46,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 832 states and 1065 transitions. [2024-11-13 15:10:46,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:46,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 832 states and 1065 transitions. [2024-11-13 15:10:46,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 832 states and 1065 transitions. [2024-11-13 15:10:46,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 832 to 832. [2024-11-13 15:10:46,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 832 states, 832 states have (on average 1.2800480769230769) internal successors, (1065), 831 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 832 states to 832 states and 1065 transitions. [2024-11-13 15:10:46,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 832 states and 1065 transitions. [2024-11-13 15:10:46,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:10:46,559 INFO L424 stractBuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2024-11-13 15:10:46,559 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:10:46,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 832 states and 1065 transitions. [2024-11-13 15:10:46,566 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-13 15:10:46,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:46,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:46,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,569 INFO L745 eck$LassoCheckResult]: Stem: 7449#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 7450#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 7478#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7423#L222 assume !(1 == ~q_req_up~0); 7409#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7410#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 7461#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8095#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8093#L275 assume !(0 == ~q_read_ev~0); 8091#L275-2 assume !(0 == ~q_write_ev~0); 8053#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8088#L65 assume !(1 == ~p_dw_pc~0); 8087#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 7514#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7446#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7447#L315 assume !(0 != activate_threads_~tmp~1#1); 7417#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7418#L84 assume !(1 == ~c_dr_pc~0); 7439#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 7433#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7434#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7394#L323 assume !(0 != activate_threads_~tmp___0~1#1); 7395#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7497#L293 assume !(1 == ~q_read_ev~0); 7498#L293-2 assume !(1 == ~q_write_ev~0); 8148#L298-1 assume { :end_inline_reset_delta_events } true; 8146#L419-2 [2024-11-13 15:10:46,569 INFO L747 eck$LassoCheckResult]: Loop: 8146#L419-2 assume !false; 8145#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 7828#L364 assume !false; 7467#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7425#L255 assume !(0 == ~p_dw_st~0); 7389#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 7391#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8124#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8104#L344 assume !(0 != eval_~tmp___1~0#1); 8105#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8204#L222-3 assume !(1 == ~q_req_up~0); 7464#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7459#L275-3 assume !(0 == ~q_read_ev~0); 7460#L275-5 assume !(0 == ~q_write_ev~0); 8189#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8216#L65-3 assume !(1 == ~p_dw_pc~0); 7437#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 7438#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7490#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7494#L315-3 assume !(0 != activate_threads_~tmp~1#1); 7495#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7392#L84-3 assume !(1 == ~c_dr_pc~0); 7393#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 7457#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7458#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7473#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 7455#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7456#L293-3 assume !(1 == ~q_read_ev~0); 7489#L293-5 assume !(1 == ~q_write_ev~0); 8157#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8156#L255-1 assume !(0 == ~p_dw_st~0); 8154#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8153#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8152#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8151#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8150#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8149#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8147#L436 assume !(0 != start_simulation_~tmp~4#1); 8146#L419-2 [2024-11-13 15:10:46,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2024-11-13 15:10:46,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404184829] [2024-11-13 15:10:46,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404184829] [2024-11-13 15:10:46,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404184829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:10:46,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590859617] [2024-11-13 15:10:46,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,617 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:10:46,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,617 INFO L85 PathProgramCache]: Analyzing trace with hash 310765730, now seen corresponding path program 1 times [2024-11-13 15:10:46,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474337693] [2024-11-13 15:10:46,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474337693] [2024-11-13 15:10:46,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474337693] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:10:46,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915363046] [2024-11-13 15:10:46,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,729 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:10:46,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:46,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:10:46,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:10:46,729 INFO L87 Difference]: Start difference. First operand 832 states and 1065 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:46,743 INFO L93 Difference]: Finished difference Result 754 states and 971 transitions. [2024-11-13 15:10:46,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 754 states and 971 transitions. [2024-11-13 15:10:46,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-13 15:10:46,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 754 states to 754 states and 971 transitions. [2024-11-13 15:10:46,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 754 [2024-11-13 15:10:46,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 754 [2024-11-13 15:10:46,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 754 states and 971 transitions. [2024-11-13 15:10:46,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:46,756 INFO L218 hiAutomatonCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-13 15:10:46,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states and 971 transitions. [2024-11-13 15:10:46,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 754. [2024-11-13 15:10:46,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 754 states, 754 states have (on average 1.2877984084880636) internal successors, (971), 753 states have internal predecessors, (971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:46,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 971 transitions. [2024-11-13 15:10:46,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-13 15:10:46,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:10:46,777 INFO L424 stractBuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2024-11-13 15:10:46,777 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:10:46,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 754 states and 971 transitions. [2024-11-13 15:10:46,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2024-11-13 15:10:46,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:46,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:46,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:46,784 INFO L745 eck$LassoCheckResult]: Stem: 9045#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9072#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9019#L222 assume !(1 == ~q_req_up~0); 9021#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9056#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9057#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9079#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9161#L275 assume !(0 == ~q_read_ev~0); 9160#L275-2 assume !(0 == ~q_write_ev~0); 9135#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9102#L65 assume !(1 == ~p_dw_pc~0); 9069#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9070#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9158#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9157#L315 assume !(0 != activate_threads_~tmp~1#1); 9156#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9155#L84 assume !(1 == ~c_dr_pc~0); 9154#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9030#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9031#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8989#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8990#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9093#L293 assume !(1 == ~q_read_ev~0); 9094#L293-2 assume !(1 == ~q_write_ev~0); 9472#L298-1 assume { :end_inline_reset_delta_events } true; 9471#L419-2 assume !false; 9470#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 9074#L364 [2024-11-13 15:10:46,784 INFO L747 eck$LassoCheckResult]: Loop: 9074#L364 assume !false; 9467#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9464#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9461#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9459#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9457#L344 assume 0 != eval_~tmp___1~0#1; 9453#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9450#L353 assume !(0 != eval_~tmp~2#1); 9448#L349 assume !(0 == ~c_dr_st~0); 9074#L364 [2024-11-13 15:10:46,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,785 INFO L85 PathProgramCache]: Analyzing trace with hash 219097329, now seen corresponding path program 1 times [2024-11-13 15:10:46,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863147842] [2024-11-13 15:10:46,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,797 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:46,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:46,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,817 INFO L85 PathProgramCache]: Analyzing trace with hash 2111081048, now seen corresponding path program 1 times [2024-11-13 15:10:46,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393178796] [2024-11-13 15:10:46,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,825 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:46,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:46,831 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:46,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:46,832 INFO L85 PathProgramCache]: Analyzing trace with hash 808218472, now seen corresponding path program 1 times [2024-11-13 15:10:46,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:46,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452966142] [2024-11-13 15:10:46,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:46,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:46,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:10:46,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:10:46,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:10:46,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452966142] [2024-11-13 15:10:46,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452966142] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:10:46,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:10:46,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:10:46,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273834471] [2024-11-13 15:10:46,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:10:46,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:10:46,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:10:46,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:10:46,981 INFO L87 Difference]: Start difference. First operand 754 states and 971 transitions. cyclomatic complexity: 221 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:47,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:10:47,024 INFO L93 Difference]: Finished difference Result 844 states and 1081 transitions. [2024-11-13 15:10:47,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1081 transitions. [2024-11-13 15:10:47,033 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 735 [2024-11-13 15:10:47,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1081 transitions. [2024-11-13 15:10:47,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2024-11-13 15:10:47,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2024-11-13 15:10:47,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1081 transitions. [2024-11-13 15:10:47,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:10:47,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 844 states and 1081 transitions. [2024-11-13 15:10:47,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1081 transitions. [2024-11-13 15:10:47,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 824. [2024-11-13 15:10:47,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 824 states, 824 states have (on average 1.2851941747572815) internal successors, (1059), 823 states have internal predecessors, (1059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:10:47,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 824 states to 824 states and 1059 transitions. [2024-11-13 15:10:47,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 824 states and 1059 transitions. [2024-11-13 15:10:47,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:10:47,063 INFO L424 stractBuchiCegarLoop]: Abstraction has 824 states and 1059 transitions. [2024-11-13 15:10:47,063 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:10:47,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 824 states and 1059 transitions. [2024-11-13 15:10:47,069 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 715 [2024-11-13 15:10:47,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:10:47,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:10:47,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:47,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:10:47,070 INFO L745 eck$LassoCheckResult]: Stem: 10652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10624#L222 assume !(1 == ~q_req_up~0); 10612#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10613#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10660#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10686#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10684#L275 assume !(0 == ~q_read_ev~0); 10685#L275-2 assume !(0 == ~q_write_ev~0); 10698#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10752#L65 assume !(1 == ~p_dw_pc~0); 10750#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10748#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10746#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10744#L315 assume !(0 != activate_threads_~tmp~1#1); 10742#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10740#L84 assume !(1 == ~c_dr_pc~0); 10738#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10736#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10734#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10732#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10730#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10728#L293 assume !(1 == ~q_read_ev~0); 10588#L293-2 assume !(1 == ~q_write_ev~0); 10589#L298-1 assume { :end_inline_reset_delta_events } true; 10695#L419-2 assume !false; 11371#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 11369#L364 [2024-11-13 15:10:47,070 INFO L747 eck$LassoCheckResult]: Loop: 11369#L364 assume !false; 11367#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11365#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11364#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11362#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 11360#L344 assume 0 != eval_~tmp___1~0#1; 11358#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 11357#L353 assume !(0 != eval_~tmp~2#1); 11143#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 11144#L368 assume !(0 != eval_~tmp___0~2#1); 11369#L364 [2024-11-13 15:10:47,071 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:47,071 INFO L85 PathProgramCache]: Analyzing trace with hash 219097329, now seen corresponding path program 2 times [2024-11-13 15:10:47,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:47,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426744183] [2024-11-13 15:10:47,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:47,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:47,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,087 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:47,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,101 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:47,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:47,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1019001298, now seen corresponding path program 1 times [2024-11-13 15:10:47,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:47,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543597318] [2024-11-13 15:10:47,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:47,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:47,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,110 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:47,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:47,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:10:47,117 INFO L85 PathProgramCache]: Analyzing trace with hash -715032894, now seen corresponding path program 1 times [2024-11-13 15:10:47,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:10:47,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915210480] [2024-11-13 15:10:47,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:10:47,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:10:47,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:47,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:47,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:10:48,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:48,119 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:10:48,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:10:48,254 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 03:10:48 BoogieIcfgContainer [2024-11-13 15:10:48,258 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 15:10:48,259 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 15:10:48,259 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 15:10:48,259 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 15:10:48,260 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:10:43" (3/4) ... [2024-11-13 15:10:48,262 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 15:10:48,325 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 15:10:48,326 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 15:10:48,326 INFO L158 Benchmark]: Toolchain (without parser) took 5600.86ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 118.9MB in the beginning and 183.5MB in the end (delta: -64.6MB). Peak memory consumption was 216.5MB. Max. memory is 16.1GB. [2024-11-13 15:10:48,327 INFO L158 Benchmark]: CDTParser took 1.12ms. Allocated memory is still 142.6MB. Free memory is still 79.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:10:48,327 INFO L158 Benchmark]: CACSL2BoogieTranslator took 342.21ms. Allocated memory is still 142.6MB. Free memory was 118.9MB in the beginning and 106.1MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:10:48,328 INFO L158 Benchmark]: Boogie Procedure Inliner took 40.18ms. Allocated memory is still 142.6MB. Free memory was 105.9MB in the beginning and 104.2MB in the end (delta: 1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:10:48,328 INFO L158 Benchmark]: Boogie Preprocessor took 54.27ms. Allocated memory is still 142.6MB. Free memory was 104.2MB in the beginning and 102.2MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:10:48,328 INFO L158 Benchmark]: RCFGBuilder took 591.47ms. Allocated memory is still 142.6MB. Free memory was 102.2MB in the beginning and 82.8MB in the end (delta: 19.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 15:10:48,329 INFO L158 Benchmark]: BuchiAutomizer took 4500.54ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 82.6MB in the beginning and 188.3MB in the end (delta: -105.7MB). Peak memory consumption was 183.0MB. Max. memory is 16.1GB. [2024-11-13 15:10:48,329 INFO L158 Benchmark]: Witness Printer took 66.55ms. Allocated memory is still 427.8MB. Free memory was 188.3MB in the beginning and 183.5MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:10:48,331 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.12ms. Allocated memory is still 142.6MB. Free memory is still 79.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 342.21ms. Allocated memory is still 142.6MB. Free memory was 118.9MB in the beginning and 106.1MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 40.18ms. Allocated memory is still 142.6MB. Free memory was 105.9MB in the beginning and 104.2MB in the end (delta: 1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 54.27ms. Allocated memory is still 142.6MB. Free memory was 104.2MB in the beginning and 102.2MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 591.47ms. Allocated memory is still 142.6MB. Free memory was 102.2MB in the beginning and 82.8MB in the end (delta: 19.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 4500.54ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 82.6MB in the beginning and 188.3MB in the end (delta: -105.7MB). Peak memory consumption was 183.0MB. Max. memory is 16.1GB. * Witness Printer took 66.55ms. Allocated memory is still 427.8MB. Free memory was 188.3MB in the beginning and 183.5MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 824 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.3s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.9s. Construction of modules took 0.4s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 10 MinimizatonAttempts, 420 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1378 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1378 mSDsluCounter, 2969 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1536 mSDsCounter, 67 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 243 IncrementalHoareTripleChecker+Invalid, 310 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 67 mSolverCounterUnsat, 1433 mSDtfsCounter, 243 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 15:10:48,367 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b1a29d24-5773-4f55-abd7-9109a95b049d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)