./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:16:02,250 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:16:02,363 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:16:02,371 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:16:02,372 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:16:02,410 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:16:02,412 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:16:02,412 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:16:02,413 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:16:02,413 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:16:02,415 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:16:02,416 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:16:02,416 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:16:02,416 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:16:02,417 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:16:02,417 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:16:02,417 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:16:02,418 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:16:02,418 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:16:02,419 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:16:02,420 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:16:02,420 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:16:02,420 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:16:02,421 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:16:02,421 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:16:02,421 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:16:02,421 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:16:02,422 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:16:02,422 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 [2024-11-13 13:16:02,806 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:16:02,819 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:16:02,823 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:16:02,825 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:16:02,826 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:16:02,828 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/pipeline.cil-2.c Unable to find full path for "g++" [2024-11-13 13:16:04,898 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:16:05,235 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:16:05,236 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/sv-benchmarks/c/systemc/pipeline.cil-2.c [2024-11-13 13:16:05,255 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/data/e8d89b5c5/9cb9f5f64ef2419bb386f1d74e1a433b/FLAG29cd3c49d [2024-11-13 13:16:05,279 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/data/e8d89b5c5/9cb9f5f64ef2419bb386f1d74e1a433b [2024-11-13 13:16:05,283 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:16:05,285 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:16:05,287 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:16:05,288 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:16:05,293 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:16:05,294 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,295 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@40196565 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05, skipping insertion in model container [2024-11-13 13:16:05,296 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,337 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:16:05,618 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:16:05,636 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:16:05,717 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:16:05,736 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:16:05,737 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05 WrapperNode [2024-11-13 13:16:05,737 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:16:05,738 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:16:05,738 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:16:05,738 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:16:05,745 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,753 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,808 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1045 [2024-11-13 13:16:05,808 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:16:05,809 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:16:05,809 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:16:05,812 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:16:05,828 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,829 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,832 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,849 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:16:05,849 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,850 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,869 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,896 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,906 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,909 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,918 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:16:05,922 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:16:05,922 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:16:05,922 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:16:05,923 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (1/1) ... [2024-11-13 13:16:05,929 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:16:05,941 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:16:05,959 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:16:05,963 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f3b4494-7e07-4997-b9a6-d4993207706a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:16:05,990 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:16:05,991 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:16:05,991 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:16:05,991 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:16:06,106 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:16:06,108 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:16:07,877 INFO L? ?]: Removed 76 outVars from TransFormulas that were not future-live. [2024-11-13 13:16:07,878 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:16:07,908 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:16:07,908 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-13 13:16:07,909 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:16:07 BoogieIcfgContainer [2024-11-13 13:16:07,909 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:16:07,910 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:16:07,910 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:16:07,915 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:16:07,916 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:16:07,916 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:16:05" (1/3) ... [2024-11-13 13:16:07,917 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a779d75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:16:07, skipping insertion in model container [2024-11-13 13:16:07,917 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:16:07,917 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:16:05" (2/3) ... [2024-11-13 13:16:07,918 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a779d75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:16:07, skipping insertion in model container [2024-11-13 13:16:07,918 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:16:07,918 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:16:07" (3/3) ... [2024-11-13 13:16:07,919 INFO L333 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-2.c [2024-11-13 13:16:08,047 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:16:08,047 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:16:08,047 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:16:08,047 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:16:08,048 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:16:08,048 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:16:08,048 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:16:08,048 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:16:08,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:08,097 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2024-11-13 13:16:08,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:08,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:08,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,108 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,108 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:16:08,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:08,126 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2024-11-13 13:16:08,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:08,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:08,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,138 INFO L745 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 358#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32#L256true assume !(1 == ~main_in1_req_up~0); 9#L256-2true assume !(1 == ~main_in2_req_up~0); 26#L267-1true assume !(1 == ~main_sum_req_up~0); 304#L278-1true assume !(1 == ~main_diff_req_up~0); 2#L289-1true assume !(1 == ~main_pres_req_up~0); 255#L300-1true assume !(1 == ~main_dbl_req_up~0); 150#L311-1true assume !(1 == ~main_zero_req_up~0); 328#L322-1true assume !(1 == ~main_clk_req_up~0); 195#L333-1true assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 125#L351-1true assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 19#L356-1true assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 119#L361-1true assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 341#L366-1true assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 114#L371-1true assume !(0 == ~main_in1_ev~0); 44#L376-1true assume !(0 == ~main_in2_ev~0); 306#L381-1true assume !(0 == ~main_sum_ev~0); 134#L386-1true assume !(0 == ~main_diff_ev~0); 323#L391-1true assume !(0 == ~main_pres_ev~0); 232#L396-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 82#L401-1true assume !(0 == ~main_zero_ev~0); 87#L406-1true assume !(0 == ~main_clk_ev~0); 353#L411-1true assume !(0 == ~main_clk_pos_edge~0); 338#L416-1true assume !(0 == ~main_clk_neg_edge~0); 395#L421-1true assume !(1 == ~main_clk_pos_edge~0); 291#L426-1true assume !(1 == ~main_clk_pos_edge~0); 107#L431-1true assume !(1 == ~main_clk_pos_edge~0); 236#L436-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 95#L441-1true assume !(1 == ~main_clk_pos_edge~0); 386#L446-1true assume !(1 == ~main_in1_ev~0); 280#L451-1true assume !(1 == ~main_in2_ev~0); 396#L456-1true assume !(1 == ~main_sum_ev~0); 138#L461-1true assume !(1 == ~main_diff_ev~0); 380#L466-1true assume !(1 == ~main_pres_ev~0); 407#L471-1true assume !(1 == ~main_dbl_ev~0); 27#L476-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 196#L481-1true assume !(1 == ~main_clk_ev~0); 92#L486-1true assume !(1 == ~main_clk_pos_edge~0); 29#L491-1true assume !(1 == ~main_clk_neg_edge~0); 250#L742-1true [2024-11-13 13:16:08,139 INFO L747 eck$LassoCheckResult]: Loop: 250#L742-1true assume !false; 376#L503true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 209#L229true assume false; 63#eval_returnLabel#1true havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 256#L509true assume !(1 == ~main_in1_req_up~0); 175#L509-2true assume !(1 == ~main_in2_req_up~0); 339#L520-1true assume !(1 == ~main_sum_req_up~0); 223#L531-1true assume !(1 == ~main_diff_req_up~0); 144#L542-1true assume !(1 == ~main_pres_req_up~0); 394#L553-1true assume !(1 == ~main_dbl_req_up~0); 161#L564-1true assume !(1 == ~main_zero_req_up~0); 245#L575-1true assume !(1 == ~main_clk_req_up~0); 343#L586-1true start_simulation_~kernel_st~0#1 := 3; 370#L605true assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 287#L605-2true assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 17#L610-1true assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 194#L615-1true assume !(0 == ~main_diff_ev~0); 191#L620-1true assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 188#L625-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 271#L630-1true assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 329#L635-1true assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 327#L640-1true assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 85#L645-1true assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 113#L650-1true assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 132#L655-1true assume !(1 == ~main_clk_pos_edge~0); 207#L660-1true assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 241#L665-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 290#L670-1true assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 184#L675-1true assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 239#L680-1true assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 313#L685-1true assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 218#L690-1true assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 406#L695-1true assume !(1 == ~main_pres_ev~0); 277#L700-1true assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 269#L705-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 375#L710-1true assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 180#L715-1true assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 136#L720-1true assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 167#L725-1true assume 0 == ~N_generate_st~0; 250#L742-1true [2024-11-13 13:16:08,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:08,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2024-11-13 13:16:08,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:08,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680267941] [2024-11-13 13:16:08,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:08,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:08,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:08,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:08,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:08,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680267941] [2024-11-13 13:16:08,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680267941] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:08,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:08,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:08,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725146447] [2024-11-13 13:16:08,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:08,678 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:08,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:08,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1104518791, now seen corresponding path program 1 times [2024-11-13 13:16:08,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:08,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17167876] [2024-11-13 13:16:08,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:08,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:08,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:08,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:08,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:08,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17167876] [2024-11-13 13:16:08,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17167876] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:08,740 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:08,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:08,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737852270] [2024-11-13 13:16:08,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:08,742 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:08,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:08,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 13:16:08,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:16:08,786 INFO L87 Difference]: Start difference. First operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:08,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:08,845 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2024-11-13 13:16:08,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2024-11-13 13:16:08,854 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2024-11-13 13:16:08,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2024-11-13 13:16:08,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2024-11-13 13:16:08,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2024-11-13 13:16:08,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2024-11-13 13:16:08,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:08,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2024-11-13 13:16:08,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2024-11-13 13:16:08,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2024-11-13 13:16:08,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:08,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2024-11-13 13:16:08,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2024-11-13 13:16:08,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 13:16:08,934 INFO L424 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2024-11-13 13:16:08,934 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:16:08,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2024-11-13 13:16:08,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2024-11-13 13:16:08,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:08,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:08,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:08,941 INFO L745 eck$LassoCheckResult]: Stem: 1071#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 912#L256 assume !(1 == ~main_in1_req_up~0); 867#L256-2 assume !(1 == ~main_in2_req_up~0); 869#L267-1 assume !(1 == ~main_sum_req_up~0); 900#L278-1 assume !(1 == ~main_diff_req_up~0); 850#L289-1 assume !(1 == ~main_pres_req_up~0); 851#L300-1 assume !(1 == ~main_dbl_req_up~0); 960#L311-1 assume !(1 == ~main_zero_req_up~0); 1103#L322-1 assume !(1 == ~main_clk_req_up~0); 1078#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1069#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 889#L356-1 assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 890#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1063#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1058#L371-1 assume !(0 == ~main_in1_ev~0); 938#L376-1 assume !(0 == ~main_in2_ev~0); 939#L381-1 assume !(0 == ~main_sum_ev~0); 1080#L386-1 assume !(0 == ~main_diff_ev~0); 1081#L391-1 assume !(0 == ~main_pres_ev~0); 1190#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1008#L401-1 assume !(0 == ~main_zero_ev~0); 1009#L406-1 assume !(0 == ~main_clk_ev~0); 1016#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1249#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1250#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1236#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1047#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1048#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1025#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1026#L446-1 assume !(1 == ~main_in1_ev~0); 1228#L451-1 assume !(1 == ~main_in2_ev~0); 1229#L456-1 assume !(1 == ~main_sum_ev~0); 1087#L461-1 assume !(1 == ~main_diff_ev~0); 1088#L466-1 assume !(1 == ~main_pres_ev~0); 1263#L471-1 assume !(1 == ~main_dbl_ev~0); 902#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 903#L481-1 assume !(1 == ~main_clk_ev~0); 1023#L486-1 assume !(1 == ~main_clk_pos_edge~0); 907#L491-1 assume !(1 == ~main_clk_neg_edge~0); 908#L742-1 [2024-11-13 13:16:08,941 INFO L747 eck$LassoCheckResult]: Loop: 908#L742-1 assume !false; 1206#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 941#L229 assume !false; 1168#L147 assume !(0 == ~N_generate_st~0); 973#L151 assume !(0 == ~S1_addsub_st~0); 974#L154 assume !(0 == ~S2_presdbl_st~0); 860#L157 assume !(0 == ~S3_zero_st~0); 862#L160 assume !(0 == ~D_print_st~0); 976#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 977#L509 assume !(1 == ~main_in1_req_up~0); 864#L509-2 assume !(1 == ~main_in2_req_up~0); 1133#L520-1 assume !(1 == ~main_sum_req_up~0); 1181#L531-1 assume !(1 == ~main_diff_req_up~0); 1095#L542-1 assume !(1 == ~main_pres_req_up~0); 871#L553-1 assume !(1 == ~main_dbl_req_up~0); 1107#L564-1 assume !(1 == ~main_zero_req_up~0); 1117#L575-1 assume !(1 == ~main_clk_req_up~0); 1201#L586-1 start_simulation_~kernel_st~0#1 := 3; 1251#L605 assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 1235#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 886#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 887#L615-1 assume !(0 == ~main_diff_ev~0); 1158#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1153#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1154#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 1222#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1246#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 1014#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1015#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1057#L655-1 assume !(1 == ~main_clk_pos_edge~0); 1079#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1167#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1198#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 1146#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 1147#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 1196#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1176#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1177#L695-1 assume !(1 == ~main_pres_ev~0); 1223#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 1220#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 1221#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1140#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 1083#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 1084#L725-1 assume 0 == ~N_generate_st~0; 908#L742-1 [2024-11-13 13:16:08,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:08,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2024-11-13 13:16:08,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:08,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864938730] [2024-11-13 13:16:08,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:08,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:08,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:09,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:09,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:09,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864938730] [2024-11-13 13:16:09,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864938730] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:09,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:09,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:09,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754942457] [2024-11-13 13:16:09,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:09,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:09,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:09,152 INFO L85 PathProgramCache]: Analyzing trace with hash -1405707748, now seen corresponding path program 1 times [2024-11-13 13:16:09,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:09,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706910609] [2024-11-13 13:16:09,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:09,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:09,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:09,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:09,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:09,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706910609] [2024-11-13 13:16:09,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706910609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:09,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:09,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:09,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973270289] [2024-11-13 13:16:09,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:09,217 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:09,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:09,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:09,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:09,218 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:09,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:09,462 INFO L93 Difference]: Finished difference Result 760 states and 1352 transitions. [2024-11-13 13:16:09,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 760 states and 1352 transitions. [2024-11-13 13:16:09,474 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2024-11-13 13:16:09,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 760 states to 760 states and 1352 transitions. [2024-11-13 13:16:09,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2024-11-13 13:16:09,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2024-11-13 13:16:09,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 760 states and 1352 transitions. [2024-11-13 13:16:09,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:09,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2024-11-13 13:16:09,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states and 1352 transitions. [2024-11-13 13:16:09,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2024-11-13 13:16:09,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.7789473684210526) internal successors, (1352), 759 states have internal predecessors, (1352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:09,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1352 transitions. [2024-11-13 13:16:09,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2024-11-13 13:16:09,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:09,574 INFO L424 stractBuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2024-11-13 13:16:09,574 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:16:09,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 1352 transitions. [2024-11-13 13:16:09,585 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2024-11-13 13:16:09,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:09,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:09,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:09,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:09,589 INFO L745 eck$LassoCheckResult]: Stem: 2258#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2100#L256 assume !(1 == ~main_in1_req_up~0); 2054#L256-2 assume !(1 == ~main_in2_req_up~0); 2056#L267-1 assume !(1 == ~main_sum_req_up~0); 2088#L278-1 assume !(1 == ~main_diff_req_up~0); 2037#L289-1 assume !(1 == ~main_pres_req_up~0); 2038#L300-1 assume !(1 == ~main_dbl_req_up~0); 2146#L311-1 assume !(1 == ~main_zero_req_up~0); 2291#L322-1 assume !(1 == ~main_clk_req_up~0); 2266#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2256#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2076#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2077#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2250#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2245#L371-1 assume !(0 == ~main_in1_ev~0); 2124#L376-1 assume !(0 == ~main_in2_ev~0); 2125#L381-1 assume !(0 == ~main_sum_ev~0); 2268#L386-1 assume !(0 == ~main_diff_ev~0); 2269#L391-1 assume !(0 == ~main_pres_ev~0); 2380#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2195#L401-1 assume !(0 == ~main_zero_ev~0); 2196#L406-1 assume !(0 == ~main_clk_ev~0); 2203#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2463#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2464#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2435#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2233#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2234#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2211#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2212#L446-1 assume !(1 == ~main_in1_ev~0); 2424#L451-1 assume !(1 == ~main_in2_ev~0); 2425#L456-1 assume !(1 == ~main_sum_ev~0); 2275#L461-1 assume !(1 == ~main_diff_ev~0); 2276#L466-1 assume !(1 == ~main_pres_ev~0); 2484#L471-1 assume !(1 == ~main_dbl_ev~0); 2090#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2091#L481-1 assume !(1 == ~main_clk_ev~0); 2210#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2095#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2096#L742-1 [2024-11-13 13:16:09,589 INFO L747 eck$LassoCheckResult]: Loop: 2096#L742-1 assume !false; 2398#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2127#L229 assume !false; 2357#L147 assume !(0 == ~N_generate_st~0); 2160#L151 assume !(0 == ~S1_addsub_st~0); 2161#L154 assume !(0 == ~S2_presdbl_st~0); 2047#L157 assume !(0 == ~S3_zero_st~0); 2049#L160 assume !(0 == ~D_print_st~0); 2163#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2164#L509 assume !(1 == ~main_in1_req_up~0); 2401#L509-2 assume !(1 == ~main_in2_req_up~0); 2777#L520-1 assume !(1 == ~main_sum_req_up~0); 2775#L531-1 assume !(1 == ~main_diff_req_up~0); 2772#L542-1 assume !(1 == ~main_pres_req_up~0); 2769#L553-1 assume !(1 == ~main_dbl_req_up~0); 2766#L564-1 assume !(1 == ~main_zero_req_up~0); 2763#L575-1 assume !(1 == ~main_clk_req_up~0); 2761#L586-1 start_simulation_~kernel_st~0#1 := 3; 2760#L605 assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 2759#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2073#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2074#L615-1 assume !(0 == ~main_diff_ev~0); 2347#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2342#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2343#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 2418#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2456#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 2201#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2202#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2244#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2267#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2356#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2388#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 2335#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 2336#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 2386#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2365#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2366#L695-1 assume !(1 == ~main_pres_ev~0); 2419#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 2416#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2417#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2329#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 2271#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2272#L725-1 assume 0 == ~N_generate_st~0; 2096#L742-1 [2024-11-13 13:16:09,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:09,590 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2024-11-13 13:16:09,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:09,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162068753] [2024-11-13 13:16:09,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:09,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:09,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:09,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:09,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:09,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162068753] [2024-11-13 13:16:09,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162068753] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:09,740 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:09,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:09,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237634165] [2024-11-13 13:16:09,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:09,741 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:09,741 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:09,741 INFO L85 PathProgramCache]: Analyzing trace with hash -1405707748, now seen corresponding path program 2 times [2024-11-13 13:16:09,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:09,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223935014] [2024-11-13 13:16:09,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:09,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:09,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:09,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:09,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:09,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223935014] [2024-11-13 13:16:09,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223935014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:09,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:09,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:09,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199335920] [2024-11-13 13:16:09,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:09,810 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:09,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:09,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:09,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:09,812 INFO L87 Difference]: Start difference. First operand 760 states and 1352 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:10,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:10,124 INFO L93 Difference]: Finished difference Result 1669 states and 2937 transitions. [2024-11-13 13:16:10,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2937 transitions. [2024-11-13 13:16:10,142 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2024-11-13 13:16:10,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2937 transitions. [2024-11-13 13:16:10,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2024-11-13 13:16:10,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2024-11-13 13:16:10,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2937 transitions. [2024-11-13 13:16:10,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:10,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2024-11-13 13:16:10,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2937 transitions. [2024-11-13 13:16:10,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1669. [2024-11-13 13:16:10,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1669 states, 1669 states have (on average 1.7597363690832835) internal successors, (2937), 1668 states have internal predecessors, (2937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:10,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 1669 states and 2937 transitions. [2024-11-13 13:16:10,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2024-11-13 13:16:10,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:16:10,244 INFO L424 stractBuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2024-11-13 13:16:10,245 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:16:10,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1669 states and 2937 transitions. [2024-11-13 13:16:10,257 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2024-11-13 13:16:10,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:10,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:10,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:10,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:10,259 INFO L745 eck$LassoCheckResult]: Stem: 4708#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4539#L256 assume !(1 == ~main_in1_req_up~0); 4493#L256-2 assume !(1 == ~main_in2_req_up~0); 4495#L267-1 assume !(1 == ~main_sum_req_up~0); 4527#L278-1 assume !(1 == ~main_diff_req_up~0); 4476#L289-1 assume !(1 == ~main_pres_req_up~0); 4477#L300-1 assume !(1 == ~main_dbl_req_up~0); 4742#L311-1 assume !(1 == ~main_zero_req_up~0); 4741#L322-1 assume !(1 == ~main_clk_req_up~0); 4713#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4703#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4704#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4947#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4946#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4945#L371-1 assume !(0 == ~main_in1_ev~0); 4944#L376-1 assume !(0 == ~main_in2_ev~0); 4892#L381-1 assume !(0 == ~main_sum_ev~0); 4893#L386-1 assume !(0 == ~main_diff_ev~0); 4902#L391-1 assume !(0 == ~main_pres_ev~0); 4833#L396-1 assume !(0 == ~main_dbl_ev~0); 4834#L401-1 assume !(0 == ~main_zero_ev~0); 5263#L406-1 assume !(0 == ~main_clk_ev~0); 5262#L411-1 assume !(0 == ~main_clk_pos_edge~0); 4910#L416-1 assume !(0 == ~main_clk_neg_edge~0); 4911#L421-1 assume !(1 == ~main_clk_pos_edge~0); 4886#L426-1 assume !(1 == ~main_clk_pos_edge~0); 4680#L431-1 assume !(1 == ~main_clk_pos_edge~0); 4681#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4656#L441-1 assume !(1 == ~main_clk_pos_edge~0); 4657#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4929#L451-1 assume !(1 == ~main_in2_ev~0); 5247#L456-1 assume !(1 == ~main_sum_ev~0); 5245#L461-1 assume !(1 == ~main_diff_ev~0); 5243#L466-1 assume !(1 == ~main_pres_ev~0); 5241#L471-1 assume !(1 == ~main_dbl_ev~0); 4939#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 5239#L481-1 assume !(1 == ~main_clk_ev~0); 5237#L486-1 assume !(1 == ~main_clk_pos_edge~0); 5200#L491-1 assume !(1 == ~main_clk_neg_edge~0); 5199#L742-1 [2024-11-13 13:16:10,259 INFO L747 eck$LassoCheckResult]: Loop: 5199#L742-1 assume !false; 5198#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5194#L229 assume !false; 5191#L147 assume !(0 == ~N_generate_st~0); 5192#L151 assume !(0 == ~S1_addsub_st~0); 5188#L154 assume !(0 == ~S2_presdbl_st~0); 5189#L157 assume !(0 == ~S3_zero_st~0); 5190#L160 assume !(0 == ~D_print_st~0); 5193#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 5296#L509 assume !(1 == ~main_in1_req_up~0); 4772#L509-2 assume !(1 == ~main_in2_req_up~0); 4773#L520-1 assume !(1 == ~main_sum_req_up~0); 4825#L531-1 assume !(1 == ~main_diff_req_up~0); 4730#L542-1 assume !(1 == ~main_pres_req_up~0); 4497#L553-1 assume !(1 == ~main_dbl_req_up~0); 4745#L564-1 assume !(1 == ~main_zero_req_up~0); 4756#L575-1 assume !(1 == ~main_clk_req_up~0); 4847#L586-1 start_simulation_~kernel_st~0#1 := 3; 4912#L605 assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 4885#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 4512#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 4513#L615-1 assume !(0 == ~main_diff_ev~0); 4801#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 4796#L625-1 assume !(0 == ~main_dbl_ev~0); 4797#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 4870#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 5261#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 5260#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 5258#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 5256#L655-1 assume !(1 == ~main_clk_pos_edge~0); 5254#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 5252#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 5250#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 5248#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4789#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 5246#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 5244#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 5242#L695-1 assume !(1 == ~main_pres_ev~0); 5240#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 4872#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 5238#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 5236#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 5235#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 5203#L725-1 assume 0 == ~N_generate_st~0; 5199#L742-1 [2024-11-13 13:16:10,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:10,260 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2024-11-13 13:16:10,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:10,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163195709] [2024-11-13 13:16:10,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:10,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:10,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:10,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:10,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:10,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163195709] [2024-11-13 13:16:10,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163195709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:10,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:10,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:10,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922661827] [2024-11-13 13:16:10,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:10,328 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:10,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:10,329 INFO L85 PathProgramCache]: Analyzing trace with hash -983005922, now seen corresponding path program 1 times [2024-11-13 13:16:10,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:10,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049281136] [2024-11-13 13:16:10,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:10,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:10,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:10,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:10,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:10,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049281136] [2024-11-13 13:16:10,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049281136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:10,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:10,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:10,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339740356] [2024-11-13 13:16:10,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:10,362 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:10,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:10,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:10,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:10,363 INFO L87 Difference]: Start difference. First operand 1669 states and 2937 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:10,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:10,718 INFO L93 Difference]: Finished difference Result 1999 states and 3465 transitions. [2024-11-13 13:16:10,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1999 states and 3465 transitions. [2024-11-13 13:16:10,736 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2024-11-13 13:16:10,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1999 states to 1999 states and 3465 transitions. [2024-11-13 13:16:10,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1999 [2024-11-13 13:16:10,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1999 [2024-11-13 13:16:10,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1999 states and 3465 transitions. [2024-11-13 13:16:10,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:10,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2024-11-13 13:16:10,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states and 3465 transitions. [2024-11-13 13:16:10,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1999. [2024-11-13 13:16:10,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1999 states, 1999 states have (on average 1.7333666833416708) internal successors, (3465), 1998 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:10,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1999 states to 1999 states and 3465 transitions. [2024-11-13 13:16:10,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2024-11-13 13:16:10,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:10,828 INFO L424 stractBuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2024-11-13 13:16:10,828 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:16:10,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1999 states and 3465 transitions. [2024-11-13 13:16:10,844 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2024-11-13 13:16:10,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:10,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:10,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:10,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:10,849 INFO L745 eck$LassoCheckResult]: Stem: 8387#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 8388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 8217#L256 assume !(1 == ~main_in1_req_up~0); 8168#L256-2 assume !(1 == ~main_in2_req_up~0); 8170#L267-1 assume !(1 == ~main_sum_req_up~0); 8203#L278-1 assume !(1 == ~main_diff_req_up~0); 8151#L289-1 assume !(1 == ~main_pres_req_up~0); 8152#L300-1 assume !(1 == ~main_dbl_req_up~0); 8426#L311-1 assume !(1 == ~main_zero_req_up~0); 8423#L322-1 assume !(1 == ~main_clk_req_up~0); 8676#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 8675#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 8190#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 8191#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 8377#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 8673#L371-1 assume !(0 == ~main_in1_ev~0); 8672#L376-1 assume !(0 == ~main_in2_ev~0); 8599#L381-1 assume !(0 == ~main_sum_ev~0); 8600#L386-1 assume !(0 == ~main_diff_ev~0); 8612#L391-1 assume !(0 == ~main_pres_ev~0); 8533#L396-1 assume !(0 == ~main_dbl_ev~0); 8534#L401-1 assume !(0 == ~main_zero_ev~0); 9669#L406-1 assume !(0 == ~main_clk_ev~0); 9667#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 9666#L416-1 assume !(0 == ~main_clk_neg_edge~0); 9664#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 9662#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 9660#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 9659#L436-1 assume !(1 == ~main_clk_pos_edge~0); 9657#L441-1 assume !(1 == ~main_clk_pos_edge~0); 9654#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 8579#L451-1 assume !(1 == ~main_in2_ev~0); 8580#L456-1 assume !(1 == ~main_sum_ev~0); 8657#L461-1 assume !(1 == ~main_diff_ev~0); 9797#L466-1 assume !(1 == ~main_pres_ev~0); 9795#L471-1 assume !(1 == ~main_dbl_ev~0); 9644#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 8495#L481-1 assume !(1 == ~main_clk_ev~0); 8335#L486-1 assume !(1 == ~main_clk_pos_edge~0); 8210#L491-1 assume !(1 == ~main_clk_neg_edge~0); 8211#L742-1 [2024-11-13 13:16:10,849 INFO L747 eck$LassoCheckResult]: Loop: 8211#L742-1 assume !false; 8551#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 8245#L229 assume !false; 8504#L147 assume !(0 == ~N_generate_st~0); 8280#L151 assume !(0 == ~S1_addsub_st~0); 8281#L154 assume !(0 == ~S2_presdbl_st~0); 8161#L157 assume !(0 == ~S3_zero_st~0); 8163#L160 assume !(0 == ~D_print_st~0); 8283#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 8284#L509 assume !(1 == ~main_in1_req_up~0); 8459#L509-2 assume !(1 == ~main_in2_req_up~0); 8460#L520-1 assume !(1 == ~main_sum_req_up~0); 8521#L531-1 assume !(1 == ~main_diff_req_up~0); 8414#L542-1 assume !(1 == ~main_pres_req_up~0); 8172#L553-1 assume !(1 == ~main_dbl_req_up~0); 8656#L564-1 assume !(1 == ~main_zero_req_up~0); 9812#L575-1 assume !(1 == ~main_clk_req_up~0); 9810#L586-1 start_simulation_~kernel_st~0#1 := 3; 9809#L605 assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 9808#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 9807#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 9806#L615-1 assume !(0 == ~main_diff_ev~0); 9805#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 8484#L625-1 assume !(0 == ~main_dbl_ev~0); 8485#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 8571#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 8613#L640-1 assume !(0 == ~main_clk_pos_edge~0); 8323#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 8324#L650-1 assume !(1 == ~main_clk_pos_edge~0); 8371#L655-1 assume !(1 == ~main_clk_pos_edge~0); 8397#L660-1 assume !(1 == ~main_clk_pos_edge~0); 8503#L665-1 assume !(1 == ~main_clk_pos_edge~0); 8543#L670-1 assume !(1 == ~main_clk_pos_edge~0); 8590#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 9543#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 9803#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 9787#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 9786#L695-1 assume !(1 == ~main_pres_ev~0); 9785#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 9532#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 9784#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 8470#L715-1 assume !(1 == ~main_clk_pos_edge~0); 8402#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 8403#L725-1 assume 0 == ~N_generate_st~0; 8211#L742-1 [2024-11-13 13:16:10,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:10,849 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2024-11-13 13:16:10,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:10,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951528050] [2024-11-13 13:16:10,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:10,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:10,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:10,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:10,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:10,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951528050] [2024-11-13 13:16:10,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951528050] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:10,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:10,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:10,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10941142] [2024-11-13 13:16:10,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:10,997 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:10,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:10,998 INFO L85 PathProgramCache]: Analyzing trace with hash -1043007590, now seen corresponding path program 1 times [2024-11-13 13:16:10,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:10,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238441017] [2024-11-13 13:16:10,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:10,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:11,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:11,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:11,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:11,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238441017] [2024-11-13 13:16:11,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238441017] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:11,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:11,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:11,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852334321] [2024-11-13 13:16:11,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:11,052 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:11,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:11,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:11,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:11,052 INFO L87 Difference]: Start difference. First operand 1999 states and 3465 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:11,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:11,540 INFO L93 Difference]: Finished difference Result 4015 states and 6814 transitions. [2024-11-13 13:16:11,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4015 states and 6814 transitions. [2024-11-13 13:16:11,572 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2024-11-13 13:16:11,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4015 states to 4015 states and 6814 transitions. [2024-11-13 13:16:11,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4015 [2024-11-13 13:16:11,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4015 [2024-11-13 13:16:11,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4015 states and 6814 transitions. [2024-11-13 13:16:11,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:11,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4015 states and 6814 transitions. [2024-11-13 13:16:11,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4015 states and 6814 transitions. [2024-11-13 13:16:11,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4015 to 3985. [2024-11-13 13:16:11,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3985 states, 3985 states have (on average 1.6948557089084064) internal successors, (6754), 3984 states have internal predecessors, (6754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:11,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 6754 transitions. [2024-11-13 13:16:11,751 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2024-11-13 13:16:11,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:16:11,754 INFO L424 stractBuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2024-11-13 13:16:11,754 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:16:11,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3985 states and 6754 transitions. [2024-11-13 13:16:11,782 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2024-11-13 13:16:11,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:11,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:11,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:11,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:11,785 INFO L745 eck$LassoCheckResult]: Stem: 14408#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 14409#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 14240#L256 assume !(1 == ~main_in1_req_up~0); 14192#L256-2 assume !(1 == ~main_in2_req_up~0); 14194#L267-1 assume !(1 == ~main_sum_req_up~0); 14227#L278-1 assume !(1 == ~main_diff_req_up~0); 14175#L289-1 assume !(1 == ~main_pres_req_up~0); 14176#L300-1 assume !(1 == ~main_dbl_req_up~0); 14448#L311-1 assume !(1 == ~main_zero_req_up~0); 14445#L322-1 assume !(1 == ~main_clk_req_up~0); 14636#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 15331#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 15329#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 15327#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 15325#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 15323#L371-1 assume !(0 == ~main_in1_ev~0); 15321#L376-1 assume !(0 == ~main_in2_ev~0); 15318#L381-1 assume !(0 == ~main_sum_ev~0); 15316#L386-1 assume !(0 == ~main_diff_ev~0); 15315#L391-1 assume !(0 == ~main_pres_ev~0); 15314#L396-1 assume !(0 == ~main_dbl_ev~0); 15313#L401-1 assume !(0 == ~main_zero_ev~0); 15312#L406-1 assume !(0 == ~main_clk_ev~0); 15311#L411-1 assume !(0 == ~main_clk_pos_edge~0); 15310#L416-1 assume !(0 == ~main_clk_neg_edge~0); 15309#L421-1 assume !(1 == ~main_clk_pos_edge~0); 15308#L426-1 assume !(1 == ~main_clk_pos_edge~0); 15307#L431-1 assume !(1 == ~main_clk_pos_edge~0); 15303#L436-1 assume !(1 == ~main_clk_pos_edge~0); 15299#L441-1 assume !(1 == ~main_clk_pos_edge~0); 15297#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 15148#L451-1 assume !(1 == ~main_in2_ev~0); 15409#L456-1 assume !(1 == ~main_sum_ev~0); 15407#L461-1 assume !(1 == ~main_diff_ev~0); 15405#L466-1 assume !(1 == ~main_pres_ev~0); 15403#L471-1 assume !(1 == ~main_dbl_ev~0); 15401#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 15399#L481-1 assume !(1 == ~main_clk_ev~0); 15398#L486-1 assume !(1 == ~main_clk_pos_edge~0); 14234#L491-1 assume !(1 == ~main_clk_neg_edge~0); 14235#L742-1 [2024-11-13 13:16:11,786 INFO L747 eck$LassoCheckResult]: Loop: 14235#L742-1 assume !false; 14570#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 14269#L229 assume !false; 14523#L147 assume !(0 == ~N_generate_st~0); 14302#L151 assume !(0 == ~S1_addsub_st~0); 14303#L154 assume !(0 == ~S2_presdbl_st~0); 14185#L157 assume !(0 == ~S3_zero_st~0); 14187#L160 assume !(0 == ~D_print_st~0); 14305#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 14306#L509 assume !(1 == ~main_in1_req_up~0); 14479#L509-2 assume !(1 == ~main_in2_req_up~0); 14480#L520-1 assume !(1 == ~main_sum_req_up~0); 14538#L531-1 assume !(1 == ~main_diff_req_up~0); 14436#L542-1 assume !(1 == ~main_pres_req_up~0); 14196#L553-1 assume !(1 == ~main_dbl_req_up~0); 14450#L564-1 assume !(1 == ~main_zero_req_up~0); 14461#L575-1 assume !(1 == ~main_clk_req_up~0); 14564#L586-1 start_simulation_~kernel_st~0#1 := 3; 14644#L605 assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1; 14608#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 14211#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 14212#L615-1 assume !(0 == ~main_diff_ev~0); 14510#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 14505#L625-1 assume !(0 == ~main_dbl_ev~0); 14506#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 15543#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 14634#L640-1 assume !(0 == ~main_clk_pos_edge~0); 14635#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 14393#L650-1 assume !(1 == ~main_clk_pos_edge~0); 14394#L655-1 assume !(1 == ~main_clk_pos_edge~0); 14418#L660-1 assume !(1 == ~main_clk_pos_edge~0); 14522#L665-1 assume !(1 == ~main_clk_pos_edge~0); 14559#L670-1 assume !(1 == ~main_clk_pos_edge~0); 14497#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 14498#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 14557#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 14624#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 14689#L695-1 assume !(1 == ~main_pres_ev~0); 14594#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 14588#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 14589#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 14490#L715-1 assume !(1 == ~main_clk_pos_edge~0); 14422#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 14423#L725-1 assume 0 == ~N_generate_st~0; 14235#L742-1 [2024-11-13 13:16:11,789 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:11,789 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2024-11-13 13:16:11,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:11,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248237432] [2024-11-13 13:16:11,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:11,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:11,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:11,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:11,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:11,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248237432] [2024-11-13 13:16:11,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248237432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:11,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:11,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:11,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282996232] [2024-11-13 13:16:11,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:11,913 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:11,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:11,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1043007590, now seen corresponding path program 2 times [2024-11-13 13:16:11,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:11,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234321023] [2024-11-13 13:16:11,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:11,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:11,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:11,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:11,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:11,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234321023] [2024-11-13 13:16:11,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234321023] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:11,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:11,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:11,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025381205] [2024-11-13 13:16:11,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:11,981 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:11,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:11,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:11,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:11,982 INFO L87 Difference]: Start difference. First operand 3985 states and 6754 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:12,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:12,502 INFO L93 Difference]: Finished difference Result 4445 states and 7522 transitions. [2024-11-13 13:16:12,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 7522 transitions. [2024-11-13 13:16:12,539 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2024-11-13 13:16:12,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 7522 transitions. [2024-11-13 13:16:12,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2024-11-13 13:16:12,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2024-11-13 13:16:12,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 7522 transitions. [2024-11-13 13:16:12,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:12,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4445 states and 7522 transitions. [2024-11-13 13:16:12,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 7522 transitions. [2024-11-13 13:16:12,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4415. [2024-11-13 13:16:12,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4415 states, 4415 states have (on average 1.6901472253680634) internal successors, (7462), 4414 states have internal predecessors, (7462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:12,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4415 states to 4415 states and 7462 transitions. [2024-11-13 13:16:12,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2024-11-13 13:16:12,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:12,707 INFO L424 stractBuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2024-11-13 13:16:12,734 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:16:12,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4415 states and 7462 transitions. [2024-11-13 13:16:12,753 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2024-11-13 13:16:12,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:12,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:12,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:12,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:12,755 INFO L745 eck$LassoCheckResult]: Stem: 22849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 22850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 22681#L256 assume !(1 == ~main_in1_req_up~0); 22633#L256-2 assume !(1 == ~main_in2_req_up~0); 22635#L267-1 assume !(1 == ~main_sum_req_up~0); 22668#L278-1 assume !(1 == ~main_diff_req_up~0); 22616#L289-1 assume !(1 == ~main_pres_req_up~0); 22617#L300-1 assume !(1 == ~main_dbl_req_up~0); 22888#L311-1 assume !(1 == ~main_zero_req_up~0); 22885#L322-1 assume !(1 == ~main_clk_req_up~0); 23799#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 23890#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 23886#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 23884#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 23882#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 23880#L371-1 assume !(0 == ~main_in1_ev~0); 23878#L376-1 assume !(0 == ~main_in2_ev~0); 23876#L381-1 assume !(0 == ~main_sum_ev~0); 23874#L386-1 assume !(0 == ~main_diff_ev~0); 23872#L391-1 assume !(0 == ~main_pres_ev~0); 23870#L396-1 assume !(0 == ~main_dbl_ev~0); 23868#L401-1 assume !(0 == ~main_zero_ev~0); 23866#L406-1 assume !(0 == ~main_clk_ev~0); 23864#L411-1 assume !(0 == ~main_clk_pos_edge~0); 23862#L416-1 assume !(0 == ~main_clk_neg_edge~0); 23860#L421-1 assume !(1 == ~main_clk_pos_edge~0); 23858#L426-1 assume !(1 == ~main_clk_pos_edge~0); 23846#L431-1 assume !(1 == ~main_clk_pos_edge~0); 23840#L436-1 assume !(1 == ~main_clk_pos_edge~0); 23835#L441-1 assume !(1 == ~main_clk_pos_edge~0); 23833#L446-1 assume !(1 == ~main_in1_ev~0); 23826#L451-1 assume !(1 == ~main_in2_ev~0); 23823#L456-1 assume !(1 == ~main_sum_ev~0); 23819#L461-1 assume !(1 == ~main_diff_ev~0); 23816#L466-1 assume !(1 == ~main_pres_ev~0); 23812#L471-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 22670#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 22671#L481-1 assume !(1 == ~main_clk_ev~0); 22798#L486-1 assume !(1 == ~main_clk_pos_edge~0); 22675#L491-1 assume !(1 == ~main_clk_neg_edge~0); 22676#L742-1 [2024-11-13 13:16:12,756 INFO L747 eck$LassoCheckResult]: Loop: 22676#L742-1 assume !false; 23020#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 22709#L229 assume !false; 23831#L147 assume !(0 == ~N_generate_st~0); 23832#L151 assume !(0 == ~S1_addsub_st~0); 23828#L154 assume !(0 == ~S2_presdbl_st~0); 23829#L157 assume !(0 == ~S3_zero_st~0); 23830#L160 assume !(0 == ~D_print_st~0); 22747#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 22748#L509 assume !(1 == ~main_in1_req_up~0); 22924#L509-2 assume !(1 == ~main_in2_req_up~0); 22925#L520-1 assume !(1 == ~main_sum_req_up~0); 23089#L531-1 assume !(1 == ~main_diff_req_up~0); 24123#L542-1 assume !(1 == ~main_pres_req_up~0); 23126#L553-1 assume !(1 == ~main_dbl_req_up~0); 23127#L564-1 assume !(1 == ~main_zero_req_up~0); 24141#L575-1 assume !(1 == ~main_clk_req_up~0); 24142#L586-1 start_simulation_~kernel_st~0#1 := 3; 23107#L605 assume !(0 == ~main_in1_ev~0); 23108#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 24145#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 24131#L615-1 assume !(0 == ~main_diff_ev~0); 24132#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 22948#L625-1 assume !(0 == ~main_dbl_ev~0); 22949#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 23038#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 23079#L640-1 assume !(0 == ~main_clk_pos_edge~0); 22785#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 22786#L650-1 assume !(1 == ~main_clk_pos_edge~0); 22834#L655-1 assume !(1 == ~main_clk_pos_edge~0); 22859#L660-1 assume !(1 == ~main_clk_pos_edge~0); 22968#L665-1 assume !(1 == ~main_clk_pos_edge~0); 23010#L670-1 assume !(1 == ~main_clk_pos_edge~0); 22941#L675-1 assume !(1 == ~main_in1_ev~0); 22942#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 23008#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 22982#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 22983#L695-1 assume !(1 == ~main_pres_ev~0); 23039#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 23036#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 23037#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 22934#L715-1 assume !(1 == ~main_clk_pos_edge~0); 22863#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 22864#L725-1 assume 0 == ~N_generate_st~0; 22676#L742-1 [2024-11-13 13:16:12,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:12,756 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2024-11-13 13:16:12,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:12,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970760054] [2024-11-13 13:16:12,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:12,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:12,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:12,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:12,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:12,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970760054] [2024-11-13 13:16:12,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970760054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:12,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:12,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:12,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437970981] [2024-11-13 13:16:12,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:12,834 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:12,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:12,835 INFO L85 PathProgramCache]: Analyzing trace with hash -279903398, now seen corresponding path program 1 times [2024-11-13 13:16:12,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:12,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283646625] [2024-11-13 13:16:12,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:12,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:12,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:12,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:12,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:12,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283646625] [2024-11-13 13:16:12,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [283646625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:12,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:12,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:12,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452372532] [2024-11-13 13:16:12,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:12,907 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:12,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:12,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:12,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:12,908 INFO L87 Difference]: Start difference. First operand 4415 states and 7462 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:13,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:13,315 INFO L93 Difference]: Finished difference Result 5574 states and 9318 transitions. [2024-11-13 13:16:13,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5574 states and 9318 transitions. [2024-11-13 13:16:13,350 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5240 [2024-11-13 13:16:13,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5574 states to 5574 states and 9318 transitions. [2024-11-13 13:16:13,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5574 [2024-11-13 13:16:13,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5574 [2024-11-13 13:16:13,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5574 states and 9318 transitions. [2024-11-13 13:16:13,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:13,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5574 states and 9318 transitions. [2024-11-13 13:16:13,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5574 states and 9318 transitions. [2024-11-13 13:16:13,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5574 to 5130. [2024-11-13 13:16:13,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5130 states, 5130 states have (on average 1.6754385964912282) internal successors, (8595), 5129 states have internal predecessors, (8595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:13,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 8595 transitions. [2024-11-13 13:16:13,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2024-11-13 13:16:13,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:13,569 INFO L424 stractBuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2024-11-13 13:16:13,569 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:16:13,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5130 states and 8595 transitions. [2024-11-13 13:16:13,595 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4812 [2024-11-13 13:16:13,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:13,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:13,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:13,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:13,597 INFO L745 eck$LassoCheckResult]: Stem: 32852#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 32853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32680#L256 assume !(1 == ~main_in1_req_up~0); 32633#L256-2 assume !(1 == ~main_in2_req_up~0); 32635#L267-1 assume !(1 == ~main_sum_req_up~0); 32667#L278-1 assume !(1 == ~main_diff_req_up~0); 32616#L289-1 assume !(1 == ~main_pres_req_up~0); 32617#L300-1 assume !(1 == ~main_dbl_req_up~0); 32727#L311-1 assume !(1 == ~main_zero_req_up~0); 33078#L322-1 assume !(1 == ~main_clk_req_up~0); 33080#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 35878#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 35876#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 35874#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 35871#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 35868#L371-1 assume !(0 == ~main_in1_ev~0); 35866#L376-1 assume !(0 == ~main_in2_ev~0); 35864#L381-1 assume !(0 == ~main_sum_ev~0); 35860#L386-1 assume !(0 == ~main_diff_ev~0); 35856#L391-1 assume !(0 == ~main_pres_ev~0); 35855#L396-1 assume !(0 == ~main_dbl_ev~0); 35854#L401-1 assume !(0 == ~main_zero_ev~0); 35853#L406-1 assume !(0 == ~main_clk_ev~0); 35852#L411-1 assume !(0 == ~main_clk_pos_edge~0); 35851#L416-1 assume !(0 == ~main_clk_neg_edge~0); 35850#L421-1 assume !(1 == ~main_clk_pos_edge~0); 35849#L426-1 assume !(1 == ~main_clk_pos_edge~0); 35848#L431-1 assume !(1 == ~main_clk_pos_edge~0); 35847#L436-1 assume !(1 == ~main_clk_pos_edge~0); 35846#L441-1 assume !(1 == ~main_clk_pos_edge~0); 35845#L446-1 assume !(1 == ~main_in1_ev~0); 35844#L451-1 assume !(1 == ~main_in2_ev~0); 35843#L456-1 assume !(1 == ~main_sum_ev~0); 35842#L461-1 assume !(1 == ~main_diff_ev~0); 35841#L466-1 assume !(1 == ~main_pres_ev~0); 35840#L471-1 assume !(1 == ~main_dbl_ev~0); 35839#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35838#L481-1 assume !(1 == ~main_clk_ev~0); 35837#L486-1 assume !(1 == ~main_clk_pos_edge~0); 32674#L491-1 assume !(1 == ~main_clk_neg_edge~0); 32675#L742-1 [2024-11-13 13:16:13,597 INFO L747 eck$LassoCheckResult]: Loop: 32675#L742-1 assume !false; 33018#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 32708#L229 assume !false; 32970#L147 assume !(0 == ~N_generate_st~0); 34614#L151 assume !(0 == ~S1_addsub_st~0); 34611#L154 assume !(0 == ~S2_presdbl_st~0); 34608#L157 assume !(0 == ~S3_zero_st~0); 34603#L160 assume !(0 == ~D_print_st~0); 34600#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 34596#L509 assume !(1 == ~main_in1_req_up~0); 34591#L509-2 assume !(1 == ~main_in2_req_up~0); 34585#L520-1 assume !(1 == ~main_sum_req_up~0); 34577#L531-1 assume !(1 == ~main_diff_req_up~0); 34568#L542-1 assume !(1 == ~main_pres_req_up~0); 34544#L553-1 assume !(1 == ~main_dbl_req_up~0); 34545#L564-1 assume !(1 == ~main_zero_req_up~0); 35833#L575-1 assume !(1 == ~main_clk_req_up~0); 35831#L586-1 start_simulation_~kernel_st~0#1 := 3; 35830#L605 assume !(0 == ~main_in1_ev~0); 35829#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 35828#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 35827#L615-1 assume !(0 == ~main_diff_ev~0); 35826#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 35825#L625-1 assume !(0 == ~main_dbl_ev~0); 35824#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 35823#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 35822#L640-1 assume !(0 == ~main_clk_pos_edge~0); 35821#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 35820#L650-1 assume !(1 == ~main_clk_pos_edge~0); 35819#L655-1 assume !(1 == ~main_clk_pos_edge~0); 35818#L660-1 assume !(1 == ~main_clk_pos_edge~0); 35817#L665-1 assume !(1 == ~main_clk_pos_edge~0); 35816#L670-1 assume !(1 == ~main_clk_pos_edge~0); 35815#L675-1 assume !(1 == ~main_in1_ev~0); 35814#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 35813#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 35812#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 35811#L695-1 assume !(1 == ~main_pres_ev~0); 35810#L700-1 assume !(1 == ~main_dbl_ev~0); 35809#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35808#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 35807#L715-1 assume !(1 == ~main_clk_pos_edge~0); 35806#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 34458#L725-1 assume 0 == ~N_generate_st~0; 32675#L742-1 [2024-11-13 13:16:13,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:13,598 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2024-11-13 13:16:13,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:13,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978257595] [2024-11-13 13:16:13,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:13,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:13,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:13,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:13,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:13,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978257595] [2024-11-13 13:16:13,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978257595] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:13,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:13,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:13,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499390988] [2024-11-13 13:16:13,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:13,727 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:13,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:13,727 INFO L85 PathProgramCache]: Analyzing trace with hash -222645096, now seen corresponding path program 1 times [2024-11-13 13:16:13,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:13,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373822829] [2024-11-13 13:16:13,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:13,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:13,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:13,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:13,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:13,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373822829] [2024-11-13 13:16:13,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373822829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:13,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:13,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:13,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954702649] [2024-11-13 13:16:13,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:13,783 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:13,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:13,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:13,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:13,784 INFO L87 Difference]: Start difference. First operand 5130 states and 8595 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:14,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:14,304 INFO L93 Difference]: Finished difference Result 9446 states and 15503 transitions. [2024-11-13 13:16:14,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9446 states and 15503 transitions. [2024-11-13 13:16:14,378 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8840 [2024-11-13 13:16:14,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9446 states to 9446 states and 15503 transitions. [2024-11-13 13:16:14,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9446 [2024-11-13 13:16:14,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9446 [2024-11-13 13:16:14,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9446 states and 15503 transitions. [2024-11-13 13:16:14,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:14,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9446 states and 15503 transitions. [2024-11-13 13:16:14,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9446 states and 15503 transitions. [2024-11-13 13:16:14,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9446 to 6978. [2024-11-13 13:16:14,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6978 states, 6978 states have (on average 1.65262252794497) internal successors, (11532), 6977 states have internal predecessors, (11532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:14,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6978 states to 6978 states and 11532 transitions. [2024-11-13 13:16:14,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2024-11-13 13:16:14,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:14,649 INFO L424 stractBuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2024-11-13 13:16:14,649 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:16:14,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6978 states and 11532 transitions. [2024-11-13 13:16:14,690 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6492 [2024-11-13 13:16:14,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:14,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:14,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:14,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:14,695 INFO L745 eck$LassoCheckResult]: Stem: 47436#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 47437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 47266#L256 assume !(1 == ~main_in1_req_up~0); 47220#L256-2 assume !(1 == ~main_in2_req_up~0); 47222#L267-1 assume !(1 == ~main_sum_req_up~0); 47253#L278-1 assume !(1 == ~main_diff_req_up~0); 47203#L289-1 assume !(1 == ~main_pres_req_up~0); 47204#L300-1 assume !(1 == ~main_dbl_req_up~0); 47314#L311-1 assume !(1 == ~main_zero_req_up~0); 47658#L322-1 assume !(1 == ~main_clk_req_up~0); 47445#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 47434#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 47242#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 47243#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 47428#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 47421#L371-1 assume !(0 == ~main_in1_ev~0); 47422#L376-1 assume !(0 == ~main_in2_ev~0); 47640#L381-1 assume !(0 == ~main_sum_ev~0); 47641#L386-1 assume !(0 == ~main_diff_ev~0); 47655#L391-1 assume !(0 == ~main_pres_ev~0); 47578#L396-1 assume !(0 == ~main_dbl_ev~0); 47365#L401-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 47366#L406-1 assume !(0 == ~main_clk_ev~0); 48009#L411-1 assume !(0 == ~main_clk_pos_edge~0); 48010#L416-1 assume !(0 == ~main_clk_neg_edge~0); 48005#L421-1 assume !(1 == ~main_clk_pos_edge~0); 48006#L426-1 assume !(1 == ~main_clk_pos_edge~0); 48001#L431-1 assume !(1 == ~main_clk_pos_edge~0); 48002#L436-1 assume !(1 == ~main_clk_pos_edge~0); 47997#L441-1 assume !(1 == ~main_clk_pos_edge~0); 47998#L446-1 assume !(1 == ~main_in1_ev~0); 47990#L451-1 assume !(1 == ~main_in2_ev~0); 47991#L456-1 assume !(1 == ~main_sum_ev~0); 47966#L461-1 assume !(1 == ~main_diff_ev~0); 47967#L466-1 assume !(1 == ~main_pres_ev~0); 48416#L471-1 assume !(1 == ~main_dbl_ev~0); 48414#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 47541#L481-1 assume !(1 == ~main_clk_ev~0); 47383#L486-1 assume !(1 == ~main_clk_pos_edge~0); 47384#L491-1 assume !(1 == ~main_clk_neg_edge~0); 48375#L742-1 [2024-11-13 13:16:14,696 INFO L747 eck$LassoCheckResult]: Loop: 48375#L742-1 assume !false; 48369#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 48363#L229 assume !false; 48357#L147 assume !(0 == ~N_generate_st~0); 48358#L151 assume !(0 == ~S1_addsub_st~0); 48354#L154 assume !(0 == ~S2_presdbl_st~0); 48355#L157 assume !(0 == ~S3_zero_st~0); 48356#L160 assume !(0 == ~D_print_st~0); 48359#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 48553#L509 assume !(1 == ~main_in1_req_up~0); 48548#L509-2 assume !(1 == ~main_in2_req_up~0); 48541#L520-1 assume !(1 == ~main_sum_req_up~0); 48533#L531-1 assume !(1 == ~main_diff_req_up~0); 48527#L542-1 assume !(1 == ~main_pres_req_up~0); 48521#L553-1 assume !(1 == ~main_dbl_req_up~0); 48515#L564-1 assume !(1 == ~main_zero_req_up~0); 48485#L575-1 assume !(1 == ~main_clk_req_up~0); 48486#L586-1 start_simulation_~kernel_st~0#1 := 3; 48552#L605 assume !(0 == ~main_in1_ev~0); 48546#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 48540#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 48531#L615-1 assume !(0 == ~main_diff_ev~0); 48525#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 48519#L625-1 assume !(0 == ~main_dbl_ev~0); 48512#L630-1 assume !(0 == ~main_zero_ev~0); 48513#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 48565#L640-1 assume !(0 == ~main_clk_pos_edge~0); 48564#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 48563#L650-1 assume !(1 == ~main_clk_pos_edge~0); 48561#L655-1 assume !(1 == ~main_clk_pos_edge~0); 48559#L660-1 assume !(1 == ~main_clk_pos_edge~0); 48557#L665-1 assume !(1 == ~main_clk_pos_edge~0); 48555#L670-1 assume !(1 == ~main_clk_pos_edge~0); 48551#L675-1 assume !(1 == ~main_in1_ev~0); 48545#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 48539#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 48530#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 48524#L695-1 assume !(1 == ~main_pres_ev~0); 48518#L700-1 assume !(1 == ~main_dbl_ev~0); 48489#L705-1 assume !(1 == ~main_zero_ev~0); 48484#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 48425#L715-1 assume !(1 == ~main_clk_pos_edge~0); 48413#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 48383#L725-1 assume 0 == ~N_generate_st~0; 48375#L742-1 [2024-11-13 13:16:14,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:14,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2024-11-13 13:16:14,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:14,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944099766] [2024-11-13 13:16:14,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:14,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:14,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:14,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:14,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:14,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944099766] [2024-11-13 13:16:14,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944099766] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:14,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:14,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:14,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161108825] [2024-11-13 13:16:14,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:14,790 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:14,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:14,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1038446504, now seen corresponding path program 1 times [2024-11-13 13:16:14,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:14,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145675077] [2024-11-13 13:16:14,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:14,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:14,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:14,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:14,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:14,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145675077] [2024-11-13 13:16:14,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145675077] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:14,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:14,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:14,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584242587] [2024-11-13 13:16:14,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:14,828 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:14,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:14,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:14,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:14,829 INFO L87 Difference]: Start difference. First operand 6978 states and 11532 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:15,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:15,096 INFO L93 Difference]: Finished difference Result 12839 states and 21043 transitions. [2024-11-13 13:16:15,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12839 states and 21043 transitions. [2024-11-13 13:16:15,204 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2024-11-13 13:16:15,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12839 states to 12839 states and 21043 transitions. [2024-11-13 13:16:15,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12839 [2024-11-13 13:16:15,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12839 [2024-11-13 13:16:15,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12839 states and 21043 transitions. [2024-11-13 13:16:15,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:15,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2024-11-13 13:16:15,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12839 states and 21043 transitions. [2024-11-13 13:16:15,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12839 to 12839. [2024-11-13 13:16:15,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12839 states, 12839 states have (on average 1.6389905755899992) internal successors, (21043), 12838 states have internal predecessors, (21043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:15,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12839 states to 12839 states and 21043 transitions. [2024-11-13 13:16:15,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2024-11-13 13:16:15,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:16:15,591 INFO L424 stractBuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2024-11-13 13:16:15,591 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:16:15,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12839 states and 21043 transitions. [2024-11-13 13:16:15,643 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2024-11-13 13:16:15,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:15,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:15,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:15,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:15,645 INFO L745 eck$LassoCheckResult]: Stem: 67268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 67269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 67095#L256 assume !(1 == ~main_in1_req_up~0); 67048#L256-2 assume !(1 == ~main_in2_req_up~0); 67050#L267-1 assume !(1 == ~main_sum_req_up~0); 67081#L278-1 assume !(1 == ~main_diff_req_up~0); 67030#L289-1 assume !(1 == ~main_pres_req_up~0); 67031#L300-1 assume !(1 == ~main_dbl_req_up~0); 67303#L311-1 assume !(1 == ~main_zero_req_up~0); 67305#L322-1 assume !(1 == ~main_clk_req_up~0); 69485#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 69484#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 69483#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 69482#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 69479#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 69475#L371-1 assume !(0 == ~main_in1_ev~0); 69473#L376-1 assume !(0 == ~main_in2_ev~0); 69471#L381-1 assume !(0 == ~main_sum_ev~0); 69469#L386-1 assume !(0 == ~main_diff_ev~0); 69467#L391-1 assume !(0 == ~main_pres_ev~0); 69465#L396-1 assume !(0 == ~main_dbl_ev~0); 69463#L401-1 assume !(0 == ~main_zero_ev~0); 69461#L406-1 assume !(0 == ~main_clk_ev~0); 69459#L411-1 assume !(0 == ~main_clk_pos_edge~0); 69457#L416-1 assume !(0 == ~main_clk_neg_edge~0); 69455#L421-1 assume !(1 == ~main_clk_pos_edge~0); 69453#L426-1 assume !(1 == ~main_clk_pos_edge~0); 69451#L431-1 assume !(1 == ~main_clk_pos_edge~0); 69449#L436-1 assume !(1 == ~main_clk_pos_edge~0); 69447#L441-1 assume !(1 == ~main_clk_pos_edge~0); 69445#L446-1 assume !(1 == ~main_in1_ev~0); 69443#L451-1 assume !(1 == ~main_in2_ev~0); 69441#L456-1 assume !(1 == ~main_sum_ev~0); 69439#L461-1 assume !(1 == ~main_diff_ev~0); 69437#L466-1 assume !(1 == ~main_pres_ev~0); 69435#L471-1 assume !(1 == ~main_dbl_ev~0); 69433#L476-1 assume !(1 == ~main_zero_ev~0); 69431#L481-1 assume !(1 == ~main_clk_ev~0); 69429#L486-1 assume !(1 == ~main_clk_pos_edge~0); 69402#L491-1 assume !(1 == ~main_clk_neg_edge~0); 69400#L742-1 [2024-11-13 13:16:15,645 INFO L747 eck$LassoCheckResult]: Loop: 69400#L742-1 assume !false; 69398#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 69393#L229 assume !false; 69391#L147 assume !(0 == ~N_generate_st~0); 69388#L151 assume !(0 == ~S1_addsub_st~0); 69386#L154 assume !(0 == ~S2_presdbl_st~0); 69384#L157 assume !(0 == ~S3_zero_st~0); 69382#L160 assume !(0 == ~D_print_st~0); 69376#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 69375#L509 assume !(1 == ~main_in1_req_up~0); 69368#L509-2 assume !(1 == ~main_in2_req_up~0); 69358#L520-1 assume !(1 == ~main_sum_req_up~0); 67398#L531-1 assume !(1 == ~main_diff_req_up~0); 67292#L542-1 assume !(1 == ~main_pres_req_up~0); 67052#L553-1 assume !(1 == ~main_dbl_req_up~0); 67542#L564-1 assume !(1 == ~main_zero_req_up~0); 69477#L575-1 assume !(1 == ~main_clk_req_up~0); 69474#L586-1 start_simulation_~kernel_st~0#1 := 3; 69472#L605 assume !(0 == ~main_in1_ev~0); 69470#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 69468#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 69466#L615-1 assume !(0 == ~main_diff_ev~0); 69464#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 69462#L625-1 assume !(0 == ~main_dbl_ev~0); 69460#L630-1 assume !(0 == ~main_zero_ev~0); 69458#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 69456#L640-1 assume !(0 == ~main_clk_pos_edge~0); 69454#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 69452#L650-1 assume !(1 == ~main_clk_pos_edge~0); 69450#L655-1 assume !(1 == ~main_clk_pos_edge~0); 69448#L660-1 assume !(1 == ~main_clk_pos_edge~0); 69446#L665-1 assume !(1 == ~main_clk_pos_edge~0); 69444#L670-1 assume !(1 == ~main_clk_pos_edge~0); 69442#L675-1 assume !(1 == ~main_in1_ev~0); 69440#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 69438#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 69436#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 69434#L695-1 assume !(1 == ~main_pres_ev~0); 69432#L700-1 assume !(1 == ~main_dbl_ev~0); 69430#L705-1 assume !(1 == ~main_zero_ev~0); 69428#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 69427#L715-1 assume !(1 == ~main_clk_pos_edge~0); 69426#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 69405#L725-1 assume 0 == ~N_generate_st~0; 69400#L742-1 [2024-11-13 13:16:15,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:15,646 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2024-11-13 13:16:15,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:15,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984092085] [2024-11-13 13:16:15,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:15,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:15,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:15,659 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:15,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:15,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:15,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:15,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1038446504, now seen corresponding path program 2 times [2024-11-13 13:16:15,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:15,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302166338] [2024-11-13 13:16:15,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:15,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:15,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:15,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:15,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:15,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302166338] [2024-11-13 13:16:15,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302166338] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:15,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:15,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:15,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557717039] [2024-11-13 13:16:15,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:15,742 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:15,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:15,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:15,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:15,742 INFO L87 Difference]: Start difference. First operand 12839 states and 21043 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:15,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:15,934 INFO L93 Difference]: Finished difference Result 18228 states and 29320 transitions. [2024-11-13 13:16:15,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18228 states and 29320 transitions. [2024-11-13 13:16:16,017 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17038 [2024-11-13 13:16:16,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18228 states to 18228 states and 29320 transitions. [2024-11-13 13:16:16,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18228 [2024-11-13 13:16:16,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18228 [2024-11-13 13:16:16,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18228 states and 29320 transitions. [2024-11-13 13:16:16,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:16,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18228 states and 29320 transitions. [2024-11-13 13:16:16,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18228 states and 29320 transitions. [2024-11-13 13:16:16,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18228 to 18228. [2024-11-13 13:16:16,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18228 states, 18228 states have (on average 1.608514373491332) internal successors, (29320), 18227 states have internal predecessors, (29320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:16,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18228 states to 18228 states and 29320 transitions. [2024-11-13 13:16:16,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18228 states and 29320 transitions. [2024-11-13 13:16:16,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:16,734 INFO L424 stractBuchiCegarLoop]: Abstraction has 18228 states and 29320 transitions. [2024-11-13 13:16:16,734 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:16:16,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18228 states and 29320 transitions. [2024-11-13 13:16:16,814 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17038 [2024-11-13 13:16:16,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:16,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:16,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:16,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:16,817 INFO L745 eck$LassoCheckResult]: Stem: 98338#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 98339#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 98168#L256 assume !(1 == ~main_in1_req_up~0); 98121#L256-2 assume !(1 == ~main_in2_req_up~0); 98123#L267-1 assume !(1 == ~main_sum_req_up~0); 98155#L278-1 assume !(1 == ~main_diff_req_up~0); 98103#L289-1 assume !(1 == ~main_pres_req_up~0); 98104#L300-1 assume !(1 == ~main_dbl_req_up~0); 98377#L311-1 assume !(1 == ~main_zero_req_up~0); 98378#L322-1 assume !(1 == ~main_clk_req_up~0); 100762#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 101487#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 101485#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 101483#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 101481#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 101479#L371-1 assume !(0 == ~main_in1_ev~0); 101477#L376-1 assume !(0 == ~main_in2_ev~0); 101476#L381-1 assume !(0 == ~main_sum_ev~0); 101475#L386-1 assume !(0 == ~main_diff_ev~0); 101474#L391-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 101473#L396-1 assume !(0 == ~main_dbl_ev~0); 101471#L401-1 assume !(0 == ~main_zero_ev~0); 101469#L406-1 assume !(0 == ~main_clk_ev~0); 101467#L411-1 assume !(0 == ~main_clk_pos_edge~0); 101465#L416-1 assume !(0 == ~main_clk_neg_edge~0); 101463#L421-1 assume !(1 == ~main_clk_pos_edge~0); 101461#L426-1 assume !(1 == ~main_clk_pos_edge~0); 101459#L431-1 assume !(1 == ~main_clk_pos_edge~0); 101457#L436-1 assume !(1 == ~main_clk_pos_edge~0); 101455#L441-1 assume !(1 == ~main_clk_pos_edge~0); 101453#L446-1 assume !(1 == ~main_in1_ev~0); 101451#L451-1 assume !(1 == ~main_in2_ev~0); 101449#L456-1 assume !(1 == ~main_sum_ev~0); 101447#L461-1 assume !(1 == ~main_diff_ev~0); 101444#L466-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 101443#L471-1 assume !(1 == ~main_dbl_ev~0); 101441#L476-1 assume !(1 == ~main_zero_ev~0); 101439#L481-1 assume !(1 == ~main_clk_ev~0); 101437#L486-1 assume !(1 == ~main_clk_pos_edge~0); 101420#L491-1 assume !(1 == ~main_clk_neg_edge~0); 101419#L742-1 [2024-11-13 13:16:16,817 INFO L747 eck$LassoCheckResult]: Loop: 101419#L742-1 assume !false; 99770#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 99765#L229 assume !false; 99763#L147 assume !(0 == ~N_generate_st~0); 99761#L151 assume !(0 == ~S1_addsub_st~0); 99759#L154 assume !(0 == ~S2_presdbl_st~0); 99757#L157 assume !(0 == ~S3_zero_st~0); 99754#L160 assume !(0 == ~D_print_st~0); 99752#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 99750#L509 assume !(1 == ~main_in1_req_up~0); 99747#L509-2 assume !(1 == ~main_in2_req_up~0); 99740#L520-1 assume !(1 == ~main_sum_req_up~0); 99736#L531-1 assume !(1 == ~main_diff_req_up~0); 99732#L542-1 assume !(1 == ~main_pres_req_up~0); 99727#L553-1 assume !(1 == ~main_dbl_req_up~0); 99723#L564-1 assume !(1 == ~main_zero_req_up~0); 99724#L575-1 assume !(1 == ~main_clk_req_up~0); 99855#L586-1 start_simulation_~kernel_st~0#1 := 3; 102180#L605 assume !(0 == ~main_in1_ev~0); 102178#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 102176#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 102174#L615-1 assume !(0 == ~main_diff_ev~0); 102171#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 102170#L625-1 assume !(0 == ~main_dbl_ev~0); 102168#L630-1 assume !(0 == ~main_zero_ev~0); 102167#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 102166#L640-1 assume !(0 == ~main_clk_pos_edge~0); 102165#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 102164#L650-1 assume !(1 == ~main_clk_pos_edge~0); 102163#L655-1 assume !(1 == ~main_clk_pos_edge~0); 102161#L660-1 assume !(1 == ~main_clk_pos_edge~0); 102159#L665-1 assume !(1 == ~main_clk_pos_edge~0); 102157#L670-1 assume !(1 == ~main_clk_pos_edge~0); 102154#L675-1 assume !(1 == ~main_in1_ev~0); 102153#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 102151#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 102149#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 102147#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 102145#L700-1 assume !(1 == ~main_dbl_ev~0); 102144#L705-1 assume !(1 == ~main_zero_ev~0); 100309#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 99798#L715-1 assume !(1 == ~main_clk_pos_edge~0); 99794#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 99795#L725-1 assume 0 == ~N_generate_st~0; 101419#L742-1 [2024-11-13 13:16:16,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:16,818 INFO L85 PathProgramCache]: Analyzing trace with hash -257063241, now seen corresponding path program 1 times [2024-11-13 13:16:16,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:16,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487444867] [2024-11-13 13:16:16,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:16,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:16,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:16,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:16,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:16,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487444867] [2024-11-13 13:16:16,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487444867] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:16,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:16,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:16,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067310844] [2024-11-13 13:16:16,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:16,911 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:16,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:16,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1481513430, now seen corresponding path program 1 times [2024-11-13 13:16:16,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:16,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672066283] [2024-11-13 13:16:16,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:16,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:16,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:17,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:17,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:17,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672066283] [2024-11-13 13:16:17,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672066283] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:17,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:17,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:17,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118357074] [2024-11-13 13:16:17,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:17,049 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:17,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:17,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:17,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:17,050 INFO L87 Difference]: Start difference. First operand 18228 states and 29320 transitions. cyclomatic complexity: 11124 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:17,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:17,429 INFO L93 Difference]: Finished difference Result 33639 states and 54033 transitions. [2024-11-13 13:16:17,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33639 states and 54033 transitions. [2024-11-13 13:16:17,578 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31818 [2024-11-13 13:16:17,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33639 states to 33639 states and 54033 transitions. [2024-11-13 13:16:17,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33639 [2024-11-13 13:16:17,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33639 [2024-11-13 13:16:17,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33639 states and 54033 transitions. [2024-11-13 13:16:17,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:17,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33639 states and 54033 transitions. [2024-11-13 13:16:17,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33639 states and 54033 transitions. [2024-11-13 13:16:18,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33639 to 33639. [2024-11-13 13:16:18,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33639 states, 33639 states have (on average 1.6062605903861589) internal successors, (54033), 33638 states have internal predecessors, (54033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:18,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33639 states to 33639 states and 54033 transitions. [2024-11-13 13:16:18,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33639 states and 54033 transitions. [2024-11-13 13:16:18,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:16:18,607 INFO L424 stractBuchiCegarLoop]: Abstraction has 33639 states and 54033 transitions. [2024-11-13 13:16:18,608 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:16:18,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33639 states and 54033 transitions. [2024-11-13 13:16:18,828 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31818 [2024-11-13 13:16:18,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:18,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:18,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:18,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:18,833 INFO L745 eck$LassoCheckResult]: Stem: 150225#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 150226#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 150044#L256 assume !(1 == ~main_in1_req_up~0); 149998#L256-2 assume !(1 == ~main_in2_req_up~0); 150000#L267-1 assume !(1 == ~main_sum_req_up~0); 150031#L278-1 assume !(1 == ~main_diff_req_up~0); 149980#L289-1 assume !(1 == ~main_pres_req_up~0); 149981#L300-1 assume !(1 == ~main_dbl_req_up~0); 151754#L311-1 assume !(1 == ~main_zero_req_up~0); 151751#L322-1 assume !(1 == ~main_clk_req_up~0); 151752#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 154662#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 154660#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 154658#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 154657#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 154655#L371-1 assume !(0 == ~main_in1_ev~0); 154653#L376-1 assume !(0 == ~main_in2_ev~0); 154651#L381-1 assume !(0 == ~main_sum_ev~0); 154650#L386-1 assume !(0 == ~main_diff_ev~0); 154648#L391-1 assume !(0 == ~main_pres_ev~0); 154647#L396-1 assume !(0 == ~main_dbl_ev~0); 154646#L401-1 assume !(0 == ~main_zero_ev~0); 154645#L406-1 assume !(0 == ~main_clk_ev~0); 151930#L411-1 assume !(0 == ~main_clk_pos_edge~0); 151928#L416-1 assume !(0 == ~main_clk_neg_edge~0); 151924#L421-1 assume !(1 == ~main_clk_pos_edge~0); 151921#L426-1 assume !(1 == ~main_clk_pos_edge~0); 151917#L431-1 assume !(1 == ~main_clk_pos_edge~0); 151914#L436-1 assume !(1 == ~main_clk_pos_edge~0); 151910#L441-1 assume !(1 == ~main_clk_pos_edge~0); 151906#L446-1 assume !(1 == ~main_in1_ev~0); 151902#L451-1 assume !(1 == ~main_in2_ev~0); 151898#L456-1 assume !(1 == ~main_sum_ev~0); 151894#L461-1 assume !(1 == ~main_diff_ev~0); 151890#L466-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 151891#L471-1 assume !(1 == ~main_dbl_ev~0); 156986#L476-1 assume !(1 == ~main_zero_ev~0); 156985#L481-1 assume !(1 == ~main_clk_ev~0); 156984#L486-1 assume !(1 == ~main_clk_pos_edge~0); 156900#L491-1 assume !(1 == ~main_clk_neg_edge~0); 156899#L742-1 [2024-11-13 13:16:18,833 INFO L747 eck$LassoCheckResult]: Loop: 156899#L742-1 assume !false; 154165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 154162#L229 assume !false; 154156#L147 assume !(0 == ~N_generate_st~0); 154157#L151 assume !(0 == ~S1_addsub_st~0); 154152#L154 assume !(0 == ~S2_presdbl_st~0); 154154#L157 assume !(0 == ~S3_zero_st~0); 154155#L160 assume !(0 == ~D_print_st~0); 154158#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 156956#L509 assume !(1 == ~main_in1_req_up~0); 156954#L509-2 assume !(1 == ~main_in2_req_up~0); 156950#L520-1 assume !(1 == ~main_sum_req_up~0); 156948#L531-1 assume !(1 == ~main_diff_req_up~0); 156945#L542-1 assume !(1 == ~main_pres_req_up~0); 156946#L553-1 assume !(1 == ~main_dbl_req_up~0); 156980#L564-1 assume !(1 == ~main_zero_req_up~0); 156977#L575-1 assume !(1 == ~main_clk_req_up~0); 156975#L586-1 start_simulation_~kernel_st~0#1 := 3; 156974#L605 assume !(0 == ~main_in1_ev~0); 156973#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 156972#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 156971#L615-1 assume !(0 == ~main_diff_ev~0); 156970#L620-1 assume !(0 == ~main_pres_ev~0); 156928#L625-1 assume !(0 == ~main_dbl_ev~0); 156969#L630-1 assume !(0 == ~main_zero_ev~0); 156968#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 156967#L640-1 assume !(0 == ~main_clk_pos_edge~0); 156966#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 156965#L650-1 assume !(1 == ~main_clk_pos_edge~0); 156964#L655-1 assume !(1 == ~main_clk_pos_edge~0); 156963#L660-1 assume !(1 == ~main_clk_pos_edge~0); 156962#L665-1 assume !(1 == ~main_clk_pos_edge~0); 156961#L670-1 assume !(1 == ~main_clk_pos_edge~0); 156960#L675-1 assume !(1 == ~main_in1_ev~0); 156959#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 156958#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 156957#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 156911#L695-1 assume !(1 == ~main_pres_ev~0); 152404#L700-1 assume !(1 == ~main_dbl_ev~0); 156910#L705-1 assume !(1 == ~main_zero_ev~0); 156909#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 156908#L715-1 assume !(1 == ~main_clk_pos_edge~0); 156907#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 156903#L725-1 assume 0 == ~N_generate_st~0; 156899#L742-1 [2024-11-13 13:16:18,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:18,834 INFO L85 PathProgramCache]: Analyzing trace with hash 165638585, now seen corresponding path program 1 times [2024-11-13 13:16:18,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:18,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97654238] [2024-11-13 13:16:18,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:18,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:18,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:18,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:18,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:18,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97654238] [2024-11-13 13:16:18,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97654238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:18,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:18,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:18,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147242851] [2024-11-13 13:16:18,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:18,910 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:18,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:18,911 INFO L85 PathProgramCache]: Analyzing trace with hash -819591786, now seen corresponding path program 1 times [2024-11-13 13:16:18,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:18,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936357951] [2024-11-13 13:16:18,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:18,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:18,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:18,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:18,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:18,944 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936357951] [2024-11-13 13:16:18,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936357951] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:18,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:18,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:18,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709484455] [2024-11-13 13:16:18,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:18,945 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:18,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:18,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:18,945 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:18,946 INFO L87 Difference]: Start difference. First operand 33639 states and 54033 transitions. cyclomatic complexity: 20458 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:19,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:19,918 INFO L93 Difference]: Finished difference Result 34837 states and 55325 transitions. [2024-11-13 13:16:19,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34837 states and 55325 transitions. [2024-11-13 13:16:20,121 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32905 [2024-11-13 13:16:20,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34837 states to 34837 states and 55325 transitions. [2024-11-13 13:16:20,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34837 [2024-11-13 13:16:20,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34837 [2024-11-13 13:16:20,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34837 states and 55325 transitions. [2024-11-13 13:16:20,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:20,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34837 states and 55325 transitions. [2024-11-13 13:16:20,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34837 states and 55325 transitions. [2024-11-13 13:16:20,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34837 to 33639. [2024-11-13 13:16:21,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33639 states, 33639 states have (on average 1.5886025149380183) internal successors, (53439), 33638 states have internal predecessors, (53439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:21,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33639 states to 33639 states and 53439 transitions. [2024-11-13 13:16:21,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33639 states and 53439 transitions. [2024-11-13 13:16:21,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:21,082 INFO L424 stractBuchiCegarLoop]: Abstraction has 33639 states and 53439 transitions. [2024-11-13 13:16:21,082 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:16:21,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33639 states and 53439 transitions. [2024-11-13 13:16:21,377 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31818 [2024-11-13 13:16:21,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:21,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:21,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:21,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:21,379 INFO L745 eck$LassoCheckResult]: Stem: 218712#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 218713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 218531#L256 assume !(1 == ~main_in1_req_up~0); 218485#L256-2 assume !(1 == ~main_in2_req_up~0); 218487#L267-1 assume !(1 == ~main_sum_req_up~0); 218518#L278-1 assume !(1 == ~main_diff_req_up~0); 218467#L289-1 assume !(1 == ~main_pres_req_up~0); 218468#L300-1 assume !(1 == ~main_dbl_req_up~0); 218581#L311-1 assume !(1 == ~main_zero_req_up~0); 218947#L322-1 assume !(1 == ~main_clk_req_up~0); 218949#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 236726#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 236725#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 236724#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 236723#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 218693#L371-1 assume !(0 == ~main_in1_ev~0); 218556#L376-1 assume !(0 == ~main_in2_ev~0); 218557#L381-1 assume !(0 == ~main_sum_ev~0); 218722#L386-1 assume !(0 == ~main_diff_ev~0); 218723#L391-1 assume !(0 == ~main_pres_ev~0); 218857#L396-1 assume !(0 == ~main_dbl_ev~0); 218858#L401-1 assume !(0 == ~main_zero_ev~0); 226150#L406-1 assume !(0 == ~main_clk_ev~0); 226146#L411-1 assume !(0 == ~main_clk_pos_edge~0); 226143#L416-1 assume !(0 == ~main_clk_neg_edge~0); 226142#L421-1 assume !(1 == ~main_clk_pos_edge~0); 226138#L426-1 assume !(1 == ~main_clk_pos_edge~0); 226137#L431-1 assume !(1 == ~main_clk_pos_edge~0); 226133#L436-1 assume !(1 == ~main_clk_pos_edge~0); 226132#L441-1 assume !(1 == ~main_clk_pos_edge~0); 226131#L446-1 assume !(1 == ~main_in1_ev~0); 226130#L451-1 assume !(1 == ~main_in2_ev~0); 226129#L456-1 assume !(1 == ~main_sum_ev~0); 226128#L461-1 assume !(1 == ~main_diff_ev~0); 226127#L466-1 assume !(1 == ~main_pres_ev~0); 226126#L471-1 assume !(1 == ~main_dbl_ev~0); 226125#L476-1 assume !(1 == ~main_zero_ev~0); 226121#L481-1 assume !(1 == ~main_clk_ev~0); 226122#L486-1 assume !(1 == ~main_clk_pos_edge~0); 223347#L491-1 assume !(1 == ~main_clk_neg_edge~0); 223348#L742-1 [2024-11-13 13:16:21,379 INFO L747 eck$LassoCheckResult]: Loop: 223348#L742-1 assume !false; 223340#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 223337#L229 assume !false; 223316#L147 assume !(0 == ~N_generate_st~0); 223317#L151 assume !(0 == ~S1_addsub_st~0); 223311#L154 assume !(0 == ~S2_presdbl_st~0); 223312#L157 assume !(0 == ~S3_zero_st~0); 223318#L160 assume !(0 == ~D_print_st~0); 223319#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 223593#L509 assume !(1 == ~main_in1_req_up~0); 223594#L509-2 assume !(1 == ~main_in2_req_up~0); 236601#L520-1 assume !(1 == ~main_sum_req_up~0); 236599#L531-1 assume !(1 == ~main_diff_req_up~0); 236597#L542-1 assume !(1 == ~main_pres_req_up~0); 223508#L553-1 assume !(1 == ~main_dbl_req_up~0); 223507#L564-1 assume !(1 == ~main_zero_req_up~0); 236719#L575-1 assume !(1 == ~main_clk_req_up~0); 236717#L586-1 start_simulation_~kernel_st~0#1 := 3; 236716#L605 assume !(0 == ~main_in1_ev~0); 236715#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 236714#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 236713#L615-1 assume !(0 == ~main_diff_ev~0); 236712#L620-1 assume !(0 == ~main_pres_ev~0); 236711#L625-1 assume !(0 == ~main_dbl_ev~0); 236710#L630-1 assume !(0 == ~main_zero_ev~0); 236709#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 236708#L640-1 assume !(0 == ~main_clk_pos_edge~0); 236707#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 236706#L650-1 assume !(1 == ~main_clk_pos_edge~0); 236705#L655-1 assume !(1 == ~main_clk_pos_edge~0); 236704#L660-1 assume !(1 == ~main_clk_pos_edge~0); 236703#L665-1 assume !(1 == ~main_clk_pos_edge~0); 236702#L670-1 assume !(1 == ~main_clk_pos_edge~0); 236701#L675-1 assume !(1 == ~main_in1_ev~0); 236700#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 236699#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 236698#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 236697#L695-1 assume !(1 == ~main_pres_ev~0); 236696#L700-1 assume !(1 == ~main_dbl_ev~0); 236695#L705-1 assume !(1 == ~main_zero_ev~0); 236694#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 236692#L715-1 assume !(1 == ~main_clk_pos_edge~0); 236690#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 223351#L725-1 assume 0 == ~N_generate_st~0; 223348#L742-1 [2024-11-13 13:16:21,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:21,380 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2024-11-13 13:16:21,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:21,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693557242] [2024-11-13 13:16:21,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:21,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:21,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:21,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:21,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:21,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:21,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:21,425 INFO L85 PathProgramCache]: Analyzing trace with hash -819591786, now seen corresponding path program 2 times [2024-11-13 13:16:21,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:21,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862572367] [2024-11-13 13:16:21,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:21,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:21,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:21,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:21,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:21,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862572367] [2024-11-13 13:16:21,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862572367] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:21,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:21,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:21,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547099507] [2024-11-13 13:16:21,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:21,460 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:21,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:21,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:21,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:21,461 INFO L87 Difference]: Start difference. First operand 33639 states and 53439 transitions. cyclomatic complexity: 19864 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:21,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:21,687 INFO L93 Difference]: Finished difference Result 46371 states and 72766 transitions. [2024-11-13 13:16:21,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46371 states and 72766 transitions. [2024-11-13 13:16:22,017 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 43178 [2024-11-13 13:16:22,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46371 states to 46371 states and 72766 transitions. [2024-11-13 13:16:22,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46371 [2024-11-13 13:16:22,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46371 [2024-11-13 13:16:22,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46371 states and 72766 transitions. [2024-11-13 13:16:22,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:22,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46371 states and 72766 transitions. [2024-11-13 13:16:22,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46371 states and 72766 transitions. [2024-11-13 13:16:23,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46371 to 46371. [2024-11-13 13:16:23,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46371 states, 46371 states have (on average 1.5692135170688577) internal successors, (72766), 46370 states have internal predecessors, (72766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:23,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46371 states to 46371 states and 72766 transitions. [2024-11-13 13:16:23,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46371 states and 72766 transitions. [2024-11-13 13:16:23,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:23,442 INFO L424 stractBuchiCegarLoop]: Abstraction has 46371 states and 72766 transitions. [2024-11-13 13:16:23,442 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:16:23,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46371 states and 72766 transitions. [2024-11-13 13:16:23,944 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 43178 [2024-11-13 13:16:23,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:23,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:23,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:23,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:23,946 INFO L745 eck$LassoCheckResult]: Stem: 298727#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 298728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 298548#L256 assume !(1 == ~main_in1_req_up~0); 298501#L256-2 assume !(1 == ~main_in2_req_up~0); 298503#L267-1 assume !(1 == ~main_sum_req_up~0); 298535#L278-1 assume !(1 == ~main_diff_req_up~0); 298483#L289-1 assume !(1 == ~main_pres_req_up~0); 298484#L300-1 assume !(1 == ~main_dbl_req_up~0); 300454#L311-1 assume !(1 == ~main_zero_req_up~0); 300452#L322-1 assume !(1 == ~main_clk_req_up~0); 298733#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 298838#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 309130#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 309128#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 309125#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 309122#L371-1 assume !(0 == ~main_in1_ev~0); 309120#L376-1 assume !(0 == ~main_in2_ev~0); 309117#L381-1 assume !(0 == ~main_sum_ev~0); 309115#L386-1 assume !(0 == ~main_diff_ev~0); 309113#L391-1 assume !(0 == ~main_pres_ev~0); 309111#L396-1 assume !(0 == ~main_dbl_ev~0); 309109#L401-1 assume !(0 == ~main_zero_ev~0); 309106#L406-1 assume !(0 == ~main_clk_ev~0); 309103#L411-1 assume !(0 == ~main_clk_pos_edge~0); 309100#L416-1 assume !(0 == ~main_clk_neg_edge~0); 309099#L421-1 assume !(1 == ~main_clk_pos_edge~0); 309098#L426-1 assume !(1 == ~main_clk_pos_edge~0); 309097#L431-1 assume !(1 == ~main_clk_pos_edge~0); 309096#L436-1 assume !(1 == ~main_clk_pos_edge~0); 309095#L441-1 assume !(1 == ~main_clk_pos_edge~0); 309094#L446-1 assume !(1 == ~main_in1_ev~0); 309093#L451-1 assume !(1 == ~main_in2_ev~0); 309092#L456-1 assume !(1 == ~main_sum_ev~0); 309091#L461-1 assume !(1 == ~main_diff_ev~0); 309090#L466-1 assume !(1 == ~main_pres_ev~0); 309089#L471-1 assume !(1 == ~main_dbl_ev~0); 309088#L476-1 assume !(1 == ~main_zero_ev~0); 309087#L481-1 assume !(1 == ~main_clk_ev~0); 309083#L486-1 assume !(1 == ~main_clk_pos_edge~0); 298542#L491-1 assume !(1 == ~main_clk_neg_edge~0); 298543#L742-1 [2024-11-13 13:16:23,947 INFO L747 eck$LassoCheckResult]: Loop: 298543#L742-1 assume !false; 298908#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 298574#L229 assume !false; 298851#L147 assume !(0 == ~N_generate_st~0); 300343#L151 assume !(0 == ~S1_addsub_st~0); 308515#L154 assume !(0 == ~S2_presdbl_st~0); 308510#L157 assume !(0 == ~S3_zero_st~0); 308509#L160 assume !(0 == ~D_print_st~0); 298619#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 298620#L509 assume !(1 == ~main_in1_req_up~0); 298805#L509-2 assume !(1 == ~main_in2_req_up~0); 298806#L520-1 assume !(1 == ~main_sum_req_up~0); 301608#L531-1 assume !(1 == ~main_diff_req_up~0); 303259#L542-1 assume !(1 == ~main_pres_req_up~0); 301598#L553-1 assume !(1 == ~main_dbl_req_up~0); 301596#L564-1 assume !(1 == ~main_zero_req_up~0); 300405#L575-1 assume !(1 == ~main_clk_req_up~0); 300406#L586-1 start_simulation_~kernel_st~0#1 := 3; 308649#L605 assume !(0 == ~main_in1_ev~0); 308648#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 308647#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 308646#L615-1 assume !(0 == ~main_diff_ev~0); 308645#L620-1 assume !(0 == ~main_pres_ev~0); 308644#L625-1 assume !(0 == ~main_dbl_ev~0); 308643#L630-1 assume !(0 == ~main_zero_ev~0); 308642#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 308641#L640-1 assume !(0 == ~main_clk_pos_edge~0); 308640#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 308639#L650-1 assume !(1 == ~main_clk_pos_edge~0); 308638#L655-1 assume !(1 == ~main_clk_pos_edge~0); 308637#L660-1 assume !(1 == ~main_clk_pos_edge~0); 308636#L665-1 assume !(1 == ~main_clk_pos_edge~0); 308634#L670-1 assume !(1 == ~main_clk_pos_edge~0); 308632#L675-1 assume !(1 == ~main_in1_ev~0); 308630#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 308628#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 308626#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 308624#L695-1 assume !(1 == ~main_pres_ev~0); 308445#L700-1 assume !(1 == ~main_dbl_ev~0); 307739#L705-1 assume !(1 == ~main_zero_ev~0); 307738#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 307736#L715-1 assume !(1 == ~main_clk_pos_edge~0); 307734#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 298791#L725-1 assume !(0 == ~N_generate_st~0); 298630#L733 assume 0 == ~S1_addsub_st~0; 298543#L742-1 [2024-11-13 13:16:23,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:23,951 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2024-11-13 13:16:23,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:23,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786643564] [2024-11-13 13:16:23,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:23,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:23,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:23,988 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:24,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:24,042 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:24,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:24,044 INFO L85 PathProgramCache]: Analyzing trace with hash 362459152, now seen corresponding path program 1 times [2024-11-13 13:16:24,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:24,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286878264] [2024-11-13 13:16:24,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:24,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:24,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:24,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:24,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:24,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286878264] [2024-11-13 13:16:24,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286878264] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:24,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:24,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:24,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915801794] [2024-11-13 13:16:24,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:24,091 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:24,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:24,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:24,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:24,093 INFO L87 Difference]: Start difference. First operand 46371 states and 72766 transitions. cyclomatic complexity: 26467 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:24,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:24,564 INFO L93 Difference]: Finished difference Result 69292 states and 107770 transitions. [2024-11-13 13:16:24,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69292 states and 107770 transitions. [2024-11-13 13:16:24,824 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 63352 [2024-11-13 13:16:25,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69292 states to 69292 states and 107770 transitions. [2024-11-13 13:16:25,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69292 [2024-11-13 13:16:25,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69292 [2024-11-13 13:16:25,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69292 states and 107770 transitions. [2024-11-13 13:16:25,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:25,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69292 states and 107770 transitions. [2024-11-13 13:16:25,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69292 states and 107770 transitions. [2024-11-13 13:16:26,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69292 to 69292. [2024-11-13 13:16:26,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69292 states, 69292 states have (on average 1.5553021993880967) internal successors, (107770), 69291 states have internal predecessors, (107770), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:26,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69292 states to 69292 states and 107770 transitions. [2024-11-13 13:16:26,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69292 states and 107770 transitions. [2024-11-13 13:16:26,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:26,504 INFO L424 stractBuchiCegarLoop]: Abstraction has 69292 states and 107770 transitions. [2024-11-13 13:16:26,504 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:16:26,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69292 states and 107770 transitions. [2024-11-13 13:16:26,915 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 63352 [2024-11-13 13:16:26,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:26,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:26,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:26,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:26,917 INFO L745 eck$LassoCheckResult]: Stem: 414404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 414405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 414218#L256 assume !(1 == ~main_in1_req_up~0); 414170#L256-2 assume !(1 == ~main_in2_req_up~0); 414172#L267-1 assume !(1 == ~main_sum_req_up~0); 414205#L278-1 assume !(1 == ~main_diff_req_up~0); 414152#L289-1 assume !(1 == ~main_pres_req_up~0); 414153#L300-1 assume !(1 == ~main_dbl_req_up~0); 414267#L311-1 assume !(1 == ~main_zero_req_up~0); 414448#L322-1 assume !(1 == ~main_clk_req_up~0); 414697#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 421393#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 428824#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 428822#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 428820#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 428818#L371-1 assume !(0 == ~main_in1_ev~0); 428816#L376-1 assume !(0 == ~main_in2_ev~0); 428814#L381-1 assume !(0 == ~main_sum_ev~0); 428812#L386-1 assume !(0 == ~main_diff_ev~0); 428810#L391-1 assume !(0 == ~main_pres_ev~0); 428808#L396-1 assume !(0 == ~main_dbl_ev~0); 428806#L401-1 assume !(0 == ~main_zero_ev~0); 428804#L406-1 assume !(0 == ~main_clk_ev~0); 428802#L411-1 assume !(0 == ~main_clk_pos_edge~0); 428800#L416-1 assume !(0 == ~main_clk_neg_edge~0); 428798#L421-1 assume !(1 == ~main_clk_pos_edge~0); 428796#L426-1 assume !(1 == ~main_clk_pos_edge~0); 428794#L431-1 assume !(1 == ~main_clk_pos_edge~0); 428792#L436-1 assume !(1 == ~main_clk_pos_edge~0); 428790#L441-1 assume !(1 == ~main_clk_pos_edge~0); 428788#L446-1 assume !(1 == ~main_in1_ev~0); 428786#L451-1 assume !(1 == ~main_in2_ev~0); 428784#L456-1 assume !(1 == ~main_sum_ev~0); 428782#L461-1 assume !(1 == ~main_diff_ev~0); 428780#L466-1 assume !(1 == ~main_pres_ev~0); 428779#L471-1 assume !(1 == ~main_dbl_ev~0); 428778#L476-1 assume !(1 == ~main_zero_ev~0); 428776#L481-1 assume !(1 == ~main_clk_ev~0); 428774#L486-1 assume !(1 == ~main_clk_pos_edge~0); 428768#L491-1 assume !(1 == ~main_clk_neg_edge~0); 428764#L742-1 [2024-11-13 13:16:26,917 INFO L747 eck$LassoCheckResult]: Loop: 428764#L742-1 assume !false; 428645#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 414539#L229 assume !false; 414540#L147 assume !(0 == ~N_generate_st~0); 414780#L151 assume !(0 == ~S1_addsub_st~0); 425459#L154 assume !(0 == ~S2_presdbl_st~0); 425458#L157 assume !(0 == ~S3_zero_st~0); 425456#L160 assume !(0 == ~D_print_st~0); 425455#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 425454#L509 assume !(1 == ~main_in1_req_up~0); 425452#L509-2 assume !(1 == ~main_in2_req_up~0); 425448#L520-1 assume !(1 == ~main_sum_req_up~0); 425446#L531-1 assume !(1 == ~main_diff_req_up~0); 425444#L542-1 assume !(1 == ~main_pres_req_up~0); 422607#L553-1 assume !(1 == ~main_dbl_req_up~0); 423107#L564-1 assume !(1 == ~main_zero_req_up~0); 423108#L575-1 assume !(1 == ~main_clk_req_up~0); 428962#L586-1 start_simulation_~kernel_st~0#1 := 3; 428961#L605 assume !(0 == ~main_in1_ev~0); 428959#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 428957#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 428955#L615-1 assume !(0 == ~main_diff_ev~0); 428953#L620-1 assume !(0 == ~main_pres_ev~0); 428951#L625-1 assume !(0 == ~main_dbl_ev~0); 428948#L630-1 assume !(0 == ~main_zero_ev~0); 428946#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 428944#L640-1 assume !(0 == ~main_clk_pos_edge~0); 428942#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 428941#L650-1 assume !(1 == ~main_clk_pos_edge~0); 428939#L655-1 assume !(1 == ~main_clk_pos_edge~0); 428938#L660-1 assume !(1 == ~main_clk_pos_edge~0); 428936#L665-1 assume !(1 == ~main_clk_pos_edge~0); 428934#L670-1 assume !(1 == ~main_clk_pos_edge~0); 428932#L675-1 assume !(1 == ~main_in1_ev~0); 428930#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 428928#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 428926#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 428924#L695-1 assume !(1 == ~main_pres_ev~0); 428922#L700-1 assume !(1 == ~main_dbl_ev~0); 428919#L705-1 assume !(1 == ~main_zero_ev~0); 428917#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 428916#L715-1 assume !(1 == ~main_clk_pos_edge~0); 428914#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 414855#L725-1 assume !(0 == ~N_generate_st~0); 414302#L733 assume !(0 == ~S1_addsub_st~0); 414303#L736 assume 0 == ~S2_presdbl_st~0; 428764#L742-1 [2024-11-13 13:16:26,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:26,917 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2024-11-13 13:16:26,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:26,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732432708] [2024-11-13 13:16:26,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:26,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:26,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:26,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:26,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:26,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:26,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:26,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1648667429, now seen corresponding path program 1 times [2024-11-13 13:16:26,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:26,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20886157] [2024-11-13 13:16:26,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:26,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:26,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:27,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:27,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:27,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20886157] [2024-11-13 13:16:27,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20886157] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:27,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:27,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:27,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323180630] [2024-11-13 13:16:27,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:27,024 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:27,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:27,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:27,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:27,025 INFO L87 Difference]: Start difference. First operand 69292 states and 107770 transitions. cyclomatic complexity: 38574 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:27,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:27,569 INFO L93 Difference]: Finished difference Result 74516 states and 115203 transitions. [2024-11-13 13:16:27,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74516 states and 115203 transitions. [2024-11-13 13:16:27,804 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 68344 [2024-11-13 13:16:28,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74516 states to 74516 states and 115203 transitions. [2024-11-13 13:16:28,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74516 [2024-11-13 13:16:28,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74516 [2024-11-13 13:16:28,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74516 states and 115203 transitions. [2024-11-13 13:16:28,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:28,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74516 states and 115203 transitions. [2024-11-13 13:16:28,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74516 states and 115203 transitions. [2024-11-13 13:16:29,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74516 to 74516. [2024-11-13 13:16:29,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74516 states, 74516 states have (on average 1.5460169627999356) internal successors, (115203), 74515 states have internal predecessors, (115203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:29,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74516 states to 74516 states and 115203 transitions. [2024-11-13 13:16:29,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74516 states and 115203 transitions. [2024-11-13 13:16:29,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:29,615 INFO L424 stractBuchiCegarLoop]: Abstraction has 74516 states and 115203 transitions. [2024-11-13 13:16:29,615 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:16:29,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74516 states and 115203 transitions. [2024-11-13 13:16:30,249 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 68344 [2024-11-13 13:16:30,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:30,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:30,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:30,251 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:30,251 INFO L745 eck$LassoCheckResult]: Stem: 558223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 558224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 558033#L256 assume !(1 == ~main_in1_req_up~0); 557984#L256-2 assume !(1 == ~main_in2_req_up~0); 557986#L267-1 assume !(1 == ~main_sum_req_up~0); 558019#L278-1 assume !(1 == ~main_diff_req_up~0); 557966#L289-1 assume !(1 == ~main_pres_req_up~0); 557967#L300-1 assume !(1 == ~main_dbl_req_up~0); 558083#L311-1 assume !(1 == ~main_zero_req_up~0); 558266#L322-1 assume !(1 == ~main_clk_req_up~0); 558560#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 564085#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 564086#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 564092#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 564088#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 564083#L371-1 assume !(0 == ~main_in1_ev~0); 564079#L376-1 assume !(0 == ~main_in2_ev~0); 564075#L381-1 assume !(0 == ~main_sum_ev~0); 564071#L386-1 assume !(0 == ~main_diff_ev~0); 564067#L391-1 assume !(0 == ~main_pres_ev~0); 564063#L396-1 assume !(0 == ~main_dbl_ev~0); 564059#L401-1 assume !(0 == ~main_zero_ev~0); 564055#L406-1 assume !(0 == ~main_clk_ev~0); 564051#L411-1 assume !(0 == ~main_clk_pos_edge~0); 564047#L416-1 assume !(0 == ~main_clk_neg_edge~0); 564043#L421-1 assume !(1 == ~main_clk_pos_edge~0); 564039#L426-1 assume !(1 == ~main_clk_pos_edge~0); 564035#L431-1 assume !(1 == ~main_clk_pos_edge~0); 564031#L436-1 assume !(1 == ~main_clk_pos_edge~0); 564027#L441-1 assume !(1 == ~main_clk_pos_edge~0); 564023#L446-1 assume !(1 == ~main_in1_ev~0); 564019#L451-1 assume !(1 == ~main_in2_ev~0); 563946#L456-1 assume !(1 == ~main_sum_ev~0); 563947#L461-1 assume !(1 == ~main_diff_ev~0); 563942#L466-1 assume !(1 == ~main_pres_ev~0); 563943#L471-1 assume !(1 == ~main_dbl_ev~0); 563938#L476-1 assume !(1 == ~main_zero_ev~0); 563939#L481-1 assume !(1 == ~main_clk_ev~0); 564004#L486-1 assume !(1 == ~main_clk_pos_edge~0); 563899#L491-1 assume !(1 == ~main_clk_neg_edge~0); 563893#L742-1 [2024-11-13 13:16:30,253 INFO L747 eck$LassoCheckResult]: Loop: 563893#L742-1 assume !false; 563894#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 563886#L229 assume !false; 563887#L147 assume !(0 == ~N_generate_st~0); 560700#L151 assume !(0 == ~S1_addsub_st~0); 560699#L154 assume !(0 == ~S2_presdbl_st~0); 560698#L157 assume !(0 == ~S3_zero_st~0); 560696#L160 assume !(0 == ~D_print_st~0); 560695#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 560694#L509 assume !(1 == ~main_in1_req_up~0); 560692#L509-2 assume !(1 == ~main_in2_req_up~0); 559352#L520-1 assume !(1 == ~main_sum_req_up~0); 559353#L531-1 assume !(1 == ~main_diff_req_up~0); 559210#L542-1 assume !(1 == ~main_pres_req_up~0); 559212#L553-1 assume !(1 == ~main_dbl_req_up~0); 561120#L564-1 assume !(1 == ~main_zero_req_up~0); 561121#L575-1 assume !(1 == ~main_clk_req_up~0); 563931#L586-1 start_simulation_~kernel_st~0#1 := 3; 563930#L605 assume !(0 == ~main_in1_ev~0); 563929#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 563928#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 563927#L615-1 assume !(0 == ~main_diff_ev~0); 563926#L620-1 assume !(0 == ~main_pres_ev~0); 563925#L625-1 assume !(0 == ~main_dbl_ev~0); 563924#L630-1 assume !(0 == ~main_zero_ev~0); 563923#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 563922#L640-1 assume !(0 == ~main_clk_pos_edge~0); 563921#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 563920#L650-1 assume !(1 == ~main_clk_pos_edge~0); 563919#L655-1 assume !(1 == ~main_clk_pos_edge~0); 563918#L660-1 assume !(1 == ~main_clk_pos_edge~0); 563917#L665-1 assume !(1 == ~main_clk_pos_edge~0); 563916#L670-1 assume !(1 == ~main_clk_pos_edge~0); 563915#L675-1 assume !(1 == ~main_in1_ev~0); 563914#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 563913#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 563912#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 563911#L695-1 assume !(1 == ~main_pres_ev~0); 563910#L700-1 assume !(1 == ~main_dbl_ev~0); 563909#L705-1 assume !(1 == ~main_zero_ev~0); 563908#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 563907#L715-1 assume !(1 == ~main_clk_pos_edge~0); 563906#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 563905#L725-1 assume !(0 == ~N_generate_st~0); 563904#L733 assume !(0 == ~S1_addsub_st~0); 563903#L736 assume !(0 == ~S2_presdbl_st~0); 563900#L739 assume 0 == ~S3_zero_st~0; 563893#L742-1 [2024-11-13 13:16:30,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:30,256 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2024-11-13 13:16:30,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:30,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909455633] [2024-11-13 13:16:30,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:30,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:30,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:30,276 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:30,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:30,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:30,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:30,299 INFO L85 PathProgramCache]: Analyzing trace with hash 430918005, now seen corresponding path program 1 times [2024-11-13 13:16:30,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:30,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983164054] [2024-11-13 13:16:30,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:30,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:30,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:30,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:30,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:30,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983164054] [2024-11-13 13:16:30,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983164054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:30,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:30,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:30,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134772766] [2024-11-13 13:16:30,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:30,333 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:30,333 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:30,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:30,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:30,334 INFO L87 Difference]: Start difference. First operand 74516 states and 115203 transitions. cyclomatic complexity: 40783 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:30,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:30,792 INFO L93 Difference]: Finished difference Result 118982 states and 183110 transitions. [2024-11-13 13:16:30,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118982 states and 183110 transitions. [2024-11-13 13:16:32,035 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 107134 [2024-11-13 13:16:32,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118982 states to 118982 states and 183110 transitions. [2024-11-13 13:16:32,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118982 [2024-11-13 13:16:32,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118982 [2024-11-13 13:16:32,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118982 states and 183110 transitions. [2024-11-13 13:16:32,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:32,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118982 states and 183110 transitions. [2024-11-13 13:16:32,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118982 states and 183110 transitions. [2024-11-13 13:16:34,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118982 to 118982. [2024-11-13 13:16:34,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118982 states, 118982 states have (on average 1.5389722815215747) internal successors, (183110), 118981 states have internal predecessors, (183110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:34,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118982 states to 118982 states and 183110 transitions. [2024-11-13 13:16:34,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118982 states and 183110 transitions. [2024-11-13 13:16:34,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:34,701 INFO L424 stractBuchiCegarLoop]: Abstraction has 118982 states and 183110 transitions. [2024-11-13 13:16:34,701 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:16:34,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118982 states and 183110 transitions. [2024-11-13 13:16:35,093 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 107134 [2024-11-13 13:16:35,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:35,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:35,094 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:35,094 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:35,095 INFO L745 eck$LassoCheckResult]: Stem: 751726#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 751727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 751536#L256 assume !(1 == ~main_in1_req_up~0); 751487#L256-2 assume !(1 == ~main_in2_req_up~0); 751489#L267-1 assume !(1 == ~main_sum_req_up~0); 751522#L278-1 assume !(1 == ~main_diff_req_up~0); 751470#L289-1 assume !(1 == ~main_pres_req_up~0); 751471#L300-1 assume !(1 == ~main_dbl_req_up~0); 758079#L311-1 assume !(1 == ~main_zero_req_up~0); 758080#L322-1 assume !(1 == ~main_clk_req_up~0); 760556#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 760557#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 760555#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 760551#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 760549#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 760546#L371-1 assume !(0 == ~main_in1_ev~0); 760544#L376-1 assume !(0 == ~main_in2_ev~0); 760542#L381-1 assume !(0 == ~main_sum_ev~0); 760540#L386-1 assume !(0 == ~main_diff_ev~0); 760538#L391-1 assume !(0 == ~main_pres_ev~0); 760536#L396-1 assume !(0 == ~main_dbl_ev~0); 760534#L401-1 assume !(0 == ~main_zero_ev~0); 760532#L406-1 assume !(0 == ~main_clk_ev~0); 760530#L411-1 assume !(0 == ~main_clk_pos_edge~0); 760528#L416-1 assume !(0 == ~main_clk_neg_edge~0); 760526#L421-1 assume !(1 == ~main_clk_pos_edge~0); 760524#L426-1 assume !(1 == ~main_clk_pos_edge~0); 760522#L431-1 assume !(1 == ~main_clk_pos_edge~0); 760520#L436-1 assume !(1 == ~main_clk_pos_edge~0); 760518#L441-1 assume !(1 == ~main_clk_pos_edge~0); 760516#L446-1 assume !(1 == ~main_in1_ev~0); 760514#L451-1 assume !(1 == ~main_in2_ev~0); 760512#L456-1 assume !(1 == ~main_sum_ev~0); 760510#L461-1 assume !(1 == ~main_diff_ev~0); 760508#L466-1 assume !(1 == ~main_pres_ev~0); 760506#L471-1 assume !(1 == ~main_dbl_ev~0); 760504#L476-1 assume !(1 == ~main_zero_ev~0); 760502#L481-1 assume !(1 == ~main_clk_ev~0); 760500#L486-1 assume !(1 == ~main_clk_pos_edge~0); 760498#L491-1 assume !(1 == ~main_clk_neg_edge~0); 758259#L742-1 [2024-11-13 13:16:35,095 INFO L747 eck$LassoCheckResult]: Loop: 758259#L742-1 assume !false; 760495#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 760491#L229 assume !false; 760487#L147 assume !(0 == ~N_generate_st~0); 760396#L151 assume !(0 == ~S1_addsub_st~0); 760400#L154 assume !(0 == ~S2_presdbl_st~0); 757568#L157 assume !(0 == ~S3_zero_st~0); 754386#L160 assume !(0 == ~D_print_st~0); 754388#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 754349#L509 assume !(1 == ~main_in1_req_up~0); 754350#L509-2 assume !(1 == ~main_in2_req_up~0); 754337#L520-1 assume !(1 == ~main_sum_req_up~0); 754338#L531-1 assume !(1 == ~main_diff_req_up~0); 757490#L542-1 assume !(1 == ~main_pres_req_up~0); 754312#L553-1 assume !(1 == ~main_dbl_req_up~0); 754313#L564-1 assume !(1 == ~main_zero_req_up~0); 754977#L575-1 assume !(1 == ~main_clk_req_up~0); 755462#L586-1 start_simulation_~kernel_st~0#1 := 3; 755704#L605 assume !(0 == ~main_in1_ev~0); 755705#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 755700#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 755701#L615-1 assume !(0 == ~main_diff_ev~0); 755696#L620-1 assume !(0 == ~main_pres_ev~0); 755697#L625-1 assume !(0 == ~main_dbl_ev~0); 755692#L630-1 assume !(0 == ~main_zero_ev~0); 755693#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 755688#L640-1 assume !(0 == ~main_clk_pos_edge~0); 755689#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 755685#L650-1 assume !(1 == ~main_clk_pos_edge~0); 755686#L655-1 assume !(1 == ~main_clk_pos_edge~0); 758276#L660-1 assume !(1 == ~main_clk_pos_edge~0); 758275#L665-1 assume !(1 == ~main_clk_pos_edge~0); 758274#L670-1 assume !(1 == ~main_clk_pos_edge~0); 758273#L675-1 assume !(1 == ~main_in1_ev~0); 758272#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 758271#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 758270#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 758269#L695-1 assume !(1 == ~main_pres_ev~0); 758268#L700-1 assume !(1 == ~main_dbl_ev~0); 758267#L705-1 assume !(1 == ~main_zero_ev~0); 758266#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 758265#L715-1 assume !(1 == ~main_clk_pos_edge~0); 758264#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 758263#L725-1 assume !(0 == ~N_generate_st~0); 758262#L733 assume !(0 == ~S1_addsub_st~0); 758261#L736 assume !(0 == ~S2_presdbl_st~0); 754035#L739 assume !(0 == ~S3_zero_st~0); 754036#L742 assume 0 == ~D_print_st~0; 758259#L742-1 [2024-11-13 13:16:35,095 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:35,095 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2024-11-13 13:16:35,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:35,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415718174] [2024-11-13 13:16:35,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:35,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:35,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:35,113 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:35,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:35,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:35,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:35,131 INFO L85 PathProgramCache]: Analyzing trace with hash 473557024, now seen corresponding path program 1 times [2024-11-13 13:16:35,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:35,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495877919] [2024-11-13 13:16:35,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:35,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:35,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:35,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:35,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:35,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495877919] [2024-11-13 13:16:35,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495877919] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:35,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:35,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:16:35,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122518399] [2024-11-13 13:16:35,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:35,173 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:35,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:35,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:16:35,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:16:35,174 INFO L87 Difference]: Start difference. First operand 118982 states and 183110 transitions. cyclomatic complexity: 64272 Second operand has 3 states, 2 states have (on average 24.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:36,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:36,633 INFO L93 Difference]: Finished difference Result 201485 states and 307482 transitions. [2024-11-13 13:16:36,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201485 states and 307482 transitions. [2024-11-13 13:16:37,375 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 174628 [2024-11-13 13:16:38,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201485 states to 201485 states and 307482 transitions. [2024-11-13 13:16:38,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201485 [2024-11-13 13:16:38,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201485 [2024-11-13 13:16:38,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201485 states and 307482 transitions. [2024-11-13 13:16:38,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:38,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201485 states and 307482 transitions. [2024-11-13 13:16:38,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201485 states and 307482 transitions. [2024-11-13 13:16:40,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201485 to 201485. [2024-11-13 13:16:41,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201485 states, 201485 states have (on average 1.5260788644315955) internal successors, (307482), 201484 states have internal predecessors, (307482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:41,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201485 states to 201485 states and 307482 transitions. [2024-11-13 13:16:41,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201485 states and 307482 transitions. [2024-11-13 13:16:41,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:16:41,597 INFO L424 stractBuchiCegarLoop]: Abstraction has 201485 states and 307482 transitions. [2024-11-13 13:16:41,597 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 13:16:41,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201485 states and 307482 transitions. [2024-11-13 13:16:42,313 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 174628 [2024-11-13 13:16:42,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:42,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:42,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:42,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:42,314 INFO L745 eck$LassoCheckResult]: Stem: 1072204#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1072205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1072009#L256 assume !(1 == ~main_in1_req_up~0); 1071960#L256-2 assume !(1 == ~main_in2_req_up~0); 1071962#L267-1 assume !(1 == ~main_sum_req_up~0); 1071995#L278-1 assume !(1 == ~main_diff_req_up~0); 1071943#L289-1 assume !(1 == ~main_pres_req_up~0); 1071944#L300-1 assume !(1 == ~main_dbl_req_up~0); 1072429#L311-1 assume !(1 == ~main_zero_req_up~0); 1097813#L322-1 assume !(1 == ~main_clk_req_up~0); 1098603#L333-1 assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0; 1098600#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1098601#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1098609#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1098605#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1098602#L371-1 assume !(0 == ~main_in1_ev~0); 1098599#L376-1 assume !(0 == ~main_in2_ev~0); 1098597#L381-1 assume !(0 == ~main_sum_ev~0); 1098594#L386-1 assume !(0 == ~main_diff_ev~0); 1098591#L391-1 assume !(0 == ~main_pres_ev~0); 1098589#L396-1 assume !(0 == ~main_dbl_ev~0); 1098587#L401-1 assume !(0 == ~main_zero_ev~0); 1098585#L406-1 assume !(0 == ~main_clk_ev~0); 1098583#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1098581#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1098579#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1098577#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1098575#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1098573#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1098571#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1098569#L446-1 assume !(1 == ~main_in1_ev~0); 1098567#L451-1 assume !(1 == ~main_in2_ev~0); 1098565#L456-1 assume !(1 == ~main_sum_ev~0); 1098563#L461-1 assume !(1 == ~main_diff_ev~0); 1098561#L466-1 assume !(1 == ~main_pres_ev~0); 1098559#L471-1 assume !(1 == ~main_dbl_ev~0); 1098557#L476-1 assume !(1 == ~main_zero_ev~0); 1098555#L481-1 assume !(1 == ~main_clk_ev~0); 1098553#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1098551#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1098549#L742-1 assume !false; 1098545#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1098543#L229 [2024-11-13 13:16:42,314 INFO L747 eck$LassoCheckResult]: Loop: 1098543#L229 assume !false; 1098539#L147 assume 0 == ~N_generate_st~0; 1098535#L160-1 assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1; 1098531#L173 assume !(0 != eval_~tmp~0#1); 1098502#L169 assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1098495#L188 assume !(0 != eval_~tmp___0~0#1); 1098496#L184 assume !(0 == ~S2_presdbl_st~0); 1098616#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1098617#L218 assume !(0 != eval_~tmp___2~0#1); 1098523#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1098524#L233 assume !(0 != eval_~tmp___3~0#1); 1098543#L229 [2024-11-13 13:16:42,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:42,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1897430681, now seen corresponding path program 1 times [2024-11-13 13:16:42,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:42,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25172253] [2024-11-13 13:16:42,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:42,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:42,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:42,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:42,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:42,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25172253] [2024-11-13 13:16:42,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25172253] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:42,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:42,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:42,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25894388] [2024-11-13 13:16:42,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:42,398 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:42,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:42,399 INFO L85 PathProgramCache]: Analyzing trace with hash -1749393548, now seen corresponding path program 1 times [2024-11-13 13:16:42,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:42,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040278178] [2024-11-13 13:16:42,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:42,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:42,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:42,405 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:42,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:42,410 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:42,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:42,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:42,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:42,512 INFO L87 Difference]: Start difference. First operand 201485 states and 307482 transitions. cyclomatic complexity: 106221 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:43,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:43,839 INFO L93 Difference]: Finished difference Result 125864 states and 190714 transitions. [2024-11-13 13:16:43,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125864 states and 190714 transitions. [2024-11-13 13:16:44,367 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 108282 [2024-11-13 13:16:44,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125864 states to 125864 states and 190714 transitions. [2024-11-13 13:16:44,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125864 [2024-11-13 13:16:44,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125864 [2024-11-13 13:16:44,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125864 states and 190714 transitions. [2024-11-13 13:16:44,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:44,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125864 states and 190714 transitions. [2024-11-13 13:16:44,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125864 states and 190714 transitions. [2024-11-13 13:16:46,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125864 to 125864. [2024-11-13 13:16:46,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125864 states, 125864 states have (on average 1.5152386703108116) internal successors, (190714), 125863 states have internal predecessors, (190714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:47,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125864 states to 125864 states and 190714 transitions. [2024-11-13 13:16:47,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125864 states and 190714 transitions. [2024-11-13 13:16:47,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:47,362 INFO L424 stractBuchiCegarLoop]: Abstraction has 125864 states and 190714 transitions. [2024-11-13 13:16:47,363 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 13:16:47,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125864 states and 190714 transitions. [2024-11-13 13:16:47,632 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 108282 [2024-11-13 13:16:47,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:47,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:47,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:47,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:47,633 INFO L745 eck$LassoCheckResult]: Stem: 1399559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1399560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1399367#L256 assume !(1 == ~main_in1_req_up~0); 1399319#L256-2 assume !(1 == ~main_in2_req_up~0); 1399321#L267-1 assume !(1 == ~main_sum_req_up~0); 1399354#L278-1 assume !(1 == ~main_diff_req_up~0); 1399302#L289-1 assume !(1 == ~main_pres_req_up~0); 1399303#L300-1 assume !(1 == ~main_dbl_req_up~0); 1399419#L311-1 assume !(1 == ~main_zero_req_up~0); 1399601#L322-1 assume !(1 == ~main_clk_req_up~0); 1399898#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1431154#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1431155#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1431274#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1431275#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1431309#L371-1 assume !(0 == ~main_in1_ev~0); 1431305#L376-1 assume !(0 == ~main_in2_ev~0); 1431300#L381-1 assume !(0 == ~main_sum_ev~0); 1431295#L386-1 assume !(0 == ~main_diff_ev~0); 1431290#L391-1 assume !(0 == ~main_pres_ev~0); 1431285#L396-1 assume !(0 == ~main_dbl_ev~0); 1431280#L401-1 assume !(0 == ~main_zero_ev~0); 1431273#L406-1 assume !(0 == ~main_clk_ev~0); 1431266#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1431260#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1431254#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1431248#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1431242#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1431236#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1431230#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1431224#L446-1 assume !(1 == ~main_in1_ev~0); 1431218#L451-1 assume !(1 == ~main_in2_ev~0); 1431212#L456-1 assume !(1 == ~main_sum_ev~0); 1431206#L461-1 assume !(1 == ~main_diff_ev~0); 1431200#L466-1 assume !(1 == ~main_pres_ev~0); 1431194#L471-1 assume !(1 == ~main_dbl_ev~0); 1431188#L476-1 assume !(1 == ~main_zero_ev~0); 1431182#L481-1 assume !(1 == ~main_clk_ev~0); 1431176#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1431163#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1431158#L742-1 assume !false; 1431090#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1431085#L229 [2024-11-13 13:16:47,633 INFO L747 eck$LassoCheckResult]: Loop: 1431085#L229 assume !false; 1431078#L147 assume !(0 == ~N_generate_st~0); 1431071#L151 assume 0 == ~S1_addsub_st~0; 1431065#L160-1 assume !(0 == ~N_generate_st~0); 1431059#L169 assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1431054#L188 assume !(0 != eval_~tmp___0~0#1); 1431047#L184 assume !(0 == ~S2_presdbl_st~0); 1431035#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1431011#L218 assume !(0 != eval_~tmp___2~0#1); 1431013#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1431082#L233 assume !(0 != eval_~tmp___3~0#1); 1431085#L229 [2024-11-13 13:16:47,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:47,633 INFO L85 PathProgramCache]: Analyzing trace with hash -2122777001, now seen corresponding path program 1 times [2024-11-13 13:16:47,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:47,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296675188] [2024-11-13 13:16:47,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:47,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:47,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:47,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:47,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:47,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296675188] [2024-11-13 13:16:47,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296675188] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:47,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:47,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:47,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368716143] [2024-11-13 13:16:47,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:47,683 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:47,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:47,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1907118790, now seen corresponding path program 1 times [2024-11-13 13:16:47,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:47,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847013334] [2024-11-13 13:16:47,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:47,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:47,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:47,690 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:47,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:47,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:47,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:47,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:47,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:47,737 INFO L87 Difference]: Start difference. First operand 125864 states and 190714 transitions. cyclomatic complexity: 64946 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:48,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:48,120 INFO L93 Difference]: Finished difference Result 94440 states and 142170 transitions. [2024-11-13 13:16:48,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94440 states and 142170 transitions. [2024-11-13 13:16:48,594 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82434 [2024-11-13 13:16:49,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94440 states to 94440 states and 142170 transitions. [2024-11-13 13:16:49,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94440 [2024-11-13 13:16:49,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94440 [2024-11-13 13:16:49,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94440 states and 142170 transitions. [2024-11-13 13:16:49,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:49,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 94440 states and 142170 transitions. [2024-11-13 13:16:49,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94440 states and 142170 transitions. [2024-11-13 13:16:50,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94440 to 94440. [2024-11-13 13:16:50,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94440 states, 94440 states have (on average 1.505400254129606) internal successors, (142170), 94439 states have internal predecessors, (142170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:50,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94440 states to 94440 states and 142170 transitions. [2024-11-13 13:16:50,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94440 states and 142170 transitions. [2024-11-13 13:16:50,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:50,908 INFO L424 stractBuchiCegarLoop]: Abstraction has 94440 states and 142170 transitions. [2024-11-13 13:16:50,908 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 13:16:50,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94440 states and 142170 transitions. [2024-11-13 13:16:51,710 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82434 [2024-11-13 13:16:51,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:51,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:51,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:51,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:51,711 INFO L745 eck$LassoCheckResult]: Stem: 1619870#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1619871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1619682#L256 assume !(1 == ~main_in1_req_up~0); 1619633#L256-2 assume !(1 == ~main_in2_req_up~0); 1619635#L267-1 assume !(1 == ~main_sum_req_up~0); 1619668#L278-1 assume !(1 == ~main_diff_req_up~0); 1619616#L289-1 assume !(1 == ~main_pres_req_up~0); 1619617#L300-1 assume !(1 == ~main_dbl_req_up~0); 1620097#L311-1 assume !(1 == ~main_zero_req_up~0); 1641772#L322-1 assume !(1 == ~main_clk_req_up~0); 1642319#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1642315#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1642311#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1642306#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1642301#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1642302#L371-1 assume !(0 == ~main_in1_ev~0); 1642335#L376-1 assume !(0 == ~main_in2_ev~0); 1642332#L381-1 assume !(0 == ~main_sum_ev~0); 1642329#L386-1 assume !(0 == ~main_diff_ev~0); 1642325#L391-1 assume !(0 == ~main_pres_ev~0); 1642320#L396-1 assume !(0 == ~main_dbl_ev~0); 1642316#L401-1 assume !(0 == ~main_zero_ev~0); 1642312#L406-1 assume !(0 == ~main_clk_ev~0); 1642308#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1642303#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1642298#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1642294#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1642290#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1642286#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1642282#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1642278#L446-1 assume !(1 == ~main_in1_ev~0); 1642274#L451-1 assume !(1 == ~main_in2_ev~0); 1642270#L456-1 assume !(1 == ~main_sum_ev~0); 1642266#L461-1 assume !(1 == ~main_diff_ev~0); 1642262#L466-1 assume !(1 == ~main_pres_ev~0); 1642258#L471-1 assume !(1 == ~main_dbl_ev~0); 1642254#L476-1 assume !(1 == ~main_zero_ev~0); 1642250#L481-1 assume !(1 == ~main_clk_ev~0); 1642246#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1642239#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1642236#L742-1 assume !false; 1642234#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1642008#L229 [2024-11-13 13:16:51,711 INFO L747 eck$LassoCheckResult]: Loop: 1642008#L229 assume !false; 1642231#L147 assume !(0 == ~N_generate_st~0); 1636933#L151 assume !(0 == ~S1_addsub_st~0); 1636934#L154 assume !(0 == ~S2_presdbl_st~0); 1642225#L157 assume 0 == ~S3_zero_st~0; 1642223#L160-1 assume !(0 == ~N_generate_st~0); 1642220#L169 assume !(0 == ~S1_addsub_st~0); 1642217#L184 assume !(0 == ~S2_presdbl_st~0); 1642214#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1642212#L218 assume !(0 != eval_~tmp___2~0#1); 1642208#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1642007#L233 assume !(0 != eval_~tmp___3~0#1); 1642008#L229 [2024-11-13 13:16:51,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:51,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1421177127, now seen corresponding path program 1 times [2024-11-13 13:16:51,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:51,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392136326] [2024-11-13 13:16:51,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:51,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:51,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:51,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:51,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:51,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392136326] [2024-11-13 13:16:51,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392136326] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:51,798 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:51,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:51,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992512018] [2024-11-13 13:16:51,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:51,798 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:51,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:51,799 INFO L85 PathProgramCache]: Analyzing trace with hash -1152841795, now seen corresponding path program 1 times [2024-11-13 13:16:51,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:51,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477830896] [2024-11-13 13:16:51,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:51,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:51,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:51,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:51,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:51,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:51,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:51,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:51,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:51,860 INFO L87 Difference]: Start difference. First operand 94440 states and 142170 transitions. cyclomatic complexity: 47794 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:52,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:52,190 INFO L93 Difference]: Finished difference Result 72384 states and 108602 transitions. [2024-11-13 13:16:52,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72384 states and 108602 transitions. [2024-11-13 13:16:52,428 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 64452 [2024-11-13 13:16:52,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72384 states to 72384 states and 108602 transitions. [2024-11-13 13:16:52,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72384 [2024-11-13 13:16:52,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72384 [2024-11-13 13:16:52,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72384 states and 108602 transitions. [2024-11-13 13:16:52,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:52,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72384 states and 108602 transitions. [2024-11-13 13:16:52,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72384 states and 108602 transitions. [2024-11-13 13:16:53,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72384 to 72384. [2024-11-13 13:16:53,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72384 states, 72384 states have (on average 1.5003591954022988) internal successors, (108602), 72383 states have internal predecessors, (108602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:54,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72384 states to 72384 states and 108602 transitions. [2024-11-13 13:16:54,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72384 states and 108602 transitions. [2024-11-13 13:16:54,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:54,013 INFO L424 stractBuchiCegarLoop]: Abstraction has 72384 states and 108602 transitions. [2024-11-13 13:16:54,013 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 13:16:54,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72384 states and 108602 transitions. [2024-11-13 13:16:54,206 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 64452 [2024-11-13 13:16:54,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:54,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:54,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:54,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:54,207 INFO L745 eck$LassoCheckResult]: Stem: 1786703#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1786704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1786516#L256 assume !(1 == ~main_in1_req_up~0); 1786467#L256-2 assume !(1 == ~main_in2_req_up~0); 1786469#L267-1 assume !(1 == ~main_sum_req_up~0); 1786502#L278-1 assume !(1 == ~main_diff_req_up~0); 1786450#L289-1 assume !(1 == ~main_pres_req_up~0); 1786451#L300-1 assume !(1 == ~main_dbl_req_up~0); 1786749#L311-1 assume !(1 == ~main_zero_req_up~0); 1786746#L322-1 assume !(1 == ~main_clk_req_up~0); 1787043#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1805291#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1805290#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1805289#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1805288#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1805287#L371-1 assume !(0 == ~main_in1_ev~0); 1805285#L376-1 assume !(0 == ~main_in2_ev~0); 1805283#L381-1 assume !(0 == ~main_sum_ev~0); 1805281#L386-1 assume !(0 == ~main_diff_ev~0); 1805279#L391-1 assume !(0 == ~main_pres_ev~0); 1805277#L396-1 assume !(0 == ~main_dbl_ev~0); 1805275#L401-1 assume !(0 == ~main_zero_ev~0); 1805273#L406-1 assume !(0 == ~main_clk_ev~0); 1805271#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1805269#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1805267#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1805265#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1805263#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1805261#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1805259#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1805257#L446-1 assume !(1 == ~main_in1_ev~0); 1805255#L451-1 assume !(1 == ~main_in2_ev~0); 1805253#L456-1 assume !(1 == ~main_sum_ev~0); 1805251#L461-1 assume !(1 == ~main_diff_ev~0); 1805249#L466-1 assume !(1 == ~main_pres_ev~0); 1805247#L471-1 assume !(1 == ~main_dbl_ev~0); 1805245#L476-1 assume !(1 == ~main_zero_ev~0); 1805243#L481-1 assume !(1 == ~main_clk_ev~0); 1805241#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1805239#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1805237#L742-1 assume !false; 1805235#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1805224#L229 [2024-11-13 13:16:54,207 INFO L747 eck$LassoCheckResult]: Loop: 1805224#L229 assume !false; 1805225#L147 assume !(0 == ~N_generate_st~0); 1805220#L151 assume !(0 == ~S1_addsub_st~0); 1805221#L154 assume !(0 == ~S2_presdbl_st~0); 1805216#L157 assume !(0 == ~S3_zero_st~0); 1805217#L160 assume 0 == ~D_print_st~0; 1805234#L160-1 assume !(0 == ~N_generate_st~0); 1805233#L169 assume !(0 == ~S1_addsub_st~0); 1805232#L184 assume !(0 == ~S2_presdbl_st~0); 1805231#L199 assume !(0 == ~S3_zero_st~0); 1805229#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1805228#L233 assume !(0 != eval_~tmp___3~0#1); 1805224#L229 [2024-11-13 13:16:54,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:54,208 INFO L85 PathProgramCache]: Analyzing trace with hash -34973733, now seen corresponding path program 1 times [2024-11-13 13:16:54,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:54,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601783437] [2024-11-13 13:16:54,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:54,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:54,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:54,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:54,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:54,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601783437] [2024-11-13 13:16:54,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1601783437] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:54,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:54,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:54,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679585620] [2024-11-13 13:16:54,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:54,270 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:54,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:54,271 INFO L85 PathProgramCache]: Analyzing trace with hash 603768178, now seen corresponding path program 1 times [2024-11-13 13:16:54,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:54,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913819193] [2024-11-13 13:16:54,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:54,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:54,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:54,277 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:16:54,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:16:54,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:16:54,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:54,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:54,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:54,326 INFO L87 Difference]: Start difference. First operand 72384 states and 108602 transitions. cyclomatic complexity: 36266 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:54,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:54,597 INFO L93 Difference]: Finished difference Result 59330 states and 88531 transitions. [2024-11-13 13:16:54,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59330 states and 88531 transitions. [2024-11-13 13:16:54,778 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 53852 [2024-11-13 13:16:54,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59330 states to 59330 states and 88531 transitions. [2024-11-13 13:16:54,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59330 [2024-11-13 13:16:54,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59330 [2024-11-13 13:16:54,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59330 states and 88531 transitions. [2024-11-13 13:16:54,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:54,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59330 states and 88531 transitions. [2024-11-13 13:16:54,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59330 states and 88531 transitions. [2024-11-13 13:16:56,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59330 to 59330. [2024-11-13 13:16:56,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59330 states, 59330 states have (on average 1.4921793359177482) internal successors, (88531), 59329 states have internal predecessors, (88531), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:56,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59330 states to 59330 states and 88531 transitions. [2024-11-13 13:16:56,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59330 states and 88531 transitions. [2024-11-13 13:16:56,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:56,170 INFO L424 stractBuchiCegarLoop]: Abstraction has 59330 states and 88531 transitions. [2024-11-13 13:16:56,170 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 13:16:56,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59330 states and 88531 transitions. [2024-11-13 13:16:56,329 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 53852 [2024-11-13 13:16:56,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:56,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:56,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:56,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:56,330 INFO L745 eck$LassoCheckResult]: Stem: 1918427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1918428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1918239#L256 assume !(1 == ~main_in1_req_up~0); 1918191#L256-2 assume !(1 == ~main_in2_req_up~0); 1918193#L267-1 assume !(1 == ~main_sum_req_up~0); 1918225#L278-1 assume !(1 == ~main_diff_req_up~0); 1918174#L289-1 assume !(1 == ~main_pres_req_up~0); 1918175#L300-1 assume !(1 == ~main_dbl_req_up~0); 1918287#L311-1 assume !(1 == ~main_zero_req_up~0); 1923853#L322-1 assume 1 == ~main_clk_req_up~0; 1923833#L334 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 1923830#L337 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 1923829#L334-1 ~main_clk_req_up~0 := 0; 1923825#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1923812#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1923811#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1923806#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1923802#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1923800#L371-1 assume !(0 == ~main_in1_ev~0); 1923798#L376-1 assume !(0 == ~main_in2_ev~0); 1923796#L381-1 assume !(0 == ~main_sum_ev~0); 1923795#L386-1 assume !(0 == ~main_diff_ev~0); 1923792#L391-1 assume !(0 == ~main_pres_ev~0); 1923790#L396-1 assume !(0 == ~main_dbl_ev~0); 1923788#L401-1 assume !(0 == ~main_zero_ev~0); 1923785#L406-1 assume !(0 == ~main_clk_ev~0); 1923782#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 1923779#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1923775#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1923771#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1923767#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1923763#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1923764#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1924152#L446-1 assume !(1 == ~main_in1_ev~0); 1924150#L451-1 assume !(1 == ~main_in2_ev~0); 1924148#L456-1 assume !(1 == ~main_sum_ev~0); 1924147#L461-1 assume !(1 == ~main_diff_ev~0); 1924145#L466-1 assume !(1 == ~main_pres_ev~0); 1924142#L471-1 assume !(1 == ~main_dbl_ev~0); 1924139#L476-1 assume !(1 == ~main_zero_ev~0); 1924137#L481-1 assume !(1 == ~main_clk_ev~0); 1924135#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1924115#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1924114#L742-1 [2024-11-13 13:16:56,331 INFO L747 eck$LassoCheckResult]: Loop: 1924114#L742-1 assume !false; 1924112#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1923742#L229 assume !false; 1924101#L147 assume !(0 == ~N_generate_st~0); 1924102#L151 assume !(0 == ~S1_addsub_st~0); 1924289#L154 assume !(0 == ~S2_presdbl_st~0); 1924290#L157 assume !(0 == ~S3_zero_st~0); 1924421#L160 assume !(0 == ~D_print_st~0); 1924427#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1928442#L509 assume !(1 == ~main_in1_req_up~0); 1928440#L509-2 assume !(1 == ~main_in2_req_up~0); 1928385#L520-1 assume !(1 == ~main_sum_req_up~0); 1921424#L531-1 assume !(1 == ~main_diff_req_up~0); 1921420#L542-1 assume !(1 == ~main_pres_req_up~0); 1921422#L553-1 assume !(1 == ~main_dbl_req_up~0); 1923873#L564-1 assume !(1 == ~main_zero_req_up~0); 1923870#L575-1 assume 1 == ~main_clk_req_up~0; 1923822#L587 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 1923818#L590 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 1923816#L587-1 ~main_clk_req_up~0 := 0; 1923814#L586-1 start_simulation_~kernel_st~0#1 := 3; 1923807#L605 assume !(0 == ~main_in1_ev~0); 1923805#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 1923801#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 1923799#L615-1 assume !(0 == ~main_diff_ev~0); 1923797#L620-1 assume !(0 == ~main_pres_ev~0); 1923793#L625-1 assume !(0 == ~main_dbl_ev~0); 1923791#L630-1 assume !(0 == ~main_zero_ev~0); 1923789#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1923786#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 1923784#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1923780#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1923777#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1923773#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1923769#L665-1 assume !(1 == ~main_clk_pos_edge~0); 1923770#L670-1 assume !(1 == ~main_clk_pos_edge~0); 1924156#L675-1 assume !(1 == ~main_in1_ev~0); 1924155#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 1924154#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1924153#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1924151#L695-1 assume !(1 == ~main_pres_ev~0); 1924149#L700-1 assume !(1 == ~main_dbl_ev~0); 1924141#L705-1 assume !(1 == ~main_zero_ev~0); 1924140#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1924121#L715-1 assume !(1 == ~main_clk_pos_edge~0); 1924119#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 1924116#L725-1 assume 0 == ~N_generate_st~0; 1924114#L742-1 [2024-11-13 13:16:56,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:56,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1830128562, now seen corresponding path program 1 times [2024-11-13 13:16:56,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:56,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68620214] [2024-11-13 13:16:56,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:56,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:56,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:56,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:56,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:56,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68620214] [2024-11-13 13:16:56,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68620214] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:56,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:56,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:56,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727479350] [2024-11-13 13:16:56,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:56,392 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:56,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:56,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1657163444, now seen corresponding path program 1 times [2024-11-13 13:16:56,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:56,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761794950] [2024-11-13 13:16:56,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:56,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:56,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:56,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:56,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:56,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761794950] [2024-11-13 13:16:56,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761794950] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:56,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:56,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:56,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743983384] [2024-11-13 13:16:56,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:56,453 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:56,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:56,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:56,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:56,453 INFO L87 Difference]: Start difference. First operand 59330 states and 88531 transitions. cyclomatic complexity: 29241 Second operand has 4 states, 4 states have (on average 10.75) internal successors, (43), 4 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:56,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:56,667 INFO L93 Difference]: Finished difference Result 35444 states and 52013 transitions. [2024-11-13 13:16:56,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35444 states and 52013 transitions. [2024-11-13 13:16:56,820 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33884 [2024-11-13 13:16:56,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35444 states to 35444 states and 52013 transitions. [2024-11-13 13:16:56,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35444 [2024-11-13 13:16:56,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35444 [2024-11-13 13:16:56,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35444 states and 52013 transitions. [2024-11-13 13:16:56,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:56,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35444 states and 52013 transitions. [2024-11-13 13:16:57,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35444 states and 52013 transitions. [2024-11-13 13:16:57,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35444 to 35428. [2024-11-13 13:16:58,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35428 states, 35428 states have (on average 1.4676809303375862) internal successors, (51997), 35427 states have internal predecessors, (51997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:58,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35428 states to 35428 states and 51997 transitions. [2024-11-13 13:16:58,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35428 states and 51997 transitions. [2024-11-13 13:16:58,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:16:58,097 INFO L424 stractBuchiCegarLoop]: Abstraction has 35428 states and 51997 transitions. [2024-11-13 13:16:58,097 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 13:16:58,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35428 states and 51997 transitions. [2024-11-13 13:16:58,223 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 33884 [2024-11-13 13:16:58,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:16:58,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:16:58,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:58,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:16:58,225 INFO L745 eck$LassoCheckResult]: Stem: 2013195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2013196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2013013#L256 assume !(1 == ~main_in1_req_up~0); 2012974#L256-2 assume !(1 == ~main_in2_req_up~0); 2012976#L267-1 assume !(1 == ~main_sum_req_up~0); 2013002#L278-1 assume !(1 == ~main_diff_req_up~0); 2012959#L289-1 assume !(1 == ~main_pres_req_up~0); 2012960#L300-1 assume !(1 == ~main_dbl_req_up~0); 2013056#L311-1 assume !(1 == ~main_zero_req_up~0); 2013500#L322-1 assume !(1 == ~main_clk_req_up~0); 2013501#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2014052#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2012993#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2012994#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2013181#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2014050#L371-1 assume !(0 == ~main_in1_ev~0); 2013038#L376-1 assume !(0 == ~main_in2_ev~0); 2013039#L381-1 assume !(0 == ~main_sum_ev~0); 2014049#L386-1 assume !(0 == ~main_diff_ev~0); 2013495#L391-1 assume !(0 == ~main_pres_ev~0); 2013496#L396-1 assume !(0 == ~main_dbl_ev~0); 2021167#L401-1 assume !(0 == ~main_zero_ev~0); 2021165#L406-1 assume !(0 == ~main_clk_ev~0); 2021163#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2021161#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2021124#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2021094#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2021086#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2021080#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2021074#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2021072#L446-1 assume !(1 == ~main_in1_ev~0); 2021070#L451-1 assume !(1 == ~main_in2_ev~0); 2021066#L456-1 assume !(1 == ~main_sum_ev~0); 2021057#L461-1 assume !(1 == ~main_diff_ev~0); 2021049#L466-1 assume !(1 == ~main_pres_ev~0); 2021045#L471-1 assume !(1 == ~main_dbl_ev~0); 2021041#L476-1 assume !(1 == ~main_zero_ev~0); 2021020#L481-1 assume !(1 == ~main_clk_ev~0); 2021019#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2021018#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2021017#L742-1 assume !false; 2021016#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2021015#L229 assume !false; 2021014#L147 assume !(0 == ~N_generate_st~0); 2021013#L151 assume !(0 == ~S1_addsub_st~0); 2021012#L154 assume !(0 == ~S2_presdbl_st~0); 2021011#L157 assume !(0 == ~S3_zero_st~0); 2021010#L160 assume !(0 == ~D_print_st~0); 2021009#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2021008#L509 assume !(1 == ~main_in1_req_up~0); 2021006#L509-2 assume !(1 == ~main_in2_req_up~0); 2021002#L520-1 assume !(1 == ~main_sum_req_up~0); 2020999#L531-1 assume !(1 == ~main_diff_req_up~0); 2020996#L542-1 assume !(1 == ~main_pres_req_up~0); 2020994#L553-1 assume !(1 == ~main_dbl_req_up~0); 2020993#L564-1 assume !(1 == ~main_zero_req_up~0); 2020992#L575-1 assume !(1 == ~main_clk_req_up~0); 2020990#L586-1 start_simulation_~kernel_st~0#1 := 3; 2020988#L605 assume !(0 == ~main_in1_ev~0); 2020986#L605-2 assume !(0 == ~main_in2_ev~0); 2020984#L610-1 assume !(0 == ~main_sum_ev~0); 2020982#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2020980#L620-1 assume !(0 == ~main_pres_ev~0); 2020978#L625-1 assume !(0 == ~main_dbl_ev~0); 2020976#L630-1 assume !(0 == ~main_zero_ev~0); 2020974#L635-1 assume !(0 == ~main_clk_ev~0); 2020972#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2020970#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2020968#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2020966#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2020964#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2020962#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2020960#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2020958#L675-1 assume !(1 == ~main_in1_ev~0); 2020956#L680-1 assume !(1 == ~main_in2_ev~0); 2020954#L685-1 assume !(1 == ~main_sum_ev~0); 2020952#L690-1 assume !(1 == ~main_diff_ev~0); 2020950#L695-1 assume !(1 == ~main_pres_ev~0); 2020948#L700-1 assume !(1 == ~main_dbl_ev~0); 2020946#L705-1 assume !(1 == ~main_zero_ev~0); 2020944#L710-1 assume !(1 == ~main_clk_ev~0); 2020942#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2020940#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2020938#L725-1 assume !(0 == ~N_generate_st~0); 2020936#L733 assume !(0 == ~S1_addsub_st~0); 2020934#L736 assume !(0 == ~S2_presdbl_st~0); 2020932#L739 assume !(0 == ~S3_zero_st~0); 2020930#L742 assume !(0 == ~D_print_st~0); 2020929#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2020927#L795-2 [2024-11-13 13:16:58,227 INFO L747 eck$LassoCheckResult]: Loop: 2020927#L795-2 assume !false; 2019846#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2019844#L256-3 assume !(1 == ~main_in1_req_up~0); 2019812#L256-5 assume !(1 == ~main_in2_req_up~0); 2019808#L267-3 assume !(1 == ~main_sum_req_up~0); 2019804#L278-3 assume !(1 == ~main_diff_req_up~0); 2019800#L289-3 assume !(1 == ~main_pres_req_up~0); 2019761#L300-3 assume !(1 == ~main_dbl_req_up~0); 2019762#L311-3 assume !(1 == ~main_zero_req_up~0); 2021064#L322-3 assume !(1 == ~main_clk_req_up~0); 2021056#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2021048#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2021044#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2021040#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2021037#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2021034#L371-3 assume !(0 == ~main_in1_ev~0); 2020731#L376-3 assume !(0 == ~main_in2_ev~0); 2020728#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2020725#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2020722#L391-3 assume !(0 == ~main_pres_ev~0); 2020719#L396-3 assume !(0 == ~main_dbl_ev~0); 2020716#L401-3 assume !(0 == ~main_zero_ev~0); 2020713#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2020710#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2020707#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2020704#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2020701#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2020698#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2020695#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2020692#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2020689#L446-3 assume !(1 == ~main_in1_ev~0); 2020686#L451-3 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 2020683#L456-3 assume !(1 == ~main_sum_ev~0); 2020680#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2020677#L466-3 assume !(1 == ~main_pres_ev~0); 2020674#L471-3 assume !(1 == ~main_dbl_ev~0); 2020671#L476-3 assume !(1 == ~main_zero_ev~0); 2020668#L481-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2020665#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2020663#L491-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2020661#L742-3 assume !false; 2020659#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2020657#L229-1 assume !false; 2020655#L147-1 assume !(0 == ~N_generate_st~0); 2020653#L151-2 assume !(0 == ~S1_addsub_st~0); 2020651#L154-2 assume !(0 == ~S2_presdbl_st~0); 2020649#L157-2 assume !(0 == ~S3_zero_st~0); 2020647#L160-2 assume !(0 == ~D_print_st~0); 2020645#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2020643#L509-3 assume !(1 == ~main_in1_req_up~0); 2020640#L509-5 assume !(1 == ~main_in2_req_up~0); 2020636#L520-3 assume !(1 == ~main_sum_req_up~0); 2020630#L531-3 assume !(1 == ~main_diff_req_up~0); 2020623#L542-3 assume !(1 == ~main_pres_req_up~0); 2020615#L553-3 assume !(1 == ~main_dbl_req_up~0); 2020609#L564-3 assume !(1 == ~main_zero_req_up~0); 2020603#L575-3 assume !(1 == ~main_clk_req_up~0); 2020598#L586-3 start_simulation_~kernel_st~0#1 := 3; 2020595#L605-3 assume !(0 == ~main_in1_ev~0); 2020592#L605-5 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2020589#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2020586#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2020583#L620-3 assume !(0 == ~main_pres_ev~0); 2020580#L625-3 assume !(0 == ~main_dbl_ev~0); 2020577#L630-3 assume !(0 == ~main_zero_ev~0); 2020574#L635-3 assume !(0 == ~main_clk_ev~0); 2020571#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2020568#L645-3 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2020565#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2020562#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2020559#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2020556#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2020553#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2020550#L675-3 assume !(1 == ~main_in1_ev~0); 2020547#L680-3 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 2020544#L685-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2020541#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2020538#L695-3 assume !(1 == ~main_pres_ev~0); 2020535#L700-3 assume !(1 == ~main_dbl_ev~0); 2020532#L705-3 assume !(1 == ~main_zero_ev~0); 2020529#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2020526#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2020524#L720-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2020522#L725-3 assume !(0 == ~N_generate_st~0); 2020520#L733-2 assume !(0 == ~S1_addsub_st~0); 2020518#L736-2 assume !(0 == ~S2_presdbl_st~0); 2020516#L739-2 assume !(0 == ~S3_zero_st~0); 2020514#L742-2 assume !(0 == ~D_print_st~0); 2020512#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2020509#L803 assume !(5 == main_~count~0#1); 2020506#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2020502#L256-6 assume !(1 == ~main_in1_req_up~0); 2020499#L256-8 assume !(1 == ~main_in2_req_up~0); 2020494#L267-5 assume !(1 == ~main_sum_req_up~0); 2020489#L278-5 assume !(1 == ~main_diff_req_up~0); 2020482#L289-5 assume !(1 == ~main_pres_req_up~0); 2020475#L300-5 assume !(1 == ~main_dbl_req_up~0); 2020468#L311-5 assume !(1 == ~main_zero_req_up~0); 2020469#L322-5 assume !(1 == ~main_clk_req_up~0); 2021109#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2021107#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2021092#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2021084#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2021078#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2020758#L371-5 assume !(0 == ~main_in1_ev~0); 2020756#L376-5 assume !(0 == ~main_in2_ev~0); 2020754#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2020753#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2020752#L391-5 assume !(0 == ~main_pres_ev~0); 2020750#L396-5 assume !(0 == ~main_dbl_ev~0); 2020748#L401-5 assume !(0 == ~main_zero_ev~0); 2020746#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2020743#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2020741#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2020388#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2020386#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2020384#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2020373#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2020372#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2020344#L446-5 assume !(1 == ~main_in1_ev~0); 2020342#L451-5 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 2020340#L456-5 assume !(1 == ~main_sum_ev~0); 2020323#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2020294#L466-5 assume !(1 == ~main_pres_ev~0); 2020277#L471-5 assume !(1 == ~main_dbl_ev~0); 2020266#L476-5 assume !(1 == ~main_zero_ev~0); 2020258#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2020250#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2020244#L491-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2020238#L742-5 assume !false; 2020232#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2020222#L229-2 assume !false; 2020220#L147-2 assume !(0 == ~N_generate_st~0); 2020218#L151-4 assume !(0 == ~S1_addsub_st~0); 2020216#L154-4 assume !(0 == ~S2_presdbl_st~0); 2020214#L157-4 assume !(0 == ~S3_zero_st~0); 2020193#L160-4 assume !(0 == ~D_print_st~0); 2020191#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2020190#L509-6 assume !(1 == ~main_in1_req_up~0); 2020188#L509-8 assume !(1 == ~main_in2_req_up~0); 2020137#L520-5 assume !(1 == ~main_sum_req_up~0); 2020134#L531-5 assume !(1 == ~main_diff_req_up~0); 2020130#L542-5 assume !(1 == ~main_pres_req_up~0); 2020125#L553-5 assume !(1 == ~main_dbl_req_up~0); 2020123#L564-5 assume !(1 == ~main_zero_req_up~0); 2020124#L575-5 assume !(1 == ~main_clk_req_up~0); 2020991#L586-5 start_simulation_~kernel_st~0#1 := 3; 2020989#L605-6 assume !(0 == ~main_in1_ev~0); 2020987#L605-8 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2020985#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2020983#L615-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2020981#L620-5 assume !(0 == ~main_pres_ev~0); 2020979#L625-5 assume !(0 == ~main_dbl_ev~0); 2020977#L630-5 assume !(0 == ~main_zero_ev~0); 2020975#L635-5 assume !(0 == ~main_clk_ev~0); 2020973#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2020971#L645-5 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2020969#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2020967#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2020965#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2020963#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2020961#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2020959#L675-5 assume !(1 == ~main_in1_ev~0); 2020957#L680-5 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 2020955#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2020953#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2020951#L695-5 assume !(1 == ~main_pres_ev~0); 2020949#L700-5 assume !(1 == ~main_dbl_ev~0); 2020947#L705-5 assume !(1 == ~main_zero_ev~0); 2020945#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2020943#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2020941#L720-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2020939#L725-5 assume !(0 == ~N_generate_st~0); 2020937#L733-4 assume !(0 == ~S1_addsub_st~0); 2020935#L736-4 assume !(0 == ~S2_presdbl_st~0); 2020933#L739-4 assume !(0 == ~S3_zero_st~0); 2020931#L742-4 assume !(0 == ~D_print_st~0); 2020928#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2020927#L795-2 [2024-11-13 13:16:58,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:58,227 INFO L85 PathProgramCache]: Analyzing trace with hash 2082688107, now seen corresponding path program 1 times [2024-11-13 13:16:58,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:58,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386857512] [2024-11-13 13:16:58,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:58,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:58,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:58,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:58,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:58,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386857512] [2024-11-13 13:16:58,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386857512] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:58,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:58,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:16:58,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295783526] [2024-11-13 13:16:58,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:58,333 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:16:58,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:16:58,334 INFO L85 PathProgramCache]: Analyzing trace with hash 517213362, now seen corresponding path program 1 times [2024-11-13 13:16:58,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:16:58,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059270352] [2024-11-13 13:16:58,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:16:58,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:16:58,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:16:58,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:16:58,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:16:58,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059270352] [2024-11-13 13:16:58,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059270352] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:16:58,417 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:16:58,417 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:16:58,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1842438780] [2024-11-13 13:16:58,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:16:58,418 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:16:58,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:16:58,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:16:58,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:16:58,419 INFO L87 Difference]: Start difference. First operand 35428 states and 51997 transitions. cyclomatic complexity: 16593 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:16:59,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:16:59,002 INFO L93 Difference]: Finished difference Result 75472 states and 109627 transitions. [2024-11-13 13:16:59,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75472 states and 109627 transitions. [2024-11-13 13:16:59,413 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 72092 [2024-11-13 13:16:59,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75472 states to 75472 states and 109627 transitions. [2024-11-13 13:16:59,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75472 [2024-11-13 13:16:59,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75472 [2024-11-13 13:16:59,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75472 states and 109627 transitions. [2024-11-13 13:16:59,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:16:59,763 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75472 states and 109627 transitions. [2024-11-13 13:16:59,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75472 states and 109627 transitions.