./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:07:24,763 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:07:24,849 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:07:24,859 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:07:24,859 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:07:24,899 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:07:24,900 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:07:24,900 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:07:24,901 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:07:24,901 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:07:24,903 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:07:24,903 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:07:24,903 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:07:24,904 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:07:24,904 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:07:24,904 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:07:24,904 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:07:24,904 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:07:24,904 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:07:24,905 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:07:24,905 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:07:24,906 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:07:24,906 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:07:24,906 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:07:24,906 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:07:24,906 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:07:24,906 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:07:24,907 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:07:24,907 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:07:24,907 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:07:24,907 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:07:24,908 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2024-11-13 15:07:25,226 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:07:25,234 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:07:25,237 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:07:25,238 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:07:25,238 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:07:25,239 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c Unable to find full path for "g++" [2024-11-13 15:07:27,104 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:07:27,463 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:07:27,464 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2024-11-13 15:07:27,490 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/data/ccbfc72bf/658ce61341d84131b248182e685ed516/FLAGebc744ed7 [2024-11-13 15:07:27,513 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/data/ccbfc72bf/658ce61341d84131b248182e685ed516 [2024-11-13 15:07:27,516 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:07:27,517 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:07:27,519 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:07:27,519 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:07:27,524 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:07:27,525 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:27,526 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60c8eefb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27, skipping insertion in model container [2024-11-13 15:07:27,526 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:27,556 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:07:27,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:07:27,814 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:07:27,867 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:07:27,886 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:07:27,886 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27 WrapperNode [2024-11-13 15:07:27,887 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:07:27,888 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:07:27,888 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:07:27,888 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:07:27,895 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:27,907 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:27,977 INFO L138 Inliner]: procedures = 34, calls = 42, calls flagged for inlining = 37, calls inlined = 65, statements flattened = 830 [2024-11-13 15:07:27,978 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:07:27,978 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:07:27,979 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:07:27,979 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:07:27,998 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:27,999 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,004 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,022 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:07:28,023 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,023 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,034 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,045 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,047 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,053 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,057 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:07:28,062 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:07:28,062 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:07:28,062 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:07:28,063 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (1/1) ... [2024-11-13 15:07:28,077 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:07:28,102 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:07:28,116 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:07:28,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:07:28,150 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:07:28,150 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:07:28,150 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:07:28,150 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:07:28,261 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:07:28,263 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:07:29,279 INFO L? ?]: Removed 148 outVars from TransFormulas that were not future-live. [2024-11-13 15:07:29,279 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:07:29,312 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:07:29,312 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-13 15:07:29,312 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:07:29 BoogieIcfgContainer [2024-11-13 15:07:29,313 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:07:29,313 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:07:29,313 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:07:29,319 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:07:29,320 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:07:29,320 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:07:27" (1/3) ... [2024-11-13 15:07:29,321 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c842e84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:07:29, skipping insertion in model container [2024-11-13 15:07:29,321 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:07:29,322 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:07:27" (2/3) ... [2024-11-13 15:07:29,322 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c842e84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:07:29, skipping insertion in model container [2024-11-13 15:07:29,322 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:07:29,322 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:07:29" (3/3) ... [2024-11-13 15:07:29,323 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2024-11-13 15:07:29,393 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:07:29,393 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:07:29,393 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:07:29,393 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:07:29,393 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:07:29,394 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:07:29,394 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:07:29,395 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:07:29,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:29,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2024-11-13 15:07:29,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:29,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:29,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,436 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:07:29,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:29,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2024-11-13 15:07:29,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:29,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:29,457 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,465 INFO L745 eck$LassoCheckResult]: Stem: 211#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 331#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 219#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 288#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 27#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 242#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 139#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L441true assume !(0 == ~M_E~0); 122#L441-2true assume !(0 == ~T1_E~0); 258#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 279#L456-1true assume !(0 == ~E_M~0); 234#L461-1true assume !(0 == ~E_1~0); 254#L466-1true assume !(0 == ~E_2~0); 303#L471-1true assume !(0 == ~E_3~0); 49#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 268#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 329#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207#L239true assume !(1 == ~t1_pc~0); 230#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 275#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212#L551true assume !(0 != activate_threads_~tmp___0~0#1); 333#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213#L258true assume 1 == ~t2_pc~0; 252#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228#L559true assume !(0 != activate_threads_~tmp___1~0#1); 131#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173#L277true assume !(1 == ~t3_pc~0); 330#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311#L489true assume !(1 == ~M_E~0); 231#L489-2true assume !(1 == ~T1_E~0); 151#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 125#L504-1true assume !(1 == ~E_M~0); 267#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 181#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2024-11-13 15:07:29,466 INFO L747 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192#L416-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 260#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 195#L451-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 35#L456-3true assume !(0 == ~E_M~0); 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 263#L471-3true assume 0 == ~E_3~0;~E_3~0 := 1; 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 162#L220-17true is_master_triggered_~__retres1~0#1 := 0; 210#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#is_master_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 224#L543-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123#L239-15true assume !(1 == ~t1_pc~0); 266#L239-17true is_transmit1_triggered_~__retres1~1#1 := 0; 286#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28#L551-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 321#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320#L258-15true assume 1 == ~t2_pc~0; 155#L259-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 283#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 338#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 237#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307#L277-15true assume !(1 == ~t3_pc~0); 14#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 332#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274#L567-15true assume !(0 != activate_threads_~tmp___2~0#1); 33#L567-17true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 225#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L499-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 108#L504-3true assume !(1 == ~E_M~0); 18#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 304#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 42#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 287#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 152#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 47#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2024-11-13 15:07:29,471 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:29,471 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2024-11-13 15:07:29,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:29,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281725571] [2024-11-13 15:07:29,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:29,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:29,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:29,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:29,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:29,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281725571] [2024-11-13 15:07:29,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281725571] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:29,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:29,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:29,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214567373] [2024-11-13 15:07:29,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:29,720 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:29,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:29,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1639802538, now seen corresponding path program 1 times [2024-11-13 15:07:29,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:29,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927450568] [2024-11-13 15:07:29,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:29,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:29,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:29,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:29,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:29,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927450568] [2024-11-13 15:07:29,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927450568] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:29,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:29,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:07:29,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654147837] [2024-11-13 15:07:29,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:29,764 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:29,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:29,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:29,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:29,794 INFO L87 Difference]: Start difference. First operand has 337 states, 336 states have (on average 1.5297619047619047) internal successors, (514), 336 states have internal predecessors, (514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:29,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:29,843 INFO L93 Difference]: Finished difference Result 333 states and 495 transitions. [2024-11-13 15:07:29,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333 states and 495 transitions. [2024-11-13 15:07:29,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:29,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333 states to 327 states and 489 transitions. [2024-11-13 15:07:29,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-13 15:07:29,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-13 15:07:29,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 489 transitions. [2024-11-13 15:07:29,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:29,877 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-13 15:07:29,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 489 transitions. [2024-11-13 15:07:29,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-13 15:07:29,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.4954128440366972) internal successors, (489), 326 states have internal predecessors, (489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:29,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 489 transitions. [2024-11-13 15:07:29,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-13 15:07:29,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:29,930 INFO L424 stractBuchiCegarLoop]: Abstraction has 327 states and 489 transitions. [2024-11-13 15:07:29,932 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:07:29,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 489 transitions. [2024-11-13 15:07:29,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:29,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:29,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:29,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:29,938 INFO L745 eck$LassoCheckResult]: Stem: 956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 969#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 968#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 887#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 737#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 738#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 906#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745#L441 assume !(0 == ~M_E~0); 746#L441-2 assume !(0 == ~T1_E~0); 883#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850#L451-1 assume !(0 == ~T3_E~0); 851#L456-1 assume !(0 == ~E_M~0); 973#L461-1 assume !(0 == ~E_1~0); 974#L466-1 assume !(0 == ~E_2~0); 984#L471-1 assume !(0 == ~E_3~0); 780#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 781#L220 assume 1 == ~m_pc~0; 840#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 813#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 808#L543 assume !(0 != activate_threads_~tmp~1#1); 809#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 955#L239 assume !(1 == ~t1_pc~0); 953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 954#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 776#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 959#L258 assume 1 == ~t2_pc~0; 960#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 837#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 971#L559 assume !(0 != activate_threads_~tmp___1~0#1); 895#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 896#L277 assume !(1 == ~t3_pc~0); 934#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 756#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713#L567 assume !(0 != activate_threads_~tmp___2~0#1); 804#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845#L489 assume !(1 == ~M_E~0); 972#L489-2 assume !(1 == ~T1_E~0); 917#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L499-1 assume !(1 == ~T3_E~0); 796#L504-1 assume !(1 == ~E_M~0); 888#L509-1 assume !(1 == ~E_1~0); 782#L514-1 assume !(1 == ~E_2~0); 783#L519-1 assume !(1 == ~E_3~0); 789#L524-1 assume { :end_inline_reset_delta_events } true; 754#L690-2 [2024-11-13 15:07:29,938 INFO L747 eck$LassoCheckResult]: Loop: 754#L690-2 assume !false; 755#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784#L416-1 assume !false; 818#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 819#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 763#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 714#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 715#L369 assume !(0 != eval_~tmp~0#1); 874#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 875#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 919#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 696#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 944#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 750#L456-3 assume !(0 == ~E_M~0); 751#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 817#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 921#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 806#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807#L220-15 assume 1 == ~m_pc~0; 701#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 702#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 865#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 866#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 894#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884#L239-15 assume 1 == ~t1_pc~0; 885#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 987#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 735#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 736#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005#L258-15 assume 1 == ~t2_pc~0; 918#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 847#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 996#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 976#L277-15 assume 1 == ~t3_pc~0; 816#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 708#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 980#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 981#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 747#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 739#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 740#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 937#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 863#L504-3 assume !(1 == ~E_M~0); 716#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 928#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 764#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 765#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 785#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 916#L709 assume !(0 == start_simulation_~tmp~3#1); 691#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 692#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 788#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 770#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 787#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 836#L722 assume !(0 != start_simulation_~tmp___0~1#1); 754#L690-2 [2024-11-13 15:07:29,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:29,939 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2024-11-13 15:07:29,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:29,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995135316] [2024-11-13 15:07:29,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:29,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:29,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995135316] [2024-11-13 15:07:30,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995135316] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29542502] [2024-11-13 15:07:30,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,065 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:30,065 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,065 INFO L85 PathProgramCache]: Analyzing trace with hash 386831266, now seen corresponding path program 1 times [2024-11-13 15:07:30,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790716247] [2024-11-13 15:07:30,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790716247] [2024-11-13 15:07:30,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790716247] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613897432] [2024-11-13 15:07:30,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,179 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:30,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:30,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:30,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:30,180 INFO L87 Difference]: Start difference. First operand 327 states and 489 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:30,210 INFO L93 Difference]: Finished difference Result 327 states and 488 transitions. [2024-11-13 15:07:30,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 488 transitions. [2024-11-13 15:07:30,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:30,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 488 transitions. [2024-11-13 15:07:30,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-13 15:07:30,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-13 15:07:30,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 488 transitions. [2024-11-13 15:07:30,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:30,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-13 15:07:30,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 488 transitions. [2024-11-13 15:07:30,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-13 15:07:30,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.492354740061162) internal successors, (488), 326 states have internal predecessors, (488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 488 transitions. [2024-11-13 15:07:30,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-13 15:07:30,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:30,235 INFO L424 stractBuchiCegarLoop]: Abstraction has 327 states and 488 transitions. [2024-11-13 15:07:30,235 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:07:30,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 488 transitions. [2024-11-13 15:07:30,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:30,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:30,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:30,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,243 INFO L745 eck$LassoCheckResult]: Stem: 1617#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1630#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1628#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1629#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1549#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1398#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1399#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1567#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1406#L441 assume !(0 == ~M_E~0); 1407#L441-2 assume !(0 == ~T1_E~0); 1544#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1509#L451-1 assume !(0 == ~T3_E~0); 1510#L456-1 assume !(0 == ~E_M~0); 1634#L461-1 assume !(0 == ~E_1~0); 1635#L466-1 assume !(0 == ~E_2~0); 1645#L471-1 assume !(0 == ~E_3~0); 1439#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1440#L220 assume 1 == ~m_pc~0; 1500#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1474#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1524#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1469#L543 assume !(0 != activate_threads_~tmp~1#1); 1470#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1616#L239 assume !(1 == ~t1_pc~0); 1614#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1615#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1437#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1438#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1619#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1620#L258 assume 1 == ~t2_pc~0; 1621#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1498#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1632#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1555#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1556#L277 assume !(1 == ~t3_pc~0); 1594#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1417#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1373#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1374#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1465#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1506#L489 assume !(1 == ~M_E~0); 1633#L489-2 assume !(1 == ~T1_E~0); 1577#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1454#L499-1 assume !(1 == ~T3_E~0); 1455#L504-1 assume !(1 == ~E_M~0); 1548#L509-1 assume !(1 == ~E_1~0); 1443#L514-1 assume !(1 == ~E_2~0); 1444#L519-1 assume !(1 == ~E_3~0); 1450#L524-1 assume { :end_inline_reset_delta_events } true; 1415#L690-2 [2024-11-13 15:07:30,243 INFO L747 eck$LassoCheckResult]: Loop: 1415#L690-2 assume !false; 1416#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1445#L416-1 assume !false; 1479#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1480#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1424#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1375#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1376#L369 assume !(0 != eval_~tmp~0#1); 1534#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1535#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1579#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1356#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1357#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1605#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1411#L456-3 assume !(0 == ~E_M~0); 1412#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1478#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1581#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1467#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1468#L220-15 assume 1 == ~m_pc~0; 1362#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1363#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1525#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1526#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1557#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1545#L239-15 assume 1 == ~t1_pc~0; 1546#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1648#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1504#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1396#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1397#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1666#L258-15 assume !(1 == ~t2_pc~0); 1507#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1508#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1656#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1657#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1636#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1637#L277-15 assume 1 == ~t3_pc~0; 1477#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1369#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1641#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1642#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 1408#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1400#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1401#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1598#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1631#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1527#L504-3 assume !(1 == ~E_M~0); 1377#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1378#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1589#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1425#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1426#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1446#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1451#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1578#L709 assume !(0 == start_simulation_~tmp~3#1); 1354#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1355#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1449#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1435#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1436#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1448#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1582#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1497#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1415#L690-2 [2024-11-13 15:07:30,243 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2024-11-13 15:07:30,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381277505] [2024-11-13 15:07:30,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381277505] [2024-11-13 15:07:30,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381277505] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277906113] [2024-11-13 15:07:30,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,334 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:30,335 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,335 INFO L85 PathProgramCache]: Analyzing trace with hash -1189726493, now seen corresponding path program 1 times [2024-11-13 15:07:30,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213677981] [2024-11-13 15:07:30,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213677981] [2024-11-13 15:07:30,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213677981] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133949084] [2024-11-13 15:07:30,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,421 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:30,421 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:30,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:30,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:30,421 INFO L87 Difference]: Start difference. First operand 327 states and 488 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:30,439 INFO L93 Difference]: Finished difference Result 327 states and 487 transitions. [2024-11-13 15:07:30,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 487 transitions. [2024-11-13 15:07:30,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:30,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 487 transitions. [2024-11-13 15:07:30,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2024-11-13 15:07:30,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2024-11-13 15:07:30,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 487 transitions. [2024-11-13 15:07:30,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:30,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-13 15:07:30,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 487 transitions. [2024-11-13 15:07:30,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2024-11-13 15:07:30,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 327 states, 327 states have (on average 1.489296636085627) internal successors, (487), 326 states have internal predecessors, (487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 487 transitions. [2024-11-13 15:07:30,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-13 15:07:30,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:30,457 INFO L424 stractBuchiCegarLoop]: Abstraction has 327 states and 487 transitions. [2024-11-13 15:07:30,457 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:07:30,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 327 states and 487 transitions. [2024-11-13 15:07:30,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2024-11-13 15:07:30,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:30,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:30,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,461 INFO L745 eck$LassoCheckResult]: Stem: 2278#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2289#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2290#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2209#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2057#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2058#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2228#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2067#L441 assume !(0 == ~M_E~0); 2068#L441-2 assume !(0 == ~T1_E~0); 2205#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2170#L451-1 assume !(0 == ~T3_E~0); 2171#L456-1 assume !(0 == ~E_M~0); 2295#L461-1 assume !(0 == ~E_1~0); 2296#L466-1 assume !(0 == ~E_2~0); 2306#L471-1 assume !(0 == ~E_3~0); 2100#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2101#L220 assume 1 == ~m_pc~0; 2161#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2135#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2185#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2130#L543 assume !(0 != activate_threads_~tmp~1#1); 2131#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2277#L239 assume !(1 == ~t1_pc~0); 2275#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2276#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2099#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2280#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2281#L258 assume 1 == ~t2_pc~0; 2282#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2159#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2293#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2216#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2217#L277 assume !(1 == ~t3_pc~0); 2255#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2078#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2034#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2035#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2126#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2167#L489 assume !(1 == ~M_E~0); 2294#L489-2 assume !(1 == ~T1_E~0); 2238#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2115#L499-1 assume !(1 == ~T3_E~0); 2116#L504-1 assume !(1 == ~E_M~0); 2210#L509-1 assume !(1 == ~E_1~0); 2104#L514-1 assume !(1 == ~E_2~0); 2105#L519-1 assume !(1 == ~E_3~0); 2111#L524-1 assume { :end_inline_reset_delta_events } true; 2076#L690-2 [2024-11-13 15:07:30,462 INFO L747 eck$LassoCheckResult]: Loop: 2076#L690-2 assume !false; 2077#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2106#L416-1 assume !false; 2140#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2141#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2085#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2036#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2037#L369 assume !(0 != eval_~tmp~0#1); 2195#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2196#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2240#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2017#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2018#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2266#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2072#L456-3 assume !(0 == ~E_M~0); 2073#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2139#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2242#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2128#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2129#L220-15 assume 1 == ~m_pc~0; 2023#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2024#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2186#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2187#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2218#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2206#L239-15 assume !(1 == ~t1_pc~0); 2208#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2309#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2165#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2059#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2060#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2327#L258-15 assume 1 == ~t2_pc~0; 2241#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2169#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2317#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2318#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2297#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2298#L277-15 assume 1 == ~t3_pc~0; 2138#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2030#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2302#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2303#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 2069#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2061#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2062#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2259#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2292#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2188#L504-3 assume !(1 == ~E_M~0); 2038#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2039#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2250#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2086#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2087#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2107#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2239#L709 assume !(0 == start_simulation_~tmp~3#1); 2015#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2016#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2110#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2097#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2109#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2243#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2158#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2076#L690-2 [2024-11-13 15:07:30,462 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,462 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2024-11-13 15:07:30,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888602114] [2024-11-13 15:07:30,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888602114] [2024-11-13 15:07:30,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888602114] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728922352] [2024-11-13 15:07:30,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,592 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:30,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,592 INFO L85 PathProgramCache]: Analyzing trace with hash -570097117, now seen corresponding path program 1 times [2024-11-13 15:07:30,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723193814] [2024-11-13 15:07:30,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723193814] [2024-11-13 15:07:30,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723193814] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:30,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286370941] [2024-11-13 15:07:30,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,684 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:30,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:30,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:07:30,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:07:30,685 INFO L87 Difference]: Start difference. First operand 327 states and 487 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:30,806 INFO L93 Difference]: Finished difference Result 569 states and 842 transitions. [2024-11-13 15:07:30,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 569 states and 842 transitions. [2024-11-13 15:07:30,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2024-11-13 15:07:30,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 569 states to 569 states and 842 transitions. [2024-11-13 15:07:30,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 569 [2024-11-13 15:07:30,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 569 [2024-11-13 15:07:30,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 569 states and 842 transitions. [2024-11-13 15:07:30,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:30,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-13 15:07:30,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states and 842 transitions. [2024-11-13 15:07:30,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 569. [2024-11-13 15:07:30,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.4797891036906854) internal successors, (842), 568 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:30,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 842 transitions. [2024-11-13 15:07:30,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-13 15:07:30,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:07:30,856 INFO L424 stractBuchiCegarLoop]: Abstraction has 569 states and 842 transitions. [2024-11-13 15:07:30,856 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:07:30,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 842 transitions. [2024-11-13 15:07:30,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2024-11-13 15:07:30,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:30,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:30,865 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,865 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:30,866 INFO L745 eck$LassoCheckResult]: Stem: 3205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3218#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3219#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3123#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2963#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2964#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3142#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2973#L441 assume !(0 == ~M_E~0); 2974#L441-2 assume !(0 == ~T1_E~0); 3119#L446-1 assume !(0 == ~T2_E~0); 3080#L451-1 assume !(0 == ~T3_E~0); 3081#L456-1 assume !(0 == ~E_M~0); 3224#L461-1 assume !(0 == ~E_1~0); 3225#L466-1 assume !(0 == ~E_2~0); 3241#L471-1 assume !(0 == ~E_3~0); 3006#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3007#L220 assume 1 == ~m_pc~0; 3069#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3042#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3096#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3037#L543 assume !(0 != activate_threads_~tmp~1#1); 3038#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3203#L239 assume !(1 == ~t1_pc~0); 3201#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3202#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3004#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3005#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3207#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3208#L258 assume 1 == ~t2_pc~0; 3209#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3067#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3068#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3222#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3130#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3131#L277 assume !(1 == ~t3_pc~0); 3171#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2984#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2940#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2941#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3033#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3077#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3223#L489-2 assume !(1 == ~T1_E~0); 3152#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3022#L499-1 assume !(1 == ~T3_E~0); 3023#L504-1 assume !(1 == ~E_M~0); 3124#L509-1 assume !(1 == ~E_1~0); 3010#L514-1 assume !(1 == ~E_2~0); 3011#L519-1 assume !(1 == ~E_3~0); 3018#L524-1 assume { :end_inline_reset_delta_events } true; 2982#L690-2 [2024-11-13 15:07:30,866 INFO L747 eck$LassoCheckResult]: Loop: 2982#L690-2 assume !false; 2983#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3012#L416-1 assume !false; 3047#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3048#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3232#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3233#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3213#L369 assume !(0 != eval_~tmp~0#1); 3215#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3154#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3155#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3268#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3471#L446-3 assume !(0 == ~T2_E~0); 3469#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3467#L456-3 assume !(0 == ~E_M~0); 3465#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3463#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3460#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3459#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3458#L220-15 assume !(1 == ~m_pc~0); 3456#L220-17 is_master_triggered_~__retres1~0#1 := 0; 3455#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3454#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3453#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3452#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3451#L239-15 assume 1 == ~t1_pc~0; 3449#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3448#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3438#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2965#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2966#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3265#L258-15 assume 1 == ~t2_pc~0; 3156#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3079#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3252#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3253#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3227#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3228#L277-15 assume 1 == ~t3_pc~0; 3045#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2936#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3236#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3237#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 2975#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2967#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2968#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3175#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3221#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3099#L504-3 assume !(1 == ~E_M~0); 2944#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2945#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3261#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3386#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3013#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3014#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3019#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3153#L709 assume !(0 == start_simulation_~tmp~3#1); 2921#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2922#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3295#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3294#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3293#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3292#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3291#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3066#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2982#L690-2 [2024-11-13 15:07:30,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,866 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2024-11-13 15:07:30,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901991396] [2024-11-13 15:07:30,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:30,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:30,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:30,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901991396] [2024-11-13 15:07:30,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901991396] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:30,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:30,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:07:30,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352460592] [2024-11-13 15:07:30,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:30,960 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:30,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:30,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1051693601, now seen corresponding path program 1 times [2024-11-13 15:07:30,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:30,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937263145] [2024-11-13 15:07:30,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:30,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:30,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:31,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:31,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:31,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937263145] [2024-11-13 15:07:31,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937263145] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:31,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:31,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:31,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687289680] [2024-11-13 15:07:31,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:31,066 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:31,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:31,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:31,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:31,066 INFO L87 Difference]: Start difference. First operand 569 states and 842 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:31,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:31,144 INFO L93 Difference]: Finished difference Result 1049 states and 1527 transitions. [2024-11-13 15:07:31,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1049 states and 1527 transitions. [2024-11-13 15:07:31,152 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 983 [2024-11-13 15:07:31,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1049 states to 1049 states and 1527 transitions. [2024-11-13 15:07:31,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1049 [2024-11-13 15:07:31,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1049 [2024-11-13 15:07:31,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1049 states and 1527 transitions. [2024-11-13 15:07:31,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:31,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1049 states and 1527 transitions. [2024-11-13 15:07:31,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1049 states and 1527 transitions. [2024-11-13 15:07:31,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1049 to 995. [2024-11-13 15:07:31,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 995 states, 995 states have (on average 1.4603015075376884) internal successors, (1453), 994 states have internal predecessors, (1453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:31,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1453 transitions. [2024-11-13 15:07:31,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 995 states and 1453 transitions. [2024-11-13 15:07:31,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:31,197 INFO L424 stractBuchiCegarLoop]: Abstraction has 995 states and 1453 transitions. [2024-11-13 15:07:31,197 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:07:31,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1453 transitions. [2024-11-13 15:07:31,204 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2024-11-13 15:07:31,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:31,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:31,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:31,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:31,208 INFO L745 eck$LassoCheckResult]: Stem: 4825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4841#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4838#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4839#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4745#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4592#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4593#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4765#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4600#L441 assume !(0 == ~M_E~0); 4601#L441-2 assume !(0 == ~T1_E~0); 4741#L446-1 assume !(0 == ~T2_E~0); 4706#L451-1 assume !(0 == ~T3_E~0); 4707#L456-1 assume !(0 == ~E_M~0); 4847#L461-1 assume !(0 == ~E_1~0); 4848#L466-1 assume !(0 == ~E_2~0); 4860#L471-1 assume !(0 == ~E_3~0); 4635#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4636#L220 assume !(1 == ~m_pc~0); 4667#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4668#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4723#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4663#L543 assume !(0 != activate_threads_~tmp~1#1); 4664#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4823#L239 assume !(1 == ~t1_pc~0); 4821#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4822#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4632#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4827#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4828#L258 assume 1 == ~t2_pc~0; 4829#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4694#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4695#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4845#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4754#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4755#L277 assume !(1 == ~t3_pc~0); 4799#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4611#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4567#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4568#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4659#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4701#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4892#L489-2 assume !(1 == ~T1_E~0); 5364#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4780#L499-1 assume !(1 == ~T3_E~0); 5358#L504-1 assume !(1 == ~E_M~0); 5356#L509-1 assume !(1 == ~E_1~0); 5354#L514-1 assume !(1 == ~E_2~0); 5352#L519-1 assume !(1 == ~E_3~0); 5349#L524-1 assume { :end_inline_reset_delta_events } true; 5346#L690-2 [2024-11-13 15:07:31,208 INFO L747 eck$LassoCheckResult]: Loop: 5346#L690-2 assume !false; 5341#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4811#L416-1 assume !false; 4673#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4674#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5335#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4569#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4570#L369 assume !(0 != eval_~tmp~0#1); 4732#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4733#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4783#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4550#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4551#L446-3 assume !(0 == ~T2_E~0); 5083#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5082#L456-3 assume !(0 == ~E_M~0); 5081#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5080#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5079#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5077#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5075#L220-15 assume !(1 == ~m_pc~0); 5074#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5029#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5025#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5022#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5019#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5016#L239-15 assume 1 == ~t1_pc~0; 5011#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5009#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5007#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5004#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5002#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5000#L258-15 assume !(1 == ~t2_pc~0); 4997#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 4995#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4991#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4988#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4986#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L277-15 assume 1 == ~t3_pc~0; 4974#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4971#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4969#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4966#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 4963#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4961#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4959#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4952#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4941#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4933#L504-3 assume !(1 == ~E_M~0); 4926#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4920#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4915#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4912#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4913#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5367#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5366#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5365#L709 assume !(0 == start_simulation_~tmp~3#1); 4805#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5362#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5359#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5357#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5355#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5353#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5351#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5350#L722 assume !(0 != start_simulation_~tmp___0~1#1); 5346#L690-2 [2024-11-13 15:07:31,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:31,211 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2024-11-13 15:07:31,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:31,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542130575] [2024-11-13 15:07:31,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:31,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:31,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:31,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:31,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:31,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542130575] [2024-11-13 15:07:31,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542130575] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:31,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:31,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:07:31,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121830605] [2024-11-13 15:07:31,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:31,354 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:31,354 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:31,354 INFO L85 PathProgramCache]: Analyzing trace with hash -524864158, now seen corresponding path program 1 times [2024-11-13 15:07:31,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:31,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101211080] [2024-11-13 15:07:31,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:31,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:31,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:31,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:31,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:31,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101211080] [2024-11-13 15:07:31,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101211080] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:31,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:31,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:31,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183091934] [2024-11-13 15:07:31,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:31,463 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:31,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:31,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:31,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:31,464 INFO L87 Difference]: Start difference. First operand 995 states and 1453 transitions. cyclomatic complexity: 462 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:31,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:31,540 INFO L93 Difference]: Finished difference Result 1789 states and 2591 transitions. [2024-11-13 15:07:31,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1789 states and 2591 transitions. [2024-11-13 15:07:31,555 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1712 [2024-11-13 15:07:31,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1789 states to 1789 states and 2591 transitions. [2024-11-13 15:07:31,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1789 [2024-11-13 15:07:31,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1789 [2024-11-13 15:07:31,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1789 states and 2591 transitions. [2024-11-13 15:07:31,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:31,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1789 states and 2591 transitions. [2024-11-13 15:07:31,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1789 states and 2591 transitions. [2024-11-13 15:07:31,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1789 to 1781. [2024-11-13 15:07:31,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.450308815272319) internal successors, (2583), 1780 states have internal predecessors, (2583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:31,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2583 transitions. [2024-11-13 15:07:31,635 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2024-11-13 15:07:31,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:31,636 INFO L424 stractBuchiCegarLoop]: Abstraction has 1781 states and 2583 transitions. [2024-11-13 15:07:31,639 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:07:31,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2583 transitions. [2024-11-13 15:07:31,651 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1704 [2024-11-13 15:07:31,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:31,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:31,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:31,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:31,657 INFO L745 eck$LassoCheckResult]: Stem: 7636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7648#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 7549#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7384#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7385#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7570#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7395#L441 assume !(0 == ~M_E~0); 7396#L441-2 assume !(0 == ~T1_E~0); 7545#L446-1 assume !(0 == ~T2_E~0); 7503#L451-1 assume !(0 == ~T3_E~0); 7504#L456-1 assume !(0 == ~E_M~0); 7656#L461-1 assume !(0 == ~E_1~0); 7657#L466-1 assume !(0 == ~E_2~0); 7674#L471-1 assume !(0 == ~E_3~0); 7428#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7429#L220 assume !(1 == ~m_pc~0); 7463#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7464#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7520#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7459#L543 assume !(0 != activate_threads_~tmp~1#1); 7460#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7634#L239 assume !(1 == ~t1_pc~0); 7632#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7633#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7426#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7427#L551 assume !(0 != activate_threads_~tmp___0~0#1); 7638#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7639#L258 assume !(1 == ~t2_pc~0); 7640#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7492#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7493#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7653#L559 assume !(0 != activate_threads_~tmp___1~0#1); 7557#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7558#L277 assume !(1 == ~t3_pc~0); 7601#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7406#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7361#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7455#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7500#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 7714#L489-2 assume !(1 == ~T1_E~0); 7582#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7444#L499-1 assume !(1 == ~T3_E~0); 7445#L504-1 assume !(1 == ~E_M~0); 7550#L509-1 assume !(1 == ~E_1~0); 8314#L514-1 assume !(1 == ~E_2~0); 8313#L519-1 assume !(1 == ~E_3~0); 8309#L524-1 assume { :end_inline_reset_delta_events } true; 8304#L690-2 [2024-11-13 15:07:31,657 INFO L747 eck$LassoCheckResult]: Loop: 8304#L690-2 assume !false; 8299#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8295#L416-1 assume !false; 8294#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8292#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8289#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8288#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8284#L369 assume !(0 != eval_~tmp~0#1); 8285#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8550#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8547#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8544#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8541#L446-3 assume !(0 == ~T2_E~0); 8538#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8535#L456-3 assume !(0 == ~E_M~0); 8532#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8529#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8526#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8522#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8519#L220-15 assume !(1 == ~m_pc~0); 8515#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8508#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8504#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8498#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8494#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8488#L239-15 assume 1 == ~t1_pc~0; 8482#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8476#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8470#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8465#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8463#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8461#L258-15 assume !(1 == ~t2_pc~0); 8456#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8454#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8452#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8449#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8446#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8442#L277-15 assume 1 == ~t3_pc~0; 8435#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8429#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7910#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7911#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 7904#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7905#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7898#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7899#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7891#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7892#L504-3 assume !(1 == ~E_M~0); 7878#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7879#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7859#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7860#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7848#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7846#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7806#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7807#L709 assume !(0 == start_simulation_~tmp~3#1); 8362#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8358#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8352#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8333#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 8328#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8320#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8316#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8310#L722 assume !(0 != start_simulation_~tmp___0~1#1); 8304#L690-2 [2024-11-13 15:07:31,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:31,658 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2024-11-13 15:07:31,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:31,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574985835] [2024-11-13 15:07:31,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:31,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:31,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:31,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:31,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:31,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574985835] [2024-11-13 15:07:31,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574985835] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:31,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:31,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:07:31,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168947109] [2024-11-13 15:07:31,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:31,749 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:31,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:31,749 INFO L85 PathProgramCache]: Analyzing trace with hash -524864158, now seen corresponding path program 2 times [2024-11-13 15:07:31,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:31,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652712929] [2024-11-13 15:07:31,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:31,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:31,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:31,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:31,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:31,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652712929] [2024-11-13 15:07:31,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652712929] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:31,845 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:31,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:31,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999752828] [2024-11-13 15:07:31,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:31,846 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:31,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:31,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:31,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:31,847 INFO L87 Difference]: Start difference. First operand 1781 states and 2583 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:31,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:31,901 INFO L93 Difference]: Finished difference Result 2597 states and 3764 transitions. [2024-11-13 15:07:31,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2597 states and 3764 transitions. [2024-11-13 15:07:31,922 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2024-11-13 15:07:31,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2597 states to 2597 states and 3764 transitions. [2024-11-13 15:07:31,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2597 [2024-11-13 15:07:31,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2597 [2024-11-13 15:07:31,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2597 states and 3764 transitions. [2024-11-13 15:07:31,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:31,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2597 states and 3764 transitions. [2024-11-13 15:07:31,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2597 states and 3764 transitions. [2024-11-13 15:07:31,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2597 to 1805. [2024-11-13 15:07:31,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.453185595567867) internal successors, (2623), 1804 states have internal predecessors, (2623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:32,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2623 transitions. [2024-11-13 15:07:32,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2024-11-13 15:07:32,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:32,010 INFO L424 stractBuchiCegarLoop]: Abstraction has 1805 states and 2623 transitions. [2024-11-13 15:07:32,010 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:07:32,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2623 transitions. [2024-11-13 15:07:32,024 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-13 15:07:32,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:32,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:32,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,026 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,026 INFO L745 eck$LassoCheckResult]: Stem: 12013#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12025#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 11930#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11769#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11770#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11951#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11779#L441 assume !(0 == ~M_E~0); 11780#L441-2 assume !(0 == ~T1_E~0); 11926#L446-1 assume !(0 == ~T2_E~0); 11886#L451-1 assume !(0 == ~T3_E~0); 11887#L456-1 assume !(0 == ~E_M~0); 12030#L461-1 assume !(0 == ~E_1~0); 12031#L466-1 assume !(0 == ~E_2~0); 12044#L471-1 assume !(0 == ~E_3~0); 11812#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11813#L220 assume !(1 == ~m_pc~0); 11846#L220-2 is_master_triggered_~__retres1~0#1 := 0; 11847#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11902#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11842#L543 assume !(0 != activate_threads_~tmp~1#1); 11843#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12012#L239 assume !(1 == ~t1_pc~0); 12010#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12011#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11810#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11811#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12015#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12016#L258 assume !(1 == ~t2_pc~0); 12017#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11875#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12028#L559 assume !(0 != activate_threads_~tmp___1~0#1); 11938#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11939#L277 assume !(1 == ~t3_pc~0); 11988#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11790#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11748#L567 assume !(0 != activate_threads_~tmp___2~0#1); 11838#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11883#L489 assume !(1 == ~M_E~0); 12029#L489-2 assume !(1 == ~T1_E~0); 11964#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11827#L499-1 assume !(1 == ~T3_E~0); 11828#L504-1 assume !(1 == ~E_M~0); 11931#L509-1 assume !(1 == ~E_1~0); 11816#L514-1 assume !(1 == ~E_2~0); 11817#L519-1 assume !(1 == ~E_3~0); 11823#L524-1 assume { :end_inline_reset_delta_events } true; 11788#L690-2 [2024-11-13 15:07:32,026 INFO L747 eck$LassoCheckResult]: Loop: 11788#L690-2 assume !false; 11789#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11818#L416-1 assume !false; 11853#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11854#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11797#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11749#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11750#L369 assume !(0 != eval_~tmp~0#1); 12021#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13518#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13517#L441-3 assume !(0 == ~M_E~0); 13516#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13515#L446-3 assume !(0 == ~T2_E~0); 13514#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13512#L456-3 assume !(0 == ~E_M~0); 11851#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11852#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12047#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11840#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11841#L220-15 assume !(1 == ~m_pc~0); 11903#L220-17 is_master_triggered_~__retres1~0#1 := 0; 11980#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11904#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11905#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11940#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11927#L239-15 assume 1 == ~t1_pc~0; 11928#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12048#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11881#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11771#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11772#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12076#L258-15 assume !(1 == ~t2_pc~0); 11884#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 11885#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12057#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12058#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12032#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12033#L277-15 assume 1 == ~t3_pc~0; 11850#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11743#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12040#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12041#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 11781#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11773#L489-3 assume !(1 == ~M_E~0); 11774#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11993#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12027#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11906#L504-3 assume !(1 == ~E_M~0); 11751#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11752#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11983#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11798#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11799#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11819#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11824#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11965#L709 assume !(0 == start_simulation_~tmp~3#1); 11966#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11917#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11822#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11808#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 11809#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11821#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11975#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11874#L722 assume !(0 != start_simulation_~tmp___0~1#1); 11788#L690-2 [2024-11-13 15:07:32,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,027 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2024-11-13 15:07:32,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295171692] [2024-11-13 15:07:32,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:32,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:32,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:32,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295171692] [2024-11-13 15:07:32,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295171692] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:32,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:32,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:32,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654630871] [2024-11-13 15:07:32,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:32,105 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:32,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,106 INFO L85 PathProgramCache]: Analyzing trace with hash 773856674, now seen corresponding path program 1 times [2024-11-13 15:07:32,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881725099] [2024-11-13 15:07:32,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:32,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:32,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:32,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881725099] [2024-11-13 15:07:32,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881725099] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:32,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:32,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:32,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181685715] [2024-11-13 15:07:32,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:32,179 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:32,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:32,180 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:07:32,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:07:32,180 INFO L87 Difference]: Start difference. First operand 1805 states and 2623 transitions. cyclomatic complexity: 822 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:32,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:32,262 INFO L93 Difference]: Finished difference Result 2591 states and 3732 transitions. [2024-11-13 15:07:32,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2591 states and 3732 transitions. [2024-11-13 15:07:32,282 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2514 [2024-11-13 15:07:32,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2591 states to 2591 states and 3732 transitions. [2024-11-13 15:07:32,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2591 [2024-11-13 15:07:32,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2591 [2024-11-13 15:07:32,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2591 states and 3732 transitions. [2024-11-13 15:07:32,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:32,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2591 states and 3732 transitions. [2024-11-13 15:07:32,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2591 states and 3732 transitions. [2024-11-13 15:07:32,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2591 to 1805. [2024-11-13 15:07:32,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4437673130193907) internal successors, (2606), 1804 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:32,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2606 transitions. [2024-11-13 15:07:32,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2024-11-13 15:07:32,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:07:32,369 INFO L424 stractBuchiCegarLoop]: Abstraction has 1805 states and 2606 transitions. [2024-11-13 15:07:32,370 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:07:32,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2606 transitions. [2024-11-13 15:07:32,381 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1736 [2024-11-13 15:07:32,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:32,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:32,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,382 INFO L745 eck$LassoCheckResult]: Stem: 16416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16427#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16336#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16178#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16179#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16356#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16188#L441 assume !(0 == ~M_E~0); 16189#L441-2 assume !(0 == ~T1_E~0); 16332#L446-1 assume !(0 == ~T2_E~0); 16293#L451-1 assume !(0 == ~T3_E~0); 16294#L456-1 assume !(0 == ~E_M~0); 16435#L461-1 assume !(0 == ~E_1~0); 16436#L466-1 assume !(0 == ~E_2~0); 16450#L471-1 assume !(0 == ~E_3~0); 16221#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16222#L220 assume !(1 == ~m_pc~0); 16256#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16257#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16309#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16252#L543 assume !(0 != activate_threads_~tmp~1#1); 16253#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16415#L239 assume !(1 == ~t1_pc~0); 16413#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16414#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16219#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16220#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16418#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16419#L258 assume !(1 == ~t2_pc~0); 16420#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16283#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16284#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16432#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16343#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16344#L277 assume !(1 == ~t3_pc~0); 16390#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16199#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16155#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16156#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16248#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16290#L489 assume !(1 == ~M_E~0); 16433#L489-2 assume !(1 == ~T1_E~0); 16368#L494-1 assume !(1 == ~T2_E~0); 16237#L499-1 assume !(1 == ~T3_E~0); 16238#L504-1 assume !(1 == ~E_M~0); 16337#L509-1 assume !(1 == ~E_1~0); 16225#L514-1 assume !(1 == ~E_2~0); 16226#L519-1 assume !(1 == ~E_3~0); 16232#L524-1 assume { :end_inline_reset_delta_events } true; 16233#L690-2 [2024-11-13 15:07:32,382 INFO L747 eck$LassoCheckResult]: Loop: 16233#L690-2 assume !false; 16824#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16822#L416-1 assume !false; 16821#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16819#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16816#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16815#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16813#L369 assume !(0 != eval_~tmp~0#1); 16812#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16811#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16810#L441-3 assume !(0 == ~M_E~0); 16809#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16808#L446-3 assume !(0 == ~T2_E~0); 16807#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16806#L456-3 assume !(0 == ~E_M~0); 16805#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16804#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16803#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16802#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16801#L220-15 assume !(1 == ~m_pc~0); 16800#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16799#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16798#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16797#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16796#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16795#L239-15 assume 1 == ~t1_pc~0; 16793#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16792#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16791#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16790#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16789#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16788#L258-15 assume !(1 == ~t2_pc~0); 16787#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16786#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16785#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16784#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16783#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16782#L277-15 assume 1 == ~t3_pc~0; 16780#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16779#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16778#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16777#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 16776#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16595#L489-3 assume !(1 == ~M_E~0); 16591#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16589#L494-3 assume !(1 == ~T2_E~0); 16578#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16571#L504-3 assume !(1 == ~E_M~0); 16565#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16557#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16549#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16542#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16536#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16526#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16516#L709 assume !(0 == start_simulation_~tmp~3#1); 16517#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16862#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16857#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16852#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 16849#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16846#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16838#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16833#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16233#L690-2 [2024-11-13 15:07:32,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,383 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2024-11-13 15:07:32,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385243777] [2024-11-13 15:07:32,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:32,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:32,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:32,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:32,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,451 INFO L85 PathProgramCache]: Analyzing trace with hash -915087068, now seen corresponding path program 1 times [2024-11-13 15:07:32,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141801969] [2024-11-13 15:07:32,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:32,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:32,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:32,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141801969] [2024-11-13 15:07:32,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141801969] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:32,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:32,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:32,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256672082] [2024-11-13 15:07:32,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:32,520 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:32,520 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:32,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:07:32,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:07:32,520 INFO L87 Difference]: Start difference. First operand 1805 states and 2606 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:32,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:32,618 INFO L93 Difference]: Finished difference Result 1861 states and 2662 transitions. [2024-11-13 15:07:32,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1861 states and 2662 transitions. [2024-11-13 15:07:32,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1792 [2024-11-13 15:07:32,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1861 states to 1861 states and 2662 transitions. [2024-11-13 15:07:32,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1861 [2024-11-13 15:07:32,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1861 [2024-11-13 15:07:32,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1861 states and 2662 transitions. [2024-11-13 15:07:32,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:32,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1861 states and 2662 transitions. [2024-11-13 15:07:32,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1861 states and 2662 transitions. [2024-11-13 15:07:32,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1861 to 1829. [2024-11-13 15:07:32,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1829 states, 1829 states have (on average 1.437944231820667) internal successors, (2630), 1828 states have internal predecessors, (2630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:32,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1829 states to 1829 states and 2630 transitions. [2024-11-13 15:07:32,690 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2024-11-13 15:07:32,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:07:32,691 INFO L424 stractBuchiCegarLoop]: Abstraction has 1829 states and 2630 transitions. [2024-11-13 15:07:32,691 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:07:32,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1829 states and 2630 transitions. [2024-11-13 15:07:32,701 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1760 [2024-11-13 15:07:32,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:32,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:32,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:32,702 INFO L745 eck$LassoCheckResult]: Stem: 20110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20123#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20121#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20122#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 20021#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19852#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19853#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20040#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19862#L441 assume !(0 == ~M_E~0); 19863#L441-2 assume !(0 == ~T1_E~0); 20017#L446-1 assume !(0 == ~T2_E~0); 19974#L451-1 assume !(0 == ~T3_E~0); 19975#L456-1 assume !(0 == ~E_M~0); 20132#L461-1 assume !(0 == ~E_1~0); 20133#L466-1 assume !(0 == ~E_2~0); 20152#L471-1 assume !(0 == ~E_3~0); 19897#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19898#L220 assume !(1 == ~m_pc~0); 19934#L220-2 is_master_triggered_~__retres1~0#1 := 0; 19935#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19990#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19930#L543 assume !(0 != activate_threads_~tmp~1#1); 19931#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20106#L239 assume !(1 == ~t1_pc~0); 20104#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20105#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19896#L551 assume !(0 != activate_threads_~tmp___0~0#1); 20112#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20113#L258 assume !(1 == ~t2_pc~0); 20114#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19962#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19963#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20129#L559 assume !(0 != activate_threads_~tmp___1~0#1); 20028#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20029#L277 assume !(1 == ~t3_pc~0); 20076#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19874#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19829#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19830#L567 assume !(0 != activate_threads_~tmp___2~0#1); 19926#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19971#L489 assume !(1 == ~M_E~0); 20130#L489-2 assume !(1 == ~T1_E~0); 20054#L494-1 assume !(1 == ~T2_E~0); 19915#L499-1 assume !(1 == ~T3_E~0); 19916#L504-1 assume !(1 == ~E_M~0); 20022#L509-1 assume !(1 == ~E_1~0); 19901#L514-1 assume !(1 == ~E_2~0); 19902#L519-1 assume !(1 == ~E_3~0); 19910#L524-1 assume { :end_inline_reset_delta_events } true; 19911#L690-2 [2024-11-13 15:07:32,703 INFO L747 eck$LassoCheckResult]: Loop: 19911#L690-2 assume !false; 20871#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20869#L416-1 assume !false; 20868#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20865#L332 assume !(0 == ~m_st~0); 20866#L336 assume !(0 == ~t1_st~0); 20862#L340 assume !(0 == ~t2_st~0); 20863#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 20864#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20851#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20852#L369 assume !(0 != eval_~tmp~0#1); 21283#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21279#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21275#L441-3 assume !(0 == ~M_E~0); 21272#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21269#L446-3 assume !(0 == ~T2_E~0); 21256#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21250#L456-3 assume !(0 == ~E_M~0); 21243#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21235#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21193#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21191#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21189#L220-15 assume !(1 == ~m_pc~0); 21187#L220-17 is_master_triggered_~__retres1~0#1 := 0; 21184#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21181#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21178#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21175#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21172#L239-15 assume 1 == ~t1_pc~0; 21168#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21164#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21161#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21158#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21155#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21152#L258-15 assume !(1 == ~t2_pc~0); 21149#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21145#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21142#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21139#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21136#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21133#L277-15 assume 1 == ~t3_pc~0; 21129#L278-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21124#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21120#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21116#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 21112#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21108#L489-3 assume !(1 == ~M_E~0); 21102#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21100#L494-3 assume !(1 == ~T2_E~0); 21097#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21094#L504-3 assume !(1 == ~E_M~0); 21091#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21088#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21085#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21068#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21065#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21061#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21059#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21057#L709 assume !(0 == start_simulation_~tmp~3#1); 21054#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21050#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21047#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 21037#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21036#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21035#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 21034#L722 assume !(0 != start_simulation_~tmp___0~1#1); 19911#L690-2 [2024-11-13 15:07:32,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2024-11-13 15:07:32,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944168235] [2024-11-13 15:07:32,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:32,714 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:32,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:32,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:32,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:32,752 INFO L85 PathProgramCache]: Analyzing trace with hash -643499992, now seen corresponding path program 1 times [2024-11-13 15:07:32,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:32,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53130590] [2024-11-13 15:07:32,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:32,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:32,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:32,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:32,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:32,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53130590] [2024-11-13 15:07:32,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53130590] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:32,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:32,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:32,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110836676] [2024-11-13 15:07:32,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:32,818 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:32,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:32,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:07:32,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:07:32,819 INFO L87 Difference]: Start difference. First operand 1829 states and 2630 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:33,036 INFO L93 Difference]: Finished difference Result 1940 states and 2741 transitions. [2024-11-13 15:07:33,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1940 states and 2741 transitions. [2024-11-13 15:07:33,048 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1868 [2024-11-13 15:07:33,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1940 states to 1940 states and 2741 transitions. [2024-11-13 15:07:33,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1940 [2024-11-13 15:07:33,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1940 [2024-11-13 15:07:33,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1940 states and 2741 transitions. [2024-11-13 15:07:33,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:33,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1940 states and 2741 transitions. [2024-11-13 15:07:33,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1940 states and 2741 transitions. [2024-11-13 15:07:33,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1940 to 1940. [2024-11-13 15:07:33,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1940 states, 1940 states have (on average 1.4128865979381444) internal successors, (2741), 1939 states have internal predecessors, (2741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1940 states to 1940 states and 2741 transitions. [2024-11-13 15:07:33,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1940 states and 2741 transitions. [2024-11-13 15:07:33,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:07:33,109 INFO L424 stractBuchiCegarLoop]: Abstraction has 1940 states and 2741 transitions. [2024-11-13 15:07:33,109 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:07:33,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1940 states and 2741 transitions. [2024-11-13 15:07:33,118 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1868 [2024-11-13 15:07:33,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:33,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:33,120 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,120 INFO L745 eck$LassoCheckResult]: Stem: 23875#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 23876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 23887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23886#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 23793#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23628#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23629#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23815#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23638#L441 assume !(0 == ~M_E~0); 23639#L441-2 assume !(0 == ~T1_E~0); 23789#L446-1 assume !(0 == ~T2_E~0); 23749#L451-1 assume !(0 == ~T3_E~0); 23750#L456-1 assume !(0 == ~E_M~0); 23891#L461-1 assume !(0 == ~E_1~0); 23892#L466-1 assume !(0 == ~E_2~0); 23905#L471-1 assume !(0 == ~E_3~0); 23672#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23673#L220 assume !(1 == ~m_pc~0); 23706#L220-2 is_master_triggered_~__retres1~0#1 := 0; 23707#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23765#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23702#L543 assume !(0 != activate_threads_~tmp~1#1); 23703#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23874#L239 assume !(1 == ~t1_pc~0); 23872#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23873#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23670#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23671#L551 assume !(0 != activate_threads_~tmp___0~0#1); 23877#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23878#L258 assume !(1 == ~t2_pc~0); 23879#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23736#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23737#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23889#L559 assume !(0 != activate_threads_~tmp___1~0#1); 23803#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23804#L277 assume !(1 == ~t3_pc~0); 23848#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23939#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23941#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23940#L567 assume !(0 != activate_threads_~tmp___2~0#1); 23698#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23746#L489 assume !(1 == ~M_E~0); 23890#L489-2 assume !(1 == ~T1_E~0); 23827#L494-1 assume !(1 == ~T2_E~0); 23687#L499-1 assume !(1 == ~T3_E~0); 23688#L504-1 assume !(1 == ~E_M~0); 23794#L509-1 assume !(1 == ~E_1~0); 23676#L514-1 assume !(1 == ~E_2~0); 23677#L519-1 assume !(1 == ~E_3~0); 23683#L524-1 assume { :end_inline_reset_delta_events } true; 23647#L690-2 [2024-11-13 15:07:33,120 INFO L747 eck$LassoCheckResult]: Loop: 23647#L690-2 assume !false; 23648#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23678#L416-1 assume !false; 23714#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23715#L332 assume !(0 == ~m_st~0); 23761#L336 assume !(0 == ~t1_st~0); 23762#L340 assume !(0 == ~t2_st~0); 23655#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 23657#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25501#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25500#L369 assume !(0 != eval_~tmp~0#1); 25499#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25498#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25497#L441-3 assume !(0 == ~M_E~0); 25496#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25494#L446-3 assume !(0 == ~T2_E~0); 25493#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25492#L456-3 assume !(0 == ~E_M~0); 25491#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25490#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25488#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25486#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25484#L220-15 assume !(1 == ~m_pc~0); 25480#L220-17 is_master_triggered_~__retres1~0#1 := 0; 25478#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25476#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25474#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25469#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25468#L239-15 assume 1 == ~t1_pc~0; 25466#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23922#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23923#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25406#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25404#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25402#L258-15 assume !(1 == ~t2_pc~0); 25400#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 25398#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25396#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25393#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25391#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25389#L277-15 assume !(1 == ~t3_pc~0); 25386#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 25383#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25380#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25377#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 25375#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25373#L489-3 assume !(1 == ~M_E~0); 25304#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25370#L494-3 assume !(1 == ~T2_E~0); 25368#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25366#L504-3 assume !(1 == ~E_M~0); 25364#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25362#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25361#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25360#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25358#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25355#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25352#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 23828#L709 assume !(0 == start_simulation_~tmp~3#1); 23587#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23588#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 23682#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 23668#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 23669#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23681#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23836#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23735#L722 assume !(0 != start_simulation_~tmp___0~1#1); 23647#L690-2 [2024-11-13 15:07:33,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2024-11-13 15:07:33,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720515618] [2024-11-13 15:07:33,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:33,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,150 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:33,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1978949673, now seen corresponding path program 1 times [2024-11-13 15:07:33,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234265493] [2024-11-13 15:07:33,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:33,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:33,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:33,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234265493] [2024-11-13 15:07:33,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234265493] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:33,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:33,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:07:33,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585662490] [2024-11-13 15:07:33,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:33,271 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:33,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:33,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:07:33,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:07:33,271 INFO L87 Difference]: Start difference. First operand 1940 states and 2741 transitions. cyclomatic complexity: 805 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:33,519 INFO L93 Difference]: Finished difference Result 2000 states and 2784 transitions. [2024-11-13 15:07:33,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2000 states and 2784 transitions. [2024-11-13 15:07:33,530 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1928 [2024-11-13 15:07:33,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2000 states to 2000 states and 2784 transitions. [2024-11-13 15:07:33,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2000 [2024-11-13 15:07:33,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2000 [2024-11-13 15:07:33,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2000 states and 2784 transitions. [2024-11-13 15:07:33,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:33,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2000 states and 2784 transitions. [2024-11-13 15:07:33,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2000 states and 2784 transitions. [2024-11-13 15:07:33,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2000 to 2000. [2024-11-13 15:07:33,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2000 states, 2000 states have (on average 1.392) internal successors, (2784), 1999 states have internal predecessors, (2784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2000 states to 2000 states and 2784 transitions. [2024-11-13 15:07:33,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2000 states and 2784 transitions. [2024-11-13 15:07:33,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:07:33,590 INFO L424 stractBuchiCegarLoop]: Abstraction has 2000 states and 2784 transitions. [2024-11-13 15:07:33,590 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:07:33,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2000 states and 2784 transitions. [2024-11-13 15:07:33,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1928 [2024-11-13 15:07:33,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:33,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:33,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,603 INFO L745 eck$LassoCheckResult]: Stem: 27833#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 27834#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27846#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27847#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 27745#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27577#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27578#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27766#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27587#L441 assume !(0 == ~M_E~0); 27588#L441-2 assume !(0 == ~T1_E~0); 27741#L446-1 assume !(0 == ~T2_E~0); 27701#L451-1 assume !(0 == ~T3_E~0); 27702#L456-1 assume !(0 == ~E_M~0); 27856#L461-1 assume !(0 == ~E_1~0); 27857#L466-1 assume !(0 == ~E_2~0); 27873#L471-1 assume !(0 == ~E_3~0); 27621#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27622#L220 assume !(1 == ~m_pc~0); 27657#L220-2 is_master_triggered_~__retres1~0#1 := 0; 27658#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27717#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27653#L543 assume !(0 != activate_threads_~tmp~1#1); 27654#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27832#L239 assume !(1 == ~t1_pc~0); 27830#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27831#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27619#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27620#L551 assume !(0 != activate_threads_~tmp___0~0#1); 27835#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27836#L258 assume !(1 == ~t2_pc~0); 27837#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27687#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27688#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27852#L559 assume !(0 != activate_threads_~tmp___1~0#1); 27754#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27755#L277 assume !(1 == ~t3_pc~0); 27804#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 27909#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27910#L567 assume !(0 != activate_threads_~tmp___2~0#1); 27649#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27698#L489 assume !(1 == ~M_E~0); 27853#L489-2 assume !(1 == ~T1_E~0); 27779#L494-1 assume !(1 == ~T2_E~0); 27638#L499-1 assume !(1 == ~T3_E~0); 27639#L504-1 assume !(1 == ~E_M~0); 27746#L509-1 assume !(1 == ~E_1~0); 27625#L514-1 assume !(1 == ~E_2~0); 27626#L519-1 assume !(1 == ~E_3~0); 27633#L524-1 assume { :end_inline_reset_delta_events } true; 27634#L690-2 [2024-11-13 15:07:33,603 INFO L747 eck$LassoCheckResult]: Loop: 27634#L690-2 assume !false; 29423#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27819#L416-1 assume !false; 29422#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29421#L332 assume !(0 == ~m_st~0); 29420#L336 assume !(0 == ~t1_st~0); 29419#L340 assume !(0 == ~t2_st~0); 29418#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 29416#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27556#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27557#L369 assume !(0 != eval_~tmp~0#1); 29415#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29408#L441-3 assume !(0 == ~M_E~0); 29407#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29406#L446-3 assume !(0 == ~T2_E~0); 29405#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29404#L456-3 assume !(0 == ~E_M~0); 29403#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29402#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29401#L471-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29400#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29399#L220-15 assume !(1 == ~m_pc~0); 29398#L220-17 is_master_triggered_~__retres1~0#1 := 0; 29382#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29372#is_master_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29368#L543-15 assume !(0 != activate_threads_~tmp~1#1); 29364#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29360#L239-15 assume 1 == ~t1_pc~0; 29355#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29351#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29347#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29344#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29338#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29334#L258-15 assume !(1 == ~t2_pc~0); 29330#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 29329#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29256#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29249#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29154#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29153#L277-15 assume !(1 == ~t3_pc~0); 29152#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 29150#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29148#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29145#L567-15 assume !(0 != activate_threads_~tmp___2~0#1); 29144#L567-17 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29143#L489-3 assume !(1 == ~M_E~0); 28810#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29140#L494-3 assume !(1 == ~T2_E~0); 29139#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29137#L504-3 assume !(1 == ~E_M~0); 29134#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29132#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29131#L519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29129#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29127#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 29124#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29123#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 27780#L709 assume !(0 == start_simulation_~tmp~3#1); 27782#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27732#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27631#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27632#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 29431#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29429#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29427#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 29426#L722 assume !(0 != start_simulation_~tmp___0~1#1); 27634#L690-2 [2024-11-13 15:07:33,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2024-11-13 15:07:33,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027122108] [2024-11-13 15:07:33,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:33,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,649 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:33,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1892370901, now seen corresponding path program 1 times [2024-11-13 15:07:33,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472975686] [2024-11-13 15:07:33,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:33,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:33,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:33,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472975686] [2024-11-13 15:07:33,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472975686] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:33,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:33,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:33,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986712321] [2024-11-13 15:07:33,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:33,695 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:07:33,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:33,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:33,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:33,697 INFO L87 Difference]: Start difference. First operand 2000 states and 2784 transitions. cyclomatic complexity: 788 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:33,775 INFO L93 Difference]: Finished difference Result 3084 states and 4220 transitions. [2024-11-13 15:07:33,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3084 states and 4220 transitions. [2024-11-13 15:07:33,792 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3008 [2024-11-13 15:07:33,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3084 states to 3084 states and 4220 transitions. [2024-11-13 15:07:33,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3084 [2024-11-13 15:07:33,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3084 [2024-11-13 15:07:33,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3084 states and 4220 transitions. [2024-11-13 15:07:33,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:33,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3084 states and 4220 transitions. [2024-11-13 15:07:33,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states and 4220 transitions. [2024-11-13 15:07:33,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 2982. [2024-11-13 15:07:33,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2982 states, 2982 states have (on average 1.3702213279678068) internal successors, (4086), 2981 states have internal predecessors, (4086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:33,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2982 states to 2982 states and 4086 transitions. [2024-11-13 15:07:33,921 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2982 states and 4086 transitions. [2024-11-13 15:07:33,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:33,922 INFO L424 stractBuchiCegarLoop]: Abstraction has 2982 states and 4086 transitions. [2024-11-13 15:07:33,922 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:07:33,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2982 states and 4086 transitions. [2024-11-13 15:07:33,932 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2906 [2024-11-13 15:07:33,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:33,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:33,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:33,933 INFO L745 eck$LassoCheckResult]: Stem: 32921#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 32922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 32933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32932#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 32829#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32666#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32667#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32852#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32676#L441 assume !(0 == ~M_E~0); 32677#L441-2 assume !(0 == ~T1_E~0); 32825#L446-1 assume !(0 == ~T2_E~0); 32786#L451-1 assume !(0 == ~T3_E~0); 32787#L456-1 assume !(0 == ~E_M~0); 32938#L461-1 assume !(0 == ~E_1~0); 32939#L466-1 assume !(0 == ~E_2~0); 32958#L471-1 assume !(0 == ~E_3~0); 32711#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32712#L220 assume !(1 == ~m_pc~0); 32746#L220-2 is_master_triggered_~__retres1~0#1 := 0; 32747#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32802#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32742#L543 assume !(0 != activate_threads_~tmp~1#1); 32743#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32920#L239 assume !(1 == ~t1_pc~0); 32918#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32919#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32709#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32710#L551 assume !(0 != activate_threads_~tmp___0~0#1); 32923#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32924#L258 assume !(1 == ~t2_pc~0); 32925#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32775#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32776#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32936#L559 assume !(0 != activate_threads_~tmp___1~0#1); 32839#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32840#L277 assume !(1 == ~t3_pc~0); 32889#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33005#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33007#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33006#L567 assume !(0 != activate_threads_~tmp___2~0#1); 32738#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32783#L489 assume !(1 == ~M_E~0); 32937#L489-2 assume !(1 == ~T1_E~0); 32864#L494-1 assume !(1 == ~T2_E~0); 32727#L499-1 assume !(1 == ~T3_E~0); 32728#L504-1 assume !(1 == ~E_M~0); 32830#L509-1 assume !(1 == ~E_1~0); 32715#L514-1 assume !(1 == ~E_2~0); 32716#L519-1 assume !(1 == ~E_3~0); 32722#L524-1 assume { :end_inline_reset_delta_events } true; 32685#L690-2 assume !false; 32686#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34741#L416-1 [2024-11-13 15:07:33,933 INFO L747 eck$LassoCheckResult]: Loop: 34741#L416-1 assume !false; 34742#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34734#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34735#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34728#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34729#L369 assume 0 != eval_~tmp~0#1; 34720#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 34721#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 32659#L377-2 havoc eval_~tmp_ndt_1~0#1; 32660#L374-1 assume !(0 == ~t1_st~0); 34751#L388-1 assume !(0 == ~t2_st~0); 34750#L402-1 assume !(0 == ~t3_st~0); 34741#L416-1 [2024-11-13 15:07:33,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976871, now seen corresponding path program 1 times [2024-11-13 15:07:33,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194858528] [2024-11-13 15:07:33,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,944 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:33,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:33,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1439702230, now seen corresponding path program 1 times [2024-11-13 15:07:33,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200886218] [2024-11-13 15:07:33,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,966 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:33,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:33,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:33,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:33,971 INFO L85 PathProgramCache]: Analyzing trace with hash -494078980, now seen corresponding path program 1 times [2024-11-13 15:07:33,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:33,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114003572] [2024-11-13 15:07:33,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:33,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:33,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:34,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:34,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:34,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114003572] [2024-11-13 15:07:34,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114003572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:34,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:34,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:34,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811802843] [2024-11-13 15:07:34,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:34,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:34,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:34,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:34,132 INFO L87 Difference]: Start difference. First operand 2982 states and 4086 transitions. cyclomatic complexity: 1110 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:34,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:34,227 INFO L93 Difference]: Finished difference Result 5388 states and 7293 transitions. [2024-11-13 15:07:34,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5388 states and 7293 transitions. [2024-11-13 15:07:34,254 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5242 [2024-11-13 15:07:34,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5388 states to 5388 states and 7293 transitions. [2024-11-13 15:07:34,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5388 [2024-11-13 15:07:34,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5388 [2024-11-13 15:07:34,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5388 states and 7293 transitions. [2024-11-13 15:07:34,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:34,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5388 states and 7293 transitions. [2024-11-13 15:07:34,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5388 states and 7293 transitions. [2024-11-13 15:07:34,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5388 to 5101. [2024-11-13 15:07:34,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5101 states, 5101 states have (on average 1.3597333856106646) internal successors, (6936), 5100 states have internal predecessors, (6936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:34,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5101 states to 5101 states and 6936 transitions. [2024-11-13 15:07:34,396 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5101 states and 6936 transitions. [2024-11-13 15:07:34,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:34,397 INFO L424 stractBuchiCegarLoop]: Abstraction has 5101 states and 6936 transitions. [2024-11-13 15:07:34,397 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:07:34,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5101 states and 6936 transitions. [2024-11-13 15:07:34,438 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4955 [2024-11-13 15:07:34,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:34,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:34,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:34,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:34,440 INFO L745 eck$LassoCheckResult]: Stem: 41306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 41307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41320#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41317#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41318#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 41214#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 41215#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42324#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42323#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42322#L441 assume !(0 == ~M_E~0); 42321#L441-2 assume !(0 == ~T1_E~0); 42320#L446-1 assume !(0 == ~T2_E~0); 42319#L451-1 assume !(0 == ~T3_E~0); 42318#L456-1 assume !(0 == ~E_M~0); 42317#L461-1 assume !(0 == ~E_1~0); 42316#L466-1 assume !(0 == ~E_2~0); 42315#L471-1 assume !(0 == ~E_3~0); 42314#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42313#L220 assume !(1 == ~m_pc~0); 42312#L220-2 is_master_triggered_~__retres1~0#1 := 0; 42311#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42310#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42309#L543 assume !(0 != activate_threads_~tmp~1#1); 42308#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42307#L239 assume !(1 == ~t1_pc~0); 42305#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42304#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42302#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41308#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41309#L258 assume !(1 == ~t2_pc~0); 41310#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41157#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41324#L559 assume !(0 != activate_threads_~tmp___1~0#1); 41225#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41226#L277 assume !(1 == ~t3_pc~0); 41275#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41387#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42291#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41390#L567 assume !(0 != activate_threads_~tmp___2~0#1); 41117#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41378#L489 assume !(1 == ~M_E~0); 41379#L489-2 assume !(1 == ~T1_E~0); 41254#L494-1 assume !(1 == ~T2_E~0); 41255#L499-1 assume !(1 == ~T3_E~0); 41216#L504-1 assume !(1 == ~E_M~0); 41217#L509-1 assume !(1 == ~E_1~0); 41094#L514-1 assume !(1 == ~E_2~0); 41095#L519-1 assume !(1 == ~E_3~0); 41100#L524-1 assume { :end_inline_reset_delta_events } true; 41101#L690-2 assume !false; 44756#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44748#L416-1 [2024-11-13 15:07:34,440 INFO L747 eck$LassoCheckResult]: Loop: 44748#L416-1 assume !false; 44741#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 44734#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 44716#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 44700#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44689#L369 assume 0 != eval_~tmp~0#1; 44665#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 43968#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 43969#L377-2 havoc eval_~tmp_ndt_1~0#1; 44771#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 44770#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 44768#L391-2 havoc eval_~tmp_ndt_2~0#1; 44766#L388-1 assume !(0 == ~t2_st~0); 44757#L402-1 assume !(0 == ~t3_st~0); 44748#L416-1 [2024-11-13 15:07:34,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:34,441 INFO L85 PathProgramCache]: Analyzing trace with hash -934376989, now seen corresponding path program 1 times [2024-11-13 15:07:34,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:34,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996365955] [2024-11-13 15:07:34,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:34,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:34,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:34,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:34,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:34,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996365955] [2024-11-13 15:07:34,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996365955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:34,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:34,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:34,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950776027] [2024-11-13 15:07:34,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:34,475 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:07:34,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:34,476 INFO L85 PathProgramCache]: Analyzing trace with hash 449013461, now seen corresponding path program 1 times [2024-11-13 15:07:34,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:34,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399614686] [2024-11-13 15:07:34,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:34,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:34,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,481 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:34,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:34,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:34,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:34,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:34,561 INFO L87 Difference]: Start difference. First operand 5101 states and 6936 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:34,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:34,592 INFO L93 Difference]: Finished difference Result 5049 states and 6864 transitions. [2024-11-13 15:07:34,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5049 states and 6864 transitions. [2024-11-13 15:07:34,613 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4955 [2024-11-13 15:07:34,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5049 states to 5049 states and 6864 transitions. [2024-11-13 15:07:34,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5049 [2024-11-13 15:07:34,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5049 [2024-11-13 15:07:34,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5049 states and 6864 transitions. [2024-11-13 15:07:34,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:34,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5049 states and 6864 transitions. [2024-11-13 15:07:34,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5049 states and 6864 transitions. [2024-11-13 15:07:34,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5049 to 5049. [2024-11-13 15:07:34,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5049 states, 5049 states have (on average 1.3594771241830066) internal successors, (6864), 5048 states have internal predecessors, (6864), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:34,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5049 states to 5049 states and 6864 transitions. [2024-11-13 15:07:34,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5049 states and 6864 transitions. [2024-11-13 15:07:34,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:34,768 INFO L424 stractBuchiCegarLoop]: Abstraction has 5049 states and 6864 transitions. [2024-11-13 15:07:34,768 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:07:34,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5049 states and 6864 transitions. [2024-11-13 15:07:34,784 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4955 [2024-11-13 15:07:34,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:34,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:34,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:34,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:34,785 INFO L745 eck$LassoCheckResult]: Stem: 51465#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 51466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51479#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51476#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51477#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 51369#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51203#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51204#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51391#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51211#L441 assume !(0 == ~M_E~0); 51212#L441-2 assume !(0 == ~T1_E~0); 51365#L446-1 assume !(0 == ~T2_E~0); 51325#L451-1 assume !(0 == ~T3_E~0); 51326#L456-1 assume !(0 == ~E_M~0); 51484#L461-1 assume !(0 == ~E_1~0); 51485#L466-1 assume !(0 == ~E_2~0); 51502#L471-1 assume !(0 == ~E_3~0); 51248#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51249#L220 assume !(1 == ~m_pc~0); 51282#L220-2 is_master_triggered_~__retres1~0#1 := 0; 51283#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51346#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51280#L543 assume !(0 != activate_threads_~tmp~1#1); 51281#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51464#L239 assume !(1 == ~t1_pc~0); 51462#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51463#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51244#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51245#L551 assume !(0 != activate_threads_~tmp___0~0#1); 51467#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51468#L258 assume !(1 == ~t2_pc~0); 51469#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51312#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51313#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51482#L559 assume !(0 != activate_threads_~tmp___1~0#1); 51379#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51380#L277 assume !(1 == ~t3_pc~0); 51431#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51552#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51554#L567 assume !(0 != activate_threads_~tmp___2~0#1); 51274#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51322#L489 assume !(1 == ~M_E~0); 51483#L489-2 assume !(1 == ~T1_E~0); 51407#L494-1 assume !(1 == ~T2_E~0); 51263#L499-1 assume !(1 == ~T3_E~0); 51264#L504-1 assume !(1 == ~E_M~0); 51370#L509-1 assume !(1 == ~E_1~0); 51252#L514-1 assume !(1 == ~E_2~0); 51253#L519-1 assume !(1 == ~E_3~0); 51257#L524-1 assume { :end_inline_reset_delta_events } true; 51258#L690-2 assume !false; 51976#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51971#L416-1 [2024-11-13 15:07:34,785 INFO L747 eck$LassoCheckResult]: Loop: 51971#L416-1 assume !false; 51966#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 51959#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 51954#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 51949#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51945#L369 assume 0 != eval_~tmp~0#1; 51935#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 51929#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 51924#L377-2 havoc eval_~tmp_ndt_1~0#1; 51900#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 51894#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 51889#L391-2 havoc eval_~tmp_ndt_2~0#1; 51883#L388-1 assume !(0 == ~t2_st~0); 51884#L402-1 assume !(0 == ~t3_st~0); 51971#L416-1 [2024-11-13 15:07:34,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:34,786 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976871, now seen corresponding path program 2 times [2024-11-13 15:07:34,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:34,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129835181] [2024-11-13 15:07:34,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:34,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:34,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,797 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:34,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:34,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:34,810 INFO L85 PathProgramCache]: Analyzing trace with hash 449013461, now seen corresponding path program 2 times [2024-11-13 15:07:34,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:34,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23554107] [2024-11-13 15:07:34,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:34,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:34,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,815 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:34,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:34,818 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:34,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:34,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1806109819, now seen corresponding path program 1 times [2024-11-13 15:07:34,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:34,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264323307] [2024-11-13 15:07:34,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:34,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:34,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:34,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:34,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:34,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264323307] [2024-11-13 15:07:34,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264323307] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:34,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:34,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:07:34,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354470759] [2024-11-13 15:07:34,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:34,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:34,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:34,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:34,969 INFO L87 Difference]: Start difference. First operand 5049 states and 6864 transitions. cyclomatic complexity: 1821 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:35,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:35,050 INFO L93 Difference]: Finished difference Result 5736 states and 7737 transitions. [2024-11-13 15:07:35,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5736 states and 7737 transitions. [2024-11-13 15:07:35,076 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5650 [2024-11-13 15:07:35,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5736 states to 5736 states and 7737 transitions. [2024-11-13 15:07:35,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5736 [2024-11-13 15:07:35,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5736 [2024-11-13 15:07:35,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5736 states and 7737 transitions. [2024-11-13 15:07:35,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:35,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5736 states and 7737 transitions. [2024-11-13 15:07:35,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5736 states and 7737 transitions. [2024-11-13 15:07:35,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5736 to 5540. [2024-11-13 15:07:35,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5540 states, 5540 states have (on average 1.353610108303249) internal successors, (7499), 5539 states have internal predecessors, (7499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:35,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5540 states to 5540 states and 7499 transitions. [2024-11-13 15:07:35,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5540 states and 7499 transitions. [2024-11-13 15:07:35,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:35,213 INFO L424 stractBuchiCegarLoop]: Abstraction has 5540 states and 7499 transitions. [2024-11-13 15:07:35,213 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:07:35,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5540 states and 7499 transitions. [2024-11-13 15:07:35,230 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5454 [2024-11-13 15:07:35,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:35,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:35,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:35,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:35,232 INFO L745 eck$LassoCheckResult]: Stem: 62254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 62255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 62268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62264#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62265#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 62165#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61998#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61999#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62188#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62006#L441 assume !(0 == ~M_E~0); 62007#L441-2 assume !(0 == ~T1_E~0); 62161#L446-1 assume !(0 == ~T2_E~0); 62123#L451-1 assume !(0 == ~T3_E~0); 62124#L456-1 assume !(0 == ~E_M~0); 62274#L461-1 assume !(0 == ~E_1~0); 62275#L466-1 assume !(0 == ~E_2~0); 62287#L471-1 assume !(0 == ~E_3~0); 62042#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62043#L220 assume !(1 == ~m_pc~0); 62077#L220-2 is_master_triggered_~__retres1~0#1 := 0; 62078#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62141#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62075#L543 assume !(0 != activate_threads_~tmp~1#1); 62076#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62253#L239 assume !(1 == ~t1_pc~0); 62251#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62252#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62038#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62039#L551 assume !(0 != activate_threads_~tmp___0~0#1); 62256#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62257#L258 assume !(1 == ~t2_pc~0); 62258#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62110#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62272#L559 assume !(0 != activate_threads_~tmp___1~0#1); 62175#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62176#L277 assume !(1 == ~t3_pc~0); 62223#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62333#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62336#L567 assume !(0 != activate_threads_~tmp___2~0#1); 62068#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62118#L489 assume !(1 == ~M_E~0); 62273#L489-2 assume !(1 == ~T1_E~0); 62203#L494-1 assume !(1 == ~T2_E~0); 62059#L499-1 assume !(1 == ~T3_E~0); 62060#L504-1 assume !(1 == ~E_M~0); 62166#L509-1 assume !(1 == ~E_1~0); 62045#L514-1 assume !(1 == ~E_2~0); 62046#L519-1 assume !(1 == ~E_3~0); 62051#L524-1 assume { :end_inline_reset_delta_events } true; 62052#L690-2 assume !false; 64391#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64386#L416-1 [2024-11-13 15:07:35,232 INFO L747 eck$LassoCheckResult]: Loop: 64386#L416-1 assume !false; 64387#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 64596#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 64377#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 64375#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64373#L369 assume 0 != eval_~tmp~0#1; 64374#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 64365#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 64366#L377-2 havoc eval_~tmp_ndt_1~0#1; 64106#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 64102#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 64099#L391-2 havoc eval_~tmp_ndt_2~0#1; 64100#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 64248#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 64249#L405-2 havoc eval_~tmp_ndt_3~0#1; 64601#L402-1 assume !(0 == ~t3_st~0); 64386#L416-1 [2024-11-13 15:07:35,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976871, now seen corresponding path program 3 times [2024-11-13 15:07:35,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819916025] [2024-11-13 15:07:35,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,244 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:35,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:35,257 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,257 INFO L85 PathProgramCache]: Analyzing trace with hash 2001193494, now seen corresponding path program 1 times [2024-11-13 15:07:35,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168405304] [2024-11-13 15:07:35,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,262 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:35,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:35,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,267 INFO L85 PathProgramCache]: Analyzing trace with hash 500735548, now seen corresponding path program 1 times [2024-11-13 15:07:35,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758953462] [2024-11-13 15:07:35,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:07:35,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:07:35,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:07:35,315 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758953462] [2024-11-13 15:07:35,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758953462] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:07:35,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:07:35,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:07:35,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8459482] [2024-11-13 15:07:35,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:07:35,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:07:35,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:07:35,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:07:35,399 INFO L87 Difference]: Start difference. First operand 5540 states and 7499 transitions. cyclomatic complexity: 1965 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:35,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:07:35,506 INFO L93 Difference]: Finished difference Result 9264 states and 12477 transitions. [2024-11-13 15:07:35,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9264 states and 12477 transitions. [2024-11-13 15:07:35,541 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9150 [2024-11-13 15:07:35,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9264 states to 9264 states and 12477 transitions. [2024-11-13 15:07:35,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9264 [2024-11-13 15:07:35,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9264 [2024-11-13 15:07:35,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9264 states and 12477 transitions. [2024-11-13 15:07:35,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:07:35,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9264 states and 12477 transitions. [2024-11-13 15:07:35,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9264 states and 12477 transitions. [2024-11-13 15:07:35,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9264 to 8958. [2024-11-13 15:07:35,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8958 states, 8958 states have (on average 1.3586738111185532) internal successors, (12171), 8957 states have internal predecessors, (12171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:07:35,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8958 states to 8958 states and 12171 transitions. [2024-11-13 15:07:35,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8958 states and 12171 transitions. [2024-11-13 15:07:35,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:07:35,807 INFO L424 stractBuchiCegarLoop]: Abstraction has 8958 states and 12171 transitions. [2024-11-13 15:07:35,807 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:07:35,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8958 states and 12171 transitions. [2024-11-13 15:07:35,844 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8844 [2024-11-13 15:07:35,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:07:35,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:07:35,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:35,845 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:07:35,846 INFO L745 eck$LassoCheckResult]: Stem: 77070#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 77071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 77082#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77080#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77081#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 76978#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76805#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76806#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76999#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76816#L441 assume !(0 == ~M_E~0); 76817#L441-2 assume !(0 == ~T1_E~0); 76974#L446-1 assume !(0 == ~T2_E~0); 76933#L451-1 assume !(0 == ~T3_E~0); 76934#L456-1 assume !(0 == ~E_M~0); 77089#L461-1 assume !(0 == ~E_1~0); 77090#L466-1 assume !(0 == ~E_2~0); 77108#L471-1 assume !(0 == ~E_3~0); 76849#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76850#L220 assume !(1 == ~m_pc~0); 76887#L220-2 is_master_triggered_~__retres1~0#1 := 0; 76888#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76949#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 76883#L543 assume !(0 != activate_threads_~tmp~1#1); 76884#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77069#L239 assume !(1 == ~t1_pc~0); 77067#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77068#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76847#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76848#L551 assume !(0 != activate_threads_~tmp___0~0#1); 77072#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77073#L258 assume !(1 == ~t2_pc~0); 77074#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76921#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77086#L559 assume !(0 != activate_threads_~tmp___1~0#1); 76987#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76988#L277 assume !(1 == ~t3_pc~0); 77036#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77157#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77162#L567 assume !(0 != activate_threads_~tmp___2~0#1); 76879#L567-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76930#L489 assume !(1 == ~M_E~0); 77087#L489-2 assume !(1 == ~T1_E~0); 77014#L494-1 assume !(1 == ~T2_E~0); 76868#L499-1 assume !(1 == ~T3_E~0); 76869#L504-1 assume !(1 == ~E_M~0); 76979#L509-1 assume !(1 == ~E_1~0); 76853#L514-1 assume !(1 == ~E_2~0); 76854#L519-1 assume !(1 == ~E_3~0); 76862#L524-1 assume { :end_inline_reset_delta_events } true; 76863#L690-2 assume !false; 82674#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82670#L416-1 [2024-11-13 15:07:35,846 INFO L747 eck$LassoCheckResult]: Loop: 82670#L416-1 assume !false; 82668#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 82663#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 82661#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 82659#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 82657#L369 assume 0 != eval_~tmp~0#1; 82653#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 82650#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 82649#L377-2 havoc eval_~tmp_ndt_1~0#1; 82648#L374-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 82512#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 82647#L391-2 havoc eval_~tmp_ndt_2~0#1; 82690#L388-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 82686#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 82687#L405-2 havoc eval_~tmp_ndt_3~0#1; 82682#L402-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 82679#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 82673#L419-2 havoc eval_~tmp_ndt_4~0#1; 82670#L416-1 [2024-11-13 15:07:35,847 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976871, now seen corresponding path program 4 times [2024-11-13 15:07:35,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122946426] [2024-11-13 15:07:35,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,861 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:35,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,877 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:35,877 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,877 INFO L85 PathProgramCache]: Analyzing trace with hash -998499371, now seen corresponding path program 1 times [2024-11-13 15:07:35,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926261967] [2024-11-13 15:07:35,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,883 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:35,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:35,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:07:35,889 INFO L85 PathProgramCache]: Analyzing trace with hash 170425979, now seen corresponding path program 1 times [2024-11-13 15:07:35,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:07:35,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224735721] [2024-11-13 15:07:35,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:07:35,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:07:35,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,905 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:35,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:35,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:07:37,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:37,314 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:07:37,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:07:37,520 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 03:07:37 BoogieIcfgContainer [2024-11-13 15:07:37,520 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 15:07:37,521 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 15:07:37,521 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 15:07:37,521 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 15:07:37,522 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:07:29" (3/4) ... [2024-11-13 15:07:37,524 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 15:07:37,646 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 15:07:37,646 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 15:07:37,647 INFO L158 Benchmark]: Toolchain (without parser) took 10129.77ms. Allocated memory was 117.4MB in the beginning and 251.7MB in the end (delta: 134.2MB). Free memory was 93.7MB in the beginning and 90.0MB in the end (delta: 3.7MB). Peak memory consumption was 138.7MB. Max. memory is 16.1GB. [2024-11-13 15:07:37,650 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 167.8MB. Free memory is still 104.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:07:37,651 INFO L158 Benchmark]: CACSL2BoogieTranslator took 368.48ms. Allocated memory is still 117.4MB. Free memory was 93.3MB in the beginning and 78.9MB in the end (delta: 14.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 15:07:37,651 INFO L158 Benchmark]: Boogie Procedure Inliner took 90.12ms. Allocated memory is still 117.4MB. Free memory was 78.9MB in the beginning and 75.7MB in the end (delta: 3.2MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:07:37,651 INFO L158 Benchmark]: Boogie Preprocessor took 82.75ms. Allocated memory is still 117.4MB. Free memory was 75.7MB in the beginning and 71.6MB in the end (delta: 4.1MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:07:37,652 INFO L158 Benchmark]: RCFGBuilder took 1250.70ms. Allocated memory is still 117.4MB. Free memory was 71.6MB in the beginning and 78.3MB in the end (delta: -6.8MB). Peak memory consumption was 49.6MB. Max. memory is 16.1GB. [2024-11-13 15:07:37,652 INFO L158 Benchmark]: BuchiAutomizer took 8206.91ms. Allocated memory was 117.4MB in the beginning and 251.7MB in the end (delta: 134.2MB). Free memory was 78.3MB in the beginning and 96.4MB in the end (delta: -18.0MB). Peak memory consumption was 115.8MB. Max. memory is 16.1GB. [2024-11-13 15:07:37,652 INFO L158 Benchmark]: Witness Printer took 125.19ms. Allocated memory is still 251.7MB. Free memory was 96.4MB in the beginning and 90.0MB in the end (delta: 6.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:07:37,656 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 167.8MB. Free memory is still 104.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 368.48ms. Allocated memory is still 117.4MB. Free memory was 93.3MB in the beginning and 78.9MB in the end (delta: 14.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 90.12ms. Allocated memory is still 117.4MB. Free memory was 78.9MB in the beginning and 75.7MB in the end (delta: 3.2MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 82.75ms. Allocated memory is still 117.4MB. Free memory was 75.7MB in the beginning and 71.6MB in the end (delta: 4.1MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 1250.70ms. Allocated memory is still 117.4MB. Free memory was 71.6MB in the beginning and 78.3MB in the end (delta: -6.8MB). Peak memory consumption was 49.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 8206.91ms. Allocated memory was 117.4MB in the beginning and 251.7MB in the end (delta: 134.2MB). Free memory was 78.3MB in the beginning and 96.4MB in the end (delta: -18.0MB). Peak memory consumption was 115.8MB. Max. memory is 16.1GB. * Witness Printer took 125.19ms. Allocated memory is still 251.7MB. Free memory was 96.4MB in the beginning and 90.0MB in the end (delta: 6.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8958 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.0s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 4.4s. Construction of modules took 0.7s. Büchi inclusion checks took 2.4s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 1.0s AutomataMinimizationTime, 16 MinimizatonAttempts, 2563 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6472 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6472 mSDsluCounter, 15727 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7568 mSDsCounter, 154 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 484 IncrementalHoareTripleChecker+Invalid, 638 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 154 mSolverCounterUnsat, 8159 mSDtfsCounter, 484 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 15:07:37,694 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f5f11a2-22d8-43a2-a3e6-2909f62decb8/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)