./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:01:13,502 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:01:13,581 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:01:13,587 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:01:13,588 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:01:13,627 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:01:13,628 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:01:13,628 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:01:13,629 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:01:13,629 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:01:13,631 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:01:13,631 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:01:13,631 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:01:13,632 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:01:13,632 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:01:13,632 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:01:13,633 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:01:13,633 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:01:13,634 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:01:13,635 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:01:13,635 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:01:13,635 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:01:13,635 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:01:13,635 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:01:13,636 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:01:13,636 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:01:13,636 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2024-11-13 15:01:13,923 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:01:13,933 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:01:13,937 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:01:13,938 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:01:13,939 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:01:13,941 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c Unable to find full path for "g++" [2024-11-13 15:01:15,856 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:01:16,122 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:01:16,125 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2024-11-13 15:01:16,135 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/data/9337718d8/f3a4c4378e0d41d9874506f340d69709/FLAGc49de982a [2024-11-13 15:01:16,149 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/data/9337718d8/f3a4c4378e0d41d9874506f340d69709 [2024-11-13 15:01:16,151 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:01:16,153 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:01:16,154 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:01:16,154 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:01:16,159 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:01:16,160 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,161 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@284bdf88 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16, skipping insertion in model container [2024-11-13 15:01:16,161 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,198 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:01:16,490 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:01:16,511 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:01:16,586 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:01:16,611 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:01:16,611 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16 WrapperNode [2024-11-13 15:01:16,612 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:01:16,613 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:01:16,613 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:01:16,613 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:01:16,619 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,633 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,701 INFO L138 Inliner]: procedures = 36, calls = 45, calls flagged for inlining = 40, calls inlined = 80, statements flattened = 1080 [2024-11-13 15:01:16,701 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:01:16,706 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:01:16,706 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:01:16,706 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:01:16,721 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,721 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,730 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,761 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:01:16,761 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,761 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,774 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,786 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,788 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,791 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,796 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:01:16,797 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:01:16,797 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:01:16,797 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:01:16,798 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (1/1) ... [2024-11-13 15:01:16,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:01:16,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:01:16,837 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:01:16,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:01:16,869 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:01:16,870 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:01:16,870 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:01:16,870 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:01:16,961 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:01:16,963 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:01:18,125 INFO L? ?]: Removed 198 outVars from TransFormulas that were not future-live. [2024-11-13 15:01:18,125 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:01:18,164 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:01:18,168 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-13 15:01:18,169 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:01:18 BoogieIcfgContainer [2024-11-13 15:01:18,169 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:01:18,170 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:01:18,170 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:01:18,176 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:01:18,177 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:01:18,177 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:01:16" (1/3) ... [2024-11-13 15:01:18,178 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552e145a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:01:18, skipping insertion in model container [2024-11-13 15:01:18,179 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:01:18,179 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:01:16" (2/3) ... [2024-11-13 15:01:18,180 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552e145a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:01:18, skipping insertion in model container [2024-11-13 15:01:18,180 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:01:18,180 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:01:18" (3/3) ... [2024-11-13 15:01:18,181 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2024-11-13 15:01:18,262 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:01:18,263 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:01:18,263 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:01:18,263 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:01:18,263 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:01:18,263 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:01:18,264 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:01:18,265 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:01:18,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:18,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2024-11-13 15:01:18,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:18,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:18,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:18,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:18,339 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:01:18,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:18,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2024-11-13 15:01:18,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:18,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:18,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:18,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:18,374 INFO L745 eck$LassoCheckResult]: Stem: 142#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 364#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 220#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 334#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 233#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 341#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 213#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195#L526true assume !(0 == ~M_E~0); 421#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 236#L531-1true assume !(0 == ~T2_E~0); 185#L536-1true assume !(0 == ~T3_E~0); 296#L541-1true assume !(0 == ~T4_E~0); 183#L546-1true assume !(0 == ~E_M~0); 248#L551-1true assume !(0 == ~E_1~0); 165#L556-1true assume !(0 == ~E_2~0); 192#L561-1true assume !(0 == ~E_3~0); 172#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 376#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168#L262true assume 1 == ~m_pc~0; 443#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 380#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 377#L649true assume !(0 != activate_threads_~tmp~1#1); 438#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129#L281true assume !(1 == ~t1_pc~0); 394#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 79#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 361#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L300true assume 1 == ~t2_pc~0; 308#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 274#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445#L319true assume !(1 == ~t3_pc~0); 17#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 277#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 27#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278#L338true assume 1 == ~t4_pc~0; 112#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 384#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 374#L584true assume !(1 == ~M_E~0); 113#L584-2true assume !(1 == ~T1_E~0); 88#L589-1true assume !(1 == ~T2_E~0); 262#L594-1true assume !(1 == ~T3_E~0); 144#L599-1true assume !(1 == ~T4_E~0); 16#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 125#L619-1true assume !(1 == ~E_3~0); 188#L624-1true assume !(1 == ~E_4~0); 401#L629-1true assume { :end_inline_reset_delta_events } true; 207#L815-2true [2024-11-13 15:01:18,379 INFO L747 eck$LassoCheckResult]: Loop: 207#L815-2true assume !false; 388#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L501-1true assume !true; 74#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 268#L526-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 75#L531-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 395#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 13#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 189#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 439#L551-3true assume !(0 == ~E_1~0); 154#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 243#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 318#L566-3true assume 0 == ~E_4~0;~E_4~0 := 1; 81#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 292#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#is_master_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 373#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163#L281-18true assume !(1 == ~t1_pc~0); 271#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 178#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 418#L657-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333#L300-18true assume !(1 == ~t2_pc~0); 14#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 255#L665-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 319#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80#L319-18true assume !(1 == ~t3_pc~0); 247#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 96#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 219#L673-18true assume !(0 != activate_threads_~tmp___2~0#1); 204#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128#L338-18true assume !(1 == ~t4_pc~0); 161#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179#L681-20true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 290#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 28#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume !(1 == ~T3_E~0); 216#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 156#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 406#L609-3true assume 1 == ~E_1~0;~E_1~0 := 2; 203#L614-3true assume 1 == ~E_2~0;~E_2~0 := 2; 24#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 214#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 249#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 257#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 199#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 101#L834true assume !(0 == start_simulation_~tmp~3#1); 223#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 355#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 295#L789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 205#L847true assume !(0 != start_simulation_~tmp___0~1#1); 207#L815-2true [2024-11-13 15:01:18,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:18,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2024-11-13 15:01:18,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:18,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095023709] [2024-11-13 15:01:18,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:18,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:18,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:18,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:18,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:18,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095023709] [2024-11-13 15:01:18,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095023709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:18,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:18,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:18,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672416050] [2024-11-13 15:01:18,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:18,715 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:18,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:18,717 INFO L85 PathProgramCache]: Analyzing trace with hash 306015160, now seen corresponding path program 1 times [2024-11-13 15:01:18,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:18,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365025967] [2024-11-13 15:01:18,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:18,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:18,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:18,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:18,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:18,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1365025967] [2024-11-13 15:01:18,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1365025967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:18,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:18,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:18,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [5459489] [2024-11-13 15:01:18,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:18,774 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:18,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:18,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:18,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:18,807 INFO L87 Difference]: Start difference. First operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:18,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:18,920 INFO L93 Difference]: Finished difference Result 441 states and 657 transitions. [2024-11-13 15:01:18,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 657 transitions. [2024-11-13 15:01:18,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:18,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 435 states and 651 transitions. [2024-11-13 15:01:18,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-11-13 15:01:18,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-11-13 15:01:18,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 651 transitions. [2024-11-13 15:01:18,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:18,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-11-13 15:01:18,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 651 transitions. [2024-11-13 15:01:19,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-13 15:01:19,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4965517241379311) internal successors, (651), 434 states have internal predecessors, (651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 651 transitions. [2024-11-13 15:01:19,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-11-13 15:01:19,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:19,029 INFO L424 stractBuchiCegarLoop]: Abstraction has 435 states and 651 transitions. [2024-11-13 15:01:19,029 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:01:19,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 651 transitions. [2024-11-13 15:01:19,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:19,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:19,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,036 INFO L745 eck$LassoCheckResult]: Stem: 1142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1235#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1236#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 993#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1244#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1205#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1206#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1230#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1215#L526 assume !(0 == ~M_E~0); 1216#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L531-1 assume !(0 == ~T2_E~0); 1201#L536-1 assume !(0 == ~T3_E~0); 1202#L541-1 assume !(0 == ~T4_E~0); 1197#L546-1 assume !(0 == ~E_M~0); 1198#L551-1 assume !(0 == ~E_1~0); 1173#L556-1 assume !(0 == ~E_2~0); 1174#L561-1 assume !(0 == ~E_3~0); 1184#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1185#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L262 assume 1 == ~m_pc~0; 1179#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1324#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1113#L649 assume !(0 != activate_threads_~tmp~1#1); 1323#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1122#L281 assume !(1 == ~t1_pc~0); 1123#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1043#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 960#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1099#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187#L300 assume 1 == ~t2_pc~0; 1188#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1277#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1209#L665 assume !(0 != activate_threads_~tmp___1~0#1); 972#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 973#L319 assume !(1 == ~t3_pc~0); 928#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 929#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916#L673 assume !(0 != activate_threads_~tmp___2~0#1); 949#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 950#L338 assume 1 == ~t4_pc~0; 1095#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1018#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L681 assume !(0 != activate_threads_~tmp___3~0#1); 895#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 896#L584 assume !(1 == ~M_E~0); 1096#L584-2 assume !(1 == ~T1_E~0); 1057#L589-1 assume !(1 == ~T2_E~0); 1058#L594-1 assume !(1 == ~T3_E~0); 1146#L599-1 assume !(1 == ~T4_E~0); 927#L604-1 assume !(1 == ~E_M~0); 913#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 914#L614-1 assume !(1 == ~E_2~0); 1032#L619-1 assume !(1 == ~E_3~0); 1114#L624-1 assume !(1 == ~E_4~0); 1207#L629-1 assume { :end_inline_reset_delta_events } true; 1226#L815-2 [2024-11-13 15:01:19,036 INFO L747 eck$LassoCheckResult]: Loop: 1226#L815-2 assume !false; 1227#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1104#L501-1 assume !false; 1320#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1321#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1038#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1251#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1252#L440 assume !(0 != eval_~tmp~0#1); 1033#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1034#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1148#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1035#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1036#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 921#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1208#L551-3 assume !(0 == ~E_1~0); 1159#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1160#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1256#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1047#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1048#L262-18 assume 1 == ~m_pc~0; 1271#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1136#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1153#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1154#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 934#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 935#L281-18 assume 1 == ~t1_pc~0; 1170#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1190#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1322#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1293#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1294#L300-18 assume 1 == ~t2_pc~0; 1168#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 924#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1233#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1262#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1044#L319-18 assume !(1 == ~t3_pc~0); 1045#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1050#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1071#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 1224#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119#L338-18 assume 1 == ~t4_pc~0; 1120#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1088#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1089#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 953#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 954#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1140#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1141#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 952#L594-3 assume !(1 == ~T3_E~0); 1133#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1163#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1223#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 943#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 944#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1231#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1260#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1026#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1078#L834 assume !(0 == start_simulation_~tmp~3#1); 1079#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1239#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1200#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 958#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1295#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1300#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1225#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1226#L815-2 [2024-11-13 15:01:19,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2024-11-13 15:01:19,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386711395] [2024-11-13 15:01:19,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386711395] [2024-11-13 15:01:19,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386711395] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598184194] [2024-11-13 15:01:19,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,170 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:19,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1261735066, now seen corresponding path program 1 times [2024-11-13 15:01:19,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969005565] [2024-11-13 15:01:19,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969005565] [2024-11-13 15:01:19,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969005565] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27440591] [2024-11-13 15:01:19,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,343 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:19,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:19,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:19,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:19,344 INFO L87 Difference]: Start difference. First operand 435 states and 651 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:19,373 INFO L93 Difference]: Finished difference Result 435 states and 650 transitions. [2024-11-13 15:01:19,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 650 transitions. [2024-11-13 15:01:19,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 650 transitions. [2024-11-13 15:01:19,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-11-13 15:01:19,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-11-13 15:01:19,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 650 transitions. [2024-11-13 15:01:19,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:19,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-11-13 15:01:19,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 650 transitions. [2024-11-13 15:01:19,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-13 15:01:19,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4942528735632183) internal successors, (650), 434 states have internal predecessors, (650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 650 transitions. [2024-11-13 15:01:19,412 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-11-13 15:01:19,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:19,413 INFO L424 stractBuchiCegarLoop]: Abstraction has 435 states and 650 transitions. [2024-11-13 15:01:19,413 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:01:19,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 650 transitions. [2024-11-13 15:01:19,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:19,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:19,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,417 INFO L745 eck$LassoCheckResult]: Stem: 2019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1869#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1870#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2121#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2082#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2083#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2107#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2092#L526 assume !(0 == ~M_E~0); 2093#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2123#L531-1 assume !(0 == ~T2_E~0); 2078#L536-1 assume !(0 == ~T3_E~0); 2079#L541-1 assume !(0 == ~T4_E~0); 2074#L546-1 assume !(0 == ~E_M~0); 2075#L551-1 assume !(0 == ~E_1~0); 2050#L556-1 assume !(0 == ~E_2~0); 2051#L561-1 assume !(0 == ~E_3~0); 2061#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2062#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2055#L262 assume 1 == ~m_pc~0; 2056#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2201#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1989#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1990#L649 assume !(0 != activate_threads_~tmp~1#1); 2200#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1999#L281 assume !(1 == ~t1_pc~0); 2000#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1920#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1837#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1976#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064#L300 assume 1 == ~t2_pc~0; 2065#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2154#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2086#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1849#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1850#L319 assume !(1 == ~t3_pc~0); 1805#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1806#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1793#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1826#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1827#L338 assume 1 == ~t4_pc~0; 1972#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1895#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1901#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1772#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1773#L584 assume !(1 == ~M_E~0); 1973#L584-2 assume !(1 == ~T1_E~0); 1934#L589-1 assume !(1 == ~T2_E~0); 1935#L594-1 assume !(1 == ~T3_E~0); 2023#L599-1 assume !(1 == ~T4_E~0); 1804#L604-1 assume !(1 == ~E_M~0); 1790#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1791#L614-1 assume !(1 == ~E_2~0); 1909#L619-1 assume !(1 == ~E_3~0); 1991#L624-1 assume !(1 == ~E_4~0); 2084#L629-1 assume { :end_inline_reset_delta_events } true; 2103#L815-2 [2024-11-13 15:01:19,418 INFO L747 eck$LassoCheckResult]: Loop: 2103#L815-2 assume !false; 2104#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1981#L501-1 assume !false; 2197#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2198#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1915#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2128#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2129#L440 assume !(0 != eval_~tmp~0#1); 1910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2024#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2025#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1912#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1913#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1798#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1799#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2085#L551-3 assume !(0 == ~E_1~0); 2036#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2037#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2133#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1924#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1925#L262-18 assume 1 == ~m_pc~0; 2148#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2013#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2030#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1811#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1812#L281-18 assume !(1 == ~t1_pc~0); 2048#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2067#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2068#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2199#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2170#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2171#L300-18 assume !(1 == ~t2_pc~0); 1800#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1801#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1868#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2110#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2139#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1921#L319-18 assume !(1 == ~t3_pc~0); 1922#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1927#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2111#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 2101#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1996#L338-18 assume 1 == ~t4_pc~0; 1997#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1965#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1966#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1830#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1831#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2017#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2018#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1828#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829#L594-3 assume !(1 == ~T3_E~0); 2010#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2039#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2040#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2100#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1820#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1821#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2108#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2137#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1903#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1955#L834 assume !(0 == start_simulation_~tmp~3#1); 1956#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2116#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2077#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1835#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2172#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2177#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2102#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2103#L815-2 [2024-11-13 15:01:19,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2024-11-13 15:01:19,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998112801] [2024-11-13 15:01:19,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998112801] [2024-11-13 15:01:19,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998112801] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595771546] [2024-11-13 15:01:19,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,475 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:19,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,475 INFO L85 PathProgramCache]: Analyzing trace with hash 654615336, now seen corresponding path program 1 times [2024-11-13 15:01:19,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784224787] [2024-11-13 15:01:19,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784224787] [2024-11-13 15:01:19,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784224787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90155771] [2024-11-13 15:01:19,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,586 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:19,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:19,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:19,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:19,587 INFO L87 Difference]: Start difference. First operand 435 states and 650 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:19,608 INFO L93 Difference]: Finished difference Result 435 states and 649 transitions. [2024-11-13 15:01:19,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 649 transitions. [2024-11-13 15:01:19,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 649 transitions. [2024-11-13 15:01:19,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-11-13 15:01:19,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-11-13 15:01:19,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 649 transitions. [2024-11-13 15:01:19,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:19,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-11-13 15:01:19,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 649 transitions. [2024-11-13 15:01:19,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-13 15:01:19,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4919540229885058) internal successors, (649), 434 states have internal predecessors, (649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 649 transitions. [2024-11-13 15:01:19,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-11-13 15:01:19,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:19,634 INFO L424 stractBuchiCegarLoop]: Abstraction has 435 states and 649 transitions. [2024-11-13 15:01:19,634 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:01:19,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 649 transitions. [2024-11-13 15:01:19,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:19,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:19,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,641 INFO L745 eck$LassoCheckResult]: Stem: 2896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2746#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2747#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2998#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2959#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2960#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2969#L526 assume !(0 == ~M_E~0); 2970#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3000#L531-1 assume !(0 == ~T2_E~0); 2955#L536-1 assume !(0 == ~T3_E~0); 2956#L541-1 assume !(0 == ~T4_E~0); 2951#L546-1 assume !(0 == ~E_M~0); 2952#L551-1 assume !(0 == ~E_1~0); 2927#L556-1 assume !(0 == ~E_2~0); 2928#L561-1 assume !(0 == ~E_3~0); 2938#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2939#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2932#L262 assume 1 == ~m_pc~0; 2933#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3078#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2867#L649 assume !(0 != activate_threads_~tmp~1#1); 3077#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2876#L281 assume !(1 == ~t1_pc~0); 2877#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2797#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2714#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2853#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2941#L300 assume 1 == ~t2_pc~0; 2942#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3031#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2963#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2726#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2727#L319 assume !(1 == ~t3_pc~0); 2682#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2683#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2670#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2703#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2704#L338 assume 1 == ~t4_pc~0; 2849#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2772#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2778#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2650#L584 assume !(1 == ~M_E~0); 2850#L584-2 assume !(1 == ~T1_E~0); 2811#L589-1 assume !(1 == ~T2_E~0); 2812#L594-1 assume !(1 == ~T3_E~0); 2900#L599-1 assume !(1 == ~T4_E~0); 2681#L604-1 assume !(1 == ~E_M~0); 2667#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2668#L614-1 assume !(1 == ~E_2~0); 2786#L619-1 assume !(1 == ~E_3~0); 2868#L624-1 assume !(1 == ~E_4~0); 2961#L629-1 assume { :end_inline_reset_delta_events } true; 2980#L815-2 [2024-11-13 15:01:19,642 INFO L747 eck$LassoCheckResult]: Loop: 2980#L815-2 assume !false; 2981#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2858#L501-1 assume !false; 3074#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3075#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2792#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3005#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3006#L440 assume !(0 != eval_~tmp~0#1); 2787#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2901#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2902#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2789#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2790#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2675#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2676#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2962#L551-3 assume !(0 == ~E_1~0); 2913#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2914#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3010#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2801#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2802#L262-18 assume 1 == ~m_pc~0; 3025#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2890#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2907#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2908#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2689#L281-18 assume 1 == ~t1_pc~0; 2924#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2944#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2945#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3076#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3047#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3048#L300-18 assume !(1 == ~t2_pc~0); 2677#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 2678#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2745#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2987#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3016#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2798#L319-18 assume 1 == ~t3_pc~0; 2800#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2804#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2825#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2988#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 2978#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2873#L338-18 assume 1 == ~t4_pc~0; 2874#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2842#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2843#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2707#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2708#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2894#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2895#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2705#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2706#L594-3 assume !(1 == ~T3_E~0); 2887#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2916#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2917#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2977#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2697#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2698#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2985#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3014#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2780#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2781#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2832#L834 assume !(0 == start_simulation_~tmp~3#1); 2833#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2954#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2712#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3049#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3054#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2979#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2980#L815-2 [2024-11-13 15:01:19,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,642 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2024-11-13 15:01:19,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085930920] [2024-11-13 15:01:19,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085930920] [2024-11-13 15:01:19,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085930920] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081310] [2024-11-13 15:01:19,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,732 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:19,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1496608422, now seen corresponding path program 1 times [2024-11-13 15:01:19,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412357349] [2024-11-13 15:01:19,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412357349] [2024-11-13 15:01:19,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412357349] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,815 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:19,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067357806] [2024-11-13 15:01:19,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,816 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:19,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:19,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:19,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:19,817 INFO L87 Difference]: Start difference. First operand 435 states and 649 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:19,842 INFO L93 Difference]: Finished difference Result 435 states and 648 transitions. [2024-11-13 15:01:19,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 648 transitions. [2024-11-13 15:01:19,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 648 transitions. [2024-11-13 15:01:19,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-11-13 15:01:19,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-11-13 15:01:19,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 648 transitions. [2024-11-13 15:01:19,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:19,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-11-13 15:01:19,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 648 transitions. [2024-11-13 15:01:19,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-13 15:01:19,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4896551724137932) internal successors, (648), 434 states have internal predecessors, (648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:19,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 648 transitions. [2024-11-13 15:01:19,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-11-13 15:01:19,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:19,867 INFO L424 stractBuchiCegarLoop]: Abstraction has 435 states and 648 transitions. [2024-11-13 15:01:19,867 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:01:19,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 648 transitions. [2024-11-13 15:01:19,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:19,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:19,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:19,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:19,874 INFO L745 eck$LassoCheckResult]: Stem: 3773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3875#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3836#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3837#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3861#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3846#L526 assume !(0 == ~M_E~0); 3847#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3877#L531-1 assume !(0 == ~T2_E~0); 3832#L536-1 assume !(0 == ~T3_E~0); 3833#L541-1 assume !(0 == ~T4_E~0); 3828#L546-1 assume !(0 == ~E_M~0); 3829#L551-1 assume !(0 == ~E_1~0); 3804#L556-1 assume !(0 == ~E_2~0); 3805#L561-1 assume !(0 == ~E_3~0); 3815#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3816#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L262 assume 1 == ~m_pc~0; 3810#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3955#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3743#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3744#L649 assume !(0 != activate_threads_~tmp~1#1); 3954#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3753#L281 assume !(1 == ~t1_pc~0); 3754#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3674#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3591#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3730#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3818#L300 assume 1 == ~t2_pc~0; 3819#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3908#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3603#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3604#L319 assume !(1 == ~t3_pc~0); 3559#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3560#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3546#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3547#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3580#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3581#L338 assume 1 == ~t4_pc~0; 3726#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3649#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3655#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3526#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3527#L584 assume !(1 == ~M_E~0); 3727#L584-2 assume !(1 == ~T1_E~0); 3688#L589-1 assume !(1 == ~T2_E~0); 3689#L594-1 assume !(1 == ~T3_E~0); 3777#L599-1 assume !(1 == ~T4_E~0); 3558#L604-1 assume !(1 == ~E_M~0); 3544#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3545#L614-1 assume !(1 == ~E_2~0); 3663#L619-1 assume !(1 == ~E_3~0); 3745#L624-1 assume !(1 == ~E_4~0); 3838#L629-1 assume { :end_inline_reset_delta_events } true; 3857#L815-2 [2024-11-13 15:01:19,874 INFO L747 eck$LassoCheckResult]: Loop: 3857#L815-2 assume !false; 3858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3735#L501-1 assume !false; 3951#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3952#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3669#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3883#L440 assume !(0 != eval_~tmp~0#1); 3664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3778#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3779#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3666#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3667#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3552#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3553#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3839#L551-3 assume !(0 == ~E_1~0); 3790#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3791#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3887#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3678#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3679#L262-18 assume !(1 == ~m_pc~0); 3766#L262-20 is_master_triggered_~__retres1~0#1 := 0; 3767#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3784#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3785#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3565#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3566#L281-18 assume 1 == ~t1_pc~0; 3801#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3821#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3822#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3953#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3924#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3925#L300-18 assume !(1 == ~t2_pc~0); 3554#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 3555#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3622#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3864#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3893#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3675#L319-18 assume !(1 == ~t3_pc~0); 3676#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3681#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3702#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3865#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 3855#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3750#L338-18 assume 1 == ~t4_pc~0; 3751#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3719#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3720#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3584#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3771#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3772#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3582#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3583#L594-3 assume !(1 == ~T3_E~0); 3764#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3793#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3794#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3854#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3574#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3575#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3862#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3891#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3657#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3658#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3709#L834 assume !(0 == start_simulation_~tmp~3#1); 3710#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3870#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3831#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3589#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3926#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3931#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3856#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3857#L815-2 [2024-11-13 15:01:19,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2024-11-13 15:01:19,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220203067] [2024-11-13 15:01:19,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:19,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:19,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:19,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220203067] [2024-11-13 15:01:19,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220203067] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:19,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:19,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:19,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933596999] [2024-11-13 15:01:19,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:19,967 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:19,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:19,967 INFO L85 PathProgramCache]: Analyzing trace with hash -2020688280, now seen corresponding path program 1 times [2024-11-13 15:01:19,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:19,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099029679] [2024-11-13 15:01:19,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:19,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:19,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099029679] [2024-11-13 15:01:20,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099029679] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:20,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703277194] [2024-11-13 15:01:20,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,018 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:20,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:20,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:20,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:20,019 INFO L87 Difference]: Start difference. First operand 435 states and 648 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:20,045 INFO L93 Difference]: Finished difference Result 435 states and 643 transitions. [2024-11-13 15:01:20,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 643 transitions. [2024-11-13 15:01:20,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:20,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 643 transitions. [2024-11-13 15:01:20,051 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2024-11-13 15:01:20,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2024-11-13 15:01:20,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 643 transitions. [2024-11-13 15:01:20,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:20,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-11-13 15:01:20,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 643 transitions. [2024-11-13 15:01:20,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-13 15:01:20,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4781609195402299) internal successors, (643), 434 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 643 transitions. [2024-11-13 15:01:20,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-11-13 15:01:20,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:20,063 INFO L424 stractBuchiCegarLoop]: Abstraction has 435 states and 643 transitions. [2024-11-13 15:01:20,063 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:01:20,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 643 transitions. [2024-11-13 15:01:20,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2024-11-13 15:01:20,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:20,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:20,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,067 INFO L745 eck$LassoCheckResult]: Stem: 4650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4500#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4501#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4753#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4713#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4714#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4739#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4723#L526 assume !(0 == ~M_E~0); 4724#L526-2 assume !(0 == ~T1_E~0); 4755#L531-1 assume !(0 == ~T2_E~0); 4709#L536-1 assume !(0 == ~T3_E~0); 4710#L541-1 assume !(0 == ~T4_E~0); 4705#L546-1 assume !(0 == ~E_M~0); 4706#L551-1 assume !(0 == ~E_1~0); 4681#L556-1 assume !(0 == ~E_2~0); 4682#L561-1 assume !(0 == ~E_3~0); 4692#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4693#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4686#L262 assume 1 == ~m_pc~0; 4687#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4832#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4620#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4621#L649 assume !(0 != activate_threads_~tmp~1#1); 4831#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4630#L281 assume !(1 == ~t1_pc~0); 4631#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4551#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4467#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4468#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4607#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4695#L300 assume 1 == ~t2_pc~0; 4696#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4785#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4746#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4717#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4480#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4481#L319 assume !(1 == ~t3_pc~0); 4436#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4437#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4424#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4457#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4458#L338 assume 1 == ~t4_pc~0; 4603#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4526#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4533#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4403#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L584 assume !(1 == ~M_E~0); 4604#L584-2 assume !(1 == ~T1_E~0); 4565#L589-1 assume !(1 == ~T2_E~0); 4566#L594-1 assume !(1 == ~T3_E~0); 4654#L599-1 assume !(1 == ~T4_E~0); 4435#L604-1 assume !(1 == ~E_M~0); 4421#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4422#L614-1 assume !(1 == ~E_2~0); 4540#L619-1 assume !(1 == ~E_3~0); 4622#L624-1 assume !(1 == ~E_4~0); 4715#L629-1 assume { :end_inline_reset_delta_events } true; 4734#L815-2 [2024-11-13 15:01:20,067 INFO L747 eck$LassoCheckResult]: Loop: 4734#L815-2 assume !false; 4735#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4612#L501-1 assume !false; 4828#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4829#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4546#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4759#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4760#L440 assume !(0 != eval_~tmp~0#1); 4541#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4655#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4656#L526-5 assume !(0 == ~T1_E~0); 4543#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4544#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4431#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4432#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4716#L551-3 assume !(0 == ~E_1~0); 4667#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4668#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4763#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4555#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L262-18 assume !(1 == ~m_pc~0); 4642#L262-20 is_master_triggered_~__retres1~0#1 := 0; 4643#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4661#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4662#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4442#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4443#L281-18 assume 1 == ~t1_pc~0; 4678#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4698#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4699#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4830#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4801#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4802#L300-18 assume 1 == ~t2_pc~0; 4676#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4430#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4741#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4770#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4552#L319-18 assume !(1 == ~t3_pc~0); 4553#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4558#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4579#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 4732#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4627#L338-18 assume 1 == ~t4_pc~0; 4628#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4596#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4597#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4461#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4462#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4648#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4649#L584-5 assume !(1 == ~T1_E~0); 4459#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4460#L594-3 assume !(1 == ~T3_E~0); 4641#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4670#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4671#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4731#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4451#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4452#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4738#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4768#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4534#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4586#L834 assume !(0 == start_simulation_~tmp~3#1); 4587#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4747#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4708#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4465#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4466#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4803#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4808#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4733#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4734#L815-2 [2024-11-13 15:01:20,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2024-11-13 15:01:20,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770760328] [2024-11-13 15:01:20,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770760328] [2024-11-13 15:01:20,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770760328] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:20,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213731774] [2024-11-13 15:01:20,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,182 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:20,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1734055449, now seen corresponding path program 1 times [2024-11-13 15:01:20,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53542842] [2024-11-13 15:01:20,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53542842] [2024-11-13 15:01:20,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53542842] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:20,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801908345] [2024-11-13 15:01:20,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,237 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:20,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:20,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:01:20,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:01:20,238 INFO L87 Difference]: Start difference. First operand 435 states and 643 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:20,413 INFO L93 Difference]: Finished difference Result 730 states and 1076 transitions. [2024-11-13 15:01:20,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 1076 transitions. [2024-11-13 15:01:20,418 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2024-11-13 15:01:20,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 730 states and 1076 transitions. [2024-11-13 15:01:20,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 730 [2024-11-13 15:01:20,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 730 [2024-11-13 15:01:20,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 730 states and 1076 transitions. [2024-11-13 15:01:20,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:20,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 730 states and 1076 transitions. [2024-11-13 15:01:20,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states and 1076 transitions. [2024-11-13 15:01:20,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 729. [2024-11-13 15:01:20,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.4746227709190671) internal successors, (1075), 728 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1075 transitions. [2024-11-13 15:01:20,446 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1075 transitions. [2024-11-13 15:01:20,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:01:20,448 INFO L424 stractBuchiCegarLoop]: Abstraction has 729 states and 1075 transitions. [2024-11-13 15:01:20,451 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:01:20,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1075 transitions. [2024-11-13 15:01:20,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2024-11-13 15:01:20,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:20,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:20,456 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,457 INFO L745 eck$LassoCheckResult]: Stem: 5825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5675#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5676#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5931#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5888#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5889#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5914#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5898#L526 assume !(0 == ~M_E~0); 5899#L526-2 assume !(0 == ~T1_E~0); 5933#L531-1 assume !(0 == ~T2_E~0); 5884#L536-1 assume !(0 == ~T3_E~0); 5885#L541-1 assume !(0 == ~T4_E~0); 5880#L546-1 assume !(0 == ~E_M~0); 5881#L551-1 assume !(0 == ~E_1~0); 5856#L556-1 assume !(0 == ~E_2~0); 5857#L561-1 assume !(0 == ~E_3~0); 5867#L566-1 assume !(0 == ~E_4~0); 5868#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5861#L262 assume 1 == ~m_pc~0; 5862#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6017#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5795#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5796#L649 assume !(0 != activate_threads_~tmp~1#1); 6016#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5805#L281 assume !(1 == ~t1_pc~0); 5806#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5726#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5643#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5782#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5870#L300 assume 1 == ~t2_pc~0; 5871#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5966#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5892#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5655#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5656#L319 assume !(1 == ~t3_pc~0); 5611#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5612#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5599#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5632#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5633#L338 assume 1 == ~t4_pc~0; 5778#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5701#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5707#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5708#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5578#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5579#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6015#L584-2 assume !(1 == ~T1_E~0); 6123#L589-1 assume !(1 == ~T2_E~0); 6115#L594-1 assume !(1 == ~T3_E~0); 5829#L599-1 assume !(1 == ~T4_E~0); 5610#L604-1 assume !(1 == ~E_M~0); 5596#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5597#L614-1 assume !(1 == ~E_2~0); 5715#L619-1 assume !(1 == ~E_3~0); 5797#L624-1 assume !(1 == ~E_4~0); 5890#L629-1 assume { :end_inline_reset_delta_events } true; 5909#L815-2 [2024-11-13 15:01:20,457 INFO L747 eck$LassoCheckResult]: Loop: 5909#L815-2 assume !false; 5910#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5787#L501-1 assume !false; 6012#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6013#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5721#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5937#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5938#L440 assume !(0 != eval_~tmp~0#1); 6021#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6027#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6025#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6026#L526-5 assume !(0 == ~T1_E~0); 6246#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6245#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6244#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6243#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6242#L551-3 assume !(0 == ~E_1~0); 6241#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6240#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6239#L566-3 assume !(0 == ~E_4~0); 6238#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6237#L262-18 assume !(1 == ~m_pc~0); 6235#L262-20 is_master_triggered_~__retres1~0#1 := 0; 6234#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6233#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6232#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6231#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6230#L281-18 assume 1 == ~t1_pc~0; 6228#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6227#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6226#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6225#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5982#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5983#L300-18 assume !(1 == ~t2_pc~0); 5604#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 5605#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5674#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5916#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5950#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5727#L319-18 assume !(1 == ~t3_pc~0); 5728#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5733#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5754#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5917#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 5907#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5802#L338-18 assume 1 == ~t4_pc~0; 5803#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5771#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5772#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5636#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5637#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5822#L584-5 assume !(1 == ~T1_E~0); 5634#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L594-3 assume !(1 == ~T3_E~0); 5816#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5844#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5845#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5906#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5626#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5627#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5913#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5946#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5709#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5710#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5761#L834 assume !(0 == start_simulation_~tmp~3#1); 5762#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5923#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5883#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5641#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5984#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5992#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5908#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5909#L815-2 [2024-11-13 15:01:20,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,459 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2024-11-13 15:01:20,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282186830] [2024-11-13 15:01:20,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1282186830] [2024-11-13 15:01:20,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1282186830] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:20,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788095840] [2024-11-13 15:01:20,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,523 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:20,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,523 INFO L85 PathProgramCache]: Analyzing trace with hash -832444758, now seen corresponding path program 1 times [2024-11-13 15:01:20,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488882712] [2024-11-13 15:01:20,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488882712] [2024-11-13 15:01:20,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488882712] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:20,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501376112] [2024-11-13 15:01:20,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,566 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:20,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:20,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:20,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:20,567 INFO L87 Difference]: Start difference. First operand 729 states and 1075 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:20,649 INFO L93 Difference]: Finished difference Result 1354 states and 1970 transitions. [2024-11-13 15:01:20,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1354 states and 1970 transitions. [2024-11-13 15:01:20,677 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2024-11-13 15:01:20,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1354 states to 1354 states and 1970 transitions. [2024-11-13 15:01:20,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1354 [2024-11-13 15:01:20,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1354 [2024-11-13 15:01:20,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1354 states and 1970 transitions. [2024-11-13 15:01:20,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:20,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1354 states and 1970 transitions. [2024-11-13 15:01:20,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1354 states and 1970 transitions. [2024-11-13 15:01:20,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1354 to 1286. [2024-11-13 15:01:20,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1286 states, 1286 states have (on average 1.4587869362363919) internal successors, (1876), 1285 states have internal predecessors, (1876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:20,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1286 states to 1286 states and 1876 transitions. [2024-11-13 15:01:20,724 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2024-11-13 15:01:20,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:20,726 INFO L424 stractBuchiCegarLoop]: Abstraction has 1286 states and 1876 transitions. [2024-11-13 15:01:20,726 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:01:20,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1286 states and 1876 transitions. [2024-11-13 15:01:20,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1206 [2024-11-13 15:01:20,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:20,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:20,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:20,735 INFO L745 eck$LassoCheckResult]: Stem: 7928#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8025#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8026#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7768#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7769#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8041#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7992#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7993#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8019#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8003#L526 assume !(0 == ~M_E~0); 8004#L526-2 assume !(0 == ~T1_E~0); 8043#L531-1 assume !(0 == ~T2_E~0); 7988#L536-1 assume !(0 == ~T3_E~0); 7989#L541-1 assume !(0 == ~T4_E~0); 7984#L546-1 assume !(0 == ~E_M~0); 7985#L551-1 assume !(0 == ~E_1~0); 7961#L556-1 assume !(0 == ~E_2~0); 7962#L561-1 assume !(0 == ~E_3~0); 7971#L566-1 assume !(0 == ~E_4~0); 7972#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7966#L262 assume !(1 == ~m_pc~0); 7967#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8147#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7896#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7897#L649 assume !(0 != activate_threads_~tmp~1#1); 8145#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7906#L281 assume !(1 == ~t1_pc~0); 7907#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7821#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7733#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7734#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7881#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L300 assume 1 == ~t2_pc~0; 7975#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8080#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7997#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7746#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7747#L319 assume !(1 == ~t3_pc~0); 7701#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7702#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7689#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7723#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7724#L338 assume 1 == ~t4_pc~0; 7877#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7794#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7801#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7668#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7669#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 8144#L584-2 assume !(1 == ~T1_E~0); 8953#L589-1 assume !(1 == ~T2_E~0); 8952#L594-1 assume !(1 == ~T3_E~0); 8951#L599-1 assume !(1 == ~T4_E~0); 8950#L604-1 assume !(1 == ~E_M~0); 8949#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8948#L614-1 assume !(1 == ~E_2~0); 8947#L619-1 assume !(1 == ~E_3~0); 8946#L624-1 assume !(1 == ~E_4~0); 7994#L629-1 assume { :end_inline_reset_delta_events } true; 8015#L815-2 [2024-11-13 15:01:20,735 INFO L747 eck$LassoCheckResult]: Loop: 8015#L815-2 assume !false; 8016#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8172#L501-1 assume !false; 8173#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8181#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7815#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8176#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8167#L440 assume !(0 != eval_~tmp~0#1); 8169#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8945#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8944#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8943#L526-5 assume !(0 == ~T1_E~0); 8942#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8941#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8940#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8939#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8938#L551-3 assume !(0 == ~E_1~0); 8937#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8936#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8935#L566-3 assume !(0 == ~E_4~0); 8934#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8933#L262-18 assume !(1 == ~m_pc~0); 8932#L262-20 is_master_triggered_~__retres1~0#1 := 0; 8931#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8930#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8929#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8928#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8927#L281-18 assume 1 == ~t1_pc~0; 8925#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8924#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8923#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8922#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8921#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8920#L300-18 assume !(1 == ~t2_pc~0); 8918#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 8917#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8916#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8915#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8914#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8913#L319-18 assume !(1 == ~t3_pc~0); 8912#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 8910#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8909#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8908#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 8907#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8906#L338-18 assume 1 == ~t4_pc~0; 8904#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8903#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8902#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8901#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8900#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8899#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7926#L584-5 assume !(1 == ~T1_E~0); 8898#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8897#L594-3 assume !(1 == ~T3_E~0); 8896#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8895#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8894#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8893#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8892#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8891#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8020#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8890#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8885#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8884#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8883#L834 assume !(0 == start_simulation_~tmp~3#1); 7914#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8031#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8764#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8763#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 8762#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8761#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8760#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 8758#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8015#L815-2 [2024-11-13 15:01:20,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,736 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2024-11-13 15:01:20,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336075113] [2024-11-13 15:01:20,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336075113] [2024-11-13 15:01:20,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336075113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:01:20,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652006601] [2024-11-13 15:01:20,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,806 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:20,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:20,806 INFO L85 PathProgramCache]: Analyzing trace with hash -832444758, now seen corresponding path program 2 times [2024-11-13 15:01:20,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:20,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553501696] [2024-11-13 15:01:20,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:20,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:20,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:20,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:20,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:20,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553501696] [2024-11-13 15:01:20,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553501696] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:20,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:20,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:20,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61479856] [2024-11-13 15:01:20,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:20,859 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:20,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:20,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:01:20,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:01:20,859 INFO L87 Difference]: Start difference. First operand 1286 states and 1876 transitions. cyclomatic complexity: 594 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:21,067 INFO L93 Difference]: Finished difference Result 1355 states and 1945 transitions. [2024-11-13 15:01:21,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1355 states and 1945 transitions. [2024-11-13 15:01:21,077 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2024-11-13 15:01:21,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1355 states to 1355 states and 1945 transitions. [2024-11-13 15:01:21,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1355 [2024-11-13 15:01:21,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1355 [2024-11-13 15:01:21,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1355 states and 1945 transitions. [2024-11-13 15:01:21,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:21,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-11-13 15:01:21,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states and 1945 transitions. [2024-11-13 15:01:21,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 1355. [2024-11-13 15:01:21,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1355 states, 1355 states have (on average 1.4354243542435425) internal successors, (1945), 1354 states have internal predecessors, (1945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1945 transitions. [2024-11-13 15:01:21,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-11-13 15:01:21,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:01:21,159 INFO L424 stractBuchiCegarLoop]: Abstraction has 1355 states and 1945 transitions. [2024-11-13 15:01:21,161 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:01:21,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1355 states and 1945 transitions. [2024-11-13 15:01:21,167 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2024-11-13 15:01:21,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:21,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:21,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,169 INFO L745 eck$LassoCheckResult]: Stem: 10575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10670#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10671#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10416#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 10417#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10682#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10639#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10640#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10665#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10649#L526 assume !(0 == ~M_E~0); 10650#L526-2 assume !(0 == ~T1_E~0); 10684#L531-1 assume !(0 == ~T2_E~0); 10635#L536-1 assume !(0 == ~T3_E~0); 10636#L541-1 assume !(0 == ~T4_E~0); 10631#L546-1 assume !(0 == ~E_M~0); 10632#L551-1 assume !(0 == ~E_1~0); 10608#L556-1 assume !(0 == ~E_2~0); 10609#L561-1 assume !(0 == ~E_3~0); 10618#L566-1 assume !(0 == ~E_4~0); 10619#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10613#L262 assume !(1 == ~m_pc~0); 10614#L262-2 is_master_triggered_~__retres1~0#1 := 0; 10797#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10546#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10547#L649 assume !(0 != activate_threads_~tmp~1#1); 10795#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10556#L281 assume !(1 == ~t1_pc~0); 10557#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10470#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10384#L657 assume !(0 != activate_threads_~tmp___0~0#1); 10531#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10621#L300 assume 1 == ~t2_pc~0; 10622#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10719#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10675#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10643#L665 assume !(0 != activate_threads_~tmp___1~0#1); 10396#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10397#L319 assume !(1 == ~t3_pc~0); 10352#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10353#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10339#L673 assume !(0 != activate_threads_~tmp___2~0#1); 10373#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10374#L338 assume 1 == ~t4_pc~0; 10527#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10444#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10450#L681 assume !(0 != activate_threads_~tmp___3~0#1); 10318#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10319#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 10794#L584-2 assume !(1 == ~T1_E~0); 11132#L589-1 assume !(1 == ~T2_E~0); 11131#L594-1 assume !(1 == ~T3_E~0); 11130#L599-1 assume !(1 == ~T4_E~0); 11103#L604-1 assume !(1 == ~E_M~0); 10336#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10337#L614-1 assume !(1 == ~E_2~0); 10458#L619-1 assume !(1 == ~E_3~0); 10548#L624-1 assume !(1 == ~E_4~0); 10641#L629-1 assume { :end_inline_reset_delta_events } true; 10661#L815-2 [2024-11-13 15:01:21,169 INFO L747 eck$LassoCheckResult]: Loop: 10661#L815-2 assume !false; 10662#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10536#L501-1 assume !false; 10814#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11062#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11057#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11056#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11055#L440 assume !(0 != eval_~tmp~0#1); 11054#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11049#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11048#L526-5 assume !(0 == ~T1_E~0); 11046#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11045#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11044#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11043#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11042#L551-3 assume !(0 == ~E_1~0); 11041#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11040#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11039#L566-3 assume !(0 == ~E_4~0); 11038#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10711#L262-18 assume !(1 == ~m_pc~0); 10568#L262-20 is_master_triggered_~__retres1~0#1 := 0; 10569#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10588#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10589#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10358#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10359#L281-18 assume 1 == ~t1_pc~0; 10605#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10800#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11620#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11619#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10739#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10740#L300-18 assume !(1 == ~t2_pc~0); 10346#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 10347#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10415#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10668#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10701#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10471#L319-18 assume !(1 == ~t3_pc~0); 10472#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 10478#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10501#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10669#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 10659#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10553#L338-18 assume 1 == ~t4_pc~0; 10554#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10519#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10520#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10377#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10378#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10573#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10574#L584-5 assume !(1 == ~T1_E~0); 10375#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10376#L594-3 assume !(1 == ~T3_E~0); 10566#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10596#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10597#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10658#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10369#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10370#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10666#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10698#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10514#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11547#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 10508#L834 assume !(0 == start_simulation_~tmp~3#1); 10509#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10676#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11124#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 11122#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10748#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10749#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 10660#L847 assume !(0 != start_simulation_~tmp___0~1#1); 10661#L815-2 [2024-11-13 15:01:21,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:21,170 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2024-11-13 15:01:21,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:21,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627104055] [2024-11-13 15:01:21,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:21,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:21,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:21,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:21,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:21,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627104055] [2024-11-13 15:01:21,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627104055] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:21,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:21,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:21,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815415369] [2024-11-13 15:01:21,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:21,245 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:21,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:21,245 INFO L85 PathProgramCache]: Analyzing trace with hash -832444758, now seen corresponding path program 3 times [2024-11-13 15:01:21,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:21,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022483961] [2024-11-13 15:01:21,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:21,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:21,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:21,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:21,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:21,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022483961] [2024-11-13 15:01:21,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022483961] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:21,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:21,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:21,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957873064] [2024-11-13 15:01:21,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:21,292 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:21,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:21,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:21,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:21,292 INFO L87 Difference]: Start difference. First operand 1355 states and 1945 transitions. cyclomatic complexity: 594 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:21,378 INFO L93 Difference]: Finished difference Result 2450 states and 3494 transitions. [2024-11-13 15:01:21,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2450 states and 3494 transitions. [2024-11-13 15:01:21,397 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2356 [2024-11-13 15:01:21,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2450 states to 2450 states and 3494 transitions. [2024-11-13 15:01:21,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2450 [2024-11-13 15:01:21,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2450 [2024-11-13 15:01:21,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2450 states and 3494 transitions. [2024-11-13 15:01:21,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:21,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2450 states and 3494 transitions. [2024-11-13 15:01:21,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2450 states and 3494 transitions. [2024-11-13 15:01:21,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2450 to 2442. [2024-11-13 15:01:21,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2442 states, 2442 states have (on average 1.4275184275184276) internal successors, (3486), 2441 states have internal predecessors, (3486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2442 states to 2442 states and 3486 transitions. [2024-11-13 15:01:21,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2024-11-13 15:01:21,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:21,507 INFO L424 stractBuchiCegarLoop]: Abstraction has 2442 states and 3486 transitions. [2024-11-13 15:01:21,507 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:01:21,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2442 states and 3486 transitions. [2024-11-13 15:01:21,520 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2348 [2024-11-13 15:01:21,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:21,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:21,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,522 INFO L745 eck$LassoCheckResult]: Stem: 14389#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 14390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14498#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14499#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14227#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 14228#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14511#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14456#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14457#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14492#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14471#L526 assume !(0 == ~M_E~0); 14472#L526-2 assume !(0 == ~T1_E~0); 14513#L531-1 assume !(0 == ~T2_E~0); 14452#L536-1 assume !(0 == ~T3_E~0); 14453#L541-1 assume !(0 == ~T4_E~0); 14448#L546-1 assume !(0 == ~E_M~0); 14449#L551-1 assume !(0 == ~E_1~0); 14424#L556-1 assume !(0 == ~E_2~0); 14425#L561-1 assume !(0 == ~E_3~0); 14434#L566-1 assume !(0 == ~E_4~0); 14435#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14429#L262 assume !(1 == ~m_pc~0); 14430#L262-2 is_master_triggered_~__retres1~0#1 := 0; 14644#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14356#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14357#L649 assume !(0 != activate_threads_~tmp~1#1); 14643#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14367#L281 assume !(1 == ~t1_pc~0); 14368#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14282#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14193#L657 assume !(0 != activate_threads_~tmp___0~0#1); 14340#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14437#L300 assume !(1 == ~t2_pc~0); 14438#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14558#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14503#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14461#L665 assume !(0 != activate_threads_~tmp___1~0#1); 14205#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14206#L319 assume !(1 == ~t3_pc~0); 14161#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14162#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14149#L673 assume !(0 != activate_threads_~tmp___2~0#1); 14182#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14183#L338 assume 1 == ~t4_pc~0; 14336#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14254#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14261#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14262#L681 assume !(0 != activate_threads_~tmp___3~0#1); 14130#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14131#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 14337#L584-2 assume !(1 == ~T1_E~0); 14297#L589-1 assume !(1 == ~T2_E~0); 14298#L594-1 assume !(1 == ~T3_E~0); 14395#L599-1 assume !(1 == ~T4_E~0); 14396#L604-1 assume !(1 == ~E_M~0); 16153#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14269#L614-1 assume !(1 == ~E_2~0); 14270#L619-1 assume !(1 == ~E_3~0); 14458#L624-1 assume !(1 == ~E_4~0); 14459#L629-1 assume { :end_inline_reset_delta_events } true; 16135#L815-2 [2024-11-13 15:01:21,522 INFO L747 eck$LassoCheckResult]: Loop: 16135#L815-2 assume !false; 16090#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15243#L501-1 assume !false; 15244#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15051#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15045#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15043#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15041#L440 assume !(0 != eval_~tmp~0#1); 15042#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15258#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15254#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15255#L526-5 assume !(0 == ~T1_E~0); 16534#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14651#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14156#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14157#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14460#L551-3 assume !(0 == ~E_1~0); 14408#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14409#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16447#L566-3 assume !(0 == ~E_4~0); 16446#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16445#L262-18 assume !(1 == ~m_pc~0); 16444#L262-20 is_master_triggered_~__retres1~0#1 := 0; 16403#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16402#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16401#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16400#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16399#L281-18 assume !(1 == ~t1_pc~0); 16396#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 16394#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16393#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16392#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 16390#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16389#L300-18 assume !(1 == ~t2_pc~0); 16388#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 16382#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16380#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16378#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16376#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16374#L319-18 assume 1 == ~t3_pc~0; 16371#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16369#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16367#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16366#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 15309#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15304#L338-18 assume 1 == ~t4_pc~0; 15305#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16240#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16239#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16238#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15292#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15293#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15291#L584-5 assume !(1 == ~T1_E~0); 16234#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15280#L594-3 assume !(1 == ~T3_E~0); 15281#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15274#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15275#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14479#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14480#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14490#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14491#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14531#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16195#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16194#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16193#L834 assume !(0 == start_simulation_~tmp~3#1); 16192#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16187#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16183#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16181#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 16179#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16177#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16175#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 16142#L847 assume !(0 != start_simulation_~tmp___0~1#1); 16135#L815-2 [2024-11-13 15:01:21,522 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:21,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2024-11-13 15:01:21,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:21,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517797820] [2024-11-13 15:01:21,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:21,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:21,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:21,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:21,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:21,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517797820] [2024-11-13 15:01:21,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517797820] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:21,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:21,570 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:21,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129067937] [2024-11-13 15:01:21,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:21,571 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:21,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:21,571 INFO L85 PathProgramCache]: Analyzing trace with hash -379762004, now seen corresponding path program 1 times [2024-11-13 15:01:21,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:21,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290744057] [2024-11-13 15:01:21,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:21,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:21,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:21,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:21,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:21,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290744057] [2024-11-13 15:01:21,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290744057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:21,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:21,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:21,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622790811] [2024-11-13 15:01:21,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:21,617 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:21,618 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:21,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:21,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:21,618 INFO L87 Difference]: Start difference. First operand 2442 states and 3486 transitions. cyclomatic complexity: 1052 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:21,725 INFO L93 Difference]: Finished difference Result 4453 states and 6327 transitions. [2024-11-13 15:01:21,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4453 states and 6327 transitions. [2024-11-13 15:01:21,761 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4328 [2024-11-13 15:01:21,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4453 states to 4453 states and 6327 transitions. [2024-11-13 15:01:21,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4453 [2024-11-13 15:01:21,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4453 [2024-11-13 15:01:21,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4453 states and 6327 transitions. [2024-11-13 15:01:21,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:21,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4453 states and 6327 transitions. [2024-11-13 15:01:21,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4453 states and 6327 transitions. [2024-11-13 15:01:21,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4453 to 4437. [2024-11-13 15:01:21,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4437 states, 4437 states have (on average 1.422357448726617) internal successors, (6311), 4436 states have internal predecessors, (6311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:21,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4437 states to 4437 states and 6311 transitions. [2024-11-13 15:01:21,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2024-11-13 15:01:21,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:21,907 INFO L424 stractBuchiCegarLoop]: Abstraction has 4437 states and 6311 transitions. [2024-11-13 15:01:21,908 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:01:21,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4437 states and 6311 transitions. [2024-11-13 15:01:21,968 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4312 [2024-11-13 15:01:21,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:21,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:21,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:21,970 INFO L745 eck$LassoCheckResult]: Stem: 21285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 21286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21383#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21128#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 21129#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21394#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21350#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21351#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21377#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21361#L526 assume !(0 == ~M_E~0); 21362#L526-2 assume !(0 == ~T1_E~0); 21396#L531-1 assume !(0 == ~T2_E~0); 21346#L536-1 assume !(0 == ~T3_E~0); 21347#L541-1 assume !(0 == ~T4_E~0); 21342#L546-1 assume !(0 == ~E_M~0); 21343#L551-1 assume !(0 == ~E_1~0); 21320#L556-1 assume !(0 == ~E_2~0); 21321#L561-1 assume !(0 == ~E_3~0); 21330#L566-1 assume !(0 == ~E_4~0); 21331#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21325#L262 assume !(1 == ~m_pc~0); 21326#L262-2 is_master_triggered_~__retres1~0#1 := 0; 21507#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21255#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21256#L649 assume !(0 != activate_threads_~tmp~1#1); 21503#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21265#L281 assume !(1 == ~t1_pc~0); 21266#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21180#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21094#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21095#L657 assume !(0 != activate_threads_~tmp___0~0#1); 21237#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21333#L300 assume !(1 == ~t2_pc~0); 21334#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21434#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21355#L665 assume !(0 != activate_threads_~tmp___1~0#1); 21107#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21108#L319 assume !(1 == ~t3_pc~0); 21063#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21064#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21050#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21051#L673 assume !(0 != activate_threads_~tmp___2~0#1); 21084#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21085#L338 assume !(1 == ~t4_pc~0); 21153#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21154#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21159#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21160#L681 assume !(0 != activate_threads_~tmp___3~0#1); 21032#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21033#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 21234#L584-2 assume !(1 == ~T1_E~0); 21194#L589-1 assume !(1 == ~T2_E~0); 21195#L594-1 assume !(1 == ~T3_E~0); 21289#L599-1 assume !(1 == ~T4_E~0); 21290#L604-1 assume !(1 == ~E_M~0); 22651#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 22648#L614-1 assume !(1 == ~E_2~0); 22646#L619-1 assume !(1 == ~E_3~0); 22644#L624-1 assume !(1 == ~E_4~0); 21352#L629-1 assume { :end_inline_reset_delta_events } true; 22625#L815-2 [2024-11-13 15:01:21,970 INFO L747 eck$LassoCheckResult]: Loop: 22625#L815-2 assume !false; 22365#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22364#L501-1 assume !false; 22363#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22362#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22357#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22356#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22354#L440 assume !(0 != eval_~tmp~0#1); 22355#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23652#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23650#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23648#L526-5 assume !(0 == ~T1_E~0); 23645#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23644#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23643#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23642#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23641#L551-3 assume !(0 == ~E_1~0); 23640#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23639#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23638#L566-3 assume !(0 == ~E_4~0); 23636#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23634#L262-18 assume !(1 == ~m_pc~0); 23633#L262-20 is_master_triggered_~__retres1~0#1 := 0; 23632#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23630#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23628#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23626#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23624#L281-18 assume 1 == ~t1_pc~0; 23621#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23619#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23617#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23612#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23610#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23607#L300-18 assume !(1 == ~t2_pc~0); 23605#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 23603#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23600#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23598#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23596#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23594#L319-18 assume 1 == ~t3_pc~0; 23591#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23589#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23586#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23584#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 23582#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23580#L338-18 assume !(1 == ~t4_pc~0); 23578#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 23576#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23574#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23572#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23570#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23568#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22837#L584-5 assume !(1 == ~T1_E~0); 23563#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23561#L594-3 assume !(1 == ~T3_E~0); 23559#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23558#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23557#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23556#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23555#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23554#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22820#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23553#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23548#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23547#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 23049#L834 assume !(0 == start_simulation_~tmp~3#1); 23045#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23028#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23021#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23017#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 23012#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23006#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23002#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 22627#L847 assume !(0 != start_simulation_~tmp___0~1#1); 22625#L815-2 [2024-11-13 15:01:21,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:21,971 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2024-11-13 15:01:21,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:21,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070173575] [2024-11-13 15:01:21,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:21,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:21,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:22,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:22,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:22,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070173575] [2024-11-13 15:01:22,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070173575] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:22,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:22,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:22,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609712936] [2024-11-13 15:01:22,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:22,023 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:22,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:22,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1439398762, now seen corresponding path program 1 times [2024-11-13 15:01:22,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:22,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186988959] [2024-11-13 15:01:22,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:22,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:22,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:22,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:22,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:22,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186988959] [2024-11-13 15:01:22,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186988959] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:22,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:22,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:22,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007447259] [2024-11-13 15:01:22,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:22,062 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:22,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:22,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:22,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:22,063 INFO L87 Difference]: Start difference. First operand 4437 states and 6311 transitions. cyclomatic complexity: 1890 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:22,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:22,135 INFO L93 Difference]: Finished difference Result 6648 states and 9441 transitions. [2024-11-13 15:01:22,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6648 states and 9441 transitions. [2024-11-13 15:01:22,177 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6508 [2024-11-13 15:01:22,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6648 states to 6648 states and 9441 transitions. [2024-11-13 15:01:22,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6648 [2024-11-13 15:01:22,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6648 [2024-11-13 15:01:22,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6648 states and 9441 transitions. [2024-11-13 15:01:22,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:22,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6648 states and 9441 transitions. [2024-11-13 15:01:22,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6648 states and 9441 transitions. [2024-11-13 15:01:22,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6648 to 4815. [2024-11-13 15:01:22,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4815 states, 4815 states have (on average 1.4188992731048806) internal successors, (6832), 4814 states have internal predecessors, (6832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:22,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4815 states to 4815 states and 6832 transitions. [2024-11-13 15:01:22,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2024-11-13 15:01:22,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:22,377 INFO L424 stractBuchiCegarLoop]: Abstraction has 4815 states and 6832 transitions. [2024-11-13 15:01:22,377 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:01:22,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4815 states and 6832 transitions. [2024-11-13 15:01:22,398 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4700 [2024-11-13 15:01:22,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:22,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:22,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:22,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:22,400 INFO L745 eck$LassoCheckResult]: Stem: 32376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 32377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32477#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32478#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32221#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 32222#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32488#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32442#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32443#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32471#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32453#L526 assume !(0 == ~M_E~0); 32454#L526-2 assume !(0 == ~T1_E~0); 32491#L531-1 assume !(0 == ~T2_E~0); 32438#L536-1 assume !(0 == ~T3_E~0); 32439#L541-1 assume !(0 == ~T4_E~0); 32434#L546-1 assume !(0 == ~E_M~0); 32435#L551-1 assume !(0 == ~E_1~0); 32411#L556-1 assume !(0 == ~E_2~0); 32412#L561-1 assume !(0 == ~E_3~0); 32421#L566-1 assume !(0 == ~E_4~0); 32422#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32416#L262 assume !(1 == ~m_pc~0); 32417#L262-2 is_master_triggered_~__retres1~0#1 := 0; 32617#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32347#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32348#L649 assume !(0 != activate_threads_~tmp~1#1); 32614#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32357#L281 assume !(1 == ~t1_pc~0); 32358#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32275#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32186#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32187#L657 assume !(0 != activate_threads_~tmp___0~0#1); 32332#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32424#L300 assume !(1 == ~t2_pc~0); 32425#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32527#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32482#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32446#L665 assume !(0 != activate_threads_~tmp___1~0#1); 32199#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32200#L319 assume !(1 == ~t3_pc~0); 32155#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32156#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32143#L673 assume !(0 != activate_threads_~tmp___2~0#1); 32176#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32177#L338 assume !(1 == ~t4_pc~0); 32247#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32248#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32253#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32254#L681 assume !(0 != activate_threads_~tmp___3~0#1); 32124#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32125#L584 assume !(1 == ~M_E~0); 32329#L584-2 assume !(1 == ~T1_E~0); 32290#L589-1 assume !(1 == ~T2_E~0); 32291#L594-1 assume !(1 == ~T3_E~0); 32380#L599-1 assume !(1 == ~T4_E~0); 32154#L604-1 assume !(1 == ~E_M~0); 32140#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32141#L614-1 assume !(1 == ~E_2~0); 32264#L619-1 assume !(1 == ~E_3~0); 32349#L624-1 assume !(1 == ~E_4~0); 32444#L629-1 assume { :end_inline_reset_delta_events } true; 32626#L815-2 [2024-11-13 15:01:22,400 INFO L747 eck$LassoCheckResult]: Loop: 32626#L815-2 assume !false; 35715#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35713#L501-1 assume !false; 35711#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35686#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35680#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35674#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35668#L440 assume !(0 != eval_~tmp~0#1); 35669#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36293#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36290#L526-3 assume !(0 == ~M_E~0); 36288#L526-5 assume !(0 == ~T1_E~0); 36286#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36284#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36282#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36280#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36265#L551-3 assume !(0 == ~E_1~0); 36258#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36254#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36250#L566-3 assume !(0 == ~E_4~0); 36226#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36225#L262-18 assume !(1 == ~m_pc~0); 36224#L262-20 is_master_triggered_~__retres1~0#1 := 0; 36223#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36222#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36221#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36220#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36218#L281-18 assume !(1 == ~t1_pc~0); 36215#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 36214#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36212#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36210#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 36208#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36207#L300-18 assume !(1 == ~t2_pc~0); 36206#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 36204#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36202#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36200#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36198#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36196#L319-18 assume 1 == ~t3_pc~0; 36193#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36191#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36188#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36186#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 36184#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36181#L338-18 assume !(1 == ~t4_pc~0); 36179#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36177#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36176#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36173#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36171#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36169#L584-3 assume !(1 == ~M_E~0); 33266#L584-5 assume !(1 == ~T1_E~0); 36166#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36164#L594-3 assume !(1 == ~T3_E~0); 36161#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36120#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36115#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36063#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36053#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36035#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34952#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 32822#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 32792#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 32786#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 32719#L834 assume !(0 == start_simulation_~tmp~3#1); 32721#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35848#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35840#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 35828#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35822#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35817#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 35803#L847 assume !(0 != start_simulation_~tmp___0~1#1); 32626#L815-2 [2024-11-13 15:01:22,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:22,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2024-11-13 15:01:22,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:22,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455082677] [2024-11-13 15:01:22,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:22,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:22,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:22,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:22,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:22,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455082677] [2024-11-13 15:01:22,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455082677] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:22,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:22,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:22,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715073959] [2024-11-13 15:01:22,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:22,461 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:22,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:22,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1083699373, now seen corresponding path program 1 times [2024-11-13 15:01:22,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:22,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448814449] [2024-11-13 15:01:22,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:22,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:22,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:22,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:22,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:22,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448814449] [2024-11-13 15:01:22,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448814449] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:22,500 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:22,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:22,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255474307] [2024-11-13 15:01:22,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:22,500 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:22,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:22,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:01:22,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:01:22,501 INFO L87 Difference]: Start difference. First operand 4815 states and 6832 transitions. cyclomatic complexity: 2025 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:22,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:22,696 INFO L93 Difference]: Finished difference Result 6567 states and 9149 transitions. [2024-11-13 15:01:22,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6567 states and 9149 transitions. [2024-11-13 15:01:22,731 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6350 [2024-11-13 15:01:22,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6567 states to 6567 states and 9149 transitions. [2024-11-13 15:01:22,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6567 [2024-11-13 15:01:22,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6567 [2024-11-13 15:01:22,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6567 states and 9149 transitions. [2024-11-13 15:01:22,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:22,824 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6567 states and 9149 transitions. [2024-11-13 15:01:22,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6567 states and 9149 transitions. [2024-11-13 15:01:22,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6567 to 5402. [2024-11-13 15:01:22,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5402 states, 5402 states have (on average 1.4009626064420584) internal successors, (7568), 5401 states have internal predecessors, (7568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:22,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5402 states to 5402 states and 7568 transitions. [2024-11-13 15:01:22,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2024-11-13 15:01:22,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:01:22,951 INFO L424 stractBuchiCegarLoop]: Abstraction has 5402 states and 7568 transitions. [2024-11-13 15:01:22,951 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:01:22,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5402 states and 7568 transitions. [2024-11-13 15:01:22,975 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5244 [2024-11-13 15:01:22,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:22,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:22,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:22,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:22,978 INFO L745 eck$LassoCheckResult]: Stem: 43768#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 43769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43873#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43613#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 43614#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43885#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43835#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43836#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43867#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43845#L526 assume !(0 == ~M_E~0); 43846#L526-2 assume !(0 == ~T1_E~0); 43888#L531-1 assume !(0 == ~T2_E~0); 43831#L536-1 assume !(0 == ~T3_E~0); 43832#L541-1 assume !(0 == ~T4_E~0); 43827#L546-1 assume !(0 == ~E_M~0); 43828#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43906#L556-1 assume !(0 == ~E_2~0); 44078#L561-1 assume !(0 == ~E_3~0); 44077#L566-1 assume !(0 == ~E_4~0); 44001#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43807#L262 assume !(1 == ~m_pc~0); 43808#L262-2 is_master_triggered_~__retres1~0#1 := 0; 44006#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43739#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43740#L649 assume !(0 != activate_threads_~tmp~1#1); 44002#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44071#L281 assume !(1 == ~t1_pc~0); 44070#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44069#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44063#L657 assume !(0 != activate_threads_~tmp___0~0#1); 44062#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44061#L300 assume !(1 == ~t2_pc~0); 44060#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44059#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44057#L665 assume !(0 != activate_threads_~tmp___1~0#1); 44056#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44055#L319 assume !(1 == ~t3_pc~0); 44053#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44052#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44051#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44050#L673 assume !(0 != activate_threads_~tmp___2~0#1); 44049#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44048#L338 assume !(1 == ~t4_pc~0); 44047#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44046#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44045#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44044#L681 assume !(0 != activate_threads_~tmp___3~0#1); 44043#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44042#L584 assume !(1 == ~M_E~0); 44041#L584-2 assume !(1 == ~T1_E~0); 44040#L589-1 assume !(1 == ~T2_E~0); 44039#L594-1 assume !(1 == ~T3_E~0); 44038#L599-1 assume !(1 == ~T4_E~0); 44037#L604-1 assume !(1 == ~E_M~0); 44036#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43533#L614-1 assume !(1 == ~E_2~0); 43654#L619-1 assume !(1 == ~E_3~0); 43741#L624-1 assume !(1 == ~E_4~0); 43837#L629-1 assume { :end_inline_reset_delta_events } true; 43860#L815-2 [2024-11-13 15:01:22,978 INFO L747 eck$LassoCheckResult]: Loop: 43860#L815-2 assume !false; 43862#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43848#L501-1 assume !false; 43994#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43995#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43660#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43893#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43894#L440 assume !(0 != eval_~tmp~0#1); 43655#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43656#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43773#L526-3 assume !(0 == ~M_E~0); 43774#L526-5 assume !(0 == ~T1_E~0); 43657#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43658#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43540#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43541#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43838#L551-3 assume !(0 == ~E_1~0); 44034#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48917#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48916#L566-3 assume !(0 == ~E_4~0); 48915#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48914#L262-18 assume !(1 == ~m_pc~0); 48913#L262-20 is_master_triggered_~__retres1~0#1 := 0; 48912#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48911#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48910#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48909#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48908#L281-18 assume !(1 == ~t1_pc~0); 48837#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 48904#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43997#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43998#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 43948#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43949#L300-18 assume !(1 == ~t2_pc~0); 48898#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 48897#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48896#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48895#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48894#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48893#L319-18 assume 1 == ~t3_pc~0; 48891#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48890#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48889#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48888#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 48887#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48886#L338-18 assume !(1 == ~t4_pc~0); 48885#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 48884#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48882#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48880#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48878#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48876#L584-3 assume !(1 == ~M_E~0); 48533#L584-5 assume !(1 == ~T1_E~0); 48853#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48850#L594-3 assume !(1 == ~T3_E~0); 43869#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43789#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 43790#L609-3 assume !(1 == ~E_1~0); 43857#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43562#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43563#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43868#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43907#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43646#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43647#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 43701#L834 assume !(0 == start_simulation_~tmp~3#1); 43702#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43878#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43830#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43577#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 43578#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43950#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43956#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 43859#L847 assume !(0 != start_simulation_~tmp___0~1#1); 43860#L815-2 [2024-11-13 15:01:22,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:22,979 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2024-11-13 15:01:22,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:22,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881548806] [2024-11-13 15:01:22,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:22,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:22,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:23,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:23,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:23,064 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881548806] [2024-11-13 15:01:23,064 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881548806] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:23,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:23,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:23,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126487679] [2024-11-13 15:01:23,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:23,065 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:23,065 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:23,066 INFO L85 PathProgramCache]: Analyzing trace with hash -504648529, now seen corresponding path program 1 times [2024-11-13 15:01:23,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:23,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801273159] [2024-11-13 15:01:23,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:23,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:23,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:23,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:23,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:23,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801273159] [2024-11-13 15:01:23,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [801273159] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:23,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:23,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:23,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489197312] [2024-11-13 15:01:23,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:23,116 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:23,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:23,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:01:23,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:01:23,117 INFO L87 Difference]: Start difference. First operand 5402 states and 7568 transitions. cyclomatic complexity: 2174 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:23,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:23,239 INFO L93 Difference]: Finished difference Result 5518 states and 7683 transitions. [2024-11-13 15:01:23,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5518 states and 7683 transitions. [2024-11-13 15:01:23,268 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5382 [2024-11-13 15:01:23,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5518 states to 5518 states and 7683 transitions. [2024-11-13 15:01:23,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5518 [2024-11-13 15:01:23,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5518 [2024-11-13 15:01:23,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5518 states and 7683 transitions. [2024-11-13 15:01:23,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:23,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5518 states and 7683 transitions. [2024-11-13 15:01:23,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5518 states and 7683 transitions. [2024-11-13 15:01:23,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5518 to 4596. [2024-11-13 15:01:23,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.3962140992167102) internal successors, (6417), 4595 states have internal predecessors, (6417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:23,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6417 transitions. [2024-11-13 15:01:23,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2024-11-13 15:01:23,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:01:23,431 INFO L424 stractBuchiCegarLoop]: Abstraction has 4596 states and 6417 transitions. [2024-11-13 15:01:23,431 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:01:23,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6417 transitions. [2024-11-13 15:01:23,449 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2024-11-13 15:01:23,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:23,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:23,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:23,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:23,451 INFO L745 eck$LassoCheckResult]: Stem: 54700#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 54701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 54800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54544#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 54545#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54814#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54766#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54767#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54796#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54778#L526 assume !(0 == ~M_E~0); 54779#L526-2 assume !(0 == ~T1_E~0); 54816#L531-1 assume !(0 == ~T2_E~0); 54762#L536-1 assume !(0 == ~T3_E~0); 54763#L541-1 assume !(0 == ~T4_E~0); 54758#L546-1 assume !(0 == ~E_M~0); 54759#L551-1 assume !(0 == ~E_1~0); 54736#L556-1 assume !(0 == ~E_2~0); 54737#L561-1 assume !(0 == ~E_3~0); 54746#L566-1 assume !(0 == ~E_4~0); 54747#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54741#L262 assume !(1 == ~m_pc~0); 54742#L262-2 is_master_triggered_~__retres1~0#1 := 0; 54923#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54668#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54669#L649 assume !(0 != activate_threads_~tmp~1#1); 54922#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54677#L281 assume !(1 == ~t1_pc~0); 54678#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54595#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54510#L657 assume !(0 != activate_threads_~tmp___0~0#1); 54652#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54749#L300 assume !(1 == ~t2_pc~0); 54750#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54849#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54770#L665 assume !(0 != activate_threads_~tmp___1~0#1); 54522#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54523#L319 assume !(1 == ~t3_pc~0); 54477#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54478#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54464#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54465#L673 assume !(0 != activate_threads_~tmp___2~0#1); 54499#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54500#L338 assume !(1 == ~t4_pc~0); 54568#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54569#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54575#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54576#L681 assume !(0 != activate_threads_~tmp___3~0#1); 54446#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54447#L584 assume !(1 == ~M_E~0); 54649#L584-2 assume !(1 == ~T1_E~0); 54610#L589-1 assume !(1 == ~T2_E~0); 54611#L594-1 assume !(1 == ~T3_E~0); 54706#L599-1 assume !(1 == ~T4_E~0); 54476#L604-1 assume !(1 == ~E_M~0); 54462#L609-1 assume !(1 == ~E_1~0); 54463#L614-1 assume !(1 == ~E_2~0); 54583#L619-1 assume !(1 == ~E_3~0); 54670#L624-1 assume !(1 == ~E_4~0); 54768#L629-1 assume { :end_inline_reset_delta_events } true; 54790#L815-2 [2024-11-13 15:01:23,451 INFO L747 eck$LassoCheckResult]: Loop: 54790#L815-2 assume !false; 54791#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54658#L501-1 assume !false; 54913#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54914#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54589#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54820#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54821#L440 assume !(0 != eval_~tmp~0#1); 54586#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54587#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54704#L526-3 assume !(0 == ~M_E~0); 54705#L526-5 assume !(0 == ~T1_E~0); 54584#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54585#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54470#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54471#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54769#L551-3 assume !(0 == ~E_1~0); 54719#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54720#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54825#L566-3 assume !(0 == ~E_4~0); 54599#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54600#L262-18 assume !(1 == ~m_pc~0); 54692#L262-20 is_master_triggered_~__retres1~0#1 := 0; 54693#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54712#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54713#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54483#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54484#L281-18 assume !(1 == ~t1_pc~0); 54734#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 54751#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54752#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54917#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 54869#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54870#L300-18 assume !(1 == ~t2_pc~0); 54472#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 54473#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54543#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54798#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54832#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54596#L319-18 assume !(1 == ~t3_pc~0); 54597#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 54602#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54623#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54799#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 54788#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54675#L338-18 assume !(1 == ~t4_pc~0); 54676#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 59041#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59040#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59039#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59038#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59037#L584-3 assume !(1 == ~M_E~0); 57292#L584-5 assume !(1 == ~T1_E~0); 59036#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54689#L594-3 assume !(1 == ~T3_E~0); 54690#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54722#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54723#L609-3 assume !(1 == ~E_1~0); 54787#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54492#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54493#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54795#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54829#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54636#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58921#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 57352#L834 assume !(0 == start_simulation_~tmp~3#1); 54686#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54806#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54761#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54507#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 54508#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54871#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54877#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 54789#L847 assume !(0 != start_simulation_~tmp___0~1#1); 54790#L815-2 [2024-11-13 15:01:23,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:23,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2024-11-13 15:01:23,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:23,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51288869] [2024-11-13 15:01:23,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:23,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:23,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:23,465 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:23,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:23,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:23,514 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:23,515 INFO L85 PathProgramCache]: Analyzing trace with hash 546800560, now seen corresponding path program 1 times [2024-11-13 15:01:23,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:23,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990126893] [2024-11-13 15:01:23,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:23,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:23,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:23,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:23,561 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:23,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990126893] [2024-11-13 15:01:23,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990126893] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:23,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:23,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:23,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714036340] [2024-11-13 15:01:23,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:23,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:23,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:23,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:23,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:23,563 INFO L87 Difference]: Start difference. First operand 4596 states and 6417 transitions. cyclomatic complexity: 1829 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:23,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:23,669 INFO L93 Difference]: Finished difference Result 5351 states and 7432 transitions. [2024-11-13 15:01:23,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5351 states and 7432 transitions. [2024-11-13 15:01:23,689 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5196 [2024-11-13 15:01:23,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5351 states to 5351 states and 7432 transitions. [2024-11-13 15:01:23,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5351 [2024-11-13 15:01:23,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5351 [2024-11-13 15:01:23,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5351 states and 7432 transitions. [2024-11-13 15:01:23,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:23,721 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5351 states and 7432 transitions. [2024-11-13 15:01:23,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5351 states and 7432 transitions. [2024-11-13 15:01:23,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5351 to 5351. [2024-11-13 15:01:23,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5351 states, 5351 states have (on average 1.3888992711642683) internal successors, (7432), 5350 states have internal predecessors, (7432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:23,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 7432 transitions. [2024-11-13 15:01:23,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5351 states and 7432 transitions. [2024-11-13 15:01:23,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:23,809 INFO L424 stractBuchiCegarLoop]: Abstraction has 5351 states and 7432 transitions. [2024-11-13 15:01:23,809 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:01:23,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5351 states and 7432 transitions. [2024-11-13 15:01:23,824 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5196 [2024-11-13 15:01:23,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:23,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:23,826 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:23,826 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:23,826 INFO L745 eck$LassoCheckResult]: Stem: 64652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64753#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64754#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64496#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 64497#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64764#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64719#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64720#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64748#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64732#L526 assume !(0 == ~M_E~0); 64733#L526-2 assume !(0 == ~T1_E~0); 64766#L531-1 assume !(0 == ~T2_E~0); 64714#L536-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64715#L541-1 assume !(0 == ~T4_E~0); 64710#L546-1 assume !(0 == ~E_M~0); 64711#L551-1 assume !(0 == ~E_1~0); 64687#L556-1 assume !(0 == ~E_2~0); 64688#L561-1 assume !(0 == ~E_3~0); 64697#L566-1 assume !(0 == ~E_4~0); 64698#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64692#L262 assume !(1 == ~m_pc~0); 64693#L262-2 is_master_triggered_~__retres1~0#1 := 0; 64876#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64619#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64620#L649 assume !(0 != activate_threads_~tmp~1#1); 64899#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64629#L281 assume !(1 == ~t1_pc~0); 64630#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64548#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64461#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 64462#L657 assume !(0 != activate_threads_~tmp___0~0#1); 64604#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64701#L300 assume !(1 == ~t2_pc~0); 64702#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 64802#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64758#L665 assume !(0 != activate_threads_~tmp___1~0#1); 64474#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64475#L319 assume !(1 == ~t3_pc~0); 64901#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64804#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64650#L673 assume !(0 != activate_threads_~tmp___2~0#1); 64651#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64806#L338 assume !(1 == ~t4_pc~0); 64519#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64520#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64525#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64526#L681 assume !(0 != activate_threads_~tmp___3~0#1); 64399#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64400#L584 assume !(1 == ~M_E~0); 64601#L584-2 assume !(1 == ~T1_E~0); 64562#L589-1 assume !(1 == ~T2_E~0); 64563#L594-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64656#L599-1 assume !(1 == ~T4_E~0); 64429#L604-1 assume !(1 == ~E_M~0); 64415#L609-1 assume !(1 == ~E_1~0); 64416#L614-1 assume !(1 == ~E_2~0); 64534#L619-1 assume !(1 == ~E_3~0); 64621#L624-1 assume !(1 == ~E_4~0); 64721#L629-1 assume { :end_inline_reset_delta_events } true; 64889#L815-2 [2024-11-13 15:01:23,827 INFO L747 eck$LassoCheckResult]: Loop: 64889#L815-2 assume !false; 66062#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66060#L501-1 assume !false; 66058#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66055#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66049#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66047#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 66044#L440 assume !(0 != eval_~tmp~0#1); 66045#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66250#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66249#L526-3 assume !(0 == ~M_E~0); 66248#L526-5 assume !(0 == ~T1_E~0); 66247#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66246#L536-3 assume !(0 == ~T3_E~0); 66245#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66243#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66241#L551-3 assume !(0 == ~E_1~0); 66239#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66237#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66235#L566-3 assume !(0 == ~E_4~0); 66233#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66231#L262-18 assume !(1 == ~m_pc~0); 66229#L262-20 is_master_triggered_~__retres1~0#1 := 0; 66227#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66225#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66223#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66221#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66219#L281-18 assume !(1 == ~t1_pc~0); 66215#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 66213#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66211#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66209#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 66207#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66205#L300-18 assume !(1 == ~t2_pc~0); 66203#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 66201#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66199#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66197#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66195#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66193#L319-18 assume !(1 == ~t3_pc~0); 66191#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 66187#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66185#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66183#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 66181#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66179#L338-18 assume !(1 == ~t4_pc~0); 66177#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 66175#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66173#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66171#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66169#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66167#L584-3 assume !(1 == ~M_E~0); 66161#L584-5 assume !(1 == ~T1_E~0); 66159#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66156#L594-3 assume !(1 == ~T3_E~0); 66155#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66154#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66152#L609-3 assume !(1 == ~E_1~0); 66150#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66148#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66146#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66144#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66142#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66135#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66133#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 66130#L834 assume !(0 == start_simulation_~tmp~3#1); 66127#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66120#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66116#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66114#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 66112#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66110#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66108#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 66105#L847 assume !(0 != start_simulation_~tmp___0~1#1); 64889#L815-2 [2024-11-13 15:01:23,827 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:23,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1923693623, now seen corresponding path program 1 times [2024-11-13 15:01:23,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:23,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121936624] [2024-11-13 15:01:23,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:23,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:23,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:23,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:23,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:23,877 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121936624] [2024-11-13 15:01:23,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121936624] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:23,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:23,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:23,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791081340] [2024-11-13 15:01:23,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:23,878 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:23,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:23,878 INFO L85 PathProgramCache]: Analyzing trace with hash -1786592078, now seen corresponding path program 1 times [2024-11-13 15:01:23,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:23,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742794063] [2024-11-13 15:01:23,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:23,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:23,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:23,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:23,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:23,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742794063] [2024-11-13 15:01:23,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742794063] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:23,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:23,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:01:23,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268888292] [2024-11-13 15:01:23,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:23,940 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:23,941 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:23,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:01:23,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:01:23,941 INFO L87 Difference]: Start difference. First operand 5351 states and 7432 transitions. cyclomatic complexity: 2089 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:24,030 INFO L93 Difference]: Finished difference Result 6647 states and 9240 transitions. [2024-11-13 15:01:24,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6647 states and 9240 transitions. [2024-11-13 15:01:24,054 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6504 [2024-11-13 15:01:24,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6647 states to 6647 states and 9240 transitions. [2024-11-13 15:01:24,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6647 [2024-11-13 15:01:24,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6647 [2024-11-13 15:01:24,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6647 states and 9240 transitions. [2024-11-13 15:01:24,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:24,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6647 states and 9240 transitions. [2024-11-13 15:01:24,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6647 states and 9240 transitions. [2024-11-13 15:01:24,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6647 to 4596. [2024-11-13 15:01:24,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4596 states, 4596 states have (on average 1.392515230635335) internal successors, (6400), 4595 states have internal predecessors, (6400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4596 states to 4596 states and 6400 transitions. [2024-11-13 15:01:24,183 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4596 states and 6400 transitions. [2024-11-13 15:01:24,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:01:24,184 INFO L424 stractBuchiCegarLoop]: Abstraction has 4596 states and 6400 transitions. [2024-11-13 15:01:24,184 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:01:24,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4596 states and 6400 transitions. [2024-11-13 15:01:24,197 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4484 [2024-11-13 15:01:24,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:24,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:24,198 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:24,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:24,199 INFO L745 eck$LassoCheckResult]: Stem: 76657#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 76658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 76757#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76758#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76503#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 76504#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76770#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76723#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76724#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76752#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76733#L526 assume !(0 == ~M_E~0); 76734#L526-2 assume !(0 == ~T1_E~0); 76772#L531-1 assume !(0 == ~T2_E~0); 76719#L536-1 assume !(0 == ~T3_E~0); 76720#L541-1 assume !(0 == ~T4_E~0); 76715#L546-1 assume !(0 == ~E_M~0); 76716#L551-1 assume !(0 == ~E_1~0); 76693#L556-1 assume !(0 == ~E_2~0); 76694#L561-1 assume !(0 == ~E_3~0); 76703#L566-1 assume !(0 == ~E_4~0); 76704#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76698#L262 assume !(1 == ~m_pc~0); 76699#L262-2 is_master_triggered_~__retres1~0#1 := 0; 76890#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76627#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76628#L649 assume !(0 != activate_threads_~tmp~1#1); 76887#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76636#L281 assume !(1 == ~t1_pc~0); 76637#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76555#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76471#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76472#L657 assume !(0 != activate_threads_~tmp___0~0#1); 76611#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76706#L300 assume !(1 == ~t2_pc~0); 76707#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76809#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76761#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76727#L665 assume !(0 != activate_threads_~tmp___1~0#1); 76484#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76485#L319 assume !(1 == ~t3_pc~0); 76440#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76441#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76427#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76428#L673 assume !(0 != activate_threads_~tmp___2~0#1); 76461#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76462#L338 assume !(1 == ~t4_pc~0); 76529#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76530#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76535#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76536#L681 assume !(0 != activate_threads_~tmp___3~0#1); 76409#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76410#L584 assume !(1 == ~M_E~0); 76608#L584-2 assume !(1 == ~T1_E~0); 76569#L589-1 assume !(1 == ~T2_E~0); 76570#L594-1 assume !(1 == ~T3_E~0); 76661#L599-1 assume !(1 == ~T4_E~0); 76439#L604-1 assume !(1 == ~E_M~0); 76425#L609-1 assume !(1 == ~E_1~0); 76426#L614-1 assume !(1 == ~E_2~0); 76544#L619-1 assume !(1 == ~E_3~0); 76629#L624-1 assume !(1 == ~E_4~0); 76725#L629-1 assume { :end_inline_reset_delta_events } true; 76899#L815-2 [2024-11-13 15:01:24,199 INFO L747 eck$LassoCheckResult]: Loop: 76899#L815-2 assume !false; 77798#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77797#L501-1 assume !false; 77788#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77776#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77760#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77752#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77743#L440 assume !(0 != eval_~tmp~0#1); 77736#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77730#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77725#L526-3 assume !(0 == ~M_E~0); 77723#L526-5 assume !(0 == ~T1_E~0); 77721#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77715#L536-3 assume !(0 == ~T3_E~0); 77713#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77711#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77708#L551-3 assume !(0 == ~E_1~0); 77706#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77704#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77702#L566-3 assume !(0 == ~E_4~0); 77700#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77698#L262-18 assume !(1 == ~m_pc~0); 77696#L262-20 is_master_triggered_~__retres1~0#1 := 0; 77694#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77692#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77690#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77686#L281-18 assume !(1 == ~t1_pc~0); 77683#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 77681#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77679#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77677#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 77675#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77673#L300-18 assume !(1 == ~t2_pc~0); 77671#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 77669#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77666#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77664#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77662#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77660#L319-18 assume 1 == ~t3_pc~0; 77657#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77655#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77653#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77650#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 77648#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77646#L338-18 assume !(1 == ~t4_pc~0); 77644#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 77642#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77640#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77637#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77635#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77633#L584-3 assume !(1 == ~M_E~0); 77523#L584-5 assume !(1 == ~T1_E~0); 77630#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77628#L594-3 assume !(1 == ~T3_E~0); 77626#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77624#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77134#L609-3 assume !(1 == ~E_1~0); 77128#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77122#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77116#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77113#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77094#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77084#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77053#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 76590#L834 assume !(0 == start_simulation_~tmp~3#1); 76591#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 77890#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 77884#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 77878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 77870#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77863#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77857#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 77850#L847 assume !(0 != start_simulation_~tmp___0~1#1); 76899#L815-2 [2024-11-13 15:01:24,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:24,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2024-11-13 15:01:24,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:24,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002974024] [2024-11-13 15:01:24,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:24,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:24,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:24,244 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:24,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:24,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:24,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:24,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1456926129, now seen corresponding path program 1 times [2024-11-13 15:01:24,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:24,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957516790] [2024-11-13 15:01:24,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:24,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:24,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:24,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:24,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:24,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957516790] [2024-11-13 15:01:24,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957516790] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:24,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:24,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:01:24,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893655632] [2024-11-13 15:01:24,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:24,348 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:24,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:24,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:01:24,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:01:24,350 INFO L87 Difference]: Start difference. First operand 4596 states and 6400 transitions. cyclomatic complexity: 1812 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:24,436 INFO L93 Difference]: Finished difference Result 4708 states and 6512 transitions. [2024-11-13 15:01:24,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4708 states and 6512 transitions. [2024-11-13 15:01:24,453 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4596 [2024-11-13 15:01:24,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4708 states to 4708 states and 6512 transitions. [2024-11-13 15:01:24,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4708 [2024-11-13 15:01:24,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4708 [2024-11-13 15:01:24,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4708 states and 6512 transitions. [2024-11-13 15:01:24,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:24,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4708 states and 6512 transitions. [2024-11-13 15:01:24,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4708 states and 6512 transitions. [2024-11-13 15:01:24,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4708 to 4644. [2024-11-13 15:01:24,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4644 states, 4644 states have (on average 1.388458225667528) internal successors, (6448), 4643 states have internal predecessors, (6448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4644 states to 4644 states and 6448 transitions. [2024-11-13 15:01:24,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4644 states and 6448 transitions. [2024-11-13 15:01:24,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:01:24,555 INFO L424 stractBuchiCegarLoop]: Abstraction has 4644 states and 6448 transitions. [2024-11-13 15:01:24,555 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:01:24,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4644 states and 6448 transitions. [2024-11-13 15:01:24,567 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4532 [2024-11-13 15:01:24,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:24,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:24,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:24,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:24,569 INFO L745 eck$LassoCheckResult]: Stem: 85969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 85970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 86073#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85816#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 85817#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86086#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86036#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86037#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86067#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86048#L526 assume !(0 == ~M_E~0); 86049#L526-2 assume !(0 == ~T1_E~0); 86088#L531-1 assume !(0 == ~T2_E~0); 86032#L536-1 assume !(0 == ~T3_E~0); 86033#L541-1 assume !(0 == ~T4_E~0); 86028#L546-1 assume !(0 == ~E_M~0); 86029#L551-1 assume !(0 == ~E_1~0); 86004#L556-1 assume !(0 == ~E_2~0); 86005#L561-1 assume !(0 == ~E_3~0); 86015#L566-1 assume !(0 == ~E_4~0); 86016#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86009#L262 assume !(1 == ~m_pc~0); 86010#L262-2 is_master_triggered_~__retres1~0#1 := 0; 86194#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85938#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 85939#L649 assume !(0 != activate_threads_~tmp~1#1); 86193#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85948#L281 assume !(1 == ~t1_pc~0); 85949#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 85866#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85783#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85784#L657 assume !(0 != activate_threads_~tmp___0~0#1); 85925#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86018#L300 assume !(1 == ~t2_pc~0); 86019#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86126#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86078#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86040#L665 assume !(0 != activate_threads_~tmp___1~0#1); 85796#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85797#L319 assume !(1 == ~t3_pc~0); 85752#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85753#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85739#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 85740#L673 assume !(0 != activate_threads_~tmp___2~0#1); 85773#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85774#L338 assume !(1 == ~t4_pc~0); 85840#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 85841#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85848#L681 assume !(0 != activate_threads_~tmp___3~0#1); 85721#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85722#L584 assume !(1 == ~M_E~0); 85922#L584-2 assume !(1 == ~T1_E~0); 85882#L589-1 assume !(1 == ~T2_E~0); 85883#L594-1 assume !(1 == ~T3_E~0); 85975#L599-1 assume !(1 == ~T4_E~0); 85751#L604-1 assume !(1 == ~E_M~0); 85737#L609-1 assume !(1 == ~E_1~0); 85738#L614-1 assume !(1 == ~E_2~0); 85855#L619-1 assume !(1 == ~E_3~0); 85940#L624-1 assume !(1 == ~E_4~0); 86038#L629-1 assume { :end_inline_reset_delta_events } true; 86200#L815-2 [2024-11-13 15:01:24,569 INFO L747 eck$LassoCheckResult]: Loop: 86200#L815-2 assume !false; 87296#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87295#L501-1 assume !false; 87294#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87293#L398 assume !(0 == ~m_st~0); 87290#L402 assume !(0 == ~t1_st~0); 87291#L406 assume !(0 == ~t2_st~0); 87292#L410 assume !(0 == ~t3_st~0); 87289#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 87287#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87285#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 87284#L440 assume !(0 != eval_~tmp~0#1); 87283#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87281#L526-3 assume !(0 == ~M_E~0); 87280#L526-5 assume !(0 == ~T1_E~0); 87279#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87278#L536-3 assume !(0 == ~T3_E~0); 87277#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87276#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87275#L551-3 assume !(0 == ~E_1~0); 87274#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87273#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87272#L566-3 assume !(0 == ~E_4~0); 87271#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87270#L262-18 assume !(1 == ~m_pc~0); 87269#L262-20 is_master_triggered_~__retres1~0#1 := 0; 87268#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87267#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 87266#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87265#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87264#L281-18 assume !(1 == ~t1_pc~0); 87262#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 87261#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87260#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87259#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 87258#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87257#L300-18 assume !(1 == ~t2_pc~0); 87256#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 87255#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87254#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87253#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87252#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87251#L319-18 assume 1 == ~t3_pc~0; 87249#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 87248#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87247#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 87246#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 87245#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87244#L338-18 assume !(1 == ~t4_pc~0); 87243#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 87242#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87241#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 87240#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87239#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87238#L584-3 assume !(1 == ~M_E~0); 87178#L584-5 assume !(1 == ~T1_E~0); 87237#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87236#L594-3 assume !(1 == ~T3_E~0); 87235#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87234#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87233#L609-3 assume !(1 == ~E_1~0); 87232#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87231#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87230#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87229#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87228#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87160#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 87153#L834 assume !(0 == start_simulation_~tmp~3#1); 87154#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 87352#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87348#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87314#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 87310#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87308#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87306#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 87303#L847 assume !(0 != start_simulation_~tmp___0~1#1); 86200#L815-2 [2024-11-13 15:01:24,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:24,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2024-11-13 15:01:24,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:24,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462780780] [2024-11-13 15:01:24,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:24,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:24,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:24,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:24,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:24,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:24,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:24,604 INFO L85 PathProgramCache]: Analyzing trace with hash 767183141, now seen corresponding path program 1 times [2024-11-13 15:01:24,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:24,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578413665] [2024-11-13 15:01:24,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:24,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:24,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:24,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:24,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:24,669 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578413665] [2024-11-13 15:01:24,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578413665] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:24,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:24,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:01:24,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18052570] [2024-11-13 15:01:24,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:24,669 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:24,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:24,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:01:24,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:01:24,670 INFO L87 Difference]: Start difference. First operand 4644 states and 6448 transitions. cyclomatic complexity: 1812 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:24,878 INFO L93 Difference]: Finished difference Result 4887 states and 6691 transitions. [2024-11-13 15:01:24,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4887 states and 6691 transitions. [2024-11-13 15:01:24,894 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4772 [2024-11-13 15:01:24,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4887 states to 4887 states and 6691 transitions. [2024-11-13 15:01:24,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4887 [2024-11-13 15:01:24,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4887 [2024-11-13 15:01:24,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4887 states and 6691 transitions. [2024-11-13 15:01:24,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:24,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4887 states and 6691 transitions. [2024-11-13 15:01:24,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4887 states and 6691 transitions. [2024-11-13 15:01:24,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4887 to 4887. [2024-11-13 15:01:24,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4887 states, 4887 states have (on average 1.3691426232862698) internal successors, (6691), 4886 states have internal predecessors, (6691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:24,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4887 states to 4887 states and 6691 transitions. [2024-11-13 15:01:24,998 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4887 states and 6691 transitions. [2024-11-13 15:01:24,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:01:25,000 INFO L424 stractBuchiCegarLoop]: Abstraction has 4887 states and 6691 transitions. [2024-11-13 15:01:25,000 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:01:25,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4887 states and 6691 transitions. [2024-11-13 15:01:25,016 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4772 [2024-11-13 15:01:25,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:25,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:25,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,021 INFO L745 eck$LassoCheckResult]: Stem: 95510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 95511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 95614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95356#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 95357#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95627#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95576#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95577#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95608#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95586#L526 assume !(0 == ~M_E~0); 95587#L526-2 assume !(0 == ~T1_E~0); 95630#L531-1 assume !(0 == ~T2_E~0); 95572#L536-1 assume !(0 == ~T3_E~0); 95573#L541-1 assume !(0 == ~T4_E~0); 95568#L546-1 assume !(0 == ~E_M~0); 95569#L551-1 assume !(0 == ~E_1~0); 95546#L556-1 assume !(0 == ~E_2~0); 95547#L561-1 assume !(0 == ~E_3~0); 95556#L566-1 assume !(0 == ~E_4~0); 95557#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95551#L262 assume !(1 == ~m_pc~0); 95552#L262-2 is_master_triggered_~__retres1~0#1 := 0; 95738#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95479#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95480#L649 assume !(0 != activate_threads_~tmp~1#1); 95734#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95489#L281 assume !(1 == ~t1_pc~0); 95490#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95407#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95322#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95323#L657 assume !(0 != activate_threads_~tmp___0~0#1); 95463#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95559#L300 assume !(1 == ~t2_pc~0); 95560#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95669#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95580#L665 assume !(0 != activate_threads_~tmp___1~0#1); 95335#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95336#L319 assume !(1 == ~t3_pc~0); 95291#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95292#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95672#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95761#L673 assume !(0 != activate_threads_~tmp___2~0#1); 95312#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95313#L338 assume !(1 == ~t4_pc~0); 95380#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95381#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95386#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95387#L681 assume !(0 != activate_threads_~tmp___3~0#1); 95260#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95261#L584 assume !(1 == ~M_E~0); 95460#L584-2 assume !(1 == ~T1_E~0); 95421#L589-1 assume !(1 == ~T2_E~0); 95422#L594-1 assume !(1 == ~T3_E~0); 95514#L599-1 assume !(1 == ~T4_E~0); 95290#L604-1 assume !(1 == ~E_M~0); 95276#L609-1 assume !(1 == ~E_1~0); 95277#L614-1 assume !(1 == ~E_2~0); 95395#L619-1 assume !(1 == ~E_3~0); 95481#L624-1 assume !(1 == ~E_4~0); 95578#L629-1 assume { :end_inline_reset_delta_events } true; 95745#L815-2 [2024-11-13 15:01:25,022 INFO L747 eck$LassoCheckResult]: Loop: 95745#L815-2 assume !false; 98574#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98569#L501-1 assume !false; 98565#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98535#L398 assume !(0 == ~m_st~0); 98532#L402 assume !(0 == ~t1_st~0); 98533#L406 assume !(0 == ~t2_st~0); 98534#L410 assume !(0 == ~t3_st~0); 98530#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 98531#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98403#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 98404#L440 assume !(0 != eval_~tmp~0#1); 98838#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98836#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98834#L526-3 assume !(0 == ~M_E~0); 98829#L526-5 assume !(0 == ~T1_E~0); 98825#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98823#L536-3 assume !(0 == ~T3_E~0); 98820#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98817#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98814#L551-3 assume !(0 == ~E_1~0); 98811#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98808#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98805#L566-3 assume !(0 == ~E_4~0); 98801#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98798#L262-18 assume !(1 == ~m_pc~0); 98795#L262-20 is_master_triggered_~__retres1~0#1 := 0; 98792#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98789#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 98786#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 98783#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98780#L281-18 assume !(1 == ~t1_pc~0); 98777#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 98775#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98773#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98771#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 98769#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98765#L300-18 assume !(1 == ~t2_pc~0); 98763#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 98761#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98759#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98755#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98752#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98749#L319-18 assume !(1 == ~t3_pc~0); 98745#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 98741#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98737#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98732#L673-18 assume !(0 != activate_threads_~tmp___2~0#1); 98729#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98724#L338-18 assume !(1 == ~t4_pc~0); 98721#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 98717#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98712#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98707#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98701#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98665#L584-3 assume !(1 == ~M_E~0); 98661#L584-5 assume !(1 == ~T1_E~0); 98658#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98656#L594-3 assume !(1 == ~T3_E~0); 98654#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98652#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98650#L609-3 assume !(1 == ~E_1~0); 98648#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98646#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98644#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98642#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98640#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98633#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98630#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 98625#L834 assume !(0 == start_simulation_~tmp~3#1); 98617#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98609#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98603#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98600#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 98595#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98592#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98589#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 98585#L847 assume !(0 != start_simulation_~tmp___0~1#1); 95745#L815-2 [2024-11-13 15:01:25,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:25,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2024-11-13 15:01:25,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:25,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211077729] [2024-11-13 15:01:25,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:25,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:25,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:25,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:25,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:25,060 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:25,061 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:25,061 INFO L85 PathProgramCache]: Analyzing trace with hash 1818632230, now seen corresponding path program 1 times [2024-11-13 15:01:25,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:25,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374544293] [2024-11-13 15:01:25,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:25,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:25,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:25,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:25,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:25,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374544293] [2024-11-13 15:01:25,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374544293] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:25,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:25,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:01:25,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903669752] [2024-11-13 15:01:25,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:25,200 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:25,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:25,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:01:25,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:01:25,200 INFO L87 Difference]: Start difference. First operand 4887 states and 6691 transitions. cyclomatic complexity: 1812 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:25,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:25,385 INFO L93 Difference]: Finished difference Result 5019 states and 6786 transitions. [2024-11-13 15:01:25,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5019 states and 6786 transitions. [2024-11-13 15:01:25,403 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4904 [2024-11-13 15:01:25,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5019 states to 5019 states and 6786 transitions. [2024-11-13 15:01:25,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5019 [2024-11-13 15:01:25,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5019 [2024-11-13 15:01:25,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5019 states and 6786 transitions. [2024-11-13 15:01:25,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:25,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5019 states and 6786 transitions. [2024-11-13 15:01:25,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5019 states and 6786 transitions. [2024-11-13 15:01:25,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5019 to 5019. [2024-11-13 15:01:25,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5019 states, 5019 states have (on average 1.3520621637776449) internal successors, (6786), 5018 states have internal predecessors, (6786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:25,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5019 states to 5019 states and 6786 transitions. [2024-11-13 15:01:25,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5019 states and 6786 transitions. [2024-11-13 15:01:25,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:01:25,514 INFO L424 stractBuchiCegarLoop]: Abstraction has 5019 states and 6786 transitions. [2024-11-13 15:01:25,514 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:01:25,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5019 states and 6786 transitions. [2024-11-13 15:01:25,528 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4904 [2024-11-13 15:01:25,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:25,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:25,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,529 INFO L745 eck$LassoCheckResult]: Stem: 105427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 105428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 105531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105532#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105271#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 105272#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105542#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105494#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105495#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105525#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105505#L526 assume !(0 == ~M_E~0); 105506#L526-2 assume !(0 == ~T1_E~0); 105546#L531-1 assume !(0 == ~T2_E~0); 105490#L536-1 assume !(0 == ~T3_E~0); 105491#L541-1 assume !(0 == ~T4_E~0); 105486#L546-1 assume !(0 == ~E_M~0); 105487#L551-1 assume !(0 == ~E_1~0); 105461#L556-1 assume !(0 == ~E_2~0); 105462#L561-1 assume !(0 == ~E_3~0); 105471#L566-1 assume !(0 == ~E_4~0); 105472#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105466#L262 assume !(1 == ~m_pc~0); 105467#L262-2 is_master_triggered_~__retres1~0#1 := 0; 105661#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105395#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105396#L649 assume !(0 != activate_threads_~tmp~1#1); 105659#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105405#L281 assume !(1 == ~t1_pc~0); 105406#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105323#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105236#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105237#L657 assume !(0 != activate_threads_~tmp___0~0#1); 105380#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105476#L300 assume !(1 == ~t2_pc~0); 105477#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105588#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105536#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105498#L665 assume !(0 != activate_threads_~tmp___1~0#1); 105249#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105250#L319 assume !(1 == ~t3_pc~0); 105205#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105206#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105591#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105690#L673 assume !(0 != activate_threads_~tmp___2~0#1); 105226#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105227#L338 assume !(1 == ~t4_pc~0); 105296#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105297#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105302#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105303#L681 assume !(0 != activate_threads_~tmp___3~0#1); 105174#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105175#L584 assume !(1 == ~M_E~0); 105377#L584-2 assume !(1 == ~T1_E~0); 105337#L589-1 assume !(1 == ~T2_E~0); 105338#L594-1 assume !(1 == ~T3_E~0); 105431#L599-1 assume !(1 == ~T4_E~0); 105204#L604-1 assume !(1 == ~E_M~0); 105190#L609-1 assume !(1 == ~E_1~0); 105191#L614-1 assume !(1 == ~E_2~0); 105311#L619-1 assume !(1 == ~E_3~0); 105397#L624-1 assume !(1 == ~E_4~0); 105496#L629-1 assume { :end_inline_reset_delta_events } true; 105668#L815-2 [2024-11-13 15:01:25,530 INFO L747 eck$LassoCheckResult]: Loop: 105668#L815-2 assume !false; 106913#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106912#L501-1 assume !false; 106911#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 106904#L398 assume !(0 == ~m_st~0); 106901#L402 assume !(0 == ~t1_st~0); 106902#L406 assume !(0 == ~t2_st~0); 106903#L410 assume !(0 == ~t3_st~0); 106899#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 106900#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 106882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 106883#L440 assume !(0 != eval_~tmp~0#1); 107860#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107854#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107845#L526-3 assume !(0 == ~M_E~0); 107838#L526-5 assume !(0 == ~T1_E~0); 107831#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107827#L536-3 assume !(0 == ~T3_E~0); 107822#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107816#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107812#L551-3 assume !(0 == ~E_1~0); 107808#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107804#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107798#L566-3 assume !(0 == ~E_4~0); 107794#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107790#L262-18 assume !(1 == ~m_pc~0); 107784#L262-20 is_master_triggered_~__retres1~0#1 := 0; 107780#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107776#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 107772#L649-18 assume !(0 != activate_threads_~tmp~1#1); 107768#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107761#L281-18 assume !(1 == ~t1_pc~0); 107755#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 107750#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107744#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107739#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 107736#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107732#L300-18 assume !(1 == ~t2_pc~0); 107729#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 107725#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107721#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107717#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107711#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107708#L319-18 assume 1 == ~t3_pc~0; 107705#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 107700#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107695#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107691#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107686#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107683#L338-18 assume !(1 == ~t4_pc~0); 107680#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 107676#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107672#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107589#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 107585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107583#L584-3 assume !(1 == ~M_E~0); 107579#L584-5 assume !(1 == ~T1_E~0); 107578#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107575#L594-3 assume !(1 == ~T3_E~0); 107574#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107568#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107566#L609-3 assume !(1 == ~E_1~0); 107564#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107562#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107560#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107558#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 107556#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 107544#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 107538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 107535#L834 assume !(0 == start_simulation_~tmp~3#1); 107532#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 107528#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 107524#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 107521#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 107518#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107516#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107511#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 107508#L847 assume !(0 != start_simulation_~tmp___0~1#1); 105668#L815-2 [2024-11-13 15:01:25,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:25,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 5 times [2024-11-13 15:01:25,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:25,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330404449] [2024-11-13 15:01:25,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:25,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:25,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:25,550 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:25,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:25,571 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:25,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:25,572 INFO L85 PathProgramCache]: Analyzing trace with hash 50064549, now seen corresponding path program 1 times [2024-11-13 15:01:25,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:25,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630927609] [2024-11-13 15:01:25,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:25,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:25,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:25,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:25,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:25,613 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630927609] [2024-11-13 15:01:25,613 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [630927609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:25,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:25,613 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:25,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022743294] [2024-11-13 15:01:25,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:25,614 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:01:25,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:25,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:25,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:25,616 INFO L87 Difference]: Start difference. First operand 5019 states and 6786 transitions. cyclomatic complexity: 1775 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:25,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:25,688 INFO L93 Difference]: Finished difference Result 7891 states and 10502 transitions. [2024-11-13 15:01:25,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7891 states and 10502 transitions. [2024-11-13 15:01:25,716 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7758 [2024-11-13 15:01:25,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7891 states to 7891 states and 10502 transitions. [2024-11-13 15:01:25,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7891 [2024-11-13 15:01:25,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7891 [2024-11-13 15:01:25,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7891 states and 10502 transitions. [2024-11-13 15:01:25,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:25,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7891 states and 10502 transitions. [2024-11-13 15:01:25,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7891 states and 10502 transitions. [2024-11-13 15:01:25,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7891 to 7611. [2024-11-13 15:01:25,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7611 states, 7611 states have (on average 1.332545000656944) internal successors, (10142), 7610 states have internal predecessors, (10142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:25,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7611 states to 7611 states and 10142 transitions. [2024-11-13 15:01:25,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7611 states and 10142 transitions. [2024-11-13 15:01:25,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:25,955 INFO L424 stractBuchiCegarLoop]: Abstraction has 7611 states and 10142 transitions. [2024-11-13 15:01:25,955 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:01:25,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7611 states and 10142 transitions. [2024-11-13 15:01:25,992 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7478 [2024-11-13 15:01:25,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:25,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:25,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,993 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:25,998 INFO L745 eck$LassoCheckResult]: Stem: 118345#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 118346#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 118445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118188#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 118189#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118463#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118411#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118412#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118441#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118423#L526 assume !(0 == ~M_E~0); 118424#L526-2 assume !(0 == ~T1_E~0); 118465#L531-1 assume !(0 == ~T2_E~0); 118407#L536-1 assume !(0 == ~T3_E~0); 118408#L541-1 assume !(0 == ~T4_E~0); 118403#L546-1 assume !(0 == ~E_M~0); 118404#L551-1 assume !(0 == ~E_1~0); 118379#L556-1 assume !(0 == ~E_2~0); 118380#L561-1 assume !(0 == ~E_3~0); 118389#L566-1 assume !(0 == ~E_4~0); 118390#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118384#L262 assume !(1 == ~m_pc~0); 118385#L262-2 is_master_triggered_~__retres1~0#1 := 0; 118579#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118314#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118315#L649 assume !(0 != activate_threads_~tmp~1#1); 118578#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118324#L281 assume !(1 == ~t1_pc~0); 118325#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118239#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118154#L657 assume !(0 != activate_threads_~tmp___0~0#1); 118298#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118392#L300 assume !(1 == ~t2_pc~0); 118393#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118504#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118449#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118415#L665 assume !(0 != activate_threads_~tmp___1~0#1); 118166#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118167#L319 assume !(1 == ~t3_pc~0); 118122#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118123#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118506#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118604#L673 assume !(0 != activate_threads_~tmp___2~0#1); 118143#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118144#L338 assume !(1 == ~t4_pc~0); 118212#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118213#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118219#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118220#L681 assume !(0 != activate_threads_~tmp___3~0#1); 118090#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118091#L584 assume !(1 == ~M_E~0); 118295#L584-2 assume !(1 == ~T1_E~0); 118254#L589-1 assume !(1 == ~T2_E~0); 118255#L594-1 assume !(1 == ~T3_E~0); 118351#L599-1 assume !(1 == ~T4_E~0); 118121#L604-1 assume !(1 == ~E_M~0); 118107#L609-1 assume !(1 == ~E_1~0); 118108#L614-1 assume !(1 == ~E_2~0); 118227#L619-1 assume !(1 == ~E_3~0); 118316#L624-1 assume !(1 == ~E_4~0); 118413#L629-1 assume { :end_inline_reset_delta_events } true; 118592#L815-2 assume !false; 122322#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122320#L501-1 [2024-11-13 15:01:25,999 INFO L747 eck$LassoCheckResult]: Loop: 122320#L501-1 assume !false; 122318#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 122315#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 122313#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 122311#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 122309#L440 assume 0 != eval_~tmp~0#1; 122306#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 122303#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 122304#L448-2 havoc eval_~tmp_ndt_1~0#1; 122341#L445-1 assume !(0 == ~t1_st~0); 122337#L459-1 assume !(0 == ~t2_st~0); 122333#L473-1 assume !(0 == ~t3_st~0); 122323#L487-1 assume !(0 == ~t4_st~0); 122320#L501-1 [2024-11-13 15:01:25,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:25,999 INFO L85 PathProgramCache]: Analyzing trace with hash 39728907, now seen corresponding path program 1 times [2024-11-13 15:01:25,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:25,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522657053] [2024-11-13 15:01:26,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:26,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:26,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,024 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:26,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,065 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:26,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:26,066 INFO L85 PathProgramCache]: Analyzing trace with hash 883271664, now seen corresponding path program 1 times [2024-11-13 15:01:26,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:26,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556720125] [2024-11-13 15:01:26,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:26,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:26,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:26,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:26,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:26,083 INFO L85 PathProgramCache]: Analyzing trace with hash -201150170, now seen corresponding path program 1 times [2024-11-13 15:01:26,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:26,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718774653] [2024-11-13 15:01:26,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:26,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:26,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:26,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:26,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:26,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718774653] [2024-11-13 15:01:26,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718774653] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:26,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:26,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:26,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809995888] [2024-11-13 15:01:26,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:26,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:26,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:26,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:26,292 INFO L87 Difference]: Start difference. First operand 7611 states and 10142 transitions. cyclomatic complexity: 2543 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:26,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:26,361 INFO L93 Difference]: Finished difference Result 12296 states and 16253 transitions. [2024-11-13 15:01:26,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12296 states and 16253 transitions. [2024-11-13 15:01:26,406 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12036 [2024-11-13 15:01:26,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12296 states to 12296 states and 16253 transitions. [2024-11-13 15:01:26,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12296 [2024-11-13 15:01:26,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12296 [2024-11-13 15:01:26,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12296 states and 16253 transitions. [2024-11-13 15:01:26,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:26,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12296 states and 16253 transitions. [2024-11-13 15:01:26,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12296 states and 16253 transitions. [2024-11-13 15:01:26,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12296 to 12296. [2024-11-13 15:01:26,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12296 states, 12296 states have (on average 1.3218119713728043) internal successors, (16253), 12295 states have internal predecessors, (16253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:26,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12296 states to 12296 states and 16253 transitions. [2024-11-13 15:01:26,784 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12296 states and 16253 transitions. [2024-11-13 15:01:26,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:26,785 INFO L424 stractBuchiCegarLoop]: Abstraction has 12296 states and 16253 transitions. [2024-11-13 15:01:26,785 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 15:01:26,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12296 states and 16253 transitions. [2024-11-13 15:01:26,818 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12036 [2024-11-13 15:01:26,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:26,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:26,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:26,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:26,820 INFO L745 eck$LassoCheckResult]: Stem: 138267#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 138268#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 138373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 138102#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 138103#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 138389#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138390#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138511#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138512#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 138351#L526 assume !(0 == ~M_E~0); 138352#L526-2 assume !(0 == ~T1_E~0); 138392#L531-1 assume !(0 == ~T2_E~0); 138393#L536-1 assume !(0 == ~T3_E~0); 138471#L541-1 assume !(0 == ~T4_E~0); 138472#L546-1 assume !(0 == ~E_M~0); 138411#L551-1 assume !(0 == ~E_1~0); 138412#L556-1 assume !(0 == ~E_2~0); 138346#L561-1 assume !(0 == ~E_3~0); 138347#L566-1 assume !(0 == ~E_4~0); 138534#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138535#L262 assume !(1 == ~m_pc~0); 138551#L262-2 is_master_triggered_~__retres1~0#1 := 0; 138552#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138236#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 138237#L649 assume !(0 != activate_threads_~tmp~1#1); 138578#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138579#L281 assume !(1 == ~t1_pc~0); 138556#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 138557#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138068#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138069#L657 assume !(0 != activate_threads_~tmp___0~0#1); 138526#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138527#L300 assume !(1 == ~t2_pc~0); 138492#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 138493#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138377#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138378#L665 assume !(0 != activate_threads_~tmp___1~0#1); 138081#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138082#L319 assume !(1 == ~t3_pc~0); 138037#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138038#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138585#L673 assume !(0 != activate_threads_~tmp___2~0#1); 139110#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139109#L338 assume !(1 == ~t4_pc~0); 138126#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 138127#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138134#L681 assume !(0 != activate_threads_~tmp___3~0#1); 138005#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138006#L584 assume !(1 == ~M_E~0); 138212#L584-2 assume !(1 == ~T1_E~0); 138213#L589-1 assume !(1 == ~T2_E~0); 138424#L594-1 assume !(1 == ~T3_E~0); 138425#L599-1 assume !(1 == ~T4_E~0); 138035#L604-1 assume !(1 == ~E_M~0); 138036#L609-1 assume !(1 == ~E_1~0); 138143#L614-1 assume !(1 == ~E_2~0); 138144#L619-1 assume !(1 == ~E_3~0); 138238#L624-1 assume !(1 == ~E_4~0); 138337#L629-1 assume { :end_inline_reset_delta_events } true; 139033#L815-2 assume !false; 139027#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 139024#L501-1 [2024-11-13 15:01:26,820 INFO L747 eck$LassoCheckResult]: Loop: 139024#L501-1 assume !false; 139021#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 139017#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 139014#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 139010#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 139006#L440 assume 0 != eval_~tmp~0#1; 139000#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 138996#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 138993#L448-2 havoc eval_~tmp_ndt_1~0#1; 138989#L445-1 assume !(0 == ~t1_st~0); 138984#L459-1 assume !(0 == ~t2_st~0); 138985#L473-1 assume !(0 == ~t3_st~0); 139028#L487-1 assume !(0 == ~t4_st~0); 139024#L501-1 [2024-11-13 15:01:26,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:26,821 INFO L85 PathProgramCache]: Analyzing trace with hash 600428685, now seen corresponding path program 1 times [2024-11-13 15:01:26,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:26,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179119490] [2024-11-13 15:01:26,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:26,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:26,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:26,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:26,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:26,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179119490] [2024-11-13 15:01:26,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179119490] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:26,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:26,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:26,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27852762] [2024-11-13 15:01:26,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:26,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:01:26,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:26,857 INFO L85 PathProgramCache]: Analyzing trace with hash 883271664, now seen corresponding path program 2 times [2024-11-13 15:01:26,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:26,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062610025] [2024-11-13 15:01:26,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:26,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:26,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,861 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:26,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:26,865 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:26,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:26,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:26,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:26,938 INFO L87 Difference]: Start difference. First operand 12296 states and 16253 transitions. cyclomatic complexity: 3969 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:26,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:26,978 INFO L93 Difference]: Finished difference Result 12233 states and 16171 transitions. [2024-11-13 15:01:26,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12233 states and 16171 transitions. [2024-11-13 15:01:27,021 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12036 [2024-11-13 15:01:27,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12233 states to 12233 states and 16171 transitions. [2024-11-13 15:01:27,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12233 [2024-11-13 15:01:27,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12233 [2024-11-13 15:01:27,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12233 states and 16171 transitions. [2024-11-13 15:01:27,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:27,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12233 states and 16171 transitions. [2024-11-13 15:01:27,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12233 states and 16171 transitions. [2024-11-13 15:01:27,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12233 to 12233. [2024-11-13 15:01:27,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12233 states, 12233 states have (on average 1.321916128504864) internal successors, (16171), 12232 states have internal predecessors, (16171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:27,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12233 states to 12233 states and 16171 transitions. [2024-11-13 15:01:27,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12233 states and 16171 transitions. [2024-11-13 15:01:27,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:27,366 INFO L424 stractBuchiCegarLoop]: Abstraction has 12233 states and 16171 transitions. [2024-11-13 15:01:27,366 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 15:01:27,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12233 states and 16171 transitions. [2024-11-13 15:01:27,409 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12036 [2024-11-13 15:01:27,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:27,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:27,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:27,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:27,410 INFO L745 eck$LassoCheckResult]: Stem: 162795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 162796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 162897#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162898#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162636#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 162637#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 162910#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162864#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162865#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162892#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 162874#L526 assume !(0 == ~M_E~0); 162875#L526-2 assume !(0 == ~T1_E~0); 162913#L531-1 assume !(0 == ~T2_E~0); 162860#L536-1 assume !(0 == ~T3_E~0); 162861#L541-1 assume !(0 == ~T4_E~0); 162856#L546-1 assume !(0 == ~E_M~0); 162857#L551-1 assume !(0 == ~E_1~0); 162832#L556-1 assume !(0 == ~E_2~0); 162833#L561-1 assume !(0 == ~E_3~0); 162842#L566-1 assume !(0 == ~E_4~0); 162843#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162837#L262 assume !(1 == ~m_pc~0); 162838#L262-2 is_master_triggered_~__retres1~0#1 := 0; 163038#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162764#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 162765#L649 assume !(0 != activate_threads_~tmp~1#1); 163033#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162773#L281 assume !(1 == ~t1_pc~0); 162774#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162688#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162602#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162603#L657 assume !(0 != activate_threads_~tmp___0~0#1); 162745#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162846#L300 assume !(1 == ~t2_pc~0); 162847#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 162954#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162902#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 162868#L665 assume !(0 != activate_threads_~tmp___1~0#1); 162615#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162616#L319 assume !(1 == ~t3_pc~0); 162571#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 162572#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 162956#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163065#L673 assume !(0 != activate_threads_~tmp___2~0#1); 162592#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162593#L338 assume !(1 == ~t4_pc~0); 162660#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 162661#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162666#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162667#L681 assume !(0 != activate_threads_~tmp___3~0#1); 162540#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162541#L584 assume !(1 == ~M_E~0); 162742#L584-2 assume !(1 == ~T1_E~0); 162702#L589-1 assume !(1 == ~T2_E~0); 162703#L594-1 assume !(1 == ~T3_E~0); 162799#L599-1 assume !(1 == ~T4_E~0); 162570#L604-1 assume !(1 == ~E_M~0); 162556#L609-1 assume !(1 == ~E_1~0); 162557#L614-1 assume !(1 == ~E_2~0); 162677#L619-1 assume !(1 == ~E_3~0); 162766#L624-1 assume !(1 == ~E_4~0); 162866#L629-1 assume { :end_inline_reset_delta_events } true; 163046#L815-2 assume !false; 164072#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164066#L501-1 [2024-11-13 15:01:27,411 INFO L747 eck$LassoCheckResult]: Loop: 164066#L501-1 assume !false; 164058#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 164049#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 164042#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164041#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 164032#L440 assume 0 != eval_~tmp~0#1; 164023#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 164017#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 164016#L448-2 havoc eval_~tmp_ndt_1~0#1; 163740#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 163736#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 163734#L462-2 havoc eval_~tmp_ndt_2~0#1; 163541#L459-1 assume !(0 == ~t2_st~0); 163542#L473-1 assume !(0 == ~t3_st~0); 164073#L487-1 assume !(0 == ~t4_st~0); 164066#L501-1 [2024-11-13 15:01:27,411 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:27,411 INFO L85 PathProgramCache]: Analyzing trace with hash 39728907, now seen corresponding path program 2 times [2024-11-13 15:01:27,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:27,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203457848] [2024-11-13 15:01:27,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:27,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:27,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:27,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:27,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:27,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:27,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:27,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1852732600, now seen corresponding path program 1 times [2024-11-13 15:01:27,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:27,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927912384] [2024-11-13 15:01:27,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:27,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:27,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:27,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:27,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:27,460 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:27,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:27,461 INFO L85 PathProgramCache]: Analyzing trace with hash -305062146, now seen corresponding path program 1 times [2024-11-13 15:01:27,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:27,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424548991] [2024-11-13 15:01:27,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:27,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:27,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:27,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:27,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:27,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424548991] [2024-11-13 15:01:27,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424548991] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:27,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:27,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:27,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148514195] [2024-11-13 15:01:27,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:27,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:27,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:27,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:27,606 INFO L87 Difference]: Start difference. First operand 12233 states and 16171 transitions. cyclomatic complexity: 3950 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:27,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:27,717 INFO L93 Difference]: Finished difference Result 14453 states and 19007 transitions. [2024-11-13 15:01:27,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14453 states and 19007 transitions. [2024-11-13 15:01:27,786 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14256 [2024-11-13 15:01:27,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14453 states to 14453 states and 19007 transitions. [2024-11-13 15:01:27,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14453 [2024-11-13 15:01:27,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14453 [2024-11-13 15:01:27,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14453 states and 19007 transitions. [2024-11-13 15:01:27,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:27,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14453 states and 19007 transitions. [2024-11-13 15:01:27,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14453 states and 19007 transitions. [2024-11-13 15:01:28,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14453 to 13879. [2024-11-13 15:01:28,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13879 states, 13879 states have (on average 1.3180344405216513) internal successors, (18293), 13878 states have internal predecessors, (18293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:28,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13879 states to 13879 states and 18293 transitions. [2024-11-13 15:01:28,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13879 states and 18293 transitions. [2024-11-13 15:01:28,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:28,188 INFO L424 stractBuchiCegarLoop]: Abstraction has 13879 states and 18293 transitions. [2024-11-13 15:01:28,188 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 15:01:28,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13879 states and 18293 transitions. [2024-11-13 15:01:28,226 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13682 [2024-11-13 15:01:28,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:28,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:28,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:28,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:28,228 INFO L745 eck$LassoCheckResult]: Stem: 189490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 189491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 189590#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 189591#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189330#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 189331#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 189603#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 189555#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 189556#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 189583#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 189566#L526 assume !(0 == ~M_E~0); 189567#L526-2 assume !(0 == ~T1_E~0); 189606#L531-1 assume !(0 == ~T2_E~0); 189551#L536-1 assume !(0 == ~T3_E~0); 189552#L541-1 assume !(0 == ~T4_E~0); 189547#L546-1 assume !(0 == ~E_M~0); 189548#L551-1 assume !(0 == ~E_1~0); 189525#L556-1 assume !(0 == ~E_2~0); 189526#L561-1 assume !(0 == ~E_3~0); 189535#L566-1 assume !(0 == ~E_4~0); 189536#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189530#L262 assume !(1 == ~m_pc~0); 189531#L262-2 is_master_triggered_~__retres1~0#1 := 0; 189743#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189460#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 189461#L649 assume !(0 != activate_threads_~tmp~1#1); 189740#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189469#L281 assume !(1 == ~t1_pc~0); 189470#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 189380#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189296#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189297#L657 assume !(0 != activate_threads_~tmp___0~0#1); 189441#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189538#L300 assume !(1 == ~t2_pc~0); 189539#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 189648#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189560#L665 assume !(0 != activate_threads_~tmp___1~0#1); 189309#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189310#L319 assume !(1 == ~t3_pc~0); 189265#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 189266#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189650#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189776#L673 assume !(0 != activate_threads_~tmp___2~0#1); 189286#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189287#L338 assume !(1 == ~t4_pc~0); 189355#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 189356#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189361#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189362#L681 assume !(0 != activate_threads_~tmp___3~0#1); 189234#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189235#L584 assume !(1 == ~M_E~0); 189438#L584-2 assume !(1 == ~T1_E~0); 189394#L589-1 assume !(1 == ~T2_E~0); 189395#L594-1 assume !(1 == ~T3_E~0); 189494#L599-1 assume !(1 == ~T4_E~0); 189264#L604-1 assume !(1 == ~E_M~0); 189250#L609-1 assume !(1 == ~E_1~0); 189251#L614-1 assume !(1 == ~E_2~0); 189370#L619-1 assume !(1 == ~E_3~0); 189462#L624-1 assume !(1 == ~E_4~0); 189557#L629-1 assume { :end_inline_reset_delta_events } true; 189754#L815-2 assume !false; 193681#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193543#L501-1 [2024-11-13 15:01:28,228 INFO L747 eck$LassoCheckResult]: Loop: 193543#L501-1 assume !false; 193677#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 193674#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 193672#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 193670#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 193668#L440 assume 0 != eval_~tmp~0#1; 193665#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 193663#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 193662#L448-2 havoc eval_~tmp_ndt_1~0#1; 193587#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 193584#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 193582#L462-2 havoc eval_~tmp_ndt_2~0#1; 193580#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 193578#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 193563#L476-2 havoc eval_~tmp_ndt_3~0#1; 193549#L473-1 assume !(0 == ~t3_st~0); 193542#L487-1 assume !(0 == ~t4_st~0); 193543#L501-1 [2024-11-13 15:01:28,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:28,228 INFO L85 PathProgramCache]: Analyzing trace with hash 39728907, now seen corresponding path program 3 times [2024-11-13 15:01:28,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:28,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589471301] [2024-11-13 15:01:28,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:28,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:28,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:28,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:28,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:28,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:28,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:28,253 INFO L85 PathProgramCache]: Analyzing trace with hash 1788077744, now seen corresponding path program 1 times [2024-11-13 15:01:28,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:28,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335629335] [2024-11-13 15:01:28,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:28,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:28,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:28,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:28,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:28,261 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:28,262 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:28,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1254267674, now seen corresponding path program 1 times [2024-11-13 15:01:28,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:28,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028249881] [2024-11-13 15:01:28,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:28,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:28,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:28,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:28,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:28,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028249881] [2024-11-13 15:01:28,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028249881] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:28,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:28,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:01:28,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435509241] [2024-11-13 15:01:28,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:28,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:28,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:28,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:28,391 INFO L87 Difference]: Start difference. First operand 13879 states and 18293 transitions. cyclomatic complexity: 4426 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:28,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:28,623 INFO L93 Difference]: Finished difference Result 24481 states and 32179 transitions. [2024-11-13 15:01:28,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24481 states and 32179 transitions. [2024-11-13 15:01:28,706 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 24156 [2024-11-13 15:01:28,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24481 states to 24481 states and 32179 transitions. [2024-11-13 15:01:28,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24481 [2024-11-13 15:01:28,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24481 [2024-11-13 15:01:28,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24481 states and 32179 transitions. [2024-11-13 15:01:28,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:28,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24481 states and 32179 transitions. [2024-11-13 15:01:28,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24481 states and 32179 transitions. [2024-11-13 15:01:28,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24481 to 23293. [2024-11-13 15:01:29,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23293 states, 23293 states have (on average 1.3243034388013566) internal successors, (30847), 23292 states have internal predecessors, (30847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:29,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23293 states to 23293 states and 30847 transitions. [2024-11-13 15:01:29,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23293 states and 30847 transitions. [2024-11-13 15:01:29,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:29,216 INFO L424 stractBuchiCegarLoop]: Abstraction has 23293 states and 30847 transitions. [2024-11-13 15:01:29,216 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 15:01:29,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23293 states and 30847 transitions. [2024-11-13 15:01:29,280 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22968 [2024-11-13 15:01:29,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:29,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:29,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:29,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:29,281 INFO L745 eck$LassoCheckResult]: Stem: 227865#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 227866#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 227971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 227972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 227702#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 227703#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227985#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 227931#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 227932#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 227963#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 227943#L526 assume !(0 == ~M_E~0); 227944#L526-2 assume !(0 == ~T1_E~0); 227988#L531-1 assume !(0 == ~T2_E~0); 227927#L536-1 assume !(0 == ~T3_E~0); 227928#L541-1 assume !(0 == ~T4_E~0); 227923#L546-1 assume !(0 == ~E_M~0); 227924#L551-1 assume !(0 == ~E_1~0); 227901#L556-1 assume !(0 == ~E_2~0); 227902#L561-1 assume !(0 == ~E_3~0); 227911#L566-1 assume !(0 == ~E_4~0); 227912#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227906#L262 assume !(1 == ~m_pc~0); 227907#L262-2 is_master_triggered_~__retres1~0#1 := 0; 228130#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227833#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 227834#L649 assume !(0 != activate_threads_~tmp~1#1); 228128#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 227843#L281 assume !(1 == ~t1_pc~0); 227844#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 227755#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227666#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 227667#L657 assume !(0 != activate_threads_~tmp___0~0#1); 227815#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 227914#L300 assume !(1 == ~t2_pc~0); 227915#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 228035#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227976#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 227936#L665 assume !(0 != activate_threads_~tmp___1~0#1); 227679#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227680#L319 assume !(1 == ~t3_pc~0); 227635#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 227636#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228037#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 228169#L673 assume !(0 != activate_threads_~tmp___2~0#1); 227656#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227657#L338 assume !(1 == ~t4_pc~0); 227727#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227728#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227733#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 227734#L681 assume !(0 != activate_threads_~tmp___3~0#1); 227602#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227603#L584 assume !(1 == ~M_E~0); 227812#L584-2 assume !(1 == ~T1_E~0); 227769#L589-1 assume !(1 == ~T2_E~0); 227770#L594-1 assume !(1 == ~T3_E~0); 227869#L599-1 assume !(1 == ~T4_E~0); 227634#L604-1 assume !(1 == ~E_M~0); 227620#L609-1 assume !(1 == ~E_1~0); 227621#L614-1 assume !(1 == ~E_2~0); 227744#L619-1 assume !(1 == ~E_3~0); 227835#L624-1 assume !(1 == ~E_4~0); 227933#L629-1 assume { :end_inline_reset_delta_events } true; 228143#L815-2 assume !false; 232250#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232248#L501-1 [2024-11-13 15:01:29,281 INFO L747 eck$LassoCheckResult]: Loop: 232248#L501-1 assume !false; 232246#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 232243#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 232240#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 232238#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 232236#L440 assume 0 != eval_~tmp~0#1; 232224#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 232215#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 232209#L448-2 havoc eval_~tmp_ndt_1~0#1; 232204#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 232175#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 232198#L462-2 havoc eval_~tmp_ndt_2~0#1; 232423#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 232418#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 232419#L476-2 havoc eval_~tmp_ndt_3~0#1; 232290#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 232286#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 232281#L490-2 havoc eval_~tmp_ndt_4~0#1; 232251#L487-1 assume !(0 == ~t4_st~0); 232248#L501-1 [2024-11-13 15:01:29,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:29,286 INFO L85 PathProgramCache]: Analyzing trace with hash 39728907, now seen corresponding path program 4 times [2024-11-13 15:01:29,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:29,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361285416] [2024-11-13 15:01:29,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:29,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:29,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:29,312 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:29,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:29,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:29,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:29,344 INFO L85 PathProgramCache]: Analyzing trace with hash 351082504, now seen corresponding path program 1 times [2024-11-13 15:01:29,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:29,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8816535] [2024-11-13 15:01:29,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:29,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:29,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:29,356 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:29,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:29,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:29,365 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:29,365 INFO L85 PathProgramCache]: Analyzing trace with hash 1529864382, now seen corresponding path program 1 times [2024-11-13 15:01:29,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:29,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123902823] [2024-11-13 15:01:29,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:29,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:29,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:01:29,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:01:29,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:01:29,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123902823] [2024-11-13 15:01:29,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123902823] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:01:29,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:01:29,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:01:29,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452093727] [2024-11-13 15:01:29,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:01:29,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:01:29,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:01:29,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:01:29,515 INFO L87 Difference]: Start difference. First operand 23293 states and 30847 transitions. cyclomatic complexity: 7566 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:29,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:01:29,673 INFO L93 Difference]: Finished difference Result 27637 states and 36417 transitions. [2024-11-13 15:01:29,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27637 states and 36417 transitions. [2024-11-13 15:01:29,959 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 27304 [2024-11-13 15:01:30,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27637 states to 27637 states and 36417 transitions. [2024-11-13 15:01:30,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27637 [2024-11-13 15:01:30,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27637 [2024-11-13 15:01:30,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27637 states and 36417 transitions. [2024-11-13 15:01:30,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:01:30,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27637 states and 36417 transitions. [2024-11-13 15:01:30,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27637 states and 36417 transitions. [2024-11-13 15:01:30,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27637 to 27349. [2024-11-13 15:01:30,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27349 states, 27349 states have (on average 1.3210355040403672) internal successors, (36129), 27348 states have internal predecessors, (36129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:01:30,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27349 states to 27349 states and 36129 transitions. [2024-11-13 15:01:30,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27349 states and 36129 transitions. [2024-11-13 15:01:30,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:01:30,555 INFO L424 stractBuchiCegarLoop]: Abstraction has 27349 states and 36129 transitions. [2024-11-13 15:01:30,555 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 15:01:30,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27349 states and 36129 transitions. [2024-11-13 15:01:30,635 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 27016 [2024-11-13 15:01:30,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:01:30,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:01:30,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:30,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:01:30,637 INFO L745 eck$LassoCheckResult]: Stem: 278801#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 278802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 278915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 278916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278640#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 278641#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 278934#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 278868#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 278869#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 278906#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 278883#L526 assume !(0 == ~M_E~0); 278884#L526-2 assume !(0 == ~T1_E~0); 278936#L531-1 assume !(0 == ~T2_E~0); 278864#L536-1 assume !(0 == ~T3_E~0); 278865#L541-1 assume !(0 == ~T4_E~0); 278860#L546-1 assume !(0 == ~E_M~0); 278861#L551-1 assume !(0 == ~E_1~0); 278837#L556-1 assume !(0 == ~E_2~0); 278838#L561-1 assume !(0 == ~E_3~0); 278847#L566-1 assume !(0 == ~E_4~0); 278848#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278842#L262 assume !(1 == ~m_pc~0); 278843#L262-2 is_master_triggered_~__retres1~0#1 := 0; 279093#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278768#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 278769#L649 assume !(0 != activate_threads_~tmp~1#1); 279092#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278778#L281 assume !(1 == ~t1_pc~0); 278779#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 278693#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 278605#L657 assume !(0 != activate_threads_~tmp___0~0#1); 278753#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278850#L300 assume !(1 == ~t2_pc~0); 278851#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278982#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 278873#L665 assume !(0 != activate_threads_~tmp___1~0#1); 278617#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278618#L319 assume !(1 == ~t3_pc~0); 278571#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 278572#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278984#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 279136#L673 assume !(0 != activate_threads_~tmp___2~0#1); 278593#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278594#L338 assume !(1 == ~t4_pc~0); 278667#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 278668#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 278675#L681 assume !(0 != activate_threads_~tmp___3~0#1); 278540#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278541#L584 assume !(1 == ~M_E~0); 278750#L584-2 assume !(1 == ~T1_E~0); 278708#L589-1 assume !(1 == ~T2_E~0); 278709#L594-1 assume !(1 == ~T3_E~0); 278807#L599-1 assume !(1 == ~T4_E~0); 278570#L604-1 assume !(1 == ~E_M~0); 278556#L609-1 assume !(1 == ~E_1~0); 278557#L614-1 assume !(1 == ~E_2~0); 278682#L619-1 assume !(1 == ~E_3~0); 278770#L624-1 assume !(1 == ~E_4~0); 278870#L629-1 assume { :end_inline_reset_delta_events } true; 279106#L815-2 assume !false; 286659#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 286656#L501-1 [2024-11-13 15:01:30,637 INFO L747 eck$LassoCheckResult]: Loop: 286656#L501-1 assume !false; 286654#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 286649#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 286647#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 286645#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 286643#L440 assume 0 != eval_~tmp~0#1; 286639#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 286636#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 285799#L448-2 havoc eval_~tmp_ndt_1~0#1; 285080#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 285073#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 285065#L462-2 havoc eval_~tmp_ndt_2~0#1; 285060#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 285055#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 285050#L476-2 havoc eval_~tmp_ndt_3~0#1; 285043#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 285013#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 285037#L490-2 havoc eval_~tmp_ndt_4~0#1; 288630#L487-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 288627#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 286660#L504-2 havoc eval_~tmp_ndt_5~0#1; 286656#L501-1 [2024-11-13 15:01:30,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:30,638 INFO L85 PathProgramCache]: Analyzing trace with hash 39728907, now seen corresponding path program 5 times [2024-11-13 15:01:30,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:30,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762600285] [2024-11-13 15:01:30,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:30,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:30,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,652 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:30,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,666 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:30,667 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:30,667 INFO L85 PathProgramCache]: Analyzing trace with hash -1912240784, now seen corresponding path program 1 times [2024-11-13 15:01:30,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:30,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963058818] [2024-11-13 15:01:30,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:30,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:30,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,671 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:30,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:30,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:01:30,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1320745126, now seen corresponding path program 1 times [2024-11-13 15:01:30,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:01:30,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935912916] [2024-11-13 15:01:30,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:01:30,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:01:30,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:30,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:30,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:01:32,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:32,339 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:01:32,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:01:32,568 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 03:01:32 BoogieIcfgContainer [2024-11-13 15:01:32,568 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 15:01:32,568 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 15:01:32,569 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 15:01:32,569 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 15:01:32,574 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:01:18" (3/4) ... [2024-11-13 15:01:32,575 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 15:01:32,667 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 15:01:32,667 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 15:01:32,670 INFO L158 Benchmark]: Toolchain (without parser) took 16514.99ms. Allocated memory was 117.4MB in the beginning and 1.3GB in the end (delta: 1.2GB). Free memory was 92.3MB in the beginning and 924.1MB in the end (delta: -831.7MB). Peak memory consumption was 376.2MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,671 INFO L158 Benchmark]: CDTParser took 0.87ms. Allocated memory is still 117.4MB. Free memory was 74.9MB in the beginning and 74.7MB in the end (delta: 196.3kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:01:32,671 INFO L158 Benchmark]: CACSL2BoogieTranslator took 457.84ms. Allocated memory is still 117.4MB. Free memory was 92.3MB in the beginning and 77.1MB in the end (delta: 15.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,671 INFO L158 Benchmark]: Boogie Procedure Inliner took 88.27ms. Allocated memory is still 117.4MB. Free memory was 77.1MB in the beginning and 73.1MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 15:01:32,672 INFO L158 Benchmark]: Boogie Preprocessor took 90.57ms. Allocated memory is still 117.4MB. Free memory was 73.1MB in the beginning and 68.4MB in the end (delta: 4.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,673 INFO L158 Benchmark]: RCFGBuilder took 1372.37ms. Allocated memory is still 117.4MB. Free memory was 68.4MB in the beginning and 62.3MB in the end (delta: 6.1MB). Peak memory consumption was 31.8MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,673 INFO L158 Benchmark]: BuchiAutomizer took 14398.01ms. Allocated memory was 117.4MB in the beginning and 1.3GB in the end (delta: 1.2GB). Free memory was 62.3MB in the beginning and 936.7MB in the end (delta: -874.4MB). Peak memory consumption was 336.0MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,674 INFO L158 Benchmark]: Witness Printer took 98.62ms. Allocated memory is still 1.3GB. Free memory was 936.7MB in the beginning and 924.1MB in the end (delta: 12.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 15:01:32,677 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.87ms. Allocated memory is still 117.4MB. Free memory was 74.9MB in the beginning and 74.7MB in the end (delta: 196.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 457.84ms. Allocated memory is still 117.4MB. Free memory was 92.3MB in the beginning and 77.1MB in the end (delta: 15.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 88.27ms. Allocated memory is still 117.4MB. Free memory was 77.1MB in the beginning and 73.1MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 90.57ms. Allocated memory is still 117.4MB. Free memory was 73.1MB in the beginning and 68.4MB in the end (delta: 4.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1372.37ms. Allocated memory is still 117.4MB. Free memory was 68.4MB in the beginning and 62.3MB in the end (delta: 6.1MB). Peak memory consumption was 31.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 14398.01ms. Allocated memory was 117.4MB in the beginning and 1.3GB in the end (delta: 1.2GB). Free memory was 62.3MB in the beginning and 936.7MB in the end (delta: -874.4MB). Peak memory consumption was 336.0MB. Max. memory is 16.1GB. * Witness Printer took 98.62ms. Allocated memory is still 1.3GB. Free memory was 936.7MB in the beginning and 924.1MB in the end (delta: 12.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 27349 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 14.1s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 5.6s. Construction of modules took 1.1s. Büchi inclusion checks took 6.6s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 3.0s AutomataMinimizationTime, 24 MinimizatonAttempts, 8458 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 1.6s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12810 SdHoareTripleChecker+Valid, 1.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12810 mSDsluCounter, 31283 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14677 mSDsCounter, 252 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 903 IncrementalHoareTripleChecker+Invalid, 1155 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 252 mSolverCounterUnsat, 16606 mSDtfsCounter, 903 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 15:01:32,717 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_94cbfae2-4b8c-4a71-931b-fd6404aa9c02/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)