./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 14:11:35,036 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 14:11:35,135 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 14:11:35,141 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 14:11:35,142 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 14:11:35,175 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 14:11:35,177 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 14:11:35,178 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 14:11:35,178 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 14:11:35,178 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 14:11:35,180 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 14:11:35,180 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 14:11:35,180 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 14:11:35,180 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 14:11:35,181 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 14:11:35,181 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 14:11:35,181 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 14:11:35,182 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 14:11:35,182 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 14:11:35,183 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 14:11:35,183 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 14:11:35,184 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 14:11:35,184 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 14:11:35,184 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 14:11:35,184 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2024-11-13 14:11:35,500 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 14:11:35,514 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 14:11:35,516 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 14:11:35,519 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 14:11:35,520 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 14:11:35,522 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c Unable to find full path for "g++" [2024-11-13 14:11:37,357 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 14:11:37,673 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 14:11:37,678 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2024-11-13 14:11:37,698 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/data/40fe1fa2b/aa092e0581444df4aaf50d1a24434cbb/FLAG646debb4f [2024-11-13 14:11:37,723 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/data/40fe1fa2b/aa092e0581444df4aaf50d1a24434cbb [2024-11-13 14:11:37,727 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 14:11:37,729 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 14:11:37,731 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 14:11:37,732 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 14:11:37,736 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 14:11:37,737 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:11:37" (1/1) ... [2024-11-13 14:11:37,740 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@769de16b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:37, skipping insertion in model container [2024-11-13 14:11:37,740 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 02:11:37" (1/1) ... [2024-11-13 14:11:37,786 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 14:11:38,104 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:11:38,117 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 14:11:38,216 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 14:11:38,245 INFO L204 MainTranslator]: Completed translation [2024-11-13 14:11:38,246 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38 WrapperNode [2024-11-13 14:11:38,247 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 14:11:38,248 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 14:11:38,248 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 14:11:38,248 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 14:11:38,262 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,273 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,356 INFO L138 Inliner]: procedures = 38, calls = 48, calls flagged for inlining = 43, calls inlined = 97, statements flattened = 1360 [2024-11-13 14:11:38,357 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 14:11:38,357 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 14:11:38,361 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 14:11:38,361 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 14:11:38,377 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,377 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,381 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,408 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 14:11:38,408 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,408 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,425 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,452 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,454 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,462 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,474 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 14:11:38,474 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 14:11:38,474 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 14:11:38,475 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 14:11:38,479 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (1/1) ... [2024-11-13 14:11:38,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:38,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:38,513 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:38,517 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 14:11:38,546 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 14:11:38,546 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 14:11:38,546 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 14:11:38,546 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 14:11:38,662 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 14:11:38,664 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 14:11:40,181 INFO L? ?]: Removed 256 outVars from TransFormulas that were not future-live. [2024-11-13 14:11:40,181 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 14:11:40,216 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 14:11:40,216 INFO L316 CfgBuilder]: Removed 8 assume(true) statements. [2024-11-13 14:11:40,217 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:11:40 BoogieIcfgContainer [2024-11-13 14:11:40,217 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 14:11:40,222 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 14:11:40,222 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 14:11:40,230 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 14:11:40,231 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:11:40,231 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 02:11:37" (1/3) ... [2024-11-13 14:11:40,234 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@388c3685 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:11:40, skipping insertion in model container [2024-11-13 14:11:40,234 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:11:40,234 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 02:11:38" (2/3) ... [2024-11-13 14:11:40,234 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@388c3685 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 02:11:40, skipping insertion in model container [2024-11-13 14:11:40,234 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 14:11:40,234 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:11:40" (3/3) ... [2024-11-13 14:11:40,237 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2024-11-13 14:11:40,317 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 14:11:40,317 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 14:11:40,317 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 14:11:40,317 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 14:11:40,317 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 14:11:40,318 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 14:11:40,318 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 14:11:40,318 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 14:11:40,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:40,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2024-11-13 14:11:40,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:40,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:40,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,378 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 14:11:40,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:40,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2024-11-13 14:11:40,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:40,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:40,415 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,429 INFO L745 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 472#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 469#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 328#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 153#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 323#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 507#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 364#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 385#L611-2true assume !(0 == ~T1_E~0); 382#L616-1true assume !(0 == ~T2_E~0); 390#L621-1true assume !(0 == ~T3_E~0); 65#L626-1true assume !(0 == ~T4_E~0); 354#L631-1true assume !(0 == ~T5_E~0); 177#L636-1true assume !(0 == ~E_M~0); 91#L641-1true assume !(0 == ~E_1~0); 188#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 498#L651-1true assume !(0 == ~E_3~0); 444#L656-1true assume !(0 == ~E_4~0); 362#L661-1true assume !(0 == ~E_5~0); 407#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530#L304true assume !(1 == ~m_pc~0); 104#L304-2true is_master_triggered_~__retres1~0#1 := 0; 52#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27#L755true assume !(0 != activate_threads_~tmp~1#1); 553#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6#L323true assume 1 == ~t1_pc~0; 309#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499#L763true assume !(0 != activate_threads_~tmp___0~0#1); 510#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37#L342true assume 1 == ~t2_pc~0; 524#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 110#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532#L771true assume !(0 != activate_threads_~tmp___1~0#1); 355#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L361true assume !(1 == ~t3_pc~0); 256#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 463#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237#L380true assume 1 == ~t4_pc~0; 77#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270#L787true assume !(0 != activate_threads_~tmp___3~0#1); 522#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78#L399true assume !(1 == ~t5_pc~0); 159#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 387#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154#L795true assume !(0 != activate_threads_~tmp___4~0#1); 458#L795-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L679true assume !(1 == ~M_E~0); 206#L679-2true assume !(1 == ~T1_E~0); 117#L684-1true assume !(1 == ~T2_E~0); 244#L689-1true assume !(1 == ~T3_E~0); 544#L694-1true assume !(1 == ~T4_E~0); 243#L699-1true assume !(1 == ~T5_E~0); 363#L704-1true assume !(1 == ~E_M~0); 224#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 180#L714-1true assume !(1 == ~E_2~0); 344#L719-1true assume !(1 == ~E_3~0); 483#L724-1true assume !(1 == ~E_4~0); 59#L729-1true assume !(1 == ~E_5~0); 465#L734-1true assume { :end_inline_reset_delta_events } true; 333#L940-2true [2024-11-13 14:11:40,431 INFO L747 eck$LassoCheckResult]: Loop: 333#L940-2true assume !false; 402#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 447#L586-1true assume !true; 96#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 412#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 303#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 60#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 319#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 57#L621-3true assume !(0 == ~T3_E~0); 30#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 563#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 31#L636-3true assume 0 == ~E_M~0;~E_M~0 := 1; 66#L641-3true assume 0 == ~E_1~0;~E_1~0 := 1; 240#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 72#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 218#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L661-3true assume !(0 == ~E_5~0); 512#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157#L304-21true assume 1 == ~m_pc~0; 519#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 267#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197#L755-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 220#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 495#L323-21true assume !(1 == ~t1_pc~0); 372#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 408#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 403#L763-21true assume !(0 != activate_threads_~tmp___0~0#1); 423#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560#L342-21true assume 1 == ~t2_pc~0; 25#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 261#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478#L361-21true assume !(1 == ~t3_pc~0); 460#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 482#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518#L380-21true assume 1 == ~t4_pc~0; 432#L381-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144#L399-21true assume 1 == ~t5_pc~0; 129#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 286#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 451#L795-23true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 185#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 230#L684-3true assume !(1 == ~T2_E~0); 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 168#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L699-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 307#L704-3true assume 1 == ~E_M~0;~E_M~0 := 2; 400#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 291#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 162#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 20#L724-3true assume !(1 == ~E_4~0); 276#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 326#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 34#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 219#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 250#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 253#L959true assume !(0 == start_simulation_~tmp~3#1); 517#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 384#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 373#L914true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 128#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 422#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 308#L972true assume !(0 != start_simulation_~tmp___0~1#1); 333#L940-2true [2024-11-13 14:11:40,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:40,436 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2024-11-13 14:11:40,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:40,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891676377] [2024-11-13 14:11:40,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:40,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:40,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:40,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:40,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:40,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891676377] [2024-11-13 14:11:40,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891676377] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:40,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:40,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:40,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900527392] [2024-11-13 14:11:40,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:40,714 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:40,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:40,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1574356605, now seen corresponding path program 1 times [2024-11-13 14:11:40,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:40,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835178945] [2024-11-13 14:11:40,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:40,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:40,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:40,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:40,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:40,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835178945] [2024-11-13 14:11:40,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [835178945] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:40,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:40,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:11:40,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280982598] [2024-11-13 14:11:40,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:40,767 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:40,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:40,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:40,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:40,800 INFO L87 Difference]: Start difference. First operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:40,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:40,860 INFO L93 Difference]: Finished difference Result 563 states and 839 transitions. [2024-11-13 14:11:40,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 563 states and 839 transitions. [2024-11-13 14:11:40,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:40,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 563 states to 557 states and 833 transitions. [2024-11-13 14:11:40,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-13 14:11:40,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-13 14:11:40,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 833 transitions. [2024-11-13 14:11:40,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:40,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-13 14:11:40,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 833 transitions. [2024-11-13 14:11:40,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-13 14:11:40,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4955116696588868) internal successors, (833), 556 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:40,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 833 transitions. [2024-11-13 14:11:40,965 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-13 14:11:40,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:40,970 INFO L424 stractBuchiCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-13 14:11:40,970 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 14:11:40,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 833 transitions. [2024-11-13 14:11:40,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:40,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:40,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:40,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:40,977 INFO L745 eck$LassoCheckResult]: Stem: 1478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1564#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1565#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1421#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1422#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1399#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1400#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1630#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1502#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1503#L611-2 assume !(0 == ~T1_E~0); 1642#L616-1 assume !(0 == ~T2_E~0); 1643#L621-1 assume !(0 == ~T3_E~0); 1267#L626-1 assume !(0 == ~T4_E~0); 1268#L631-1 assume !(0 == ~T5_E~0); 1459#L636-1 assume !(0 == ~E_M~0); 1319#L641-1 assume !(0 == ~E_1~0); 1320#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1476#L651-1 assume !(0 == ~E_3~0); 1671#L656-1 assume !(0 == ~E_4~0); 1628#L661-1 assume !(0 == ~E_5~0); 1629#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1655#L304 assume !(1 == ~m_pc~0); 1345#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1242#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1193#L755 assume !(0 != activate_threads_~tmp~1#1); 1194#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1149#L323 assume 1 == ~t1_pc~0; 1150#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1212#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1228#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1691#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1215#L342 assume 1 == ~t2_pc~0; 1216#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1351#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1352#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1580#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1625#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1535#L361 assume !(1 == ~t3_pc~0); 1536#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1560#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234#L380 assume 1 == ~t4_pc~0; 1289#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1290#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1567#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1292#L399 assume !(1 == ~t5_pc~0); 1293#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1423#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1424#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L679 assume !(1 == ~M_E~0); 1500#L679-2 assume !(1 == ~T1_E~0); 1364#L684-1 assume !(1 == ~T2_E~0); 1365#L689-1 assume !(1 == ~T3_E~0); 1543#L694-1 assume !(1 == ~T4_E~0); 1541#L699-1 assume !(1 == ~T5_E~0); 1542#L704-1 assume !(1 == ~E_M~0); 1525#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1466#L714-1 assume !(1 == ~E_2~0); 1467#L719-1 assume !(1 == ~E_3~0); 1621#L724-1 assume !(1 == ~E_4~0); 1253#L729-1 assume !(1 == ~E_5~0); 1254#L734-1 assume { :end_inline_reset_delta_events } true; 1597#L940-2 [2024-11-13 14:11:40,979 INFO L747 eck$LassoCheckResult]: Loop: 1597#L940-2 assume !false; 1611#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1327#L586-1 assume !false; 1674#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1677#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1538#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1539#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1534#L511 assume !(0 != eval_~tmp~0#1); 1330#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1591#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1256#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1251#L621-3 assume !(0 == ~T3_E~0); 1200#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1201#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1202#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1203#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1269#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1279#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1280#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1519#L661-3 assume !(0 == ~E_5~0); 1692#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1428#L304-21 assume !(1 == ~m_pc~0); 1282#L304-23 is_master_triggered_~__retres1~0#1 := 0; 1283#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1358#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1359#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1487#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1521#L323-21 assume 1 == ~t1_pc~0; 1162#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1163#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1301#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1302#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 1653#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664#L342-21 assume 1 == ~t2_pc~0; 1188#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1189#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1498#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1499#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1295#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1296#L361-21 assume !(1 == ~t3_pc~0); 1681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1686#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1462#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1198#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1199#L380-21 assume 1 == ~t4_pc~0; 1670#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1262#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1568#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1409#L399-21 assume !(1 == ~t5_pc~0); 1265#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1266#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1558#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1559#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1191#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1192#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1472#L684-3 assume !(1 == ~T2_E~0); 1139#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1140#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1180#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1181#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1595#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1586#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1433#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1178#L724-3 assume !(1 == ~E_4~0); 1179#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1574#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1209#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1210#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1553#L959 assume !(0 == start_simulation_~tmp~3#1); 1557#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1463#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1464#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1225#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1383#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1384#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1596#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1597#L940-2 [2024-11-13 14:11:40,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:40,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2024-11-13 14:11:40,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:40,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977958879] [2024-11-13 14:11:40,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:40,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977958879] [2024-11-13 14:11:41,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977958879] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698407548] [2024-11-13 14:11:41,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,103 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:41,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1301619801, now seen corresponding path program 1 times [2024-11-13 14:11:41,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325908967] [2024-11-13 14:11:41,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325908967] [2024-11-13 14:11:41,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325908967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430678193] [2024-11-13 14:11:41,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,269 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:41,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:41,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:41,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:41,271 INFO L87 Difference]: Start difference. First operand 557 states and 833 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:41,295 INFO L93 Difference]: Finished difference Result 557 states and 832 transitions. [2024-11-13 14:11:41,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 832 transitions. [2024-11-13 14:11:41,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 832 transitions. [2024-11-13 14:11:41,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-13 14:11:41,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-13 14:11:41,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 832 transitions. [2024-11-13 14:11:41,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:41,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-13 14:11:41,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 832 transitions. [2024-11-13 14:11:41,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-13 14:11:41,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4937163375224416) internal successors, (832), 556 states have internal predecessors, (832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 832 transitions. [2024-11-13 14:11:41,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-13 14:11:41,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:41,323 INFO L424 stractBuchiCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-13 14:11:41,323 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 14:11:41,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 832 transitions. [2024-11-13 14:11:41,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:41,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:41,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,330 INFO L745 eck$LassoCheckResult]: Stem: 2599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2685#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2686#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2542#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2543#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2520#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2521#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2751#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2623#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2624#L611-2 assume !(0 == ~T1_E~0); 2763#L616-1 assume !(0 == ~T2_E~0); 2764#L621-1 assume !(0 == ~T3_E~0); 2388#L626-1 assume !(0 == ~T4_E~0); 2389#L631-1 assume !(0 == ~T5_E~0); 2583#L636-1 assume !(0 == ~E_M~0); 2440#L641-1 assume !(0 == ~E_1~0); 2441#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2597#L651-1 assume !(0 == ~E_3~0); 2792#L656-1 assume !(0 == ~E_4~0); 2749#L661-1 assume !(0 == ~E_5~0); 2750#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2776#L304 assume !(1 == ~m_pc~0); 2467#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2363#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2364#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2316#L755 assume !(0 != activate_threads_~tmp~1#1); 2317#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2270#L323 assume 1 == ~t1_pc~0; 2271#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2333#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2349#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2812#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2340#L342 assume 1 == ~t2_pc~0; 2341#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2472#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2701#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2746#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2656#L361 assume !(1 == ~t3_pc~0); 2657#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2681#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2287#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2354#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2355#L380 assume 1 == ~t4_pc~0; 2410#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2411#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2436#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2437#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2688#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2413#L399 assume !(1 == ~t5_pc~0); 2414#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2552#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2544#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2545#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L679 assume !(1 == ~M_E~0); 2621#L679-2 assume !(1 == ~T1_E~0); 2485#L684-1 assume !(1 == ~T2_E~0); 2486#L689-1 assume !(1 == ~T3_E~0); 2664#L694-1 assume !(1 == ~T4_E~0); 2662#L699-1 assume !(1 == ~T5_E~0); 2663#L704-1 assume !(1 == ~E_M~0); 2646#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2587#L714-1 assume !(1 == ~E_2~0); 2588#L719-1 assume !(1 == ~E_3~0); 2742#L724-1 assume !(1 == ~E_4~0); 2374#L729-1 assume !(1 == ~E_5~0); 2375#L734-1 assume { :end_inline_reset_delta_events } true; 2718#L940-2 [2024-11-13 14:11:41,331 INFO L747 eck$LassoCheckResult]: Loop: 2718#L940-2 assume !false; 2732#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2448#L586-1 assume !false; 2795#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2798#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2659#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2660#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2655#L511 assume !(0 != eval_~tmp~0#1); 2451#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2712#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2376#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2377#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2373#L621-3 assume !(0 == ~T3_E~0); 2321#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2322#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2323#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2324#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2390#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2400#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2401#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2640#L661-3 assume !(0 == ~E_5~0); 2813#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2549#L304-21 assume !(1 == ~m_pc~0); 2403#L304-23 is_master_triggered_~__retres1~0#1 := 0; 2404#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2479#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2480#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2608#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2642#L323-21 assume 1 == ~t1_pc~0; 2283#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2422#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2423#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 2774#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2785#L342-21 assume 1 == ~t2_pc~0; 2309#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2310#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2617#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2618#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2416#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2417#L361-21 assume !(1 == ~t3_pc~0); 2802#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2803#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2807#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2582#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2314#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L380-21 assume 1 == ~t4_pc~0; 2791#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2381#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2456#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2739#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2689#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2530#L399-21 assume !(1 == ~t5_pc~0); 2386#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2387#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2679#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2680#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2797#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2312#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2313#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2593#L684-3 assume !(1 == ~T2_E~0); 2260#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2261#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2301#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2302#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2716#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2707#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2554#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2299#L724-3 assume !(1 == ~E_4~0); 2300#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2695#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2330#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2331#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L959 assume !(0 == start_simulation_~tmp~3#1); 2678#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2584#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2585#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2346#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2504#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2505#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2717#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2718#L940-2 [2024-11-13 14:11:41,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2024-11-13 14:11:41,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31582278] [2024-11-13 14:11:41,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31582278] [2024-11-13 14:11:41,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31582278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116341726] [2024-11-13 14:11:41,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,393 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:41,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,394 INFO L85 PathProgramCache]: Analyzing trace with hash 1301619801, now seen corresponding path program 2 times [2024-11-13 14:11:41,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838415982] [2024-11-13 14:11:41,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838415982] [2024-11-13 14:11:41,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1838415982] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190559259] [2024-11-13 14:11:41,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,458 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:41,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:41,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:41,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:41,458 INFO L87 Difference]: Start difference. First operand 557 states and 832 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:41,476 INFO L93 Difference]: Finished difference Result 557 states and 831 transitions. [2024-11-13 14:11:41,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 831 transitions. [2024-11-13 14:11:41,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 831 transitions. [2024-11-13 14:11:41,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-13 14:11:41,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-13 14:11:41,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 831 transitions. [2024-11-13 14:11:41,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:41,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-13 14:11:41,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 831 transitions. [2024-11-13 14:11:41,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-13 14:11:41,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4919210053859964) internal successors, (831), 556 states have internal predecessors, (831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 831 transitions. [2024-11-13 14:11:41,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-13 14:11:41,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:41,552 INFO L424 stractBuchiCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-13 14:11:41,552 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 14:11:41,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 831 transitions. [2024-11-13 14:11:41,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:41,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:41,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,558 INFO L745 eck$LassoCheckResult]: Stem: 3720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3806#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3807#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3663#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3664#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3641#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3642#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3872#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3744#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3745#L611-2 assume !(0 == ~T1_E~0); 3885#L616-1 assume !(0 == ~T2_E~0); 3886#L621-1 assume !(0 == ~T3_E~0); 3509#L626-1 assume !(0 == ~T4_E~0); 3510#L631-1 assume !(0 == ~T5_E~0); 3704#L636-1 assume !(0 == ~E_M~0); 3561#L641-1 assume !(0 == ~E_1~0); 3562#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3718#L651-1 assume !(0 == ~E_3~0); 3913#L656-1 assume !(0 == ~E_4~0); 3870#L661-1 assume !(0 == ~E_5~0); 3871#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3897#L304 assume !(1 == ~m_pc~0); 3590#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3484#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3485#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3437#L755 assume !(0 != activate_threads_~tmp~1#1); 3438#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L323 assume 1 == ~t1_pc~0; 3392#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3454#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3470#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3933#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3461#L342 assume 1 == ~t2_pc~0; 3462#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3593#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3822#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3867#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3777#L361 assume !(1 == ~t3_pc~0); 3778#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3802#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3407#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3408#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3475#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3476#L380 assume 1 == ~t4_pc~0; 3531#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3532#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3558#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3534#L399 assume !(1 == ~t5_pc~0); 3535#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3674#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3665#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3666#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3922#L679 assume !(1 == ~M_E~0); 3743#L679-2 assume !(1 == ~T1_E~0); 3606#L684-1 assume !(1 == ~T2_E~0); 3607#L689-1 assume !(1 == ~T3_E~0); 3785#L694-1 assume !(1 == ~T4_E~0); 3783#L699-1 assume !(1 == ~T5_E~0); 3784#L704-1 assume !(1 == ~E_M~0); 3767#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3708#L714-1 assume !(1 == ~E_2~0); 3709#L719-1 assume !(1 == ~E_3~0); 3863#L724-1 assume !(1 == ~E_4~0); 3495#L729-1 assume !(1 == ~E_5~0); 3496#L734-1 assume { :end_inline_reset_delta_events } true; 3839#L940-2 [2024-11-13 14:11:41,558 INFO L747 eck$LassoCheckResult]: Loop: 3839#L940-2 assume !false; 3853#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3569#L586-1 assume !false; 3916#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3919#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3780#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3776#L511 assume !(0 != eval_~tmp~0#1); 3572#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3573#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3833#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3497#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3498#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3494#L621-3 assume !(0 == ~T3_E~0); 3442#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3443#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3444#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3445#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3511#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3521#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3522#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3761#L661-3 assume !(0 == ~E_5~0); 3934#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3670#L304-21 assume !(1 == ~m_pc~0); 3524#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3525#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3600#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3601#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3729#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3763#L323-21 assume 1 == ~t1_pc~0; 3404#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3405#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3543#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3544#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 3895#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3906#L342-21 assume 1 == ~t2_pc~0; 3430#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3431#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3738#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3739#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3538#L361-21 assume !(1 == ~t3_pc~0); 3923#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3924#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3928#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3703#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3435#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3436#L380-21 assume 1 == ~t4_pc~0; 3912#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3504#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3577#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3860#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3810#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3651#L399-21 assume !(1 == ~t5_pc~0); 3507#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3508#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3800#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3801#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3918#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3433#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3434#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3714#L684-3 assume !(1 == ~T2_E~0); 3381#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3382#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3422#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3423#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3837#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3828#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3675#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L724-3 assume !(1 == ~E_4~0); 3421#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3818#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3451#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3452#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3795#L959 assume !(0 == start_simulation_~tmp~3#1); 3799#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3705#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3706#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3467#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3625#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3626#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3838#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3839#L940-2 [2024-11-13 14:11:41,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,559 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2024-11-13 14:11:41,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131016396] [2024-11-13 14:11:41,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,604 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131016396] [2024-11-13 14:11:41,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131016396] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436765640] [2024-11-13 14:11:41,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,605 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:41,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1301619801, now seen corresponding path program 3 times [2024-11-13 14:11:41,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130847467] [2024-11-13 14:11:41,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130847467] [2024-11-13 14:11:41,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130847467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414108477] [2024-11-13 14:11:41,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,689 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:41,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:41,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:41,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:41,690 INFO L87 Difference]: Start difference. First operand 557 states and 831 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:41,709 INFO L93 Difference]: Finished difference Result 557 states and 830 transitions. [2024-11-13 14:11:41,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 830 transitions. [2024-11-13 14:11:41,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 830 transitions. [2024-11-13 14:11:41,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-13 14:11:41,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-13 14:11:41,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 830 transitions. [2024-11-13 14:11:41,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:41,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-13 14:11:41,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 830 transitions. [2024-11-13 14:11:41,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-13 14:11:41,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4901256732495511) internal successors, (830), 556 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 830 transitions. [2024-11-13 14:11:41,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-13 14:11:41,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:41,733 INFO L424 stractBuchiCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-13 14:11:41,733 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 14:11:41,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 830 transitions. [2024-11-13 14:11:41,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:41,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:41,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,739 INFO L745 eck$LassoCheckResult]: Stem: 4841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4927#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4928#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4784#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4762#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4763#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4993#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4865#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4866#L611-2 assume !(0 == ~T1_E~0); 5006#L616-1 assume !(0 == ~T2_E~0); 5007#L621-1 assume !(0 == ~T3_E~0); 4634#L626-1 assume !(0 == ~T4_E~0); 4635#L631-1 assume !(0 == ~T5_E~0); 4825#L636-1 assume !(0 == ~E_M~0); 4685#L641-1 assume !(0 == ~E_1~0); 4686#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4839#L651-1 assume !(0 == ~E_3~0); 5034#L656-1 assume !(0 == ~E_4~0); 4991#L661-1 assume !(0 == ~E_5~0); 4992#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5018#L304 assume !(1 == ~m_pc~0); 4712#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4605#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4606#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4558#L755 assume !(0 != activate_threads_~tmp~1#1); 4559#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4514#L323 assume 1 == ~t1_pc~0; 4515#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4575#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4576#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4591#L763 assume !(0 != activate_threads_~tmp___0~0#1); 5054#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4584#L342 assume 1 == ~t2_pc~0; 4585#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4714#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4943#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4988#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L361 assume !(1 == ~t3_pc~0); 4899#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4923#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4529#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4596#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L380 assume 1 == ~t4_pc~0; 4652#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4653#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4681#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4930#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4655#L399 assume !(1 == ~t5_pc~0); 4656#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4795#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4786#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4787#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5043#L679 assume !(1 == ~M_E~0); 4864#L679-2 assume !(1 == ~T1_E~0); 4727#L684-1 assume !(1 == ~T2_E~0); 4728#L689-1 assume !(1 == ~T3_E~0); 4906#L694-1 assume !(1 == ~T4_E~0); 4904#L699-1 assume !(1 == ~T5_E~0); 4905#L704-1 assume !(1 == ~E_M~0); 4888#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4830#L714-1 assume !(1 == ~E_2~0); 4831#L719-1 assume !(1 == ~E_3~0); 4984#L724-1 assume !(1 == ~E_4~0); 4616#L729-1 assume !(1 == ~E_5~0); 4617#L734-1 assume { :end_inline_reset_delta_events } true; 4961#L940-2 [2024-11-13 14:11:41,739 INFO L747 eck$LassoCheckResult]: Loop: 4961#L940-2 assume !false; 4974#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4690#L586-1 assume !false; 5037#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5040#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4901#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4897#L511 assume !(0 != eval_~tmp~0#1); 4693#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4954#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4618#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4619#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4615#L621-3 assume !(0 == ~T3_E~0); 4563#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4564#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4565#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4566#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4628#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4642#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4643#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4881#L661-3 assume !(0 == ~E_5~0); 5055#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4791#L304-21 assume !(1 == ~m_pc~0); 4645#L304-23 is_master_triggered_~__retres1~0#1 := 0; 4646#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4721#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4722#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4850#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4884#L323-21 assume 1 == ~t1_pc~0; 4525#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4526#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4664#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4665#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 5016#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5027#L342-21 assume 1 == ~t2_pc~0; 4551#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4552#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4658#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4659#L361-21 assume !(1 == ~t3_pc~0); 5044#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 5045#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5049#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4824#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4556#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4557#L380-21 assume !(1 == ~t4_pc~0); 4624#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4625#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4698#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4982#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4931#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4772#L399-21 assume !(1 == ~t5_pc~0); 4632#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4633#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4921#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4922#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5039#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4554#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4555#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4835#L684-3 assume !(1 == ~T2_E~0); 4502#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4503#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4544#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4959#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4949#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4796#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4541#L724-3 assume !(1 == ~E_4~0); 4542#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4939#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4572#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4573#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4916#L959 assume !(0 == start_simulation_~tmp~3#1); 4920#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4827#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4828#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4590#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4746#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4747#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4960#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4961#L940-2 [2024-11-13 14:11:41,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,740 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2024-11-13 14:11:41,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989888524] [2024-11-13 14:11:41,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989888524] [2024-11-13 14:11:41,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1989888524] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81479010] [2024-11-13 14:11:41,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,780 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:41,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1868087526, now seen corresponding path program 1 times [2024-11-13 14:11:41,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757646261] [2024-11-13 14:11:41,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757646261] [2024-11-13 14:11:41,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757646261] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:41,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760986484] [2024-11-13 14:11:41,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,839 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:41,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:41,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:41,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:41,840 INFO L87 Difference]: Start difference. First operand 557 states and 830 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:41,860 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2024-11-13 14:11:41,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2024-11-13 14:11:41,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 829 transitions. [2024-11-13 14:11:41,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-13 14:11:41,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-13 14:11:41,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 829 transitions. [2024-11-13 14:11:41,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:41,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-13 14:11:41,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 829 transitions. [2024-11-13 14:11:41,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-13 14:11:41,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.488330341113106) internal successors, (829), 556 states have internal predecessors, (829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:41,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 829 transitions. [2024-11-13 14:11:41,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-13 14:11:41,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:41,884 INFO L424 stractBuchiCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-13 14:11:41,884 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 14:11:41,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 829 transitions. [2024-11-13 14:11:41,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-13 14:11:41,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:41,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:41,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:41,889 INFO L745 eck$LassoCheckResult]: Stem: 5962#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6048#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 6049#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5905#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5906#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5883#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5884#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6114#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5986#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5987#L611-2 assume !(0 == ~T1_E~0); 6127#L616-1 assume !(0 == ~T2_E~0); 6128#L621-1 assume !(0 == ~T3_E~0); 5755#L626-1 assume !(0 == ~T4_E~0); 5756#L631-1 assume !(0 == ~T5_E~0); 5946#L636-1 assume !(0 == ~E_M~0); 5806#L641-1 assume !(0 == ~E_1~0); 5807#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5960#L651-1 assume !(0 == ~E_3~0); 6155#L656-1 assume !(0 == ~E_4~0); 6112#L661-1 assume !(0 == ~E_5~0); 6113#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6139#L304 assume !(1 == ~m_pc~0); 5833#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5726#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5727#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5682#L755 assume !(0 != activate_threads_~tmp~1#1); 5683#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5635#L323 assume 1 == ~t1_pc~0; 5636#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5696#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5712#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6175#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5705#L342 assume 1 == ~t2_pc~0; 5706#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5835#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5836#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6064#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6109#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6019#L361 assume !(1 == ~t3_pc~0); 6020#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6044#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5650#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5717#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5718#L380 assume 1 == ~t4_pc~0; 5776#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5777#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5799#L787 assume !(0 != activate_threads_~tmp___3~0#1); 6051#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5773#L399 assume !(1 == ~t5_pc~0); 5774#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5915#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5920#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5907#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5908#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6164#L679 assume !(1 == ~M_E~0); 5984#L679-2 assume !(1 == ~T1_E~0); 5848#L684-1 assume !(1 == ~T2_E~0); 5849#L689-1 assume !(1 == ~T3_E~0); 6027#L694-1 assume !(1 == ~T4_E~0); 6025#L699-1 assume !(1 == ~T5_E~0); 6026#L704-1 assume !(1 == ~E_M~0); 6009#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5947#L714-1 assume !(1 == ~E_2~0); 5948#L719-1 assume !(1 == ~E_3~0); 6105#L724-1 assume !(1 == ~E_4~0); 5737#L729-1 assume !(1 == ~E_5~0); 5738#L734-1 assume { :end_inline_reset_delta_events } true; 6082#L940-2 [2024-11-13 14:11:41,890 INFO L747 eck$LassoCheckResult]: Loop: 6082#L940-2 assume !false; 6095#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5811#L586-1 assume !false; 6157#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6161#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6022#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6023#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6018#L511 assume !(0 != eval_~tmp~0#1); 5814#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6075#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5739#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5740#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5735#L621-3 assume !(0 == ~T3_E~0); 5684#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5685#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5686#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5687#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5749#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5763#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5764#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6003#L661-3 assume !(0 == ~E_5~0); 6176#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5912#L304-21 assume !(1 == ~m_pc~0); 5766#L304-23 is_master_triggered_~__retres1~0#1 := 0; 5767#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5842#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5843#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5971#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6005#L323-21 assume !(1 == ~t1_pc~0); 5648#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5647#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5785#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5786#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 6137#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6148#L342-21 assume 1 == ~t2_pc~0; 5672#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5673#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5982#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5983#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5779#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5780#L361-21 assume !(1 == ~t3_pc~0); 6165#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6166#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6170#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5945#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5680#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5681#L380-21 assume !(1 == ~t4_pc~0); 5745#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5746#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5819#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6104#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6052#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5893#L399-21 assume !(1 == ~t5_pc~0); 5753#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5754#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6042#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6043#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6160#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5675#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5956#L684-3 assume !(1 == ~T2_E~0); 5623#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5624#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5664#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6080#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6070#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5917#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5662#L724-3 assume !(1 == ~E_4~0); 5663#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6060#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5693#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5694#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6037#L959 assume !(0 == start_simulation_~tmp~3#1); 6041#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5950#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5951#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5711#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5867#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5868#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6081#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6082#L940-2 [2024-11-13 14:11:41,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,891 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2024-11-13 14:11:41,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779421629] [2024-11-13 14:11:41,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:41,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:41,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:41,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779421629] [2024-11-13 14:11:41,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779421629] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:41,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:41,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:11:41,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654510807] [2024-11-13 14:11:41,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:41,956 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:41,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:41,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1318751131, now seen corresponding path program 1 times [2024-11-13 14:11:41,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:41,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531232269] [2024-11-13 14:11:41,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:41,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:41,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531232269] [2024-11-13 14:11:42,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531232269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:42,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389581248] [2024-11-13 14:11:42,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:42,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:42,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:42,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:42,065 INFO L87 Difference]: Start difference. First operand 557 states and 829 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:42,123 INFO L93 Difference]: Finished difference Result 991 states and 1469 transitions. [2024-11-13 14:11:42,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1469 transitions. [2024-11-13 14:11:42,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-13 14:11:42,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1469 transitions. [2024-11-13 14:11:42,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2024-11-13 14:11:42,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2024-11-13 14:11:42,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1469 transitions. [2024-11-13 14:11:42,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:42,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-13 14:11:42,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1469 transitions. [2024-11-13 14:11:42,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2024-11-13 14:11:42,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4823410696266397) internal successors, (1469), 990 states have internal predecessors, (1469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1469 transitions. [2024-11-13 14:11:42,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-13 14:11:42,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:42,183 INFO L424 stractBuchiCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-13 14:11:42,183 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 14:11:42,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1469 transitions. [2024-11-13 14:11:42,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-13 14:11:42,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:42,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:42,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,195 INFO L745 eck$LassoCheckResult]: Stem: 7523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7627#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7628#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7612#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7613#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7464#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7465#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7442#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7443#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7695#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7547#L611 assume !(0 == ~M_E~0); 7548#L611-2 assume !(0 == ~T1_E~0); 7709#L616-1 assume !(0 == ~T2_E~0); 7710#L621-1 assume !(0 == ~T3_E~0); 7304#L626-1 assume !(0 == ~T4_E~0); 7305#L631-1 assume !(0 == ~T5_E~0); 7504#L636-1 assume !(0 == ~E_M~0); 7359#L641-1 assume !(0 == ~E_1~0); 7360#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7521#L651-1 assume !(0 == ~E_3~0); 7754#L656-1 assume !(0 == ~E_4~0); 7693#L661-1 assume !(0 == ~E_5~0); 7694#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7729#L304 assume !(1 == ~m_pc~0); 7386#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7281#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7282#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7232#L755 assume !(0 != activate_threads_~tmp~1#1); 7233#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186#L323 assume 1 == ~t1_pc~0; 7187#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7251#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7267#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7782#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7254#L342 assume 1 == ~t2_pc~0; 7255#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7392#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7393#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7629#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7688#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7581#L361 assume !(1 == ~t3_pc~0); 7582#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7607#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7204#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7205#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7270#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7271#L380 assume 1 == ~t4_pc~0; 7328#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7329#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7355#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7615#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7331#L399 assume !(1 == ~t5_pc~0); 7332#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7474#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7480#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7466#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7467#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7767#L679 assume !(1 == ~M_E~0); 7545#L679-2 assume !(1 == ~T1_E~0); 7405#L684-1 assume !(1 == ~T2_E~0); 7406#L689-1 assume !(1 == ~T3_E~0); 7589#L694-1 assume !(1 == ~T4_E~0); 7587#L699-1 assume !(1 == ~T5_E~0); 7588#L704-1 assume !(1 == ~E_M~0); 7570#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7508#L714-1 assume !(1 == ~E_2~0); 7509#L719-1 assume !(1 == ~E_3~0); 7682#L724-1 assume !(1 == ~E_4~0); 7292#L729-1 assume !(1 == ~E_5~0); 7293#L734-1 assume { :end_inline_reset_delta_events } true; 7652#L940-2 [2024-11-13 14:11:42,195 INFO L747 eck$LassoCheckResult]: Loop: 7652#L940-2 assume !false; 7724#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7367#L586-1 assume !false; 7803#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7799#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7796#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7643#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7579#L511 assume !(0 != eval_~tmp~0#1); 7370#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7645#L611-3 assume !(0 == ~M_E~0); 7294#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7295#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7290#L621-3 assume !(0 == ~T3_E~0); 7239#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7240#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7241#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7242#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7306#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7318#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7319#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7564#L661-3 assume !(0 == ~E_5~0); 7783#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7471#L304-21 assume 1 == ~m_pc~0; 7472#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7322#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7399#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7400#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7532#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7566#L323-21 assume 1 == ~t1_pc~0; 7201#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7202#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7341#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7342#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 7725#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7741#L342-21 assume 1 == ~t2_pc~0; 7227#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7228#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7543#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7544#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7334#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7335#L361-21 assume !(1 == ~t3_pc~0); 7768#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7769#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7776#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7507#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7237#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L380-21 assume !(1 == ~t4_pc~0); 7300#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7301#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7375#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7681#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7616#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7452#L399-21 assume 1 == ~t5_pc~0; 7426#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7311#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7605#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7606#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7761#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7230#L679-3 assume !(1 == ~M_E~0); 7231#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7517#L684-3 assume !(1 == ~T2_E~0); 7178#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7179#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7219#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7220#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7650#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7636#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7477#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7217#L724-3 assume !(1 == ~E_4~0); 7218#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7624#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7665#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7957#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7956#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7954#L959 assume !(0 == start_simulation_~tmp~3#1); 7952#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7511#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7512#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7265#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7266#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7424#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7425#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7651#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7652#L940-2 [2024-11-13 14:11:42,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2024-11-13 14:11:42,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935640867] [2024-11-13 14:11:42,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935640867] [2024-11-13 14:11:42,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935640867] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:11:42,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335993380] [2024-11-13 14:11:42,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,290 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:42,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,290 INFO L85 PathProgramCache]: Analyzing trace with hash -97377256, now seen corresponding path program 1 times [2024-11-13 14:11:42,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033724144] [2024-11-13 14:11:42,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033724144] [2024-11-13 14:11:42,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033724144] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:42,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071888618] [2024-11-13 14:11:42,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,363 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:42,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:42,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:42,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:42,364 INFO L87 Difference]: Start difference. First operand 991 states and 1469 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:42,432 INFO L93 Difference]: Finished difference Result 991 states and 1447 transitions. [2024-11-13 14:11:42,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1447 transitions. [2024-11-13 14:11:42,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-13 14:11:42,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1447 transitions. [2024-11-13 14:11:42,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2024-11-13 14:11:42,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2024-11-13 14:11:42,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1447 transitions. [2024-11-13 14:11:42,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:42,449 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-13 14:11:42,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1447 transitions. [2024-11-13 14:11:42,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2024-11-13 14:11:42,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4601412714429869) internal successors, (1447), 990 states have internal predecessors, (1447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1447 transitions. [2024-11-13 14:11:42,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-13 14:11:42,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:42,475 INFO L424 stractBuchiCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-13 14:11:42,475 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 14:11:42,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1447 transitions. [2024-11-13 14:11:42,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-13 14:11:42,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:42,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:42,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,484 INFO L745 eck$LassoCheckResult]: Stem: 9511#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9618#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9619#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9603#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9604#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9452#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9453#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9430#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9431#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9683#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9535#L611 assume !(0 == ~M_E~0); 9536#L611-2 assume !(0 == ~T1_E~0); 9697#L616-1 assume !(0 == ~T2_E~0); 9698#L621-1 assume !(0 == ~T3_E~0); 9298#L626-1 assume !(0 == ~T4_E~0); 9299#L631-1 assume !(0 == ~T5_E~0); 9492#L636-1 assume !(0 == ~E_M~0); 9347#L641-1 assume !(0 == ~E_1~0); 9348#L646-1 assume !(0 == ~E_2~0); 9509#L651-1 assume !(0 == ~E_3~0); 9742#L656-1 assume !(0 == ~E_4~0); 9681#L661-1 assume !(0 == ~E_5~0); 9682#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9716#L304 assume !(1 == ~m_pc~0); 9374#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9269#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9270#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9220#L755 assume !(0 != activate_threads_~tmp~1#1); 9221#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9175#L323 assume 1 == ~t1_pc~0; 9176#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9239#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9255#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9770#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9242#L342 assume !(1 == ~t2_pc~0); 9244#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9380#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9620#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9678#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9569#L361 assume !(1 == ~t3_pc~0); 9570#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9596#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9194#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9258#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9259#L380 assume 1 == ~t4_pc~0; 9316#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9317#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9343#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9606#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9319#L399 assume !(1 == ~t5_pc~0); 9320#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9462#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9468#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9454#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9455#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9754#L679 assume !(1 == ~M_E~0); 9533#L679-2 assume !(1 == ~T1_E~0); 9393#L684-1 assume !(1 == ~T2_E~0); 9394#L689-1 assume !(1 == ~T3_E~0); 9577#L694-1 assume !(1 == ~T4_E~0); 9575#L699-1 assume !(1 == ~T5_E~0); 9576#L704-1 assume !(1 == ~E_M~0); 9558#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9496#L714-1 assume !(1 == ~E_2~0); 9497#L719-1 assume !(1 == ~E_3~0); 9672#L724-1 assume !(1 == ~E_4~0); 9280#L729-1 assume !(1 == ~E_5~0); 9281#L734-1 assume { :end_inline_reset_delta_events } true; 9643#L940-2 [2024-11-13 14:11:42,484 INFO L747 eck$LassoCheckResult]: Loop: 9643#L940-2 assume !false; 9711#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9355#L586-1 assume !false; 9745#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9749#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9572#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9573#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9781#L511 assume !(0 != eval_~tmp~0#1); 9358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9359#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9636#L611-3 assume !(0 == ~M_E~0); 9282#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9283#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9278#L621-3 assume !(0 == ~T3_E~0); 9227#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9228#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9229#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9230#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9292#L646-3 assume !(0 == ~E_2~0); 9306#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9307#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9552#L661-3 assume !(0 == ~E_5~0); 9771#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L304-21 assume 1 == ~m_pc~0; 9460#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9310#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9387#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9388#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9520#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9554#L323-21 assume 1 == ~t1_pc~0; 9190#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9191#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9329#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9330#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 9712#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9729#L342-21 assume !(1 == ~t2_pc~0); 9217#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9599#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9531#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9532#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9322#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9323#L361-21 assume 1 == ~t3_pc~0; 9763#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9756#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9764#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9495#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9225#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9226#L380-21 assume !(1 == ~t4_pc~0); 9288#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9289#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9363#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9671#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9607#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9440#L399-21 assume !(1 == ~t5_pc~0); 9296#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9297#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9594#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9595#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9748#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9218#L679-3 assume !(1 == ~M_E~0); 9219#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9505#L684-3 assume !(1 == ~T2_E~0); 9167#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9168#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9208#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9209#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9641#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9627#L714-3 assume !(1 == ~E_2~0); 9465#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9206#L724-3 assume !(1 == ~E_4~0); 9207#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9615#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9236#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9237#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9587#L959 assume !(0 == start_simulation_~tmp~3#1); 9948#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9947#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9939#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9937#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9935#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9933#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9728#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9642#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9643#L940-2 [2024-11-13 14:11:42,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,484 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2024-11-13 14:11:42,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910667071] [2024-11-13 14:11:42,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910667071] [2024-11-13 14:11:42,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910667071] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:11:42,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275293823] [2024-11-13 14:11:42,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,578 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:42,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,578 INFO L85 PathProgramCache]: Analyzing trace with hash -324523239, now seen corresponding path program 1 times [2024-11-13 14:11:42,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241551179] [2024-11-13 14:11:42,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241551179] [2024-11-13 14:11:42,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241551179] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:42,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912697181] [2024-11-13 14:11:42,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,633 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:42,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:42,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:42,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:42,634 INFO L87 Difference]: Start difference. First operand 991 states and 1447 transitions. cyclomatic complexity: 457 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:42,737 INFO L93 Difference]: Finished difference Result 1799 states and 2607 transitions. [2024-11-13 14:11:42,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1799 states and 2607 transitions. [2024-11-13 14:11:42,753 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1717 [2024-11-13 14:11:42,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1799 states to 1799 states and 2607 transitions. [2024-11-13 14:11:42,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1799 [2024-11-13 14:11:42,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1799 [2024-11-13 14:11:42,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1799 states and 2607 transitions. [2024-11-13 14:11:42,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:42,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1799 states and 2607 transitions. [2024-11-13 14:11:42,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1799 states and 2607 transitions. [2024-11-13 14:11:42,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1799 to 1795. [2024-11-13 14:11:42,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1795 states, 1795 states have (on average 1.4501392757660168) internal successors, (2603), 1794 states have internal predecessors, (2603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:42,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1795 states to 1795 states and 2603 transitions. [2024-11-13 14:11:42,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2024-11-13 14:11:42,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:42,832 INFO L424 stractBuchiCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2024-11-13 14:11:42,834 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 14:11:42,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1795 states and 2603 transitions. [2024-11-13 14:11:42,847 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1713 [2024-11-13 14:11:42,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:42,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:42,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:42,851 INFO L745 eck$LassoCheckResult]: Stem: 12324#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12444#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12445#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12426#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 12427#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12258#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12259#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12237#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12238#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12532#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12351#L611 assume !(0 == ~M_E~0); 12352#L611-2 assume !(0 == ~T1_E~0); 12550#L616-1 assume !(0 == ~T2_E~0); 12551#L621-1 assume !(0 == ~T3_E~0); 12090#L626-1 assume !(0 == ~T4_E~0); 12091#L631-1 assume !(0 == ~T5_E~0); 12301#L636-1 assume !(0 == ~E_M~0); 12147#L641-1 assume !(0 == ~E_1~0); 12148#L646-1 assume !(0 == ~E_2~0); 12320#L651-1 assume !(0 == ~E_3~0); 12607#L656-1 assume !(0 == ~E_4~0); 12530#L661-1 assume !(0 == ~E_5~0); 12531#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12578#L304 assume !(1 == ~m_pc~0); 12175#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12067#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12068#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12016#L755 assume !(0 != activate_threads_~tmp~1#1); 12017#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11972#L323 assume !(1 == ~t1_pc~0); 11973#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12035#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12052#L763 assume !(0 != activate_threads_~tmp___0~0#1); 12646#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12038#L342 assume !(1 == ~t2_pc~0); 12040#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12183#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12184#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12447#L771 assume !(0 != activate_threads_~tmp___1~0#1); 12524#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L361 assume !(1 == ~t3_pc~0); 12390#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12418#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11990#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12055#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12056#L380 assume 1 == ~t4_pc~0; 12115#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12116#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12143#L787 assume !(0 != activate_threads_~tmp___3~0#1); 12433#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12118#L399 assume !(1 == ~t5_pc~0); 12119#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12269#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12276#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12260#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12261#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12618#L679 assume !(1 == ~M_E~0); 12349#L679-2 assume !(1 == ~T1_E~0); 12197#L684-1 assume !(1 == ~T2_E~0); 12198#L689-1 assume !(1 == ~T3_E~0); 12397#L694-1 assume !(1 == ~T4_E~0); 12395#L699-1 assume !(1 == ~T5_E~0); 12396#L704-1 assume !(1 == ~E_M~0); 12376#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12305#L714-1 assume !(1 == ~E_2~0); 12306#L719-1 assume !(1 == ~E_3~0); 12511#L724-1 assume !(1 == ~E_4~0); 12078#L729-1 assume !(1 == ~E_5~0); 12079#L734-1 assume { :end_inline_reset_delta_events } true; 12622#L940-2 [2024-11-13 14:11:42,852 INFO L747 eck$LassoCheckResult]: Loop: 12622#L940-2 assume !false; 13393#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13390#L586-1 assume !false; 12738#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12739#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12716#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12717#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12709#L511 assume !(0 != eval_~tmp~0#1); 12159#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12465#L611-3 assume !(0 == ~M_E~0); 12466#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13623#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13622#L621-3 assume !(0 == ~T3_E~0); 13621#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13620#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13619#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13618#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13617#L646-3 assume !(0 == ~E_2~0); 13616#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13615#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13614#L661-3 assume !(0 == ~E_5~0); 13613#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13612#L304-21 assume !(1 == ~m_pc~0); 13610#L304-23 is_master_triggered_~__retres1~0#1 := 0; 13609#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13608#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13607#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12371#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12372#L323-21 assume !(1 == ~t1_pc~0); 12541#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12542#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12128#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12129#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 12589#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12590#L342-21 assume !(1 == ~t2_pc~0); 12013#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12424#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12347#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12348#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12121#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12122#L361-21 assume 1 == ~t3_pc~0; 12634#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12620#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12638#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12304#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12021#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12022#L380-21 assume !(1 == ~t4_pc~0); 12086#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 12087#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12164#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12510#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12434#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12246#L399-21 assume !(1 == ~t5_pc~0); 12096#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 12097#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12416#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12417#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12614#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12014#L679-3 assume !(1 == ~M_E~0); 12015#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13536#L684-3 assume !(1 == ~T2_E~0); 13534#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13532#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13529#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13527#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13525#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13523#L714-3 assume !(1 == ~E_2~0); 13521#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13520#L724-3 assume !(1 == ~E_4~0); 13519#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13515#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13513#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13066#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12696#L959 assume !(0 == start_simulation_~tmp~3#1); 13406#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13405#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13399#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13398#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 13397#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13396#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13395#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 13394#L972 assume !(0 != start_simulation_~tmp___0~1#1); 12622#L940-2 [2024-11-13 14:11:42,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2024-11-13 14:11:42,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957324933] [2024-11-13 14:11:42,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:42,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:42,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:42,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957324933] [2024-11-13 14:11:42,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957324933] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:42,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:42,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:42,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007319667] [2024-11-13 14:11:42,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:42,960 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:42,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:42,960 INFO L85 PathProgramCache]: Analyzing trace with hash -404119717, now seen corresponding path program 1 times [2024-11-13 14:11:42,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:42,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716485670] [2024-11-13 14:11:42,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:42,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:42,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:43,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:43,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:43,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716485670] [2024-11-13 14:11:43,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716485670] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:43,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:43,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:43,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642198997] [2024-11-13 14:11:43,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:43,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:43,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:43,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:43,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:43,024 INFO L87 Difference]: Start difference. First operand 1795 states and 2603 transitions. cyclomatic complexity: 810 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:43,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:43,269 INFO L93 Difference]: Finished difference Result 1882 states and 2690 transitions. [2024-11-13 14:11:43,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1882 states and 2690 transitions. [2024-11-13 14:11:43,282 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1797 [2024-11-13 14:11:43,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1882 states to 1882 states and 2690 transitions. [2024-11-13 14:11:43,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1882 [2024-11-13 14:11:43,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1882 [2024-11-13 14:11:43,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1882 states and 2690 transitions. [2024-11-13 14:11:43,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:43,299 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-13 14:11:43,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states and 2690 transitions. [2024-11-13 14:11:43,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2024-11-13 14:11:43,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1882 states, 1882 states have (on average 1.4293304994686504) internal successors, (2690), 1881 states have internal predecessors, (2690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:43,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2690 transitions. [2024-11-13 14:11:43,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-13 14:11:43,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:43,346 INFO L424 stractBuchiCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-13 14:11:43,346 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 14:11:43,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1882 states and 2690 transitions. [2024-11-13 14:11:43,374 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1797 [2024-11-13 14:11:43,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:43,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:43,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:43,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:43,376 INFO L745 eck$LassoCheckResult]: Stem: 15998#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 15999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16097#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 16098#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15935#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15936#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15914#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15915#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16177#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16023#L611 assume !(0 == ~M_E~0); 16024#L611-2 assume !(0 == ~T1_E~0); 16191#L616-1 assume !(0 == ~T2_E~0); 16192#L621-1 assume !(0 == ~T3_E~0); 15777#L626-1 assume !(0 == ~T4_E~0); 15778#L631-1 assume !(0 == ~T5_E~0); 15976#L636-1 assume !(0 == ~E_M~0); 15832#L641-1 assume !(0 == ~E_1~0); 15833#L646-1 assume !(0 == ~E_2~0); 15994#L651-1 assume !(0 == ~E_3~0); 16228#L656-1 assume !(0 == ~E_4~0); 16175#L661-1 assume !(0 == ~E_5~0); 16176#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16208#L304 assume !(1 == ~m_pc~0); 15859#L304-2 is_master_triggered_~__retres1~0#1 := 0; 15754#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15755#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15702#L755 assume !(0 != activate_threads_~tmp~1#1); 15703#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15658#L323 assume !(1 == ~t1_pc~0); 15659#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15721#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15722#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L763 assume !(0 != activate_threads_~tmp___0~0#1); 16263#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15725#L342 assume !(1 == ~t2_pc~0); 15727#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15865#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15866#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16113#L771 assume !(0 != activate_threads_~tmp___1~0#1); 16169#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16062#L361 assume !(1 == ~t3_pc~0); 16063#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16090#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15675#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15676#L779 assume !(0 != activate_threads_~tmp___2~0#1); 15741#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15742#L380 assume 1 == ~t4_pc~0; 15801#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15802#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15828#L787 assume !(0 != activate_threads_~tmp___3~0#1); 16100#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15804#L399 assume !(1 == ~t5_pc~0); 15805#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15946#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15952#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15937#L795 assume !(0 != activate_threads_~tmp___4~0#1); 15938#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16239#L679 assume !(1 == ~M_E~0); 16021#L679-2 assume !(1 == ~T1_E~0); 15878#L684-1 assume !(1 == ~T2_E~0); 15879#L689-1 assume !(1 == ~T3_E~0); 16070#L694-1 assume !(1 == ~T4_E~0); 16068#L699-1 assume !(1 == ~T5_E~0); 16069#L704-1 assume !(1 == ~E_M~0); 16048#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15980#L714-1 assume !(1 == ~E_2~0); 15981#L719-1 assume !(1 == ~E_3~0); 16163#L724-1 assume !(1 == ~E_4~0); 15765#L729-1 assume !(1 == ~E_5~0); 15766#L734-1 assume { :end_inline_reset_delta_events } true; 16243#L940-2 [2024-11-13 14:11:43,376 INFO L747 eck$LassoCheckResult]: Loop: 16243#L940-2 assume !false; 16382#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16379#L586-1 assume !false; 16374#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16375#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16310#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16311#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16306#L511 assume !(0 != eval_~tmp~0#1); 16307#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16488#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16486#L611-3 assume !(0 == ~M_E~0); 16479#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16480#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16475#L621-3 assume !(0 == ~T3_E~0); 16476#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16471#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16472#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16467#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16468#L646-3 assume !(0 == ~E_2~0); 16463#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16464#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16458#L661-3 assume !(0 == ~E_5~0); 16459#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16342#L304-21 assume 1 == ~m_pc~0; 16343#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17032#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17031#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17030#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17029#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17027#L323-21 assume !(1 == ~t1_pc~0); 17025#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 17023#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17021#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17018#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 17016#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17014#L342-21 assume !(1 == ~t2_pc~0); 17012#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 17011#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17010#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17009#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17006#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17002#L361-21 assume 1 == ~t3_pc~0; 16997#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16992#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16986#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16981#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16977#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16974#L380-21 assume 1 == ~t4_pc~0; 16971#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16969#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16967#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16965#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16963#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16960#L399-21 assume !(1 == ~t5_pc~0); 16957#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 16955#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16953#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16951#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16950#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16949#L679-3 assume !(1 == ~M_E~0); 16945#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16943#L684-3 assume !(1 == ~T2_E~0); 16941#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16939#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16937#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16934#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16932#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16930#L714-3 assume !(1 == ~E_2~0); 16928#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16926#L724-3 assume !(1 == ~E_4~0); 16853#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16850#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16848#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16840#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16838#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 16296#L959 assume !(0 == start_simulation_~tmp~3#1); 16297#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16407#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16400#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16397#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 16398#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16517#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16516#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 16387#L972 assume !(0 != start_simulation_~tmp___0~1#1); 16243#L940-2 [2024-11-13 14:11:43,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:43,377 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2024-11-13 14:11:43,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:43,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69230662] [2024-11-13 14:11:43,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:43,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:43,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:43,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:43,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:43,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69230662] [2024-11-13 14:11:43,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69230662] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:43,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:43,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:11:43,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721607485] [2024-11-13 14:11:43,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:43,443 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:43,444 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:43,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1737055449, now seen corresponding path program 1 times [2024-11-13 14:11:43,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:43,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074668719] [2024-11-13 14:11:43,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:43,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:43,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:43,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:43,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:43,500 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074668719] [2024-11-13 14:11:43,500 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074668719] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:43,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:43,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:43,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638645658] [2024-11-13 14:11:43,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:43,501 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:43,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:43,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:43,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:43,502 INFO L87 Difference]: Start difference. First operand 1882 states and 2690 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:43,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:43,622 INFO L93 Difference]: Finished difference Result 3468 states and 4930 transitions. [2024-11-13 14:11:43,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3468 states and 4930 transitions. [2024-11-13 14:11:43,647 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2024-11-13 14:11:43,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3468 states to 3468 states and 4930 transitions. [2024-11-13 14:11:43,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3468 [2024-11-13 14:11:43,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3468 [2024-11-13 14:11:43,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3468 states and 4930 transitions. [2024-11-13 14:11:43,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:43,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3468 states and 4930 transitions. [2024-11-13 14:11:43,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3468 states and 4930 transitions. [2024-11-13 14:11:43,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3468 to 3460. [2024-11-13 14:11:43,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4225433526011562) internal successors, (4922), 3459 states have internal predecessors, (4922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:43,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4922 transitions. [2024-11-13 14:11:43,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2024-11-13 14:11:43,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:43,753 INFO L424 stractBuchiCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2024-11-13 14:11:43,753 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 14:11:43,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4922 transitions. [2024-11-13 14:11:43,769 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2024-11-13 14:11:43,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:43,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:43,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:43,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:43,771 INFO L745 eck$LassoCheckResult]: Stem: 21350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21461#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21462#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21447#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 21448#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21287#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21288#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21266#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21267#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21526#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21375#L611 assume !(0 == ~M_E~0); 21376#L611-2 assume !(0 == ~T1_E~0); 21541#L616-1 assume !(0 == ~T2_E~0); 21542#L621-1 assume !(0 == ~T3_E~0); 21132#L626-1 assume !(0 == ~T4_E~0); 21133#L631-1 assume !(0 == ~T5_E~0); 21326#L636-1 assume !(0 == ~E_M~0); 21186#L641-1 assume !(0 == ~E_1~0); 21187#L646-1 assume !(0 == ~E_2~0); 21346#L651-1 assume !(0 == ~E_3~0); 21586#L656-1 assume !(0 == ~E_4~0); 21524#L661-1 assume !(0 == ~E_5~0); 21525#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21558#L304 assume !(1 == ~m_pc~0); 21212#L304-2 is_master_triggered_~__retres1~0#1 := 0; 21109#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21110#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21059#L755 assume !(0 != activate_threads_~tmp~1#1); 21060#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21015#L323 assume !(1 == ~t1_pc~0); 21016#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21077#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21094#L763 assume !(0 != activate_threads_~tmp___0~0#1); 21621#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21081#L342 assume !(1 == ~t2_pc~0); 21083#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21218#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21219#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21463#L771 assume !(0 != activate_threads_~tmp___1~0#1); 21521#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21412#L361 assume !(1 == ~t3_pc~0); 21413#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21441#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21033#L779 assume !(0 != activate_threads_~tmp___2~0#1); 21097#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21098#L380 assume !(1 == ~t4_pc~0); 21411#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21534#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21179#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21180#L787 assume !(0 != activate_threads_~tmp___3~0#1); 21450#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21156#L399 assume !(1 == ~t5_pc~0); 21157#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21297#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21303#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21289#L795 assume !(0 != activate_threads_~tmp___4~0#1); 21290#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21599#L679 assume !(1 == ~M_E~0); 21373#L679-2 assume !(1 == ~T1_E~0); 21231#L684-1 assume !(1 == ~T2_E~0); 21232#L689-1 assume !(1 == ~T3_E~0); 21422#L694-1 assume !(1 == ~T4_E~0); 21420#L699-1 assume !(1 == ~T5_E~0); 21421#L704-1 assume !(1 == ~E_M~0); 21400#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21331#L714-1 assume !(1 == ~E_2~0); 21332#L719-1 assume !(1 == ~E_3~0); 21515#L724-1 assume !(1 == ~E_4~0); 21120#L729-1 assume !(1 == ~E_5~0); 21121#L734-1 assume { :end_inline_reset_delta_events } true; 21603#L940-2 [2024-11-13 14:11:43,771 INFO L747 eck$LassoCheckResult]: Loop: 21603#L940-2 assume !false; 22219#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22215#L586-1 assume !false; 22214#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22207#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22203#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22201#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22198#L511 assume !(0 != eval_~tmp~0#1); 22196#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22192#L611-3 assume !(0 == ~M_E~0); 22190#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22188#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22186#L621-3 assume !(0 == ~T3_E~0); 22184#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22182#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22180#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22178#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22176#L646-3 assume !(0 == ~E_2~0); 22174#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22171#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22169#L661-3 assume !(0 == ~E_5~0); 22167#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22165#L304-21 assume !(1 == ~m_pc~0); 22162#L304-23 is_master_triggered_~__retres1~0#1 := 0; 22160#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22158#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22156#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22154#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22153#L323-21 assume !(1 == ~t1_pc~0); 22152#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 22150#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22149#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22148#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 22147#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22145#L342-21 assume !(1 == ~t2_pc~0); 22142#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 22139#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22137#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22135#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22133#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22131#L361-21 assume 1 == ~t3_pc~0; 22128#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22124#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22122#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22118#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22115#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22113#L380-21 assume !(1 == ~t4_pc~0); 22111#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 22109#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22107#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22105#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22103#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22101#L399-21 assume !(1 == ~t5_pc~0); 22098#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 22095#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22093#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22091#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22089#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22087#L679-3 assume !(1 == ~M_E~0); 22086#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22505#L684-3 assume !(1 == ~T2_E~0); 22504#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22074#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22075#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22070#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22071#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22065#L714-3 assume !(1 == ~E_2~0); 22066#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22061#L724-3 assume !(1 == ~E_4~0); 22062#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22057#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22058#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22319#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 21796#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 21797#L959 assume !(0 == start_simulation_~tmp~3#1); 22248#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22243#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22236#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 22233#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 22230#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22229#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22222#L972 assume !(0 != start_simulation_~tmp___0~1#1); 21603#L940-2 [2024-11-13 14:11:43,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:43,772 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2024-11-13 14:11:43,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:43,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811032482] [2024-11-13 14:11:43,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:43,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:43,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:43,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:43,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:43,840 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811032482] [2024-11-13 14:11:43,840 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811032482] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:43,840 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:43,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:43,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901388892] [2024-11-13 14:11:43,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:43,841 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:43,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:43,841 INFO L85 PathProgramCache]: Analyzing trace with hash -404119717, now seen corresponding path program 2 times [2024-11-13 14:11:43,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:43,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902055191] [2024-11-13 14:11:43,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:43,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:43,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:43,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:43,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:43,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902055191] [2024-11-13 14:11:43,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902055191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:43,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:43,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:43,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523282624] [2024-11-13 14:11:43,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:43,911 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:43,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:43,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:11:43,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:11:43,911 INFO L87 Difference]: Start difference. First operand 3460 states and 4922 transitions. cyclomatic complexity: 1466 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:44,083 INFO L93 Difference]: Finished difference Result 5489 states and 7747 transitions. [2024-11-13 14:11:44,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5489 states and 7747 transitions. [2024-11-13 14:11:44,113 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5284 [2024-11-13 14:11:44,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5489 states to 5489 states and 7747 transitions. [2024-11-13 14:11:44,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5489 [2024-11-13 14:11:44,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5489 [2024-11-13 14:11:44,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5489 states and 7747 transitions. [2024-11-13 14:11:44,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:44,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5489 states and 7747 transitions. [2024-11-13 14:11:44,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5489 states and 7747 transitions. [2024-11-13 14:11:44,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5489 to 3972. [2024-11-13 14:11:44,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3972 states, 3972 states have (on average 1.4149043303121853) internal successors, (5620), 3971 states have internal predecessors, (5620), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3972 states to 3972 states and 5620 transitions. [2024-11-13 14:11:44,231 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2024-11-13 14:11:44,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:11:44,232 INFO L424 stractBuchiCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2024-11-13 14:11:44,232 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 14:11:44,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3972 states and 5620 transitions. [2024-11-13 14:11:44,249 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2024-11-13 14:11:44,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:44,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:44,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,251 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,251 INFO L745 eck$LassoCheckResult]: Stem: 30313#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 30314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30427#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30412#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 30413#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30251#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30252#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30228#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30229#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30489#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30337#L611 assume !(0 == ~M_E~0); 30338#L611-2 assume !(0 == ~T1_E~0); 30508#L616-1 assume !(0 == ~T2_E~0); 30509#L621-1 assume !(0 == ~T3_E~0); 30097#L626-1 assume !(0 == ~T4_E~0); 30098#L631-1 assume !(0 == ~T5_E~0); 30296#L636-1 assume !(0 == ~E_M~0); 30145#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30146#L646-1 assume !(0 == ~E_2~0); 30583#L651-1 assume !(0 == ~E_3~0); 30584#L656-1 assume !(0 == ~E_4~0); 30673#L661-1 assume !(0 == ~E_5~0); 30672#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30599#L304 assume !(1 == ~m_pc~0); 30173#L304-2 is_master_triggered_~__retres1~0#1 := 0; 30067#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30668#L755 assume !(0 != activate_threads_~tmp~1#1); 30619#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30620#L323 assume !(1 == ~t1_pc~0); 30667#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30036#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30052#L763 assume !(0 != activate_threads_~tmp___0~0#1); 30585#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30588#L342 assume !(1 == ~t2_pc~0); 30486#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30175#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30176#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30600#L771 assume !(0 != activate_threads_~tmp___1~0#1); 30601#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30661#L361 assume !(1 == ~t3_pc~0); 30659#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30657#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30654#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30646#L779 assume !(0 != activate_threads_~tmp___2~0#1); 30645#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30644#L380 assume !(1 == ~t4_pc~0); 30606#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30500#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30141#L787 assume !(0 != activate_threads_~tmp___3~0#1); 30641#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30115#L399 assume !(1 == ~t5_pc~0); 30116#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30640#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30270#L795 assume !(0 != activate_threads_~tmp___4~0#1); 30639#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30602#L679 assume !(1 == ~M_E~0); 30335#L679-2 assume !(1 == ~T1_E~0); 30188#L684-1 assume !(1 == ~T2_E~0); 30189#L689-1 assume !(1 == ~T3_E~0); 30386#L694-1 assume !(1 == ~T4_E~0); 30635#L699-1 assume !(1 == ~T5_E~0); 30634#L704-1 assume !(1 == ~E_M~0); 30633#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30297#L714-1 assume !(1 == ~E_2~0); 30298#L719-1 assume !(1 == ~E_3~0); 30475#L724-1 assume !(1 == ~E_4~0); 30078#L729-1 assume !(1 == ~E_5~0); 30079#L734-1 assume { :end_inline_reset_delta_events } true; 30567#L940-2 [2024-11-13 14:11:44,252 INFO L747 eck$LassoCheckResult]: Loop: 30567#L940-2 assume !false; 32026#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32017#L586-1 assume !false; 32015#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32000#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31993#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31987#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31981#L511 assume !(0 != eval_~tmp~0#1); 31975#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31969#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31963#L611-3 assume !(0 == ~M_E~0); 31957#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31951#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31946#L621-3 assume !(0 == ~T3_E~0); 31939#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31934#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31929#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31921#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31920#L646-3 assume !(0 == ~E_2~0); 31919#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31918#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31917#L661-3 assume !(0 == ~E_5~0); 31916#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31915#L304-21 assume !(1 == ~m_pc~0); 31913#L304-23 is_master_triggered_~__retres1~0#1 := 0; 31912#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31911#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31910#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31909#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31908#L323-21 assume !(1 == ~t1_pc~0); 31907#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 31906#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31905#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31904#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 31903#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31902#L342-21 assume !(1 == ~t2_pc~0); 31900#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 31899#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31898#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31897#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31896#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31895#L361-21 assume 1 == ~t3_pc~0; 31893#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31891#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31889#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31887#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31886#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31885#L380-21 assume !(1 == ~t4_pc~0); 31884#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 31883#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31882#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31881#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31880#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31879#L399-21 assume !(1 == ~t5_pc~0); 31877#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 31876#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31875#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31874#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31873#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31872#L679-3 assume !(1 == ~M_E~0); 31573#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31871#L684-3 assume !(1 == ~T2_E~0); 31870#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31869#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31868#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31867#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31865#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31843#L714-3 assume !(1 == ~E_2~0); 31797#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31795#L724-3 assume !(1 == ~E_4~0); 30762#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30759#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30757#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30744#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30739#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30734#L959 assume !(0 == start_simulation_~tmp~3#1); 30735#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32092#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32085#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32083#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 32081#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 32078#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32067#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 32044#L972 assume !(0 != start_simulation_~tmp___0~1#1); 30567#L940-2 [2024-11-13 14:11:44,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:44,252 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2024-11-13 14:11:44,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:44,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481603738] [2024-11-13 14:11:44,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:44,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:44,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:44,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:44,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:44,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481603738] [2024-11-13 14:11:44,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481603738] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:44,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:44,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:44,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810342211] [2024-11-13 14:11:44,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:44,309 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:44,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:44,310 INFO L85 PathProgramCache]: Analyzing trace with hash -404119717, now seen corresponding path program 3 times [2024-11-13 14:11:44,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:44,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264663960] [2024-11-13 14:11:44,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:44,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:44,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:44,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:44,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:44,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264663960] [2024-11-13 14:11:44,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264663960] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:44,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:44,376 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:44,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784953466] [2024-11-13 14:11:44,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:44,377 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:44,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:44,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:11:44,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:11:44,377 INFO L87 Difference]: Start difference. First operand 3972 states and 5620 transitions. cyclomatic complexity: 1652 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:44,492 INFO L93 Difference]: Finished difference Result 4826 states and 6797 transitions. [2024-11-13 14:11:44,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4826 states and 6797 transitions. [2024-11-13 14:11:44,518 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4682 [2024-11-13 14:11:44,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4826 states to 4826 states and 6797 transitions. [2024-11-13 14:11:44,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4826 [2024-11-13 14:11:44,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4826 [2024-11-13 14:11:44,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4826 states and 6797 transitions. [2024-11-13 14:11:44,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:44,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4826 states and 6797 transitions. [2024-11-13 14:11:44,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4826 states and 6797 transitions. [2024-11-13 14:11:44,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4826 to 3460. [2024-11-13 14:11:44,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.408092485549133) internal successors, (4872), 3459 states have internal predecessors, (4872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4872 transitions. [2024-11-13 14:11:44,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2024-11-13 14:11:44,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:11:44,622 INFO L424 stractBuchiCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2024-11-13 14:11:44,622 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 14:11:44,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4872 transitions. [2024-11-13 14:11:44,637 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2024-11-13 14:11:44,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:44,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:44,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,639 INFO L745 eck$LassoCheckResult]: Stem: 39119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 39120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 39233#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39234#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39219#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 39220#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39058#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39059#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39035#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39036#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39298#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39144#L611 assume !(0 == ~M_E~0); 39145#L611-2 assume !(0 == ~T1_E~0); 39314#L616-1 assume !(0 == ~T2_E~0); 39315#L621-1 assume !(0 == ~T3_E~0); 38898#L626-1 assume !(0 == ~T4_E~0); 38899#L631-1 assume !(0 == ~T5_E~0); 39096#L636-1 assume !(0 == ~E_M~0); 38949#L641-1 assume !(0 == ~E_1~0); 38950#L646-1 assume !(0 == ~E_2~0); 39115#L651-1 assume !(0 == ~E_3~0); 39354#L656-1 assume !(0 == ~E_4~0); 39296#L661-1 assume !(0 == ~E_5~0); 39297#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39331#L304 assume !(1 == ~m_pc~0); 38975#L304-2 is_master_triggered_~__retres1~0#1 := 0; 38875#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38876#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38825#L755 assume !(0 != activate_threads_~tmp~1#1); 38826#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38782#L323 assume !(1 == ~t1_pc~0); 38783#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38843#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38844#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38860#L763 assume !(0 != activate_threads_~tmp___0~0#1); 39393#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38847#L342 assume !(1 == ~t2_pc~0); 38849#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38982#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38983#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39237#L771 assume !(0 != activate_threads_~tmp___1~0#1); 39291#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39185#L361 assume !(1 == ~t3_pc~0); 39186#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39212#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38798#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38799#L779 assume !(0 != activate_threads_~tmp___2~0#1); 38863#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38864#L380 assume !(1 == ~t4_pc~0); 39184#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39306#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38944#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38945#L787 assume !(0 != activate_threads_~tmp___3~0#1); 39222#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38922#L399 assume !(1 == ~t5_pc~0); 38923#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39068#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39060#L795 assume !(0 != activate_threads_~tmp___4~0#1); 39061#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39368#L679 assume !(1 == ~M_E~0); 39142#L679-2 assume !(1 == ~T1_E~0); 38995#L684-1 assume !(1 == ~T2_E~0); 38996#L689-1 assume !(1 == ~T3_E~0); 39193#L694-1 assume !(1 == ~T4_E~0); 39191#L699-1 assume !(1 == ~T5_E~0); 39192#L704-1 assume !(1 == ~E_M~0); 39169#L709-1 assume !(1 == ~E_1~0); 39101#L714-1 assume !(1 == ~E_2~0); 39102#L719-1 assume !(1 == ~E_3~0); 39286#L724-1 assume !(1 == ~E_4~0); 38886#L729-1 assume !(1 == ~E_5~0); 38887#L734-1 assume { :end_inline_reset_delta_events } true; 39373#L940-2 [2024-11-13 14:11:44,640 INFO L747 eck$LassoCheckResult]: Loop: 39373#L940-2 assume !false; 40897#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40892#L586-1 assume !false; 40890#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40885#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40881#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40875#L511 assume !(0 != eval_~tmp~0#1); 40873#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40869#L611-3 assume !(0 == ~M_E~0); 40867#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40864#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40862#L621-3 assume !(0 == ~T3_E~0); 40860#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40858#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40856#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40853#L641-3 assume !(0 == ~E_1~0); 40849#L646-3 assume !(0 == ~E_2~0); 40845#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40841#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40837#L661-3 assume !(0 == ~E_5~0); 40833#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40829#L304-21 assume !(1 == ~m_pc~0); 40825#L304-23 is_master_triggered_~__retres1~0#1 := 0; 40822#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40819#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40816#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40813#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40809#L323-21 assume !(1 == ~t1_pc~0); 40806#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 40802#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40799#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40796#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 40794#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40792#L342-21 assume !(1 == ~t2_pc~0); 40787#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 40765#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40760#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40756#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40753#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40750#L361-21 assume 1 == ~t3_pc~0; 40746#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40742#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40738#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40734#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40731#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40727#L380-21 assume !(1 == ~t4_pc~0); 40724#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 40721#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40716#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40711#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40704#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40700#L399-21 assume !(1 == ~t5_pc~0); 40695#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 40690#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40686#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40681#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40671#L679-3 assume !(1 == ~M_E~0); 40380#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40667#L684-3 assume !(1 == ~T2_E~0); 40666#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40665#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40664#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40663#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40661#L709-3 assume !(1 == ~E_1~0); 40658#L714-3 assume !(1 == ~E_2~0); 40656#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40654#L724-3 assume !(1 == ~E_4~0); 40652#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40650#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40647#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40641#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40640#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 39475#L959 assume !(0 == start_simulation_~tmp~3#1); 39476#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40953#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40946#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 40934#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 40929#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40918#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 40910#L972 assume !(0 != start_simulation_~tmp___0~1#1); 39373#L940-2 [2024-11-13 14:11:44,640 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:44,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2024-11-13 14:11:44,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:44,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477425478] [2024-11-13 14:11:44,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:44,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:44,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:44,652 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:44,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:44,694 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:44,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:44,695 INFO L85 PathProgramCache]: Analyzing trace with hash 680549147, now seen corresponding path program 1 times [2024-11-13 14:11:44,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:44,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476058736] [2024-11-13 14:11:44,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:44,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:44,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:44,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:44,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:44,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476058736] [2024-11-13 14:11:44,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476058736] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:44,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:44,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:44,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686794356] [2024-11-13 14:11:44,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:44,735 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:44,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:44,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:44,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:44,736 INFO L87 Difference]: Start difference. First operand 3460 states and 4872 transitions. cyclomatic complexity: 1416 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:44,780 INFO L93 Difference]: Finished difference Result 3972 states and 5589 transitions. [2024-11-13 14:11:44,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3972 states and 5589 transitions. [2024-11-13 14:11:44,801 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2024-11-13 14:11:44,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3972 states to 3972 states and 5589 transitions. [2024-11-13 14:11:44,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3972 [2024-11-13 14:11:44,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3972 [2024-11-13 14:11:44,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3972 states and 5589 transitions. [2024-11-13 14:11:44,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:44,854 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3972 states and 5589 transitions. [2024-11-13 14:11:44,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3972 states and 5589 transitions. [2024-11-13 14:11:44,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3972 to 3972. [2024-11-13 14:11:44,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3972 states, 3972 states have (on average 1.4070996978851964) internal successors, (5589), 3971 states have internal predecessors, (5589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:44,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3972 states to 3972 states and 5589 transitions. [2024-11-13 14:11:44,938 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3972 states and 5589 transitions. [2024-11-13 14:11:44,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:44,939 INFO L424 stractBuchiCegarLoop]: Abstraction has 3972 states and 5589 transitions. [2024-11-13 14:11:44,939 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 14:11:44,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3972 states and 5589 transitions. [2024-11-13 14:11:44,961 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2024-11-13 14:11:44,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:44,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:44,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:44,963 INFO L745 eck$LassoCheckResult]: Stem: 46559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 46560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 46663#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46664#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46649#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 46650#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46496#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46497#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46473#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46474#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46737#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46582#L611 assume !(0 == ~M_E~0); 46583#L611-2 assume !(0 == ~T1_E~0); 46752#L616-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46753#L621-1 assume !(0 == ~T3_E~0); 46758#L626-1 assume !(0 == ~T4_E~0); 46727#L631-1 assume !(0 == ~T5_E~0); 46728#L636-1 assume !(0 == ~E_M~0); 46388#L641-1 assume !(0 == ~E_1~0); 46389#L646-1 assume !(0 == ~E_2~0); 46843#L651-1 assume !(0 == ~E_3~0); 46800#L656-1 assume !(0 == ~E_4~0); 46735#L661-1 assume !(0 == ~E_5~0); 46736#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46860#L304 assume !(1 == ~m_pc~0); 46414#L304-2 is_master_triggered_~__retres1~0#1 := 0; 46415#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46916#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46915#L755 assume !(0 != activate_threads_~tmp~1#1); 46870#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46220#L323 assume !(1 == ~t1_pc~0); 46221#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46281#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46296#L763 assume !(0 != activate_threads_~tmp___0~0#1); 46844#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46848#L342 assume !(1 == ~t2_pc~0); 46901#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46900#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46665#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46666#L771 assume !(0 != activate_threads_~tmp___1~0#1); 46898#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46897#L361 assume !(1 == ~t3_pc~0); 46895#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46893#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46891#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46887#L779 assume !(0 != activate_threads_~tmp___2~0#1); 46886#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46885#L380 assume !(1 == ~t4_pc~0); 46865#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46745#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46381#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46382#L787 assume !(0 != activate_threads_~tmp___3~0#1); 46882#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46881#L399 assume !(1 == ~t5_pc~0); 46879#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46878#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46877#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46876#L795 assume !(0 != activate_threads_~tmp___4~0#1); 46875#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46863#L679 assume !(1 == ~M_E~0); 46580#L679-2 assume !(1 == ~T1_E~0); 46437#L684-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46438#L689-1 assume !(1 == ~T3_E~0); 46625#L694-1 assume !(1 == ~T4_E~0); 46623#L699-1 assume !(1 == ~T5_E~0); 46624#L704-1 assume !(1 == ~E_M~0); 46605#L709-1 assume !(1 == ~E_1~0); 46540#L714-1 assume !(1 == ~E_2~0); 46541#L719-1 assume !(1 == ~E_3~0); 46722#L724-1 assume !(1 == ~E_4~0); 46323#L729-1 assume !(1 == ~E_5~0); 46324#L734-1 assume { :end_inline_reset_delta_events } true; 46816#L940-2 [2024-11-13 14:11:44,963 INFO L747 eck$LassoCheckResult]: Loop: 46816#L940-2 assume !false; 47282#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47278#L586-1 assume !false; 47275#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 47263#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 47259#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 47258#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47254#L511 assume !(0 != eval_~tmp~0#1); 47255#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49775#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49774#L611-3 assume !(0 == ~M_E~0); 49772#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49769#L616-3 assume !(0 == ~T2_E~0); 49768#L621-3 assume !(0 == ~T3_E~0); 49767#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49766#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49765#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49764#L641-3 assume !(0 == ~E_1~0); 49763#L646-3 assume !(0 == ~E_2~0); 49762#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49761#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49759#L661-3 assume !(0 == ~E_5~0); 49757#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49755#L304-21 assume !(1 == ~m_pc~0); 49751#L304-23 is_master_triggered_~__retres1~0#1 := 0; 49749#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49747#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49745#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49743#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49741#L323-21 assume !(1 == ~t1_pc~0); 49739#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 49737#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49735#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49733#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 49667#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49664#L342-21 assume !(1 == ~t2_pc~0); 49661#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 49659#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49657#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49655#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49653#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49651#L361-21 assume 1 == ~t3_pc~0; 49648#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49646#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49644#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49641#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49639#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49637#L380-21 assume !(1 == ~t4_pc~0); 49634#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 49632#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49630#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49628#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49626#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49624#L399-21 assume !(1 == ~t5_pc~0); 49621#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 49619#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49617#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49614#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49612#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49610#L679-3 assume !(1 == ~M_E~0); 49606#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49569#L684-3 assume !(1 == ~T2_E~0); 49567#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49565#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49563#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49560#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49558#L709-3 assume !(1 == ~E_1~0); 49556#L714-3 assume !(1 == ~E_2~0); 49554#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49552#L724-3 assume !(1 == ~E_4~0); 49550#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46706#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 46278#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 46279#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 46599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 46635#L959 assume !(0 == start_simulation_~tmp~3#1); 46639#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 47302#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 47295#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 47293#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 47292#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 47289#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47287#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 47285#L972 assume !(0 != start_simulation_~tmp___0~1#1); 46816#L940-2 [2024-11-13 14:11:44,964 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:44,964 INFO L85 PathProgramCache]: Analyzing trace with hash 97892357, now seen corresponding path program 1 times [2024-11-13 14:11:44,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:44,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986639744] [2024-11-13 14:11:44,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:44,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:44,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:45,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:45,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:45,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986639744] [2024-11-13 14:11:45,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986639744] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:45,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:45,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:45,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799534299] [2024-11-13 14:11:45,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:45,034 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:45,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:45,035 INFO L85 PathProgramCache]: Analyzing trace with hash 757449945, now seen corresponding path program 1 times [2024-11-13 14:11:45,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:45,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995923057] [2024-11-13 14:11:45,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:45,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:45,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:45,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:45,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:45,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995923057] [2024-11-13 14:11:45,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995923057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:45,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:45,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:45,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811554589] [2024-11-13 14:11:45,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:45,105 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:45,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:45,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:11:45,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:11:45,106 INFO L87 Difference]: Start difference. First operand 3972 states and 5589 transitions. cyclomatic complexity: 1621 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:45,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:45,218 INFO L93 Difference]: Finished difference Result 5020 states and 7045 transitions. [2024-11-13 14:11:45,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5020 states and 7045 transitions. [2024-11-13 14:11:45,244 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4906 [2024-11-13 14:11:45,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5020 states to 5020 states and 7045 transitions. [2024-11-13 14:11:45,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5020 [2024-11-13 14:11:45,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5020 [2024-11-13 14:11:45,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5020 states and 7045 transitions. [2024-11-13 14:11:45,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:45,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5020 states and 7045 transitions. [2024-11-13 14:11:45,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5020 states and 7045 transitions. [2024-11-13 14:11:45,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5020 to 3460. [2024-11-13 14:11:45,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4054913294797688) internal successors, (4863), 3459 states have internal predecessors, (4863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:45,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4863 transitions. [2024-11-13 14:11:45,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4863 transitions. [2024-11-13 14:11:45,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:11:45,361 INFO L424 stractBuchiCegarLoop]: Abstraction has 3460 states and 4863 transitions. [2024-11-13 14:11:45,361 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 14:11:45,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4863 transitions. [2024-11-13 14:11:45,376 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2024-11-13 14:11:45,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:45,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:45,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:45,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:45,378 INFO L745 eck$LassoCheckResult]: Stem: 55556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 55557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 55665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55653#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 55654#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55496#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55497#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55472#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55473#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55730#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55579#L611 assume !(0 == ~M_E~0); 55580#L611-2 assume !(0 == ~T1_E~0); 55747#L616-1 assume !(0 == ~T2_E~0); 55748#L621-1 assume !(0 == ~T3_E~0); 55338#L626-1 assume !(0 == ~T4_E~0); 55339#L631-1 assume !(0 == ~T5_E~0); 55534#L636-1 assume !(0 == ~E_M~0); 55391#L641-1 assume !(0 == ~E_1~0); 55392#L646-1 assume !(0 == ~E_2~0); 55553#L651-1 assume !(0 == ~E_3~0); 55784#L656-1 assume !(0 == ~E_4~0); 55728#L661-1 assume !(0 == ~E_5~0); 55729#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55760#L304 assume !(1 == ~m_pc~0); 55417#L304-2 is_master_triggered_~__retres1~0#1 := 0; 55315#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55316#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55265#L755 assume !(0 != activate_threads_~tmp~1#1); 55266#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55222#L323 assume !(1 == ~t1_pc~0); 55223#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55283#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55284#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55299#L763 assume !(0 != activate_threads_~tmp___0~0#1); 55826#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55287#L342 assume !(1 == ~t2_pc~0); 55289#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55423#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55424#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55667#L771 assume !(0 != activate_threads_~tmp___1~0#1); 55724#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55619#L361 assume !(1 == ~t3_pc~0); 55620#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55647#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55239#L779 assume !(0 != activate_threads_~tmp___2~0#1); 55302#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55303#L380 assume !(1 == ~t4_pc~0); 55618#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55738#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55384#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55385#L787 assume !(0 != activate_threads_~tmp___3~0#1); 55655#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55362#L399 assume !(1 == ~t5_pc~0); 55363#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 55506#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55511#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55498#L795 assume !(0 != activate_threads_~tmp___4~0#1); 55499#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55798#L679 assume !(1 == ~M_E~0); 55577#L679-2 assume !(1 == ~T1_E~0); 55436#L684-1 assume !(1 == ~T2_E~0); 55437#L689-1 assume !(1 == ~T3_E~0); 55627#L694-1 assume !(1 == ~T4_E~0); 55625#L699-1 assume !(1 == ~T5_E~0); 55626#L704-1 assume !(1 == ~E_M~0); 55603#L709-1 assume !(1 == ~E_1~0); 55539#L714-1 assume !(1 == ~E_2~0); 55540#L719-1 assume !(1 == ~E_3~0); 55718#L724-1 assume !(1 == ~E_4~0); 55326#L729-1 assume !(1 == ~E_5~0); 55327#L734-1 assume { :end_inline_reset_delta_events } true; 55689#L940-2 [2024-11-13 14:11:45,378 INFO L747 eck$LassoCheckResult]: Loop: 55689#L940-2 assume !false; 55706#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55399#L586-1 assume !false; 55787#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55793#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55622#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55623#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 55616#L511 assume !(0 != eval_~tmp~0#1); 55617#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57474#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57473#L611-3 assume !(0 == ~M_E~0); 57472#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57471#L616-3 assume !(0 == ~T2_E~0); 57470#L621-3 assume !(0 == ~T3_E~0); 57469#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57468#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57467#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57466#L641-3 assume !(0 == ~E_1~0); 57465#L646-3 assume !(0 == ~E_2~0); 57464#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57463#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57462#L661-3 assume !(0 == ~E_5~0); 57461#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57460#L304-21 assume !(1 == ~m_pc~0); 57458#L304-23 is_master_triggered_~__retres1~0#1 := 0; 57457#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57456#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57455#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57454#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57453#L323-21 assume !(1 == ~t1_pc~0); 57452#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 57451#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57450#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57449#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 57448#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57447#L342-21 assume !(1 == ~t2_pc~0); 57445#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 57444#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57443#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57442#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57441#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57440#L361-21 assume 1 == ~t3_pc~0; 57438#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57436#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57434#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57432#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57431#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57430#L380-21 assume !(1 == ~t4_pc~0); 57429#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 57428#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57427#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57426#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57425#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57424#L399-21 assume !(1 == ~t5_pc~0); 57422#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 57421#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57420#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57419#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57418#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57417#L679-3 assume !(1 == ~M_E~0); 56924#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57416#L684-3 assume !(1 == ~T2_E~0); 57415#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57414#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57413#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57412#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57411#L709-3 assume !(1 == ~E_1~0); 57410#L714-3 assume !(1 == ~E_2~0); 57409#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57408#L724-3 assume !(1 == ~E_4~0); 57407#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57406#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57405#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57399#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55638#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 55639#L959 assume !(0 == start_simulation_~tmp~3#1); 55643#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55542#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55543#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55297#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 55298#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 55455#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55456#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 55688#L972 assume !(0 != start_simulation_~tmp___0~1#1); 55689#L940-2 [2024-11-13 14:11:45,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:45,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2024-11-13 14:11:45,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:45,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329727806] [2024-11-13 14:11:45,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:45,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:45,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:45,393 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:45,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:45,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:45,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:45,425 INFO L85 PathProgramCache]: Analyzing trace with hash 757449945, now seen corresponding path program 2 times [2024-11-13 14:11:45,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:45,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272290857] [2024-11-13 14:11:45,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:45,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:45,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:45,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:45,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:45,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272290857] [2024-11-13 14:11:45,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272290857] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:45,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:45,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:45,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616942355] [2024-11-13 14:11:45,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:45,471 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:45,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:45,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:45,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:45,472 INFO L87 Difference]: Start difference. First operand 3460 states and 4863 transitions. cyclomatic complexity: 1407 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:45,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:45,606 INFO L93 Difference]: Finished difference Result 5180 states and 7248 transitions. [2024-11-13 14:11:45,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5180 states and 7248 transitions. [2024-11-13 14:11:45,635 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5024 [2024-11-13 14:11:45,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5180 states to 5180 states and 7248 transitions. [2024-11-13 14:11:45,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5180 [2024-11-13 14:11:45,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5180 [2024-11-13 14:11:45,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5180 states and 7248 transitions. [2024-11-13 14:11:45,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:45,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5180 states and 7248 transitions. [2024-11-13 14:11:45,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5180 states and 7248 transitions. [2024-11-13 14:11:45,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5180 to 5176. [2024-11-13 14:11:45,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5176 states, 5176 states have (on average 1.3995363214837713) internal successors, (7244), 5175 states have internal predecessors, (7244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:45,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5176 states to 5176 states and 7244 transitions. [2024-11-13 14:11:45,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5176 states and 7244 transitions. [2024-11-13 14:11:45,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:45,756 INFO L424 stractBuchiCegarLoop]: Abstraction has 5176 states and 7244 transitions. [2024-11-13 14:11:45,756 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 14:11:45,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5176 states and 7244 transitions. [2024-11-13 14:11:45,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5020 [2024-11-13 14:11:45,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:45,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:45,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:45,774 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:45,775 INFO L745 eck$LassoCheckResult]: Stem: 64208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 64209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 64324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64310#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 64311#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64146#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64147#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64121#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64122#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64395#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64232#L611 assume !(0 == ~M_E~0); 64233#L611-2 assume !(0 == ~T1_E~0); 64414#L616-1 assume !(0 == ~T2_E~0); 64415#L621-1 assume !(0 == ~T3_E~0); 63986#L626-1 assume !(0 == ~T4_E~0); 63987#L631-1 assume !(0 == ~T5_E~0); 64187#L636-1 assume !(0 == ~E_M~0); 64038#L641-1 assume !(0 == ~E_1~0); 64039#L646-1 assume !(0 == ~E_2~0); 64205#L651-1 assume !(0 == ~E_3~0); 64466#L656-1 assume 0 == ~E_4~0;~E_4~0 := 1; 64393#L661-1 assume !(0 == ~E_5~0); 64394#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64520#L304 assume !(1 == ~m_pc~0); 64521#L304-2 is_master_triggered_~__retres1~0#1 := 0; 63963#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63964#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63911#L755 assume !(0 != activate_threads_~tmp~1#1); 63912#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63868#L323 assume !(1 == ~t1_pc~0); 63869#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63930#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63931#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64508#L763 assume !(0 != activate_threads_~tmp___0~0#1); 64509#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63934#L342 assume !(1 == ~t2_pc~0); 63936#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 64070#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64071#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64525#L771 assume !(0 != activate_threads_~tmp___1~0#1); 64386#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64273#L361 assume !(1 == ~t3_pc~0); 64274#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64301#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64485#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64460#L779 assume !(0 != activate_threads_~tmp___2~0#1); 63952#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63953#L380 assume !(1 == ~t4_pc~0); 64272#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64564#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64313#L787 assume !(0 != activate_threads_~tmp___3~0#1); 64314#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64010#L399 assume !(1 == ~t5_pc~0); 64011#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 64158#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64163#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64148#L795 assume !(0 != activate_threads_~tmp___4~0#1); 64149#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64479#L679 assume !(1 == ~M_E~0); 64553#L679-2 assume !(1 == ~T1_E~0); 64552#L684-1 assume !(1 == ~T2_E~0); 64551#L689-1 assume !(1 == ~T3_E~0); 64530#L694-1 assume !(1 == ~T4_E~0); 64280#L699-1 assume !(1 == ~T5_E~0); 64281#L704-1 assume !(1 == ~E_M~0); 64257#L709-1 assume !(1 == ~E_1~0); 64190#L714-1 assume !(1 == ~E_2~0); 64191#L719-1 assume !(1 == ~E_3~0); 64381#L724-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63974#L729-1 assume !(1 == ~E_5~0); 63975#L734-1 assume { :end_inline_reset_delta_events } true; 64486#L940-2 [2024-11-13 14:11:45,775 INFO L747 eck$LassoCheckResult]: Loop: 64486#L940-2 assume !false; 66193#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66189#L586-1 assume !false; 66187#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66176#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66172#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66170#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 66167#L511 assume !(0 != eval_~tmp~0#1); 66168#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66724#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66720#L611-3 assume !(0 == ~M_E~0); 66715#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66711#L616-3 assume !(0 == ~T2_E~0); 66707#L621-3 assume !(0 == ~T3_E~0); 66704#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66700#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66694#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66693#L641-3 assume !(0 == ~E_1~0); 66692#L646-3 assume !(0 == ~E_2~0); 66690#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66688#L656-3 assume !(0 == ~E_4~0); 66689#L661-3 assume !(0 == ~E_5~0); 66749#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66746#L304-21 assume 1 == ~m_pc~0; 66743#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 66739#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66736#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66733#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66730#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66726#L323-21 assume !(1 == ~t1_pc~0); 66722#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 66717#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66713#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66709#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 66705#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66702#L342-21 assume !(1 == ~t2_pc~0); 66697#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 66623#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66614#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66607#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66606#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66602#L361-21 assume !(1 == ~t3_pc~0); 66598#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 66596#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66594#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66592#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 66589#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66586#L380-21 assume !(1 == ~t4_pc~0); 66584#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 66582#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66580#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66578#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66577#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66576#L399-21 assume !(1 == ~t5_pc~0); 66573#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 66570#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66568#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66566#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66564#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66562#L679-3 assume !(1 == ~M_E~0); 66556#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66554#L684-3 assume !(1 == ~T2_E~0); 66552#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66550#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66548#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66546#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66544#L709-3 assume !(1 == ~E_1~0); 66542#L714-3 assume !(1 == ~E_2~0); 66540#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66537#L724-3 assume !(1 == ~E_4~0); 66536#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66526#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66491#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66483#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66477#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 66222#L959 assume !(0 == start_simulation_~tmp~3#1); 66219#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66217#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66210#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66206#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 66204#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 66202#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66200#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 66197#L972 assume !(0 != start_simulation_~tmp___0~1#1); 64486#L940-2 [2024-11-13 14:11:45,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:45,775 INFO L85 PathProgramCache]: Analyzing trace with hash -537561083, now seen corresponding path program 1 times [2024-11-13 14:11:45,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:45,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912725841] [2024-11-13 14:11:45,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:45,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:45,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:45,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:45,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:45,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912725841] [2024-11-13 14:11:45,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1912725841] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:45,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:45,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:45,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033549842] [2024-11-13 14:11:45,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:45,855 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:45,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:45,855 INFO L85 PathProgramCache]: Analyzing trace with hash -272311975, now seen corresponding path program 1 times [2024-11-13 14:11:45,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:45,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574246534] [2024-11-13 14:11:45,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:45,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:45,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:45,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:45,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:45,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574246534] [2024-11-13 14:11:45,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574246534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:45,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:45,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:45,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911631025] [2024-11-13 14:11:45,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:45,943 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:45,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:45,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 14:11:45,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 14:11:45,944 INFO L87 Difference]: Start difference. First operand 5176 states and 7244 transitions. cyclomatic complexity: 2072 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:46,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:46,123 INFO L93 Difference]: Finished difference Result 6951 states and 9714 transitions. [2024-11-13 14:11:46,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6951 states and 9714 transitions. [2024-11-13 14:11:46,154 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 6694 [2024-11-13 14:11:46,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6951 states to 6951 states and 9714 transitions. [2024-11-13 14:11:46,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6951 [2024-11-13 14:11:46,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6951 [2024-11-13 14:11:46,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6951 states and 9714 transitions. [2024-11-13 14:11:46,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:46,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6951 states and 9714 transitions. [2024-11-13 14:11:46,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6951 states and 9714 transitions. [2024-11-13 14:11:46,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6951 to 4894. [2024-11-13 14:11:46,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4894 states, 4894 states have (on average 1.3984470780547609) internal successors, (6844), 4893 states have internal predecessors, (6844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:46,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4894 states to 4894 states and 6844 transitions. [2024-11-13 14:11:46,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4894 states and 6844 transitions. [2024-11-13 14:11:46,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 14:11:46,319 INFO L424 stractBuchiCegarLoop]: Abstraction has 4894 states and 6844 transitions. [2024-11-13 14:11:46,319 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 14:11:46,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4894 states and 6844 transitions. [2024-11-13 14:11:46,334 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4794 [2024-11-13 14:11:46,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:46,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:46,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:46,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:46,336 INFO L745 eck$LassoCheckResult]: Stem: 76343#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 76344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76455#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76456#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76441#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 76442#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76282#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76283#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76257#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76258#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76536#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76367#L611 assume !(0 == ~M_E~0); 76368#L611-2 assume !(0 == ~T1_E~0); 76554#L616-1 assume !(0 == ~T2_E~0); 76555#L621-1 assume !(0 == ~T3_E~0); 76123#L626-1 assume !(0 == ~T4_E~0); 76124#L631-1 assume !(0 == ~T5_E~0); 76321#L636-1 assume !(0 == ~E_M~0); 76175#L641-1 assume !(0 == ~E_1~0); 76176#L646-1 assume !(0 == ~E_2~0); 76338#L651-1 assume !(0 == ~E_3~0); 76598#L656-1 assume !(0 == ~E_4~0); 76534#L661-1 assume !(0 == ~E_5~0); 76535#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76572#L304 assume !(1 == ~m_pc~0); 76201#L304-2 is_master_triggered_~__retres1~0#1 := 0; 76100#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76101#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76050#L755 assume !(0 != activate_threads_~tmp~1#1); 76051#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76007#L323 assume !(1 == ~t1_pc~0); 76008#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76069#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76070#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76086#L763 assume !(0 != activate_threads_~tmp___0~0#1); 76629#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76073#L342 assume !(1 == ~t2_pc~0); 76075#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76208#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76209#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76457#L771 assume !(0 != activate_threads_~tmp___1~0#1); 76527#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76405#L361 assume !(1 == ~t3_pc~0); 76406#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76433#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76023#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76024#L779 assume !(0 != activate_threads_~tmp___2~0#1); 76089#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76090#L380 assume !(1 == ~t4_pc~0); 76404#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76546#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76171#L787 assume !(0 != activate_threads_~tmp___3~0#1); 76444#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76147#L399 assume !(1 == ~t5_pc~0); 76148#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76292#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76297#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76284#L795 assume !(0 != activate_threads_~tmp___4~0#1); 76285#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76611#L679 assume !(1 == ~M_E~0); 76365#L679-2 assume !(1 == ~T1_E~0); 76221#L684-1 assume !(1 == ~T2_E~0); 76222#L689-1 assume !(1 == ~T3_E~0); 76414#L694-1 assume !(1 == ~T4_E~0); 76412#L699-1 assume !(1 == ~T5_E~0); 76413#L704-1 assume !(1 == ~E_M~0); 76392#L709-1 assume !(1 == ~E_1~0); 76324#L714-1 assume !(1 == ~E_2~0); 76325#L719-1 assume !(1 == ~E_3~0); 76517#L724-1 assume !(1 == ~E_4~0); 76111#L729-1 assume !(1 == ~E_5~0); 76112#L734-1 assume { :end_inline_reset_delta_events } true; 76617#L940-2 [2024-11-13 14:11:46,336 INFO L747 eck$LassoCheckResult]: Loop: 76617#L940-2 assume !false; 78583#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78577#L586-1 assume !false; 78574#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78524#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78516#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78499#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 78468#L511 assume !(0 != eval_~tmp~0#1); 78464#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78458#L611-3 assume !(0 == ~M_E~0); 78445#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78241#L616-3 assume !(0 == ~T2_E~0); 78238#L621-3 assume !(0 == ~T3_E~0); 78234#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78230#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78142#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78127#L641-3 assume !(0 == ~E_1~0); 78119#L646-3 assume !(0 == ~E_2~0); 78113#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78105#L656-3 assume !(0 == ~E_4~0); 78102#L661-3 assume !(0 == ~E_5~0); 78094#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78090#L304-21 assume 1 == ~m_pc~0; 78087#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 78082#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78079#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78076#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78073#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78070#L323-21 assume !(1 == ~t1_pc~0); 78067#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 78064#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78061#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78058#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 78055#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78052#L342-21 assume !(1 == ~t2_pc~0); 78048#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 78045#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78042#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78039#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78035#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78032#L361-21 assume 1 == ~t3_pc~0; 78027#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78023#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78019#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78015#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78012#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78009#L380-21 assume !(1 == ~t4_pc~0); 78006#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 78003#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78000#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77996#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77993#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77989#L399-21 assume !(1 == ~t5_pc~0); 77985#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 77982#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77979#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77976#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77972#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77968#L679-3 assume !(1 == ~M_E~0); 77636#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77959#L684-3 assume !(1 == ~T2_E~0); 77955#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77951#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77947#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77943#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77940#L709-3 assume !(1 == ~E_1~0); 77937#L714-3 assume !(1 == ~E_2~0); 77934#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77931#L724-3 assume !(1 == ~E_4~0); 77927#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77924#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 77918#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 77910#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 77908#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 76428#L959 assume !(0 == start_simulation_~tmp~3#1); 76429#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78628#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78621#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78619#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 78617#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 78614#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78603#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 78595#L972 assume !(0 != start_simulation_~tmp___0~1#1); 76617#L940-2 [2024-11-13 14:11:46,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:46,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2024-11-13 14:11:46,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:46,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396887926] [2024-11-13 14:11:46,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:46,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:46,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:46,351 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:46,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:46,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:46,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:46,380 INFO L85 PathProgramCache]: Analyzing trace with hash -325475114, now seen corresponding path program 1 times [2024-11-13 14:11:46,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:46,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412331626] [2024-11-13 14:11:46,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:46,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:46,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:46,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:46,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:46,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412331626] [2024-11-13 14:11:46,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412331626] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:46,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:46,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:46,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619244946] [2024-11-13 14:11:46,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:46,462 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:46,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:46,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:46,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:46,462 INFO L87 Difference]: Start difference. First operand 4894 states and 6844 transitions. cyclomatic complexity: 1954 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:46,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:46,573 INFO L93 Difference]: Finished difference Result 4962 states and 6912 transitions. [2024-11-13 14:11:46,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4962 states and 6912 transitions. [2024-11-13 14:11:46,592 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4862 [2024-11-13 14:11:46,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4962 states to 4962 states and 6912 transitions. [2024-11-13 14:11:46,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4962 [2024-11-13 14:11:46,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4962 [2024-11-13 14:11:46,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4962 states and 6912 transitions. [2024-11-13 14:11:46,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:46,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4962 states and 6912 transitions. [2024-11-13 14:11:46,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4962 states and 6912 transitions. [2024-11-13 14:11:46,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4962 to 4930. [2024-11-13 14:11:46,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4930 states, 4930 states have (on average 1.3955375253549696) internal successors, (6880), 4929 states have internal predecessors, (6880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:46,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4930 states to 4930 states and 6880 transitions. [2024-11-13 14:11:46,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4930 states and 6880 transitions. [2024-11-13 14:11:46,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:46,698 INFO L424 stractBuchiCegarLoop]: Abstraction has 4930 states and 6880 transitions. [2024-11-13 14:11:46,698 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 14:11:46,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4930 states and 6880 transitions. [2024-11-13 14:11:46,712 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4830 [2024-11-13 14:11:46,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:46,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:46,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:46,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:46,714 INFO L745 eck$LassoCheckResult]: Stem: 86209#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 86210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 86328#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86329#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86314#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 86315#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86147#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86148#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86123#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86124#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86403#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86234#L611 assume !(0 == ~M_E~0); 86235#L611-2 assume !(0 == ~T1_E~0); 86424#L616-1 assume !(0 == ~T2_E~0); 86425#L621-1 assume !(0 == ~T3_E~0); 85994#L626-1 assume !(0 == ~T4_E~0); 85995#L631-1 assume !(0 == ~T5_E~0); 86190#L636-1 assume !(0 == ~E_M~0); 86042#L641-1 assume !(0 == ~E_1~0); 86043#L646-1 assume !(0 == ~E_2~0); 86206#L651-1 assume !(0 == ~E_3~0); 86478#L656-1 assume !(0 == ~E_4~0); 86401#L661-1 assume !(0 == ~E_5~0); 86402#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86446#L304 assume !(1 == ~m_pc~0); 86070#L304-2 is_master_triggered_~__retres1~0#1 := 0; 85964#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85965#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85919#L755 assume !(0 != activate_threads_~tmp~1#1); 85920#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85875#L323 assume !(1 == ~t1_pc~0); 85876#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 85933#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85934#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85950#L763 assume !(0 != activate_threads_~tmp___0~0#1); 86515#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85943#L342 assume !(1 == ~t2_pc~0); 85945#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86072#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86331#L771 assume !(0 != activate_threads_~tmp___1~0#1); 86395#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86276#L361 assume !(1 == ~t3_pc~0); 86277#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86304#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85888#L779 assume !(0 != activate_threads_~tmp___2~0#1); 85955#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85956#L380 assume !(1 == ~t4_pc~0); 86275#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86417#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86037#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86038#L787 assume !(0 != activate_threads_~tmp___3~0#1); 86318#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86012#L399 assume !(1 == ~t5_pc~0); 86013#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86158#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86164#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86149#L795 assume !(0 != activate_threads_~tmp___4~0#1); 86150#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86489#L679 assume !(1 == ~M_E~0); 86233#L679-2 assume !(1 == ~T1_E~0); 86085#L684-1 assume !(1 == ~T2_E~0); 86086#L689-1 assume !(1 == ~T3_E~0); 86284#L694-1 assume !(1 == ~T4_E~0); 86282#L699-1 assume !(1 == ~T5_E~0); 86283#L704-1 assume !(1 == ~E_M~0); 86261#L709-1 assume !(1 == ~E_1~0); 86195#L714-1 assume !(1 == ~E_2~0); 86196#L719-1 assume !(1 == ~E_3~0); 86391#L724-1 assume !(1 == ~E_4~0); 85975#L729-1 assume !(1 == ~E_5~0); 85976#L734-1 assume { :end_inline_reset_delta_events } true; 86494#L940-2 [2024-11-13 14:11:46,714 INFO L747 eck$LassoCheckResult]: Loop: 86494#L940-2 assume !false; 87787#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87783#L586-1 assume !false; 87782#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 87777#L464 assume !(0 == ~m_st~0); 87778#L468 assume !(0 == ~t1_st~0); 87780#L472 assume !(0 == ~t2_st~0); 87775#L476 assume !(0 == ~t3_st~0); 87776#L480 assume !(0 == ~t4_st~0); 87779#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 87781#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 87495#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 87496#L511 assume !(0 != eval_~tmp~0#1); 88058#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88054#L611-3 assume !(0 == ~M_E~0); 88052#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88050#L616-3 assume !(0 == ~T2_E~0); 88048#L621-3 assume !(0 == ~T3_E~0); 88046#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88044#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88042#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88040#L641-3 assume !(0 == ~E_1~0); 88038#L646-3 assume !(0 == ~E_2~0); 88036#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88034#L656-3 assume !(0 == ~E_4~0); 88032#L661-3 assume !(0 == ~E_5~0); 88030#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88028#L304-21 assume !(1 == ~m_pc~0); 88025#L304-23 is_master_triggered_~__retres1~0#1 := 0; 88022#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88020#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88018#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88016#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88014#L323-21 assume !(1 == ~t1_pc~0); 88012#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 88010#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88008#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88006#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 88004#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88002#L342-21 assume !(1 == ~t2_pc~0); 87998#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 87996#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87994#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 87992#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87990#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87988#L361-21 assume 1 == ~t3_pc~0; 87985#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 87981#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87977#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 87973#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87970#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87968#L380-21 assume !(1 == ~t4_pc~0); 87966#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 87964#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87962#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87960#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87958#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87956#L399-21 assume !(1 == ~t5_pc~0); 87953#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 87950#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87948#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87946#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87944#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87942#L679-3 assume !(1 == ~M_E~0); 87939#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87938#L684-3 assume !(1 == ~T2_E~0); 87937#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87936#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87935#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87934#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87933#L709-3 assume !(1 == ~E_1~0); 87932#L714-3 assume !(1 == ~E_2~0); 87931#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87930#L724-3 assume !(1 == ~E_4~0); 87929#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87928#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 87927#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 87920#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 87751#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 86299#L959 assume !(0 == start_simulation_~tmp~3#1); 86300#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 88064#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 87921#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 87821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 87815#L914 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 87811#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87804#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 87798#L972 assume !(0 != start_simulation_~tmp___0~1#1); 86494#L940-2 [2024-11-13 14:11:46,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:46,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2024-11-13 14:11:46,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:46,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763748975] [2024-11-13 14:11:46,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:46,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:46,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:46,729 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:46,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:46,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:46,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:46,751 INFO L85 PathProgramCache]: Analyzing trace with hash 274684384, now seen corresponding path program 1 times [2024-11-13 14:11:46,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:46,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742000494] [2024-11-13 14:11:46,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:46,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:46,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:46,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:46,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:46,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742000494] [2024-11-13 14:11:46,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742000494] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:46,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:46,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:46,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700367856] [2024-11-13 14:11:46,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:46,828 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:46,829 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:46,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:46,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:46,829 INFO L87 Difference]: Start difference. First operand 4930 states and 6880 transitions. cyclomatic complexity: 1954 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:46,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:46,965 INFO L93 Difference]: Finished difference Result 4970 states and 6920 transitions. [2024-11-13 14:11:46,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4970 states and 6920 transitions. [2024-11-13 14:11:46,983 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4870 [2024-11-13 14:11:47,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4970 states to 4970 states and 6920 transitions. [2024-11-13 14:11:47,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4970 [2024-11-13 14:11:47,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4970 [2024-11-13 14:11:47,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4970 states and 6920 transitions. [2024-11-13 14:11:47,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:47,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4970 states and 6920 transitions. [2024-11-13 14:11:47,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4970 states and 6920 transitions. [2024-11-13 14:11:47,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4970 to 4954. [2024-11-13 14:11:47,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4954 states, 4954 states have (on average 1.3936213161081954) internal successors, (6904), 4953 states have internal predecessors, (6904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:47,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4954 states to 4954 states and 6904 transitions. [2024-11-13 14:11:47,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4954 states and 6904 transitions. [2024-11-13 14:11:47,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:47,095 INFO L424 stractBuchiCegarLoop]: Abstraction has 4954 states and 6904 transitions. [2024-11-13 14:11:47,095 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 14:11:47,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4954 states and 6904 transitions. [2024-11-13 14:11:47,110 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4854 [2024-11-13 14:11:47,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:47,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:47,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:47,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:47,112 INFO L745 eck$LassoCheckResult]: Stem: 96118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 96119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 96230#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96231#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96217#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 96218#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96057#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96058#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96034#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96035#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96306#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96143#L611 assume !(0 == ~M_E~0); 96144#L611-2 assume !(0 == ~T1_E~0); 96323#L616-1 assume !(0 == ~T2_E~0); 96324#L621-1 assume !(0 == ~T3_E~0); 95895#L626-1 assume !(0 == ~T4_E~0); 95896#L631-1 assume !(0 == ~T5_E~0); 96095#L636-1 assume !(0 == ~E_M~0); 95947#L641-1 assume !(0 == ~E_1~0); 95948#L646-1 assume !(0 == ~E_2~0); 96115#L651-1 assume !(0 == ~E_3~0); 96373#L656-1 assume !(0 == ~E_4~0); 96304#L661-1 assume !(0 == ~E_5~0); 96305#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96341#L304 assume !(1 == ~m_pc~0); 95974#L304-2 is_master_triggered_~__retres1~0#1 := 0; 95872#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95873#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95822#L755 assume !(0 != activate_threads_~tmp~1#1); 95823#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95779#L323 assume !(1 == ~t1_pc~0); 95780#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95841#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95842#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95856#L763 assume !(0 != activate_threads_~tmp___0~0#1); 96409#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95844#L342 assume !(1 == ~t2_pc~0); 95846#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95980#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96232#L771 assume !(0 != activate_threads_~tmp___1~0#1); 96299#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96182#L361 assume !(1 == ~t3_pc~0); 96183#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96209#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95796#L779 assume !(0 != activate_threads_~tmp___2~0#1); 95859#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95860#L380 assume !(1 == ~t4_pc~0); 96181#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96316#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95941#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95942#L787 assume !(0 != activate_threads_~tmp___3~0#1); 96220#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95919#L399 assume !(1 == ~t5_pc~0); 95920#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96067#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96059#L795 assume !(0 != activate_threads_~tmp___4~0#1); 96060#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96385#L679 assume !(1 == ~M_E~0); 96141#L679-2 assume !(1 == ~T1_E~0); 95994#L684-1 assume !(1 == ~T2_E~0); 95995#L689-1 assume !(1 == ~T3_E~0); 96190#L694-1 assume !(1 == ~T4_E~0); 96188#L699-1 assume !(1 == ~T5_E~0); 96189#L704-1 assume !(1 == ~E_M~0); 96170#L709-1 assume !(1 == ~E_1~0); 96098#L714-1 assume !(1 == ~E_2~0); 96099#L719-1 assume !(1 == ~E_3~0); 96292#L724-1 assume !(1 == ~E_4~0); 95883#L729-1 assume !(1 == ~E_5~0); 95884#L734-1 assume { :end_inline_reset_delta_events } true; 96390#L940-2 [2024-11-13 14:11:47,112 INFO L747 eck$LassoCheckResult]: Loop: 96390#L940-2 assume !false; 97477#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97473#L586-1 assume !false; 97472#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97467#L464 assume !(0 == ~m_st~0); 97468#L468 assume !(0 == ~t1_st~0); 97470#L472 assume !(0 == ~t2_st~0); 97465#L476 assume !(0 == ~t3_st~0); 97466#L480 assume !(0 == ~t4_st~0); 97469#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 97471#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 97452#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 97453#L511 assume !(0 != eval_~tmp~0#1); 98059#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98057#L611-3 assume !(0 == ~M_E~0); 98056#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98055#L616-3 assume !(0 == ~T2_E~0); 98054#L621-3 assume !(0 == ~T3_E~0); 98053#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98052#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98051#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98050#L641-3 assume !(0 == ~E_1~0); 98049#L646-3 assume !(0 == ~E_2~0); 98048#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98047#L656-3 assume !(0 == ~E_4~0); 98046#L661-3 assume !(0 == ~E_5~0); 98045#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98044#L304-21 assume 1 == ~m_pc~0; 98043#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 98041#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98040#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98039#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 98038#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98037#L323-21 assume !(1 == ~t1_pc~0); 98036#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 98035#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98034#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98033#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 98032#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98031#L342-21 assume !(1 == ~t2_pc~0); 98029#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 98028#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98027#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98026#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98025#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98024#L361-21 assume !(1 == ~t3_pc~0); 98023#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 98021#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98019#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98017#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 98015#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98014#L380-21 assume !(1 == ~t4_pc~0); 98013#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98012#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98011#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98010#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98009#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98008#L399-21 assume 1 == ~t5_pc~0; 98007#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 98005#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98004#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98003#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98002#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98001#L679-3 assume !(1 == ~M_E~0); 97865#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98000#L684-3 assume !(1 == ~T2_E~0); 97999#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97998#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97997#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97996#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97995#L709-3 assume !(1 == ~E_1~0); 97994#L714-3 assume !(1 == ~E_2~0); 97993#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97992#L724-3 assume !(1 == ~E_4~0); 97991#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97990#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97989#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 96161#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 96162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 96200#L959 assume !(0 == start_simulation_~tmp~3#1); 97536#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97529#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 97520#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 97513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 97506#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97501#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97494#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 97488#L972 assume !(0 != start_simulation_~tmp___0~1#1); 96390#L940-2 [2024-11-13 14:11:47,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:47,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2024-11-13 14:11:47,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:47,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288692211] [2024-11-13 14:11:47,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:47,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:47,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:47,128 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:47,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:47,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:47,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:47,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1070726755, now seen corresponding path program 1 times [2024-11-13 14:11:47,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:47,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857445926] [2024-11-13 14:11:47,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:47,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:47,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:47,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:47,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:47,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857445926] [2024-11-13 14:11:47,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857445926] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:47,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:47,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:47,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195534110] [2024-11-13 14:11:47,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:47,251 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:47,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:47,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:47,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:47,252 INFO L87 Difference]: Start difference. First operand 4954 states and 6904 transitions. cyclomatic complexity: 1954 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:47,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:47,456 INFO L93 Difference]: Finished difference Result 4972 states and 6853 transitions. [2024-11-13 14:11:47,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4972 states and 6853 transitions. [2024-11-13 14:11:47,475 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4872 [2024-11-13 14:11:47,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4972 states to 4972 states and 6853 transitions. [2024-11-13 14:11:47,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4972 [2024-11-13 14:11:47,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4972 [2024-11-13 14:11:47,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4972 states and 6853 transitions. [2024-11-13 14:11:47,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:47,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4972 states and 6853 transitions. [2024-11-13 14:11:47,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4972 states and 6853 transitions. [2024-11-13 14:11:47,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4972 to 4972. [2024-11-13 14:11:47,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4972 states, 4972 states have (on average 1.3783185840707965) internal successors, (6853), 4971 states have internal predecessors, (6853), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:47,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4972 states to 4972 states and 6853 transitions. [2024-11-13 14:11:47,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4972 states and 6853 transitions. [2024-11-13 14:11:47,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:47,631 INFO L424 stractBuchiCegarLoop]: Abstraction has 4972 states and 6853 transitions. [2024-11-13 14:11:47,631 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 14:11:47,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4972 states and 6853 transitions. [2024-11-13 14:11:47,648 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4872 [2024-11-13 14:11:47,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:47,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:47,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:47,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:47,650 INFO L745 eck$LassoCheckResult]: Stem: 106047#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 106048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 106158#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106159#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106144#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 106145#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105985#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105986#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105961#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105962#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 106227#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106071#L611 assume !(0 == ~M_E~0); 106072#L611-2 assume !(0 == ~T1_E~0); 106245#L616-1 assume !(0 == ~T2_E~0); 106246#L621-1 assume !(0 == ~T3_E~0); 105828#L626-1 assume !(0 == ~T4_E~0); 105829#L631-1 assume !(0 == ~T5_E~0); 106024#L636-1 assume !(0 == ~E_M~0); 105880#L641-1 assume !(0 == ~E_1~0); 105881#L646-1 assume !(0 == ~E_2~0); 106044#L651-1 assume !(0 == ~E_3~0); 106288#L656-1 assume !(0 == ~E_4~0); 106225#L661-1 assume !(0 == ~E_5~0); 106226#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106261#L304 assume !(1 == ~m_pc~0); 105905#L304-2 is_master_triggered_~__retres1~0#1 := 0; 105805#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105806#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105756#L755 assume !(0 != activate_threads_~tmp~1#1); 105757#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105713#L323 assume !(1 == ~t1_pc~0); 105714#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105774#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105775#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105789#L763 assume !(0 != activate_threads_~tmp___0~0#1); 106318#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105777#L342 assume !(1 == ~t2_pc~0); 105779#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105911#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105912#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106160#L771 assume !(0 != activate_threads_~tmp___1~0#1); 106219#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106110#L361 assume !(1 == ~t3_pc~0); 106111#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106137#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105729#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105730#L779 assume !(0 != activate_threads_~tmp___2~0#1); 105792#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105793#L380 assume !(1 == ~t4_pc~0); 106109#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 106237#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105874#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105875#L787 assume !(0 != activate_threads_~tmp___3~0#1); 106148#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105852#L399 assume !(1 == ~t5_pc~0); 105853#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 105995#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106000#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105987#L795 assume !(0 != activate_threads_~tmp___4~0#1); 105988#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106298#L679 assume !(1 == ~M_E~0); 106069#L679-2 assume !(1 == ~T1_E~0); 105924#L684-1 assume !(1 == ~T2_E~0); 105925#L689-1 assume !(1 == ~T3_E~0); 106118#L694-1 assume !(1 == ~T4_E~0); 106116#L699-1 assume !(1 == ~T5_E~0); 106117#L704-1 assume !(1 == ~E_M~0); 106097#L709-1 assume !(1 == ~E_1~0); 106028#L714-1 assume !(1 == ~E_2~0); 106029#L719-1 assume !(1 == ~E_3~0); 106215#L724-1 assume !(1 == ~E_4~0); 105816#L729-1 assume !(1 == ~E_5~0); 105817#L734-1 assume { :end_inline_reset_delta_events } true; 106303#L940-2 [2024-11-13 14:11:47,650 INFO L747 eck$LassoCheckResult]: Loop: 106303#L940-2 assume !false; 110077#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110073#L586-1 assume !false; 110071#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 109941#L464 assume !(0 == ~m_st~0); 109942#L468 assume !(0 == ~t1_st~0); 109944#L472 assume !(0 == ~t2_st~0); 109939#L476 assume !(0 == ~t3_st~0); 109940#L480 assume !(0 == ~t4_st~0); 109943#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 109945#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 110674#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 110673#L511 assume !(0 != eval_~tmp~0#1); 105891#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106177#L611-3 assume !(0 == ~M_E~0); 105818#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 105819#L616-3 assume !(0 == ~T2_E~0); 105814#L621-3 assume !(0 == ~T3_E~0); 105763#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105764#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106344#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 110662#L641-3 assume !(0 == ~E_1~0); 110661#L646-3 assume !(0 == ~E_2~0); 110660#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 110659#L656-3 assume !(0 == ~E_4~0); 110658#L661-3 assume !(0 == ~E_5~0); 110657#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110656#L304-21 assume 1 == ~m_pc~0; 110655#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 110653#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110652#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110651#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110650#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110648#L323-21 assume !(1 == ~t1_pc~0); 110646#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 110644#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110642#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110640#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 110639#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110638#L342-21 assume !(1 == ~t2_pc~0); 110636#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 110634#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106067#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106068#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 105855#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105856#L361-21 assume 1 == ~t3_pc~0; 106308#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 106322#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110563#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110562#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105761#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105762#L380-21 assume !(1 == ~t4_pc~0); 105824#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 105825#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105896#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106214#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106149#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105970#L399-21 assume 1 == ~t5_pc~0; 105945#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 105835#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106135#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106136#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106294#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105754#L679-3 assume !(1 == ~M_E~0); 105755#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108059#L684-3 assume !(1 == ~T2_E~0); 105705#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105706#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110339#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110338#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 110337#L709-3 assume !(1 == ~E_1~0); 110336#L714-3 assume !(1 == ~E_2~0); 110335#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110334#L724-3 assume !(1 == ~E_4~0); 110333#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110332#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105771#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 105772#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106090#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 106128#L959 assume !(0 == start_simulation_~tmp~3#1); 110108#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 110106#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 110096#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 110245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 110087#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110084#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 110082#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 110080#L972 assume !(0 != start_simulation_~tmp___0~1#1); 106303#L940-2 [2024-11-13 14:11:47,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:47,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2024-11-13 14:11:47,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:47,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602084877] [2024-11-13 14:11:47,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:47,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:47,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:47,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:47,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:47,703 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:47,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:47,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1911049954, now seen corresponding path program 1 times [2024-11-13 14:11:47,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:47,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500291763] [2024-11-13 14:11:47,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:47,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:47,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:47,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:47,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:47,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500291763] [2024-11-13 14:11:47,832 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500291763] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:47,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:47,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:47,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800779313] [2024-11-13 14:11:47,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:47,833 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:47,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:47,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:47,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:47,833 INFO L87 Difference]: Start difference. First operand 4972 states and 6853 transitions. cyclomatic complexity: 1885 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:48,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:48,113 INFO L93 Difference]: Finished difference Result 5050 states and 6882 transitions. [2024-11-13 14:11:48,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5050 states and 6882 transitions. [2024-11-13 14:11:48,142 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4950 [2024-11-13 14:11:48,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5050 states to 5050 states and 6882 transitions. [2024-11-13 14:11:48,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5050 [2024-11-13 14:11:48,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5050 [2024-11-13 14:11:48,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5050 states and 6882 transitions. [2024-11-13 14:11:48,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:48,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5050 states and 6882 transitions. [2024-11-13 14:11:48,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5050 states and 6882 transitions. [2024-11-13 14:11:48,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5050 to 5050. [2024-11-13 14:11:48,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5050 states, 5050 states have (on average 1.3627722772277229) internal successors, (6882), 5049 states have internal predecessors, (6882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:48,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5050 states to 5050 states and 6882 transitions. [2024-11-13 14:11:48,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5050 states and 6882 transitions. [2024-11-13 14:11:48,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:48,303 INFO L424 stractBuchiCegarLoop]: Abstraction has 5050 states and 6882 transitions. [2024-11-13 14:11:48,303 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 14:11:48,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5050 states and 6882 transitions. [2024-11-13 14:11:48,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4950 [2024-11-13 14:11:48,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:48,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:48,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:48,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:48,326 INFO L745 eck$LassoCheckResult]: Stem: 116075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 116076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 116185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116172#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 116173#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116017#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116018#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115993#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115994#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116251#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116099#L611 assume !(0 == ~M_E~0); 116100#L611-2 assume !(0 == ~T1_E~0); 116267#L616-1 assume !(0 == ~T2_E~0); 116268#L621-1 assume !(0 == ~T3_E~0); 115864#L626-1 assume !(0 == ~T4_E~0); 115865#L631-1 assume !(0 == ~T5_E~0); 116057#L636-1 assume !(0 == ~E_M~0); 115913#L641-1 assume !(0 == ~E_1~0); 115914#L646-1 assume !(0 == ~E_2~0); 116072#L651-1 assume !(0 == ~E_3~0); 116315#L656-1 assume !(0 == ~E_4~0); 116249#L661-1 assume !(0 == ~E_5~0); 116250#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116286#L304 assume !(1 == ~m_pc~0); 115939#L304-2 is_master_triggered_~__retres1~0#1 := 0; 115835#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115836#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115791#L755 assume !(0 != activate_threads_~tmp~1#1); 115792#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115745#L323 assume !(1 == ~t1_pc~0); 115746#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115805#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115806#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 115821#L763 assume !(0 != activate_threads_~tmp___0~0#1); 116354#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115814#L342 assume !(1 == ~t2_pc~0); 115816#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115943#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116187#L771 assume !(0 != activate_threads_~tmp___1~0#1); 116243#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116139#L361 assume !(1 == ~t3_pc~0); 116140#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116166#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115759#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115760#L779 assume !(0 != activate_threads_~tmp___2~0#1); 115826#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115827#L380 assume !(1 == ~t4_pc~0); 116138#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116259#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115909#L787 assume !(0 != activate_threads_~tmp___3~0#1); 116175#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115882#L399 assume !(1 == ~t5_pc~0); 115883#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 116028#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116032#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116019#L795 assume !(0 != activate_threads_~tmp___4~0#1); 116020#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116326#L679 assume !(1 == ~M_E~0); 116098#L679-2 assume !(1 == ~T1_E~0); 115956#L684-1 assume !(1 == ~T2_E~0); 115957#L689-1 assume !(1 == ~T3_E~0); 116147#L694-1 assume !(1 == ~T4_E~0); 116145#L699-1 assume !(1 == ~T5_E~0); 116146#L704-1 assume !(1 == ~E_M~0); 116125#L709-1 assume !(1 == ~E_1~0); 116059#L714-1 assume !(1 == ~E_2~0); 116060#L719-1 assume !(1 == ~E_3~0); 116239#L724-1 assume !(1 == ~E_4~0); 115846#L729-1 assume !(1 == ~E_5~0); 115847#L734-1 assume { :end_inline_reset_delta_events } true; 116333#L940-2 [2024-11-13 14:11:48,326 INFO L747 eck$LassoCheckResult]: Loop: 116333#L940-2 assume !false; 119223#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119220#L586-1 assume !false; 119219#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119202#L464 assume !(0 == ~m_st~0); 119203#L468 assume !(0 == ~t1_st~0); 119205#L472 assume !(0 == ~t2_st~0); 119200#L476 assume !(0 == ~t3_st~0); 119201#L480 assume !(0 == ~t4_st~0); 119204#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 119206#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119148#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 119149#L511 assume !(0 != eval_~tmp~0#1); 119484#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119482#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119480#L611-3 assume !(0 == ~M_E~0); 119478#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119476#L616-3 assume !(0 == ~T2_E~0); 119474#L621-3 assume !(0 == ~T3_E~0); 119472#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119470#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119468#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119466#L641-3 assume !(0 == ~E_1~0); 119464#L646-3 assume !(0 == ~E_2~0); 119462#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119460#L656-3 assume !(0 == ~E_4~0); 119458#L661-3 assume !(0 == ~E_5~0); 119456#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119454#L304-21 assume !(1 == ~m_pc~0); 119451#L304-23 is_master_triggered_~__retres1~0#1 := 0; 119448#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119446#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119444#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119442#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119440#L323-21 assume !(1 == ~t1_pc~0); 119438#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 119436#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119434#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119432#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 119430#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119427#L342-21 assume !(1 == ~t2_pc~0); 119421#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 119418#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119415#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119412#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 119408#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119403#L361-21 assume !(1 == ~t3_pc~0); 119399#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 119393#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119387#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119380#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 119374#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119370#L380-21 assume !(1 == ~t4_pc~0); 119365#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 119360#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119354#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119349#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 119345#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119341#L399-21 assume 1 == ~t5_pc~0; 119337#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 119330#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119325#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119320#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119316#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119277#L679-3 assume !(1 == ~M_E~0); 119273#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119271#L684-3 assume !(1 == ~T2_E~0); 119269#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119267#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119264#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119262#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119260#L709-3 assume !(1 == ~E_1~0); 119258#L714-3 assume !(1 == ~E_2~0); 119248#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119240#L724-3 assume !(1 == ~E_4~0); 119234#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119229#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119215#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119208#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119207#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 116161#L959 assume !(0 == start_simulation_~tmp~3#1); 116162#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119256#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119246#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119238#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 119232#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119228#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119225#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 119224#L972 assume !(0 != start_simulation_~tmp___0~1#1); 116333#L940-2 [2024-11-13 14:11:48,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:48,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2024-11-13 14:11:48,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:48,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837911359] [2024-11-13 14:11:48,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:48,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:48,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:48,346 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:48,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:48,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:48,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:48,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1374608600, now seen corresponding path program 1 times [2024-11-13 14:11:48,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:48,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422914321] [2024-11-13 14:11:48,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:48,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:48,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:48,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:48,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:48,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422914321] [2024-11-13 14:11:48,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422914321] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:48,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:48,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 14:11:48,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183443848] [2024-11-13 14:11:48,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:48,500 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:48,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:48,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 14:11:48,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 14:11:48,501 INFO L87 Difference]: Start difference. First operand 5050 states and 6882 transitions. cyclomatic complexity: 1836 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:48,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:48,771 INFO L93 Difference]: Finished difference Result 5275 states and 7107 transitions. [2024-11-13 14:11:48,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5275 states and 7107 transitions. [2024-11-13 14:11:48,793 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5172 [2024-11-13 14:11:48,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5275 states to 5275 states and 7107 transitions. [2024-11-13 14:11:48,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5275 [2024-11-13 14:11:48,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5275 [2024-11-13 14:11:48,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5275 states and 7107 transitions. [2024-11-13 14:11:48,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:48,829 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5275 states and 7107 transitions. [2024-11-13 14:11:48,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5275 states and 7107 transitions. [2024-11-13 14:11:48,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5275 to 5275. [2024-11-13 14:11:48,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5275 states, 5275 states have (on average 1.347298578199052) internal successors, (7107), 5274 states have internal predecessors, (7107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:48,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5275 states to 5275 states and 7107 transitions. [2024-11-13 14:11:48,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5275 states and 7107 transitions. [2024-11-13 14:11:48,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 14:11:48,978 INFO L424 stractBuchiCegarLoop]: Abstraction has 5275 states and 7107 transitions. [2024-11-13 14:11:48,978 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 14:11:48,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5275 states and 7107 transitions. [2024-11-13 14:11:48,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5172 [2024-11-13 14:11:48,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:48,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:48,995 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:48,995 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:48,996 INFO L745 eck$LassoCheckResult]: Stem: 126409#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 126410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 126520#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126521#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126506#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 126507#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126347#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126348#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126326#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126327#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126595#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126435#L611 assume !(0 == ~M_E~0); 126436#L611-2 assume !(0 == ~T1_E~0); 126612#L616-1 assume !(0 == ~T2_E~0); 126613#L621-1 assume !(0 == ~T3_E~0); 126198#L626-1 assume !(0 == ~T4_E~0); 126199#L631-1 assume !(0 == ~T5_E~0); 126389#L636-1 assume !(0 == ~E_M~0); 126247#L641-1 assume !(0 == ~E_1~0); 126248#L646-1 assume !(0 == ~E_2~0); 126405#L651-1 assume !(0 == ~E_3~0); 126653#L656-1 assume !(0 == ~E_4~0); 126593#L661-1 assume !(0 == ~E_5~0); 126594#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126627#L304 assume !(1 == ~m_pc~0); 126274#L304-2 is_master_triggered_~__retres1~0#1 := 0; 126168#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126169#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126124#L755 assume !(0 != activate_threads_~tmp~1#1); 126125#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126080#L323 assume !(1 == ~t1_pc~0); 126081#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126137#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126138#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126154#L763 assume !(0 != activate_threads_~tmp___0~0#1); 126683#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126147#L342 assume !(1 == ~t2_pc~0); 126149#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126276#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126277#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 126523#L771 assume !(0 != activate_threads_~tmp___1~0#1); 126586#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126474#L361 assume !(1 == ~t3_pc~0); 126475#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126499#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 126093#L779 assume !(0 != activate_threads_~tmp___2~0#1); 126159#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126160#L380 assume !(1 == ~t4_pc~0); 126473#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126605#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 126243#L787 assume !(0 != activate_threads_~tmp___3~0#1); 126508#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126216#L399 assume !(1 == ~t5_pc~0); 126217#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 126358#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126363#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 126349#L795 assume !(0 != activate_threads_~tmp___4~0#1); 126350#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126665#L679 assume !(1 == ~M_E~0); 126434#L679-2 assume !(1 == ~T1_E~0); 126289#L684-1 assume !(1 == ~T2_E~0); 126290#L689-1 assume !(1 == ~T3_E~0); 126482#L694-1 assume !(1 == ~T4_E~0); 126480#L699-1 assume !(1 == ~T5_E~0); 126481#L704-1 assume !(1 == ~E_M~0); 126461#L709-1 assume !(1 == ~E_1~0); 126394#L714-1 assume !(1 == ~E_2~0); 126395#L719-1 assume !(1 == ~E_3~0); 126581#L724-1 assume !(1 == ~E_4~0); 126179#L729-1 assume !(1 == ~E_5~0); 126180#L734-1 assume { :end_inline_reset_delta_events } true; 126669#L940-2 [2024-11-13 14:11:48,996 INFO L747 eck$LassoCheckResult]: Loop: 126669#L940-2 assume !false; 128503#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128497#L586-1 assume !false; 128495#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 128493#L464 assume !(0 == ~m_st~0); 128491#L468 assume !(0 == ~t1_st~0); 128489#L472 assume !(0 == ~t2_st~0); 128487#L476 assume !(0 == ~t3_st~0); 128485#L480 assume !(0 == ~t4_st~0); 128482#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 128479#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 128477#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 128475#L511 assume !(0 != eval_~tmp~0#1); 128473#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128471#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128469#L611-3 assume !(0 == ~M_E~0); 128467#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 128465#L616-3 assume !(0 == ~T2_E~0); 128463#L621-3 assume !(0 == ~T3_E~0); 128461#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128459#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128457#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 128455#L641-3 assume !(0 == ~E_1~0); 128453#L646-3 assume !(0 == ~E_2~0); 128451#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 128449#L656-3 assume !(0 == ~E_4~0); 128447#L661-3 assume !(0 == ~E_5~0); 128445#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128443#L304-21 assume !(1 == ~m_pc~0); 128441#L304-23 is_master_triggered_~__retres1~0#1 := 0; 128437#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128433#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 128429#L755-21 assume !(0 != activate_threads_~tmp~1#1); 128425#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128423#L323-21 assume !(1 == ~t1_pc~0); 128421#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 128419#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128417#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 128415#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 128413#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128411#L342-21 assume !(1 == ~t2_pc~0); 128407#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 128405#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128403#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 128401#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 128399#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128397#L361-21 assume !(1 == ~t3_pc~0); 128395#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 128391#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128387#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 128383#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 128379#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128377#L380-21 assume !(1 == ~t4_pc~0); 128375#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 128373#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128371#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 128369#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 128367#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128365#L399-21 assume 1 == ~t5_pc~0; 128363#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 128359#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128357#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 128355#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 128353#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128351#L679-3 assume !(1 == ~M_E~0); 126892#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126886#L684-3 assume !(1 == ~T2_E~0); 126879#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126880#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130488#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 130486#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 126857#L709-3 assume !(1 == ~E_1~0); 126851#L714-3 assume !(1 == ~E_2~0); 126844#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 126845#L724-3 assume !(1 == ~E_4~0); 130473#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 126827#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 126828#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 126803#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 126804#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 126794#L959 assume !(0 == start_simulation_~tmp~3#1); 126795#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 128611#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 128604#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 128602#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 128601#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128598#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128596#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 128594#L972 assume !(0 != start_simulation_~tmp___0~1#1); 126669#L940-2 [2024-11-13 14:11:48,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:48,997 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2024-11-13 14:11:48,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:48,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689753005] [2024-11-13 14:11:48,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:48,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:49,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,011 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:49,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,030 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:49,030 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:49,030 INFO L85 PathProgramCache]: Analyzing trace with hash -113691350, now seen corresponding path program 1 times [2024-11-13 14:11:49,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:49,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492630389] [2024-11-13 14:11:49,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:49,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:49,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:49,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:49,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:49,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1492630389] [2024-11-13 14:11:49,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1492630389] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:49,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:49,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:49,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695590040] [2024-11-13 14:11:49,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:49,088 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:49,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:49,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:49,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:49,089 INFO L87 Difference]: Start difference. First operand 5275 states and 7107 transitions. cyclomatic complexity: 1836 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:49,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:49,183 INFO L93 Difference]: Finished difference Result 9727 states and 12917 transitions. [2024-11-13 14:11:49,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9727 states and 12917 transitions. [2024-11-13 14:11:49,224 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9604 [2024-11-13 14:11:49,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9727 states to 9727 states and 12917 transitions. [2024-11-13 14:11:49,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9727 [2024-11-13 14:11:49,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9727 [2024-11-13 14:11:49,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9727 states and 12917 transitions. [2024-11-13 14:11:49,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 14:11:49,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9727 states and 12917 transitions. [2024-11-13 14:11:49,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9727 states and 12917 transitions. [2024-11-13 14:11:49,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9727 to 9245. [2024-11-13 14:11:49,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9245 states, 9245 states have (on average 1.331638723634397) internal successors, (12311), 9244 states have internal predecessors, (12311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:49,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9245 states to 9245 states and 12311 transitions. [2024-11-13 14:11:49,433 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9245 states and 12311 transitions. [2024-11-13 14:11:49,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:49,434 INFO L424 stractBuchiCegarLoop]: Abstraction has 9245 states and 12311 transitions. [2024-11-13 14:11:49,434 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 14:11:49,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9245 states and 12311 transitions. [2024-11-13 14:11:49,463 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9122 [2024-11-13 14:11:49,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:49,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:49,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:49,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:49,465 INFO L745 eck$LassoCheckResult]: Stem: 141419#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 141420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 141538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 141539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141522#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 141523#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 141359#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141360#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141337#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141338#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141614#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 141447#L611 assume !(0 == ~M_E~0); 141448#L611-2 assume !(0 == ~T1_E~0); 141629#L616-1 assume !(0 == ~T2_E~0); 141630#L621-1 assume !(0 == ~T3_E~0); 141201#L626-1 assume !(0 == ~T4_E~0); 141202#L631-1 assume !(0 == ~T5_E~0); 141398#L636-1 assume !(0 == ~E_M~0); 141254#L641-1 assume !(0 == ~E_1~0); 141255#L646-1 assume !(0 == ~E_2~0); 141416#L651-1 assume !(0 == ~E_3~0); 141675#L656-1 assume !(0 == ~E_4~0); 141612#L661-1 assume !(0 == ~E_5~0); 141613#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141647#L304 assume !(1 == ~m_pc~0); 141280#L304-2 is_master_triggered_~__retres1~0#1 := 0; 141178#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141179#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 141127#L755 assume !(0 != activate_threads_~tmp~1#1); 141128#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141084#L323 assume !(1 == ~t1_pc~0); 141085#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 141145#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 141162#L763 assume !(0 != activate_threads_~tmp___0~0#1); 141706#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141149#L342 assume !(1 == ~t2_pc~0); 141151#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 141288#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141289#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141542#L771 assume !(0 != activate_threads_~tmp___1~0#1); 141608#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141486#L361 assume !(1 == ~t3_pc~0); 141487#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 141514#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141100#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 141101#L779 assume !(0 != activate_threads_~tmp___2~0#1); 141165#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141166#L380 assume !(1 == ~t4_pc~0); 141485#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141621#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141249#L787 assume !(0 != activate_threads_~tmp___3~0#1); 141526#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141225#L399 assume !(1 == ~t5_pc~0); 141226#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 141370#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141361#L795 assume !(0 != activate_threads_~tmp___4~0#1); 141362#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141687#L679 assume !(1 == ~M_E~0); 141445#L679-2 assume !(1 == ~T1_E~0); 141301#L684-1 assume !(1 == ~T2_E~0); 141302#L689-1 assume !(1 == ~T3_E~0); 141496#L694-1 assume !(1 == ~T4_E~0); 141494#L699-1 assume !(1 == ~T5_E~0); 141495#L704-1 assume !(1 == ~E_M~0); 141473#L709-1 assume !(1 == ~E_1~0); 141402#L714-1 assume !(1 == ~E_2~0); 141403#L719-1 assume !(1 == ~E_3~0); 141603#L724-1 assume !(1 == ~E_4~0); 141189#L729-1 assume !(1 == ~E_5~0); 141190#L734-1 assume { :end_inline_reset_delta_events } true; 141691#L940-2 [2024-11-13 14:11:49,465 INFO L747 eck$LassoCheckResult]: Loop: 141691#L940-2 assume !false; 145342#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145325#L586-1 assume !false; 145314#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 145312#L464 assume !(0 == ~m_st~0); 145313#L468 assume !(0 == ~t1_st~0); 145849#L472 assume !(0 == ~t2_st~0); 145846#L476 assume !(0 == ~t3_st~0); 145847#L480 assume !(0 == ~t4_st~0); 145848#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 145850#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 145840#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 145841#L511 assume !(0 != eval_~tmp~0#1); 147882#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 147873#L611-3 assume !(0 == ~M_E~0); 145749#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 145748#L616-3 assume !(0 == ~T2_E~0); 145747#L621-3 assume !(0 == ~T3_E~0); 145745#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 145744#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 145743#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 145742#L641-3 assume !(0 == ~E_1~0); 145740#L646-3 assume !(0 == ~E_2~0); 145738#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 145736#L656-3 assume !(0 == ~E_4~0); 145732#L661-3 assume !(0 == ~E_5~0); 145730#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145728#L304-21 assume 1 == ~m_pc~0; 145726#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 145723#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145719#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 145714#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 145708#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145704#L323-21 assume !(1 == ~t1_pc~0); 145699#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 145692#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145683#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145676#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 145669#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145661#L342-21 assume !(1 == ~t2_pc~0); 145654#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 145649#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145645#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145644#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 145643#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145642#L361-21 assume !(1 == ~t3_pc~0); 145640#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 145638#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145636#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 145635#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 145633#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145631#L380-21 assume !(1 == ~t4_pc~0); 145629#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 145626#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145624#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 145622#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 145620#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145618#L399-21 assume 1 == ~t5_pc~0; 145616#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145613#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145610#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 145608#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 145606#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145585#L679-3 assume !(1 == ~M_E~0); 145577#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 145571#L684-3 assume !(1 == ~T2_E~0); 145564#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145557#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 145550#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 145545#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 145540#L709-3 assume !(1 == ~E_1~0); 145531#L714-3 assume !(1 == ~E_2~0); 145492#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 145483#L724-3 assume !(1 == ~E_4~0); 145475#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 145468#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 145458#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 145452#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 145446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 145364#L959 assume !(0 == start_simulation_~tmp~3#1); 145361#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 145358#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 145356#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 145354#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 145352#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145350#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145347#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 145345#L972 assume !(0 != start_simulation_~tmp___0~1#1); 141691#L940-2 [2024-11-13 14:11:49,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:49,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 9 times [2024-11-13 14:11:49,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:49,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774547520] [2024-11-13 14:11:49,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:49,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:49,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,479 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:49,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:49,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:49,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1891826535, now seen corresponding path program 1 times [2024-11-13 14:11:49,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:49,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159261923] [2024-11-13 14:11:49,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:49,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:49,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,513 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:49,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:49,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:49,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:49,538 INFO L85 PathProgramCache]: Analyzing trace with hash -504824925, now seen corresponding path program 1 times [2024-11-13 14:11:49,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:49,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10176167] [2024-11-13 14:11:49,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:49,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:49,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:49,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:49,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:49,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10176167] [2024-11-13 14:11:49,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10176167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:49,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:49,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:49,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156124152] [2024-11-13 14:11:49,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:51,467 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 14:11:51,468 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 14:11:51,468 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 14:11:51,468 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 14:11:51,468 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 14:11:51,469 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:51,469 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 14:11:51,469 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 14:11:51,469 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration23_Loop [2024-11-13 14:11:51,469 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 14:11:51,470 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 14:11:51,497 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,526 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,544 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,558 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,594 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,604 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,690 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:51,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,489 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 14:11:52,490 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 14:11:52,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,495 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,530 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 14:11:52,531 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 14:11:52,531 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,556 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 14:11:52,556 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 14:11:52,575 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 14:11:52,576 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,576 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,578 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 14:11:52,582 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 14:11:52,582 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,619 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 14:11:52,619 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 14:11:52,638 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 14:11:52,639 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,639 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,641 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 14:11:52,645 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 14:11:52,645 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,665 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 14:11:52,665 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 14:11:52,686 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 14:11:52,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,688 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,690 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 14:11:52,692 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 14:11:52,692 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,711 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 14:11:52,712 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 14:11:52,731 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 14:11:52,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,733 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 14:11:52,736 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 14:11:52,736 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,772 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 14:11:52,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:52,775 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:52,777 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 14:11:52,778 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 14:11:52,778 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 14:11:52,799 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 14:11:52,818 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 14:11:52,818 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 14:11:52,818 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 14:11:52,818 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 14:11:52,818 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 14:11:52,819 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 14:11:52,819 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:52,819 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 14:11:52,819 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 14:11:52,819 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration23_Loop [2024-11-13 14:11:52,819 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 14:11:52,819 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 14:11:52,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,857 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,903 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,977 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:52,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,040 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,043 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,045 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,050 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,060 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,062 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 14:11:53,676 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 14:11:53,680 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 14:11:53,681 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,683 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 14:11:53,688 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 14:11:53,704 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 14:11:53,704 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 14:11:53,704 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 14:11:53,704 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 14:11:53,705 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 14:11:53,712 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 14:11:53,712 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 14:11:53,716 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 14:11:53,734 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-13 14:11:53,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,736 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,738 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 14:11:53,739 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 14:11:53,753 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 14:11:53,753 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 14:11:53,753 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 14:11:53,753 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 14:11:53,753 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 14:11:53,755 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 14:11:53,756 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 14:11:53,761 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 14:11:53,778 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 14:11:53,778 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,778 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,780 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 14:11:53,784 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 14:11:53,798 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 14:11:53,798 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 14:11:53,798 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 14:11:53,798 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 14:11:53,799 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 14:11:53,799 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 14:11:53,799 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 14:11:53,802 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 14:11:53,819 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 14:11:53,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,821 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,824 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 14:11:53,824 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 14:11:53,839 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 14:11:53,839 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 14:11:53,839 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 14:11:53,839 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 14:11:53,839 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 14:11:53,840 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 14:11:53,840 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 14:11:53,845 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 14:11:53,862 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 14:11:53,862 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,863 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,864 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 14:11:53,869 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 14:11:53,883 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 14:11:53,883 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 14:11:53,883 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 14:11:53,883 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 14:11:53,883 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 14:11:53,884 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 14:11:53,884 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 14:11:53,888 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 14:11:53,892 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 14:11:53,895 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 14:11:53,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 14:11:53,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 14:11:53,902 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 14:11:53,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 14:11:53,904 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 14:11:53,905 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 14:11:53,905 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 14:11:53,905 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2024-11-13 14:11:53,923 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 14:11:53,925 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 14:11:53,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:54,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:54,005 INFO L255 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 14:11:54,008 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 14:11:54,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:54,190 INFO L255 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 14:11:54,192 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 14:11:54,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:54,446 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 14:11:54,448 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 9245 states and 12311 transitions. cyclomatic complexity: 3070 Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:54,784 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 9245 states and 12311 transitions. cyclomatic complexity: 3070. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 25315 states and 33926 transitions. Complement of second has 5 states. [2024-11-13 14:11:54,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 14:11:54,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:54,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 729 transitions. [2024-11-13 14:11:54,792 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 729 transitions. Stem has 73 letters. Loop has 89 letters. [2024-11-13 14:11:54,797 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 14:11:54,799 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 729 transitions. Stem has 162 letters. Loop has 89 letters. [2024-11-13 14:11:54,800 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 14:11:54,801 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 729 transitions. Stem has 73 letters. Loop has 178 letters. [2024-11-13 14:11:54,804 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 14:11:54,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25315 states and 33926 transitions. [2024-11-13 14:11:54,954 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 14:11:54,992 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17040 [2024-11-13 14:11:55,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25315 states to 25291 states and 33902 transitions. [2024-11-13 14:11:55,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17228 [2024-11-13 14:11:55,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17273 [2024-11-13 14:11:55,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25291 states and 33902 transitions. [2024-11-13 14:11:55,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:11:55,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25291 states and 33902 transitions. [2024-11-13 14:11:55,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25291 states and 33902 transitions. [2024-11-13 14:11:55,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25291 to 25222. [2024-11-13 14:11:55,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25222 states, 25222 states have (on average 1.3396637855840139) internal successors, (33789), 25221 states have internal predecessors, (33789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:55,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25222 states to 25222 states and 33789 transitions. [2024-11-13 14:11:55,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25222 states and 33789 transitions. [2024-11-13 14:11:55,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:55,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:55,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:55,560 INFO L87 Difference]: Start difference. First operand 25222 states and 33789 transitions. Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:55,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:55,733 INFO L93 Difference]: Finished difference Result 26668 states and 35487 transitions. [2024-11-13 14:11:55,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26668 states and 35487 transitions. [2024-11-13 14:11:55,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18004 [2024-11-13 14:11:56,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26668 states to 26668 states and 35487 transitions. [2024-11-13 14:11:56,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18168 [2024-11-13 14:11:56,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18168 [2024-11-13 14:11:56,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26668 states and 35487 transitions. [2024-11-13 14:11:56,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:11:56,095 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26668 states and 35487 transitions. [2024-11-13 14:11:56,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26668 states and 35487 transitions. [2024-11-13 14:11:56,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26668 to 25222. [2024-11-13 14:11:56,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25222 states, 25222 states have (on average 1.3349060344144001) internal successors, (33669), 25221 states have internal predecessors, (33669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:56,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25222 states to 25222 states and 33669 transitions. [2024-11-13 14:11:56,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25222 states and 33669 transitions. [2024-11-13 14:11:56,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:56,426 INFO L424 stractBuchiCegarLoop]: Abstraction has 25222 states and 33669 transitions. [2024-11-13 14:11:56,426 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 14:11:56,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25222 states and 33669 transitions. [2024-11-13 14:11:56,517 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17040 [2024-11-13 14:11:56,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:56,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:56,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:56,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:56,520 INFO L745 eck$LassoCheckResult]: Stem: 228658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 228659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 228881#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 228882#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 228851#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 228852#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 228543#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 228544#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 228498#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 228499#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 229019#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 228708#L611 assume !(0 == ~M_E~0); 228709#L611-2 assume !(0 == ~T1_E~0); 229053#L616-1 assume !(0 == ~T2_E~0); 229054#L621-1 assume !(0 == ~T3_E~0); 228242#L626-1 assume !(0 == ~T4_E~0); 228243#L631-1 assume !(0 == ~T5_E~0); 228618#L636-1 assume !(0 == ~E_M~0); 228337#L641-1 assume !(0 == ~E_1~0); 228338#L646-1 assume !(0 == ~E_2~0); 228650#L651-1 assume !(0 == ~E_3~0); 229143#L656-1 assume !(0 == ~E_4~0); 229017#L661-1 assume !(0 == ~E_5~0); 229018#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229089#L304 assume !(1 == ~m_pc~0); 228388#L304-2 is_master_triggered_~__retres1~0#1 := 0; 228389#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 228553#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 228123#L755 assume !(0 != activate_threads_~tmp~1#1); 228124#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 228050#L323 assume !(1 == ~t1_pc~0); 228051#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 228153#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 228154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 228177#L763 assume !(0 != activate_threads_~tmp___0~0#1); 229219#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 228156#L342 assume !(1 == ~t2_pc~0); 228158#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 228402#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 228403#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 228885#L771 assume !(0 != activate_threads_~tmp___1~0#1); 229012#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228780#L361 assume !(1 == ~t3_pc~0); 228781#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 228833#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 229283#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 229134#L779 assume !(0 != activate_threads_~tmp___2~0#1); 228182#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 228183#L380 assume !(1 == ~t4_pc~0); 228779#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 229039#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 228327#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 228328#L787 assume !(0 != activate_threads_~tmp___3~0#1); 228858#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 228289#L399 assume !(1 == ~t5_pc~0); 228290#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 228563#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 228575#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 228545#L795 assume !(0 != activate_threads_~tmp___4~0#1); 228546#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 229170#L679 assume !(1 == ~M_E~0); 228705#L679-2 assume !(1 == ~T1_E~0); 228426#L684-1 assume !(1 == ~T2_E~0); 228427#L689-1 assume !(1 == ~T3_E~0); 228794#L694-1 assume !(1 == ~T4_E~0); 228792#L699-1 assume !(1 == ~T5_E~0); 228793#L704-1 assume !(1 == ~E_M~0); 228759#L709-1 assume !(1 == ~E_1~0); 228625#L714-1 assume !(1 == ~E_2~0); 228626#L719-1 assume !(1 == ~E_3~0); 229001#L724-1 assume !(1 == ~E_4~0); 228220#L729-1 assume !(1 == ~E_5~0); 228221#L734-1 assume { :end_inline_reset_delta_events } true; 229180#L940-2 assume !false; 231815#L941 [2024-11-13 14:11:56,521 INFO L747 eck$LassoCheckResult]: Loop: 231815#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 243795#L586-1 assume !false; 243793#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 243791#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 243789#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 243787#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 243785#L511 assume 0 != eval_~tmp~0#1; 243782#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 243764#L519 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 243765#L68 assume 0 == ~m_pc~0; 244723#L104 assume !false; 244722#L80 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244721#L304-3 assume !(1 == ~m_pc~0); 244720#L304-5 is_master_triggered_~__retres1~0#1 := 0; 244718#L315-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244716#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 244714#L755-3 assume !(0 != activate_threads_~tmp~1#1); 244710#L755-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244708#L323-3 assume !(1 == ~t1_pc~0); 244706#L323-5 is_transmit1_triggered_~__retres1~1#1 := 0; 244704#L334-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244702#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244700#L763-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244698#L763-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244677#L342-3 assume !(1 == ~t2_pc~0); 244672#L342-5 is_transmit2_triggered_~__retres1~2#1 := 0; 244668#L353-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244664#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244661#L771-3 assume !(0 != activate_threads_~tmp___1~0#1); 244657#L771-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244655#L361-3 assume !(1 == ~t3_pc~0); 244653#L361-5 is_transmit3_triggered_~__retres1~3#1 := 0; 244649#L372-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244646#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244643#L779-3 assume !(0 != activate_threads_~tmp___2~0#1); 244640#L779-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244637#L380-3 assume !(1 == ~t4_pc~0); 244635#L380-5 is_transmit4_triggered_~__retres1~4#1 := 0; 244633#L391-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244630#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244627#L787-3 assume !(0 != activate_threads_~tmp___3~0#1); 244624#L787-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244621#L399-3 assume 1 == ~t5_pc~0; 244619#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 244612#L410-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244610#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244590#L795-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 244587#L795-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 241530#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 241523#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 239663#L519-2 havoc eval_~tmp_ndt_1~0#1; 239660#L516-1 assume !(0 == ~t1_st~0); 239661#L530-1 assume !(0 == ~t2_st~0); 242055#L544-1 assume !(0 == ~t3_st~0); 242051#L558-1 assume !(0 == ~t4_st~0); 239799#L572-1 assume !(0 == ~t5_st~0); 239795#L586-1 assume !false; 239793#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 239791#L464 assume !(0 == ~m_st~0); 239783#L468 assume !(0 == ~t1_st~0); 239784#L472 assume !(0 == ~t2_st~0); 239780#L476 assume !(0 == ~t3_st~0); 239781#L480 assume !(0 == ~t4_st~0); 239782#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 239785#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 242144#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 242142#L511 assume !(0 != eval_~tmp~0#1); 242140#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 242138#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 242136#L611-3 assume !(0 == ~M_E~0); 242132#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 242130#L616-3 assume !(0 == ~T2_E~0); 242128#L621-3 assume !(0 == ~T3_E~0); 242126#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 242123#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 242121#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 242119#L641-3 assume !(0 == ~E_1~0); 242117#L646-3 assume !(0 == ~E_2~0); 242115#L651-3 assume !(0 == ~E_3~0); 242111#L656-3 assume !(0 == ~E_4~0); 242109#L661-3 assume !(0 == ~E_5~0); 242106#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242104#L304-21 assume 1 == ~m_pc~0; 242101#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 242099#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242097#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 242093#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 242091#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242089#L323-21 assume !(1 == ~t1_pc~0); 242088#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 242085#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 242084#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 242083#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 242082#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242079#L342-21 assume !(1 == ~t2_pc~0); 242076#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 242074#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242073#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 242070#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 242069#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242068#L361-21 assume 1 == ~t3_pc~0; 242067#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 242066#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242064#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242060#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 242057#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242053#L380-21 assume !(1 == ~t4_pc~0); 242049#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 242048#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242047#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242045#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 242044#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 242043#L399-21 assume 1 == ~t5_pc~0; 242042#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 242039#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242038#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 242037#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 242036#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242035#L679-3 assume !(1 == ~M_E~0); 241689#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 242033#L684-3 assume !(1 == ~T2_E~0); 242032#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 242030#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 242028#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 242025#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 242023#L709-3 assume !(1 == ~E_1~0); 242020#L714-3 assume !(1 == ~E_2~0); 242018#L719-3 assume !(1 == ~E_3~0); 242015#L724-3 assume !(1 == ~E_4~0); 242012#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 242009#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 242006#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 242003#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 241999#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 241992#L959 assume !(0 == start_simulation_~tmp~3#1); 241993#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 243948#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 243946#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 243944#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 243941#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 243939#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243937#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 243935#L972 assume !(0 != start_simulation_~tmp___0~1#1); 243933#L940-2 assume !false; 231815#L941 [2024-11-13 14:11:56,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:56,521 INFO L85 PathProgramCache]: Analyzing trace with hash 959436206, now seen corresponding path program 1 times [2024-11-13 14:11:56,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:56,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574131872] [2024-11-13 14:11:56,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:56,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:56,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:56,536 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:56,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:56,552 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:56,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:56,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1905263643, now seen corresponding path program 1 times [2024-11-13 14:11:56,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:56,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314799453] [2024-11-13 14:11:56,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:56,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:56,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:56,613 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:56,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:56,613 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314799453] [2024-11-13 14:11:56,613 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [314799453] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:56,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:56,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:56,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927454793] [2024-11-13 14:11:56,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:56,614 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:56,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:56,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:56,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:56,615 INFO L87 Difference]: Start difference. First operand 25222 states and 33669 transitions. cyclomatic complexity: 8459 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:56,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:56,949 INFO L93 Difference]: Finished difference Result 47678 states and 63173 transitions. [2024-11-13 14:11:56,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47678 states and 63173 transitions. [2024-11-13 14:11:57,168 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30268 [2024-11-13 14:11:57,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47678 states to 47678 states and 63173 transitions. [2024-11-13 14:11:57,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32570 [2024-11-13 14:11:57,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32570 [2024-11-13 14:11:57,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47678 states and 63173 transitions. [2024-11-13 14:11:57,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:11:57,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47678 states and 63173 transitions. [2024-11-13 14:11:57,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47678 states and 63173 transitions. [2024-11-13 14:11:58,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47678 to 46286. [2024-11-13 14:11:58,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46286 states, 46286 states have (on average 1.3267294646329344) internal successors, (61409), 46285 states have internal predecessors, (61409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:58,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46286 states to 46286 states and 61409 transitions. [2024-11-13 14:11:58,472 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46286 states and 61409 transitions. [2024-11-13 14:11:58,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:58,476 INFO L424 stractBuchiCegarLoop]: Abstraction has 46286 states and 61409 transitions. [2024-11-13 14:11:58,476 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 14:11:58,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46286 states and 61409 transitions. [2024-11-13 14:11:58,827 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29340 [2024-11-13 14:11:58,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:58,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:58,830 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:58,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:58,831 INFO L745 eck$LassoCheckResult]: Stem: 301555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 301556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 301781#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 301782#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 301752#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 301753#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 301875#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307813#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307812#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307811#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 307810#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307809#L611 assume !(0 == ~M_E~0); 307808#L611-2 assume !(0 == ~T1_E~0); 307807#L616-1 assume !(0 == ~T2_E~0); 307806#L621-1 assume !(0 == ~T3_E~0); 307805#L626-1 assume !(0 == ~T4_E~0); 301929#L631-1 assume !(0 == ~T5_E~0); 301930#L636-1 assume !(0 == ~E_M~0); 301251#L641-1 assume !(0 == ~E_1~0); 301252#L646-1 assume !(0 == ~E_2~0); 302147#L651-1 assume !(0 == ~E_3~0); 302077#L656-1 assume !(0 == ~E_4~0); 301939#L661-1 assume !(0 == ~E_5~0); 301940#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 302186#L304 assume !(1 == ~m_pc~0); 302187#L304-2 is_master_triggered_~__retres1~0#1 := 0; 301112#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 301113#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 301039#L755 assume !(0 != activate_threads_~tmp~1#1); 301040#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 300962#L323 assume !(1 == ~t1_pc~0); 300963#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 301059#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 301060#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302148#L763 assume !(0 != activate_threads_~tmp___0~0#1); 302150#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 301075#L342 assume !(1 == ~t2_pc~0); 301077#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 301308#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 301786#L771 assume !(0 != activate_threads_~tmp___1~0#1); 301931#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 301686#L361 assume !(1 == ~t3_pc~0); 301687#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 301736#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 302106#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 302068#L779 assume !(0 != activate_threads_~tmp___2~0#1); 301095#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301096#L380 assume !(1 == ~t4_pc~0); 301684#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 306809#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306807#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 306805#L787 assume !(0 != activate_threads_~tmp___3~0#1); 306803#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306801#L399 assume !(1 == ~t5_pc~0); 306798#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 306794#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 306792#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 306790#L795 assume !(0 != activate_threads_~tmp___4~0#1); 306788#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306785#L679 assume !(1 == ~M_E~0); 301606#L679-2 assume !(1 == ~T1_E~0); 301332#L684-1 assume !(1 == ~T2_E~0); 301333#L689-1 assume !(1 == ~T3_E~0); 301700#L694-1 assume !(1 == ~T4_E~0); 306563#L699-1 assume !(1 == ~T5_E~0); 306561#L704-1 assume !(1 == ~E_M~0); 301657#L709-1 assume !(1 == ~E_1~0); 301527#L714-1 assume !(1 == ~E_2~0); 301528#L719-1 assume !(1 == ~E_3~0); 301916#L724-1 assume !(1 == ~E_4~0); 305801#L729-1 assume !(1 == ~E_5~0); 305797#L734-1 assume { :end_inline_reset_delta_events } true; 305794#L940-2 assume !false; 305795#L941 [2024-11-13 14:11:58,832 INFO L747 eck$LassoCheckResult]: Loop: 305795#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 321031#L586-1 assume !false; 321024#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 321020#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 319417#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 319412#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 319410#L511 assume 0 != eval_~tmp~0#1; 319408#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 319404#L519 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 319405#L68 assume 0 == ~m_pc~0; 319701#L104 assume !false; 319699#L80 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319697#L304-3 assume !(1 == ~m_pc~0); 319693#L304-5 is_master_triggered_~__retres1~0#1 := 0; 319691#L315-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319688#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 319686#L755-3 assume !(0 != activate_threads_~tmp~1#1); 319683#L755-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319682#L323-3 assume !(1 == ~t1_pc~0); 319679#L323-5 is_transmit1_triggered_~__retres1~1#1 := 0; 319678#L334-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319677#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319675#L763-3 assume !(0 != activate_threads_~tmp___0~0#1); 319673#L763-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319671#L342-3 assume !(1 == ~t2_pc~0); 319669#L342-5 is_transmit2_triggered_~__retres1~2#1 := 0; 319666#L353-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319662#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319659#L771-3 assume !(0 != activate_threads_~tmp___1~0#1); 319656#L771-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319650#L361-3 assume !(1 == ~t3_pc~0); 319648#L361-5 is_transmit3_triggered_~__retres1~3#1 := 0; 319646#L372-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 319643#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319641#L779-3 assume !(0 != activate_threads_~tmp___2~0#1); 319638#L779-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319637#L380-3 assume !(1 == ~t4_pc~0); 319636#L380-5 is_transmit4_triggered_~__retres1~4#1 := 0; 319634#L391-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319632#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 319631#L787-3 assume !(0 != activate_threads_~tmp___3~0#1); 319630#L787-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319629#L399-3 assume !(1 == ~t5_pc~0); 319626#L399-5 is_transmit5_triggered_~__retres1~5#1 := 0; 319623#L410-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319621#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 319619#L795-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 319614#L795-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 319612#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 319610#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 319400#L519-2 havoc eval_~tmp_ndt_1~0#1; 319396#L516-1 assume !(0 == ~t1_st~0); 319392#L530-1 assume !(0 == ~t2_st~0); 319393#L544-1 assume !(0 == ~t3_st~0); 320599#L558-1 assume !(0 == ~t4_st~0); 320594#L572-1 assume !(0 == ~t5_st~0); 320592#L586-1 assume !false; 320591#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 320590#L464 assume !(0 == ~m_st~0); 320587#L468 assume !(0 == ~t1_st~0); 320586#L472 assume !(0 == ~t2_st~0); 320585#L476 assume !(0 == ~t3_st~0); 320584#L480 assume !(0 == ~t4_st~0); 320582#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 320581#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 320579#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 320577#L511 assume !(0 != eval_~tmp~0#1); 320575#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 320574#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 320572#L611-3 assume !(0 == ~M_E~0); 320570#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 320568#L616-3 assume !(0 == ~T2_E~0); 320566#L621-3 assume !(0 == ~T3_E~0); 320563#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 320561#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 320558#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 320556#L641-3 assume !(0 == ~E_1~0); 320554#L646-3 assume !(0 == ~E_2~0); 320552#L651-3 assume !(0 == ~E_3~0); 320550#L656-3 assume !(0 == ~E_4~0); 320548#L661-3 assume !(0 == ~E_5~0); 320544#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320542#L304-21 assume 1 == ~m_pc~0; 320539#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 320537#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 320534#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320531#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 320529#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320527#L323-21 assume !(1 == ~t1_pc~0); 320525#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 320523#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 320521#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 320518#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 320516#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320513#L342-21 assume !(1 == ~t2_pc~0); 320510#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 320508#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320506#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320504#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 320503#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320502#L361-21 assume 1 == ~t3_pc~0; 320500#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 320499#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320498#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 320346#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 320344#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320341#L380-21 assume !(1 == ~t4_pc~0); 320339#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 320337#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320335#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 320332#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 320330#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 320328#L399-21 assume !(1 == ~t5_pc~0); 320325#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 320323#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 320321#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 320319#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 320317#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320315#L679-3 assume !(1 == ~M_E~0); 318493#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 320312#L684-3 assume !(1 == ~T2_E~0); 320247#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 320243#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 320237#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 320233#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 320230#L709-3 assume !(1 == ~E_1~0); 320226#L714-3 assume !(1 == ~E_2~0); 320221#L719-3 assume !(1 == ~E_3~0); 318612#L724-3 assume !(1 == ~E_4~0); 318610#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 318608#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 318606#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 318604#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 318602#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 318599#L959 assume !(0 == start_simulation_~tmp~3#1); 318600#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 321065#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 321063#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 321060#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 321058#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 321056#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321054#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 321052#L972 assume !(0 != start_simulation_~tmp___0~1#1); 321050#L940-2 assume !false; 305795#L941 [2024-11-13 14:11:58,833 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:58,833 INFO L85 PathProgramCache]: Analyzing trace with hash 466810032, now seen corresponding path program 1 times [2024-11-13 14:11:58,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:58,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254880817] [2024-11-13 14:11:58,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:58,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:58,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:59,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:59,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:59,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254880817] [2024-11-13 14:11:59,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254880817] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:59,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:59,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:59,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574173184] [2024-11-13 14:11:59,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:59,006 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 14:11:59,006 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:59,007 INFO L85 PathProgramCache]: Analyzing trace with hash -606703583, now seen corresponding path program 1 times [2024-11-13 14:11:59,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:59,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534303625] [2024-11-13 14:11:59,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:59,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:59,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:11:59,055 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:11:59,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:11:59,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534303625] [2024-11-13 14:11:59,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534303625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:11:59,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:11:59,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:11:59,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214253500] [2024-11-13 14:11:59,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:11:59,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 14:11:59,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:11:59,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:11:59,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:11:59,057 INFO L87 Difference]: Start difference. First operand 46286 states and 61409 transitions. cyclomatic complexity: 15147 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:59,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:11:59,140 INFO L93 Difference]: Finished difference Result 28075 states and 37174 transitions. [2024-11-13 14:11:59,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28075 states and 37174 transitions. [2024-11-13 14:11:59,240 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19064 [2024-11-13 14:11:59,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28075 states to 28075 states and 37174 transitions. [2024-11-13 14:11:59,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19213 [2024-11-13 14:11:59,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19213 [2024-11-13 14:11:59,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28075 states and 37174 transitions. [2024-11-13 14:11:59,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:11:59,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28075 states and 37174 transitions. [2024-11-13 14:11:59,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28075 states and 37174 transitions. [2024-11-13 14:11:59,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28075 to 28075. [2024-11-13 14:11:59,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28075 states, 28075 states have (on average 1.3240961709706145) internal successors, (37174), 28074 states have internal predecessors, (37174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:11:59,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28075 states to 28075 states and 37174 transitions. [2024-11-13 14:11:59,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28075 states and 37174 transitions. [2024-11-13 14:11:59,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:11:59,727 INFO L424 stractBuchiCegarLoop]: Abstraction has 28075 states and 37174 transitions. [2024-11-13 14:11:59,727 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 14:11:59,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28075 states and 37174 transitions. [2024-11-13 14:11:59,930 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19064 [2024-11-13 14:11:59,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:11:59,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:11:59,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:59,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:11:59,931 INFO L745 eck$LassoCheckResult]: Stem: 375928#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 375929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 376150#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 376151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 376119#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 376120#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 375807#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 375808#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 375768#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 375769#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 376300#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 375981#L611 assume !(0 == ~M_E~0); 375982#L611-2 assume !(0 == ~T1_E~0); 376331#L616-1 assume !(0 == ~T2_E~0); 376332#L621-1 assume !(0 == ~T3_E~0); 375516#L626-1 assume !(0 == ~T4_E~0); 375517#L631-1 assume !(0 == ~T5_E~0); 375883#L636-1 assume !(0 == ~E_M~0); 375610#L641-1 assume !(0 == ~E_1~0); 375611#L646-1 assume !(0 == ~E_2~0); 375918#L651-1 assume !(0 == ~E_3~0); 376423#L656-1 assume !(0 == ~E_4~0); 376298#L661-1 assume !(0 == ~E_5~0); 376299#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 376364#L304 assume !(1 == ~m_pc~0); 375660#L304-2 is_master_triggered_~__retres1~0#1 := 0; 375661#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 375817#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 375397#L755 assume !(0 != activate_threads_~tmp~1#1); 375398#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 375324#L323 assume !(1 == ~t1_pc~0); 375325#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 375427#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 375428#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 375451#L763 assume !(0 != activate_threads_~tmp___0~0#1); 376480#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 375431#L342 assume !(1 == ~t2_pc~0); 375433#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 375676#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 375677#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 376154#L771 assume !(0 != activate_threads_~tmp___1~0#1); 376291#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 376050#L361 assume !(1 == ~t3_pc~0); 376051#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 376101#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 376536#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 376414#L779 assume !(0 != activate_threads_~tmp___2~0#1); 375456#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 375457#L380 assume !(1 == ~t4_pc~0); 376049#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 376316#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 375600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 375601#L787 assume !(0 != activate_threads_~tmp___3~0#1); 376128#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375561#L399 assume !(1 == ~t5_pc~0); 375562#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 375826#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 375839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 375809#L795 assume !(0 != activate_threads_~tmp___4~0#1); 375810#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376443#L679 assume !(1 == ~M_E~0); 375977#L679-2 assume !(1 == ~T1_E~0); 375699#L684-1 assume !(1 == ~T2_E~0); 375700#L689-1 assume !(1 == ~T3_E~0); 376065#L694-1 assume !(1 == ~T4_E~0); 376063#L699-1 assume !(1 == ~T5_E~0); 376064#L704-1 assume !(1 == ~E_M~0); 376029#L709-1 assume !(1 == ~E_1~0); 375890#L714-1 assume !(1 == ~E_2~0); 375891#L719-1 assume !(1 == ~E_3~0); 376276#L724-1 assume !(1 == ~E_4~0); 375494#L729-1 assume !(1 == ~E_5~0); 375495#L734-1 assume { :end_inline_reset_delta_events } true; 376448#L940-2 assume !false; 384613#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 395814#L586-1 [2024-11-13 14:11:59,932 INFO L747 eck$LassoCheckResult]: Loop: 395814#L586-1 assume !false; 395812#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 395810#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 395808#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 395805#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 395804#L511 assume 0 != eval_~tmp~0#1; 395803#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 395801#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 395800#L519-2 havoc eval_~tmp_ndt_1~0#1; 395799#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 395797#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 395794#L533-2 havoc eval_~tmp_ndt_2~0#1; 395786#L530-1 assume !(0 == ~t2_st~0); 395782#L544-1 assume !(0 == ~t3_st~0); 395778#L558-1 assume !(0 == ~t4_st~0); 395779#L572-1 assume !(0 == ~t5_st~0); 395814#L586-1 [2024-11-13 14:11:59,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:59,934 INFO L85 PathProgramCache]: Analyzing trace with hash -322248345, now seen corresponding path program 1 times [2024-11-13 14:11:59,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:59,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134588072] [2024-11-13 14:11:59,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:59,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:59,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:59,947 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:59,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:59,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:59,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:59,966 INFO L85 PathProgramCache]: Analyzing trace with hash -910539952, now seen corresponding path program 1 times [2024-11-13 14:11:59,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:59,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058172421] [2024-11-13 14:11:59,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:59,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:59,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:59,971 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:11:59,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:11:59,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:11:59,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:11:59,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1381079222, now seen corresponding path program 1 times [2024-11-13 14:11:59,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:11:59,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390572818] [2024-11-13 14:11:59,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:11:59,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:11:59,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:12:00,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:12:00,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:12:00,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390572818] [2024-11-13 14:12:00,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390572818] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:12:00,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:12:00,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:12:00,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636012727] [2024-11-13 14:12:00,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:12:00,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:12:00,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:12:00,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:12:00,105 INFO L87 Difference]: Start difference. First operand 28075 states and 37174 transitions. cyclomatic complexity: 9111 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:00,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:12:00,269 INFO L93 Difference]: Finished difference Result 49384 states and 64977 transitions. [2024-11-13 14:12:00,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49384 states and 64977 transitions. [2024-11-13 14:12:00,586 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33190 [2024-11-13 14:12:00,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49384 states to 49384 states and 64977 transitions. [2024-11-13 14:12:00,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33403 [2024-11-13 14:12:00,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33403 [2024-11-13 14:12:00,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49384 states and 64977 transitions. [2024-11-13 14:12:00,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:12:00,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49384 states and 64977 transitions. [2024-11-13 14:12:00,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49384 states and 64977 transitions. [2024-11-13 14:12:01,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49384 to 49384. [2024-11-13 14:12:01,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49384 states, 49384 states have (on average 1.315750040498947) internal successors, (64977), 49383 states have internal predecessors, (64977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:01,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49384 states to 49384 states and 64977 transitions. [2024-11-13 14:12:01,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49384 states and 64977 transitions. [2024-11-13 14:12:01,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:12:01,649 INFO L424 stractBuchiCegarLoop]: Abstraction has 49384 states and 64977 transitions. [2024-11-13 14:12:01,649 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 14:12:01,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49384 states and 64977 transitions. [2024-11-13 14:12:01,884 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33190 [2024-11-13 14:12:01,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:12:01,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:12:01,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:01,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:01,887 INFO L745 eck$LassoCheckResult]: Stem: 453384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 453385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 453607#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453608#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 453581#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 453582#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 453274#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 453275#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 453234#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 453235#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 453759#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 453433#L611 assume !(0 == ~M_E~0); 453434#L611-2 assume !(0 == ~T1_E~0); 453790#L616-1 assume !(0 == ~T2_E~0); 453791#L621-1 assume !(0 == ~T3_E~0); 452985#L626-1 assume !(0 == ~T4_E~0); 452986#L631-1 assume !(0 == ~T5_E~0); 453345#L636-1 assume !(0 == ~E_M~0); 453081#L641-1 assume !(0 == ~E_1~0); 453082#L646-1 assume !(0 == ~E_2~0); 453377#L651-1 assume !(0 == ~E_3~0); 453889#L656-1 assume !(0 == ~E_4~0); 453757#L661-1 assume !(0 == ~E_5~0); 453758#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453833#L304 assume !(1 == ~m_pc~0); 453132#L304-2 is_master_triggered_~__retres1~0#1 := 0; 453133#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 453284#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 452864#L755 assume !(0 != activate_threads_~tmp~1#1); 452865#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452791#L323 assume !(1 == ~t1_pc~0); 452792#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 452895#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 452896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 452919#L763 assume !(0 != activate_threads_~tmp___0~0#1); 453961#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 452899#L342 assume !(1 == ~t2_pc~0); 452901#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 453144#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453145#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 453613#L771 assume !(0 != activate_threads_~tmp___1~0#1); 453751#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 453513#L361 assume !(1 == ~t3_pc~0); 453514#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 453566#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454001#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 453878#L779 assume !(0 != activate_threads_~tmp___2~0#1); 452924#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 452925#L380 assume !(1 == ~t4_pc~0); 453512#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 453775#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453071#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 453072#L787 assume !(0 != activate_threads_~tmp___3~0#1); 453584#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453032#L399 assume !(1 == ~t5_pc~0); 453033#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 453293#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453304#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453276#L795 assume !(0 != activate_threads_~tmp___4~0#1); 453277#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 453910#L679 assume !(1 == ~M_E~0); 453430#L679-2 assume !(1 == ~T1_E~0); 453167#L684-1 assume !(1 == ~T2_E~0); 453168#L689-1 assume !(1 == ~T3_E~0); 453527#L694-1 assume !(1 == ~T4_E~0); 453525#L699-1 assume !(1 == ~T5_E~0); 453526#L704-1 assume !(1 == ~E_M~0); 453490#L709-1 assume !(1 == ~E_1~0); 453352#L714-1 assume !(1 == ~E_2~0); 453353#L719-1 assume !(1 == ~E_3~0); 453740#L724-1 assume !(1 == ~E_4~0); 452962#L729-1 assume !(1 == ~E_5~0); 452963#L734-1 assume { :end_inline_reset_delta_events } true; 453919#L940-2 assume !false; 469319#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 501528#L586-1 [2024-11-13 14:12:01,887 INFO L747 eck$LassoCheckResult]: Loop: 501528#L586-1 assume !false; 501527#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 501526#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 501525#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 453652#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 453653#L511 assume 0 != eval_~tmp~0#1; 497514#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 497512#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 497510#L519-2 havoc eval_~tmp_ndt_1~0#1; 497508#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 497506#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 497505#L533-2 havoc eval_~tmp_ndt_2~0#1; 491974#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 491972#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 491973#L547-2 havoc eval_~tmp_ndt_3~0#1; 495690#L544-1 assume !(0 == ~t3_st~0); 495687#L558-1 assume !(0 == ~t4_st~0); 495688#L572-1 assume !(0 == ~t5_st~0); 501528#L586-1 [2024-11-13 14:12:01,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:01,892 INFO L85 PathProgramCache]: Analyzing trace with hash -322248345, now seen corresponding path program 2 times [2024-11-13 14:12:01,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:01,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426205942] [2024-11-13 14:12:01,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:01,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:01,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:01,908 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:01,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:01,928 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:01,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:01,929 INFO L85 PathProgramCache]: Analyzing trace with hash 190041983, now seen corresponding path program 1 times [2024-11-13 14:12:01,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:01,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469839824] [2024-11-13 14:12:01,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:01,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:01,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:01,933 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:01,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:01,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:01,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:01,939 INFO L85 PathProgramCache]: Analyzing trace with hash -882154651, now seen corresponding path program 1 times [2024-11-13 14:12:01,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:01,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135041136] [2024-11-13 14:12:01,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:01,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:01,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:12:02,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:12:02,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:12:02,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135041136] [2024-11-13 14:12:02,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135041136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:12:02,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:12:02,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:12:02,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092027653] [2024-11-13 14:12:02,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:12:02,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:12:02,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:12:02,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:12:02,319 INFO L87 Difference]: Start difference. First operand 49384 states and 64977 transitions. cyclomatic complexity: 15605 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:02,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:12:02,870 INFO L93 Difference]: Finished difference Result 91698 states and 120375 transitions. [2024-11-13 14:12:02,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91698 states and 120375 transitions. [2024-11-13 14:12:03,300 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 61728 [2024-11-13 14:12:03,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91698 states to 91698 states and 120375 transitions. [2024-11-13 14:12:03,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62069 [2024-11-13 14:12:03,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62069 [2024-11-13 14:12:03,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91698 states and 120375 transitions. [2024-11-13 14:12:03,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:12:03,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91698 states and 120375 transitions. [2024-11-13 14:12:03,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91698 states and 120375 transitions. [2024-11-13 14:12:04,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91698 to 89418. [2024-11-13 14:12:04,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89418 states, 89418 states have (on average 1.315339193450983) internal successors, (117615), 89417 states have internal predecessors, (117615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:05,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89418 states to 89418 states and 117615 transitions. [2024-11-13 14:12:05,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89418 states and 117615 transitions. [2024-11-13 14:12:05,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:12:05,097 INFO L424 stractBuchiCegarLoop]: Abstraction has 89418 states and 117615 transitions. [2024-11-13 14:12:05,097 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 14:12:05,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89418 states and 117615 transitions. [2024-11-13 14:12:05,459 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 60208 [2024-11-13 14:12:05,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:12:05,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:12:05,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:05,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:05,466 INFO L745 eck$LassoCheckResult]: Stem: 594496#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 594497#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 594747#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 594748#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 594709#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 594710#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 594376#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 594377#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 594335#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 594336#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 594912#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 594547#L611 assume !(0 == ~M_E~0); 594548#L611-2 assume !(0 == ~T1_E~0); 594949#L616-1 assume !(0 == ~T2_E~0); 594950#L621-1 assume !(0 == ~T3_E~0); 594086#L626-1 assume !(0 == ~T4_E~0); 594087#L631-1 assume !(0 == ~T5_E~0); 594457#L636-1 assume !(0 == ~E_M~0); 594177#L641-1 assume !(0 == ~E_1~0); 594178#L646-1 assume !(0 == ~E_2~0); 594485#L651-1 assume !(0 == ~E_3~0); 595061#L656-1 assume !(0 == ~E_4~0); 594910#L661-1 assume !(0 == ~E_5~0); 594911#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 594998#L304 assume !(1 == ~m_pc~0); 594232#L304-2 is_master_triggered_~__retres1~0#1 := 0; 594034#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 594035#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 593964#L755 assume !(0 != activate_threads_~tmp~1#1); 593965#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 593887#L323 assume !(1 == ~t1_pc~0); 593888#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 593985#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 593986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 594010#L763 assume !(0 != activate_threads_~tmp___0~0#1); 595143#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 594001#L342 assume !(1 == ~t2_pc~0); 594003#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 594236#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 594237#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 594751#L771 assume !(0 != activate_threads_~tmp___1~0#1); 594901#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 594632#L361 assume !(1 == ~t3_pc~0); 594633#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 594691#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 595093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 595050#L779 assume !(0 != activate_threads_~tmp___2~0#1); 594019#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 594020#L380 assume !(1 == ~t4_pc~0); 594630#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 594936#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 594169#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 594170#L787 assume !(0 != activate_threads_~tmp___3~0#1); 594717#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594120#L399 assume !(1 == ~t5_pc~0); 594121#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 594396#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 594406#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 594378#L795 assume !(0 != activate_threads_~tmp___4~0#1); 594379#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 595084#L679 assume !(1 == ~M_E~0); 594546#L679-2 assume !(1 == ~T1_E~0); 594260#L684-1 assume !(1 == ~T2_E~0); 594261#L689-1 assume !(1 == ~T3_E~0); 594649#L694-1 assume !(1 == ~T4_E~0); 594647#L699-1 assume !(1 == ~T5_E~0); 594648#L704-1 assume !(1 == ~E_M~0); 594605#L709-1 assume !(1 == ~E_1~0); 594464#L714-1 assume !(1 == ~E_2~0); 594465#L719-1 assume !(1 == ~E_3~0); 594886#L724-1 assume !(1 == ~E_4~0); 594050#L729-1 assume !(1 == ~E_5~0); 594051#L734-1 assume { :end_inline_reset_delta_events } true; 595098#L940-2 assume !false; 608347#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 653580#L586-1 [2024-11-13 14:12:05,467 INFO L747 eck$LassoCheckResult]: Loop: 653580#L586-1 assume !false; 653577#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 653576#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 653575#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 653574#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 653572#L511 assume 0 != eval_~tmp~0#1; 653570#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 653567#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 653568#L519-2 havoc eval_~tmp_ndt_1~0#1; 653641#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 653639#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 653637#L533-2 havoc eval_~tmp_ndt_2~0#1; 653626#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 652642#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 653617#L547-2 havoc eval_~tmp_ndt_3~0#1; 653623#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 652721#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 653606#L561-2 havoc eval_~tmp_ndt_4~0#1; 653597#L558-1 assume !(0 == ~t4_st~0); 653587#L572-1 assume !(0 == ~t5_st~0); 653580#L586-1 [2024-11-13 14:12:05,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:05,467 INFO L85 PathProgramCache]: Analyzing trace with hash -322248345, now seen corresponding path program 3 times [2024-11-13 14:12:05,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:05,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964438003] [2024-11-13 14:12:05,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:05,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:05,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:05,502 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:05,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:05,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:05,522 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:05,523 INFO L85 PathProgramCache]: Analyzing trace with hash 2072437968, now seen corresponding path program 1 times [2024-11-13 14:12:05,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:05,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94636980] [2024-11-13 14:12:05,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:05,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:05,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:05,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:05,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:05,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:05,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:05,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1811343562, now seen corresponding path program 1 times [2024-11-13 14:12:05,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:05,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052370478] [2024-11-13 14:12:05,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:05,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:05,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:12:05,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:12:05,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:12:05,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052370478] [2024-11-13 14:12:05,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052370478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:12:05,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:12:05,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 14:12:05,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715131219] [2024-11-13 14:12:05,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:12:05,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:12:05,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:12:05,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:12:05,880 INFO L87 Difference]: Start difference. First operand 89418 states and 117615 transitions. cyclomatic complexity: 28209 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:06,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:12:06,459 INFO L93 Difference]: Finished difference Result 121357 states and 159390 transitions. [2024-11-13 14:12:06,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121357 states and 159390 transitions. [2024-11-13 14:12:07,095 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 82034 [2024-11-13 14:12:07,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121357 states to 121357 states and 159390 transitions. [2024-11-13 14:12:07,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82375 [2024-11-13 14:12:07,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82375 [2024-11-13 14:12:07,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121357 states and 159390 transitions. [2024-11-13 14:12:07,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:12:07,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121357 states and 159390 transitions. [2024-11-13 14:12:07,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121357 states and 159390 transitions. [2024-11-13 14:12:08,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121357 to 120037. [2024-11-13 14:12:08,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120037 states, 120037 states have (on average 1.3138448978231712) internal successors, (157710), 120036 states have internal predecessors, (157710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:09,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120037 states to 120037 states and 157710 transitions. [2024-11-13 14:12:09,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120037 states and 157710 transitions. [2024-11-13 14:12:09,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:12:09,344 INFO L424 stractBuchiCegarLoop]: Abstraction has 120037 states and 157710 transitions. [2024-11-13 14:12:09,344 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 14:12:09,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120037 states and 157710 transitions. [2024-11-13 14:12:09,694 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 81154 [2024-11-13 14:12:09,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:12:09,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:12:09,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:09,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:09,696 INFO L745 eck$LassoCheckResult]: Stem: 805284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 805285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 805530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 805531#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 805496#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 805497#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 805161#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 805162#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 805121#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 805122#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 805708#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 805335#L611 assume !(0 == ~M_E~0); 805336#L611-2 assume !(0 == ~T1_E~0); 805752#L616-1 assume !(0 == ~T2_E~0); 805753#L621-1 assume !(0 == ~T3_E~0); 804872#L626-1 assume !(0 == ~T4_E~0); 804873#L631-1 assume !(0 == ~T5_E~0); 805249#L636-1 assume !(0 == ~E_M~0); 804963#L641-1 assume !(0 == ~E_1~0); 804964#L646-1 assume !(0 == ~E_2~0); 805276#L651-1 assume !(0 == ~E_3~0); 805889#L656-1 assume !(0 == ~E_4~0); 805706#L661-1 assume !(0 == ~E_5~0); 805707#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 805804#L304 assume !(1 == ~m_pc~0); 805017#L304-2 is_master_triggered_~__retres1~0#1 := 0; 804817#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804818#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 804747#L755 assume !(0 != activate_threads_~tmp~1#1); 804748#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804666#L323 assume !(1 == ~t1_pc~0); 804667#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 804768#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804769#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 804793#L763 assume !(0 != activate_threads_~tmp___0~0#1); 805988#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 804784#L342 assume !(1 == ~t2_pc~0); 804786#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 805021#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 805022#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 805536#L771 assume !(0 != activate_threads_~tmp___1~0#1); 805696#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 805422#L361 assume !(1 == ~t3_pc~0); 805423#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 805477#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 805922#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 805874#L779 assume !(0 != activate_threads_~tmp___2~0#1); 804802#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804803#L380 assume !(1 == ~t4_pc~0); 805419#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 805732#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804955#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 804956#L787 assume !(0 != activate_threads_~tmp___3~0#1); 805502#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804907#L399 assume !(1 == ~t5_pc~0); 804908#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 805186#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 805198#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 805163#L795 assume !(0 != activate_threads_~tmp___4~0#1); 805164#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805915#L679 assume !(1 == ~M_E~0); 805334#L679-2 assume !(1 == ~T1_E~0); 805046#L684-1 assume !(1 == ~T2_E~0); 805047#L689-1 assume !(1 == ~T3_E~0); 805439#L694-1 assume !(1 == ~T4_E~0); 805437#L699-1 assume !(1 == ~T5_E~0); 805438#L704-1 assume !(1 == ~E_M~0); 805395#L709-1 assume !(1 == ~E_1~0); 805252#L714-1 assume !(1 == ~E_2~0); 805253#L719-1 assume !(1 == ~E_3~0); 805677#L724-1 assume !(1 == ~E_4~0); 804836#L729-1 assume !(1 == ~E_5~0); 804837#L734-1 assume { :end_inline_reset_delta_events } true; 805928#L940-2 assume !false; 824812#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 858972#L586-1 [2024-11-13 14:12:09,696 INFO L747 eck$LassoCheckResult]: Loop: 858972#L586-1 assume !false; 858969#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 858967#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 858965#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 858960#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 858958#L511 assume 0 != eval_~tmp~0#1; 858955#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 858952#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 858950#L519-2 havoc eval_~tmp_ndt_1~0#1; 858948#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 858945#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 858946#L533-2 havoc eval_~tmp_ndt_2~0#1; 859241#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 859231#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 859221#L547-2 havoc eval_~tmp_ndt_3~0#1; 859071#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 859069#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 859067#L561-2 havoc eval_~tmp_ndt_4~0#1; 859053#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 858996#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 858985#L575-2 havoc eval_~tmp_ndt_5~0#1; 858975#L572-1 assume !(0 == ~t5_st~0); 858972#L586-1 [2024-11-13 14:12:09,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:09,697 INFO L85 PathProgramCache]: Analyzing trace with hash -322248345, now seen corresponding path program 4 times [2024-11-13 14:12:09,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:09,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549757646] [2024-11-13 14:12:09,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:09,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:09,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:09,709 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:09,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:09,724 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:09,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:09,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1257345857, now seen corresponding path program 1 times [2024-11-13 14:12:09,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:09,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426215212] [2024-11-13 14:12:09,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:09,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:09,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:09,729 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:09,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:09,733 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:09,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:09,734 INFO L85 PathProgramCache]: Analyzing trace with hash -1244815963, now seen corresponding path program 1 times [2024-11-13 14:12:09,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:09,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913369530] [2024-11-13 14:12:09,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:09,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:09,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 14:12:10,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 14:12:10,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 14:12:10,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913369530] [2024-11-13 14:12:10,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913369530] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 14:12:10,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 14:12:10,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 14:12:10,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496347029] [2024-11-13 14:12:10,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 14:12:10,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 14:12:10,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 14:12:10,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 14:12:10,120 INFO L87 Difference]: Start difference. First operand 120037 states and 157710 transitions. cyclomatic complexity: 37685 Second operand has 3 states, 2 states have (on average 48.5) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:10,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 14:12:10,992 INFO L93 Difference]: Finished difference Result 207548 states and 272162 transitions. [2024-11-13 14:12:10,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207548 states and 272162 transitions. [2024-11-13 14:12:11,906 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 140684 [2024-11-13 14:12:12,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207548 states to 207548 states and 272162 transitions. [2024-11-13 14:12:12,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141281 [2024-11-13 14:12:12,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141281 [2024-11-13 14:12:12,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 207548 states and 272162 transitions. [2024-11-13 14:12:12,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 14:12:12,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 207548 states and 272162 transitions. [2024-11-13 14:12:13,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207548 states and 272162 transitions. [2024-11-13 14:12:14,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207548 to 205340. [2024-11-13 14:12:14,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 205340 states, 205340 states have (on average 1.3146683549235414) internal successors, (269954), 205339 states have internal predecessors, (269954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 14:12:15,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205340 states to 205340 states and 269954 transitions. [2024-11-13 14:12:15,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 205340 states and 269954 transitions. [2024-11-13 14:12:15,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 14:12:15,349 INFO L424 stractBuchiCegarLoop]: Abstraction has 205340 states and 269954 transitions. [2024-11-13 14:12:15,349 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 14:12:15,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 205340 states and 269954 transitions. [2024-11-13 14:12:16,248 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 139212 [2024-11-13 14:12:16,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 14:12:16,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 14:12:16,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:16,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 14:12:16,250 INFO L745 eck$LassoCheckResult]: Stem: 1132872#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1132873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1133119#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1133120#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1133082#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1133083#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1132750#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1132751#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1132710#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1132711#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1133290#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1132922#L611 assume !(0 == ~M_E~0); 1132923#L611-2 assume !(0 == ~T1_E~0); 1133327#L616-1 assume !(0 == ~T2_E~0); 1133328#L621-1 assume !(0 == ~T3_E~0); 1132463#L626-1 assume !(0 == ~T4_E~0); 1132464#L631-1 assume !(0 == ~T5_E~0); 1132836#L636-1 assume !(0 == ~E_M~0); 1132553#L641-1 assume !(0 == ~E_1~0); 1132554#L646-1 assume !(0 == ~E_2~0); 1132864#L651-1 assume !(0 == ~E_3~0); 1133444#L656-1 assume !(0 == ~E_4~0); 1133288#L661-1 assume !(0 == ~E_5~0); 1133289#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133375#L304 assume !(1 == ~m_pc~0); 1132610#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1132411#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1132412#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1132340#L755 assume !(0 != activate_threads_~tmp~1#1); 1132341#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1132263#L323 assume !(1 == ~t1_pc~0); 1132264#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1132361#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132362#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1132385#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1133533#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1132377#L342 assume !(1 == ~t2_pc~0); 1132379#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1132613#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1132614#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1133125#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1133279#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1133009#L361 assume !(1 == ~t3_pc~0); 1133010#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1133066#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133480#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1133431#L779 assume !(0 != activate_threads_~tmp___2~0#1); 1132394#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1132395#L380 assume !(1 == ~t4_pc~0); 1133005#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1133312#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1132545#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1132546#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1133092#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1132497#L399 assume !(1 == ~t5_pc~0); 1132498#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1132772#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1132785#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1132752#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1132753#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133470#L679 assume !(1 == ~M_E~0); 1132921#L679-2 assume !(1 == ~T1_E~0); 1132637#L684-1 assume !(1 == ~T2_E~0); 1132638#L689-1 assume !(1 == ~T3_E~0); 1133024#L694-1 assume !(1 == ~T4_E~0); 1133022#L699-1 assume !(1 == ~T5_E~0); 1133023#L704-1 assume !(1 == ~E_M~0); 1132978#L709-1 assume !(1 == ~E_1~0); 1132843#L714-1 assume !(1 == ~E_2~0); 1132844#L719-1 assume !(1 == ~E_3~0); 1133267#L724-1 assume !(1 == ~E_4~0); 1132427#L729-1 assume !(1 == ~E_5~0); 1132428#L734-1 assume { :end_inline_reset_delta_events } true; 1133485#L940-2 assume !false; 1149299#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1226733#L586-1 [2024-11-13 14:12:16,250 INFO L747 eck$LassoCheckResult]: Loop: 1226733#L586-1 assume !false; 1226728#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1226724#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1226722#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1226720#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1226716#L511 assume 0 != eval_~tmp~0#1; 1226712#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1226708#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1226709#L519-2 havoc eval_~tmp_ndt_1~0#1; 1227113#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1227110#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1226692#L533-2 havoc eval_~tmp_ndt_2~0#1; 1226239#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1226236#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1226234#L547-2 havoc eval_~tmp_ndt_3~0#1; 1226232#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1226229#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1226227#L561-2 havoc eval_~tmp_ndt_4~0#1; 1226224#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1226221#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 1226219#L575-2 havoc eval_~tmp_ndt_5~0#1; 1226217#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 1226038#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 1226215#L589-2 havoc eval_~tmp_ndt_6~0#1; 1226733#L586-1 [2024-11-13 14:12:16,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:16,251 INFO L85 PathProgramCache]: Analyzing trace with hash -322248345, now seen corresponding path program 5 times [2024-11-13 14:12:16,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:16,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680583906] [2024-11-13 14:12:16,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:16,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:16,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,268 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:16,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,287 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:16,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:16,287 INFO L85 PathProgramCache]: Analyzing trace with hash -1423679920, now seen corresponding path program 1 times [2024-11-13 14:12:16,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:16,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905925558] [2024-11-13 14:12:16,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:16,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:16,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,292 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:16,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:16,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 14:12:16,298 INFO L85 PathProgramCache]: Analyzing trace with hash 2027613622, now seen corresponding path program 1 times [2024-11-13 14:12:16,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 14:12:16,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007883121] [2024-11-13 14:12:16,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 14:12:16,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 14:12:16,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,312 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:16,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:16,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 14:12:18,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:18,112 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 14:12:18,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 14:12:18,413 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.11 02:12:18 BoogieIcfgContainer [2024-11-13 14:12:18,413 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-13 14:12:18,413 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 14:12:18,414 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 14:12:18,414 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 14:12:18,415 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 02:11:40" (3/4) ... [2024-11-13 14:12:18,417 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-13 14:12:18,549 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 14:12:18,549 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 14:12:18,550 INFO L158 Benchmark]: Toolchain (without parser) took 40821.07ms. Allocated memory was 142.6MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 118.6MB in the beginning and 9.3GB in the end (delta: -9.2GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2024-11-13 14:12:18,550 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 79.4MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:12:18,550 INFO L158 Benchmark]: CACSL2BoogieTranslator took 515.82ms. Allocated memory is still 142.6MB. Free memory was 118.4MB in the beginning and 102.3MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 14:12:18,550 INFO L158 Benchmark]: Boogie Procedure Inliner took 109.34ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 97.6MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 14:12:18,551 INFO L158 Benchmark]: Boogie Preprocessor took 116.28ms. Allocated memory is still 142.6MB. Free memory was 97.6MB in the beginning and 91.9MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 14:12:18,551 INFO L158 Benchmark]: RCFGBuilder took 1742.60ms. Allocated memory is still 142.6MB. Free memory was 91.9MB in the beginning and 83.6MB in the end (delta: 8.2MB). Peak memory consumption was 58.6MB. Max. memory is 16.1GB. [2024-11-13 14:12:18,551 INFO L158 Benchmark]: BuchiAutomizer took 38190.98ms. Allocated memory was 142.6MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 82.9MB in the beginning and 9.3GB in the end (delta: -9.2GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2024-11-13 14:12:18,551 INFO L158 Benchmark]: Witness Printer took 135.53ms. Allocated memory is still 11.5GB. Free memory was 9.3GB in the beginning and 9.3GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-13 14:12:18,556 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 79.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 515.82ms. Allocated memory is still 142.6MB. Free memory was 118.4MB in the beginning and 102.3MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 109.34ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 97.6MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 116.28ms. Allocated memory is still 142.6MB. Free memory was 97.6MB in the beginning and 91.9MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1742.60ms. Allocated memory is still 142.6MB. Free memory was 91.9MB in the beginning and 83.6MB in the end (delta: 8.2MB). Peak memory consumption was 58.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 38190.98ms. Allocated memory was 142.6MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 82.9MB in the beginning and 9.3GB in the end (delta: -9.2GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. * Witness Printer took 135.53ms. Allocated memory is still 11.5GB. Free memory was 9.3GB in the beginning and 9.3GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 30 terminating modules (29 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * E_3) + 1) and consists of 3 locations. 29 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 205340 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 37.9s and 30 iterations. TraceHistogramMax:2. Analysis of lassos took 11.5s. Construction of modules took 1.6s. Büchi inclusion checks took 20.9s. Highest rank in rank-based complementation 3. Minimization of det autom 22. Minimization of nondet autom 8. Automata minimization 10.3s AutomataMinimizationTime, 30 MinimizatonAttempts, 15761 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 6.2s Buchi closure took 0.3s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 19393 SdHoareTripleChecker+Valid, 2.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 19392 mSDsluCounter, 53053 SdHoareTripleChecker+Invalid, 1.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 26213 mSDsCounter, 376 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1229 IncrementalHoareTripleChecker+Invalid, 1605 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 376 mSolverCounterUnsat, 26840 mSDtfsCounter, 1229 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc4 concLT1 SILN0 SILU0 SILI15 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital136 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 26ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 14:12:18,599 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ea3e8f3-f68e-43b2-92e0-c5a6f7e0124c/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)