./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:43:08,607 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:43:08,709 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:43:08,716 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:43:08,717 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:43:08,760 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:43:08,761 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:43:08,761 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:43:08,761 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:43:08,762 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:43:08,762 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:43:08,763 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:43:08,763 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:43:08,764 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:43:08,765 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:43:08,766 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:43:08,766 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:43:08,767 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:43:08,768 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:43:08,768 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:43:08,768 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:43:08,768 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:43:08,768 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:43:08,770 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2024-11-13 15:43:09,156 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:43:09,165 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:43:09,168 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:43:09,170 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:43:09,171 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:43:09,172 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c Unable to find full path for "g++" [2024-11-13 15:43:11,297 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:43:11,724 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:43:11,725 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2024-11-13 15:43:11,737 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/data/eb5c9a35c/093d0f9f4c1b459cb9e1598d6cb16e5d/FLAG27a434c97 [2024-11-13 15:43:11,758 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/data/eb5c9a35c/093d0f9f4c1b459cb9e1598d6cb16e5d [2024-11-13 15:43:11,767 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:43:11,770 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:43:11,773 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:43:11,774 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:43:11,779 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:43:11,780 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:43:11" (1/1) ... [2024-11-13 15:43:11,781 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7a0cdac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:11, skipping insertion in model container [2024-11-13 15:43:11,783 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:43:11" (1/1) ... [2024-11-13 15:43:11,839 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:43:12,205 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:43:12,225 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:43:12,334 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:43:12,366 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:43:12,367 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12 WrapperNode [2024-11-13 15:43:12,367 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:43:12,369 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:43:12,369 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:43:12,369 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:43:12,378 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,394 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,503 INFO L138 Inliner]: procedures = 40, calls = 51, calls flagged for inlining = 46, calls inlined = 116, statements flattened = 1670 [2024-11-13 15:43:12,507 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:43:12,507 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:43:12,507 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:43:12,508 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:43:12,521 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,522 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,532 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,574 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:43:12,577 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,578 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,605 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,623 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,626 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,629 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,636 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:43:12,637 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:43:12,637 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:43:12,637 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:43:12,638 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (1/1) ... [2024-11-13 15:43:12,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:12,668 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:12,696 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:12,703 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:43:12,734 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:43:12,734 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:43:12,734 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:43:12,735 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:43:12,896 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:43:12,898 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:43:15,092 INFO L? ?]: Removed 322 outVars from TransFormulas that were not future-live. [2024-11-13 15:43:15,092 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:43:15,135 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:43:15,136 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-11-13 15:43:15,136 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:43:15 BoogieIcfgContainer [2024-11-13 15:43:15,136 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:43:15,144 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:43:15,144 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:43:15,151 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:43:15,152 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:43:15,152 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:43:11" (1/3) ... [2024-11-13 15:43:15,154 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4b03af59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:43:15, skipping insertion in model container [2024-11-13 15:43:15,154 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:43:15,155 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:43:12" (2/3) ... [2024-11-13 15:43:15,155 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4b03af59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:43:15, skipping insertion in model container [2024-11-13 15:43:15,155 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:43:15,155 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:43:15" (3/3) ... [2024-11-13 15:43:15,157 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2024-11-13 15:43:15,253 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:43:15,253 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:43:15,253 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:43:15,253 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:43:15,253 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:43:15,254 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:43:15,254 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:43:15,254 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:43:15,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:15,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2024-11-13 15:43:15,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:15,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:15,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:15,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:15,360 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:43:15,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:15,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2024-11-13 15:43:15,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:15,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:15,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:15,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:15,393 INFO L745 eck$LassoCheckResult]: Stem: 199#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 569#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 564#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 523#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 129#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 268#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 40#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 149#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 115#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 540#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222#L696true assume !(0 == ~M_E~0); 534#L696-2true assume !(0 == ~T1_E~0); 537#L701-1true assume !(0 == ~T2_E~0); 567#L706-1true assume !(0 == ~T3_E~0); 305#L711-1true assume !(0 == ~T4_E~0); 151#L716-1true assume !(0 == ~T5_E~0); 587#L721-1true assume !(0 == ~T6_E~0); 273#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 476#L731-1true assume !(0 == ~E_1~0); 247#L736-1true assume !(0 == ~E_2~0); 317#L741-1true assume !(0 == ~E_3~0); 626#L746-1true assume !(0 == ~E_4~0); 169#L751-1true assume !(0 == ~E_5~0); 232#L756-1true assume !(0 == ~E_6~0); 148#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51#L346true assume !(1 == ~m_pc~0); 179#L346-2true is_master_triggered_~__retres1~0#1 := 0; 420#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 553#L861true assume !(0 != activate_threads_~tmp~1#1); 475#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69#L365true assume 1 == ~t1_pc~0; 138#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 518#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64#L869true assume !(0 != activate_threads_~tmp___0~0#1); 371#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502#L384true assume !(1 == ~t2_pc~0); 367#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 628#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 236#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L403true assume 1 == ~t3_pc~0; 152#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 681#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 416#L885true assume !(0 != activate_threads_~tmp___2~0#1); 226#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 524#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 438#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451#L893true assume !(0 != activate_threads_~tmp___3~0#1); 291#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L441true assume !(1 == ~t5_pc~0); 469#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 616#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 698#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 421#L909true assume !(0 != activate_threads_~tmp___5~0#1); 550#L909-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L774true assume !(1 == ~M_E~0); 592#L774-2true assume !(1 == ~T1_E~0); 442#L779-1true assume !(1 == ~T2_E~0); 210#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 588#L789-1true assume !(1 == ~T4_E~0); 60#L794-1true assume !(1 == ~T5_E~0); 667#L799-1true assume !(1 == ~T6_E~0); 602#L804-1true assume !(1 == ~E_M~0); 659#L809-1true assume !(1 == ~E_1~0); 270#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 325#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 649#L829-1true assume !(1 == ~E_5~0); 429#L834-1true assume !(1 == ~E_6~0); 139#L839-1true assume { :end_inline_reset_delta_events } true; 131#L1065-2true [2024-11-13 15:43:15,399 INFO L747 eck$LassoCheckResult]: Loop: 131#L1065-2true assume !false; 341#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397#L671-1true assume false; 105#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 582#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 198#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 673#L706-3true assume !(0 == ~T3_E~0); 548#L711-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 535#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 321#L721-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 184#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 309#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 511#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 310#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 145#L746-3true assume !(0 == ~E_4~0); 228#L751-3true assume 0 == ~E_5~0;~E_5~0 := 1; 430#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 73#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L346-24true assume 1 == ~m_pc~0; 413#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 311#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 500#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111#L365-24true assume 1 == ~t1_pc~0; 322#L366-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 655#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 586#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83#L384-24true assume 1 == ~t2_pc~0; 702#L385-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 640#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 675#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L877-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171#L403-24true assume 1 == ~t3_pc~0; 627#L404-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 577#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130#L422-24true assume 1 == ~t4_pc~0; 574#L423-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539#L893-24true assume !(0 != activate_threads_~tmp___3~0#1); 448#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L441-24true assume !(1 == ~t5_pc~0); 292#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 286#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 243#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65#L901-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 378#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L460-24true assume 1 == ~t6_pc~0; 590#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 687#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 468#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 368#L909-26true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L774-3true assume 1 == ~M_E~0;~M_E~0 := 2; 298#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L779-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 686#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 70#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 284#L804-3true assume !(1 == ~E_M~0); 521#L809-3true assume 1 == ~E_1~0;~E_1~0 := 2; 68#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 221#L819-3true assume 1 == ~E_3~0;~E_3~0 := 2; 156#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 144#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 346#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 59#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 452#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28#L1084true assume !(0 == start_simulation_~tmp~3#1); 492#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 167#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 170#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 175#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 131#L1065-2true [2024-11-13 15:43:15,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:15,407 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2024-11-13 15:43:15,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:15,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919141893] [2024-11-13 15:43:15,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:15,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:15,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:15,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:15,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:15,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919141893] [2024-11-13 15:43:15,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919141893] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:15,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:15,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:15,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617410630] [2024-11-13 15:43:15,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:15,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:15,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:15,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1070251301, now seen corresponding path program 1 times [2024-11-13 15:43:15,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:15,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037130058] [2024-11-13 15:43:15,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:15,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:15,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:15,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:15,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:15,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037130058] [2024-11-13 15:43:15,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037130058] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:15,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:15,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:15,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637198699] [2024-11-13 15:43:15,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:15,958 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:15,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:15,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:15,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:16,001 INFO L87 Difference]: Start difference. First operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:16,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:16,107 INFO L93 Difference]: Finished difference Result 699 states and 1041 transitions. [2024-11-13 15:43:16,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 699 states and 1041 transitions. [2024-11-13 15:43:16,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:16,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 699 states to 693 states and 1035 transitions. [2024-11-13 15:43:16,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:16,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:16,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1035 transitions. [2024-11-13 15:43:16,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:16,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-11-13 15:43:16,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1035 transitions. [2024-11-13 15:43:16,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:16,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4935064935064934) internal successors, (1035), 692 states have internal predecessors, (1035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:16,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1035 transitions. [2024-11-13 15:43:16,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-11-13 15:43:16,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:16,262 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1035 transitions. [2024-11-13 15:43:16,262 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:43:16,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1035 transitions. [2024-11-13 15:43:16,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:16,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:16,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:16,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:16,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:16,276 INFO L745 eck$LassoCheckResult]: Stem: 1771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2069#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1668#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1500#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1501#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1473#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1474#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1642#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1802#L696 assume !(0 == ~M_E~0); 1803#L696-2 assume !(0 == ~T1_E~0); 2072#L701-1 assume !(0 == ~T2_E~0); 2075#L706-1 assume !(0 == ~T3_E~0); 1910#L711-1 assume !(0 == ~T4_E~0); 1703#L716-1 assume !(0 == ~T5_E~0); 1704#L721-1 assume !(0 == ~T6_E~0); 1868#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1869#L731-1 assume !(0 == ~E_1~0); 1838#L736-1 assume !(0 == ~E_2~0); 1839#L741-1 assume !(0 == ~E_3~0); 1919#L746-1 assume !(0 == ~E_4~0); 1728#L751-1 assume !(0 == ~E_5~0); 1729#L756-1 assume !(0 == ~E_6~0); 1700#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1521#L346 assume !(1 == ~m_pc~0); 1522#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1742#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1734#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1735#L861 assume !(0 != activate_threads_~tmp~1#1); 2051#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1554#L365 assume 1 == ~t1_pc~0; 1555#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1689#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1508#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1543#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966#L384 assume !(1 == ~t2_pc~0); 1962#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1963#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1463#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1464#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1818#L403 assume 1 == ~t3_pc~0; 1705#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1706#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1813#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1814#L422 assume 1 == ~t4_pc~0; 1458#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1459#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1606#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1607#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1475#L441 assume !(1 == ~t5_pc~0); 1476#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2048#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1899#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1900#L460 assume 1 == ~t6_pc~0; 1419#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1420#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1921#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2010#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1877#L774 assume !(1 == ~M_E~0); 1878#L774-2 assume !(1 == ~T1_E~0); 2027#L779-1 assume !(1 == ~T2_E~0); 1788#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1789#L789-1 assume !(1 == ~T4_E~0); 1538#L794-1 assume !(1 == ~T5_E~0); 1539#L799-1 assume !(1 == ~T6_E~0); 2092#L804-1 assume !(1 == ~E_M~0); 2093#L809-1 assume !(1 == ~E_1~0); 1866#L814-1 assume !(1 == ~E_2~0); 1437#L819-1 assume !(1 == ~E_3~0); 1438#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1927#L829-1 assume !(1 == ~E_5~0); 2017#L834-1 assume !(1 == ~E_6~0); 1690#L839-1 assume { :end_inline_reset_delta_events } true; 1673#L1065-2 [2024-11-13 15:43:16,277 INFO L747 eck$LassoCheckResult]: Loop: 1673#L1065-2 assume !false; 1674#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1644#L671-1 assume !false; 1995#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1997#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1510#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1954#L582 assume !(0 != eval_~tmp~0#1); 1622#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1719#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1720#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1767#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1768#L706-3 assume !(0 == ~T3_E~0); 2079#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2073#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1923#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1749#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1750#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1915#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1916#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1697#L746-3 assume !(0 == ~E_4~0); 1698#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1815#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1561#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1562#L346-24 assume !(1 == ~m_pc~0); 1600#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1693#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1640#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1641#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2025#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632#L365-24 assume !(1 == ~t1_pc~0); 1633#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1922#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2070#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1986#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1987#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1579#L384-24 assume 1 == ~t2_pc~0; 1580#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1601#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2100#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1906#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1609#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1610#L403-24 assume 1 == ~t3_pc~0; 1730#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1769#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1863#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1864#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1670#L422-24 assume !(1 == ~t4_pc~0); 1671#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1617#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 2033#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1686#L441-24 assume 1 == ~t5_pc~0; 1687#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1882#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1834#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1544#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1545#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1967#L460-24 assume !(1 == ~t6_pc~0); 1968#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2028#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1960#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1961#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1898#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1748#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1457#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1435#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1436#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1553#L804-3 assume !(1 == ~E_M~0); 1881#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1551#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1552#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1711#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1695#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1696#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1536#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1537#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1534#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1628#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1470#L1084 assume !(0 == start_simulation_~tmp~3#1); 1472#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1724#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1440#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1498#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1499#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1566#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1567#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1736#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1673#L1065-2 [2024-11-13 15:43:16,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:16,278 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2024-11-13 15:43:16,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:16,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974844924] [2024-11-13 15:43:16,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:16,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:16,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:16,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:16,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:16,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974844924] [2024-11-13 15:43:16,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974844924] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:16,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:16,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:16,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496468957] [2024-11-13 15:43:16,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:16,391 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:16,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:16,392 INFO L85 PathProgramCache]: Analyzing trace with hash -761149731, now seen corresponding path program 1 times [2024-11-13 15:43:16,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:16,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782443320] [2024-11-13 15:43:16,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:16,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:16,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:16,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:16,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:16,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782443320] [2024-11-13 15:43:16,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782443320] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:16,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:16,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:16,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206156550] [2024-11-13 15:43:16,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:16,626 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:16,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:16,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:16,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:16,627 INFO L87 Difference]: Start difference. First operand 693 states and 1035 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:16,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:16,669 INFO L93 Difference]: Finished difference Result 693 states and 1034 transitions. [2024-11-13 15:43:16,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1034 transitions. [2024-11-13 15:43:16,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:16,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1034 transitions. [2024-11-13 15:43:16,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:16,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:16,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1034 transitions. [2024-11-13 15:43:16,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:16,684 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-11-13 15:43:16,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1034 transitions. [2024-11-13 15:43:16,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:16,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.492063492063492) internal successors, (1034), 692 states have internal predecessors, (1034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:16,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1034 transitions. [2024-11-13 15:43:16,725 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-11-13 15:43:16,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:16,727 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1034 transitions. [2024-11-13 15:43:16,727 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:43:16,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1034 transitions. [2024-11-13 15:43:16,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:16,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:16,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:16,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:16,741 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:16,741 INFO L745 eck$LassoCheckResult]: Stem: 3162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3462#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3061#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3062#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2889#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2890#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2866#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2867#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3035#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3195#L696 assume !(0 == ~M_E~0); 3196#L696-2 assume !(0 == ~T1_E~0); 3465#L701-1 assume !(0 == ~T2_E~0); 3467#L706-1 assume !(0 == ~T3_E~0); 3303#L711-1 assume !(0 == ~T4_E~0); 3096#L716-1 assume !(0 == ~T5_E~0); 3097#L721-1 assume !(0 == ~T6_E~0); 3261#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3262#L731-1 assume !(0 == ~E_1~0); 3231#L736-1 assume !(0 == ~E_2~0); 3232#L741-1 assume !(0 == ~E_3~0); 3312#L746-1 assume !(0 == ~E_4~0); 3121#L751-1 assume !(0 == ~E_5~0); 3122#L756-1 assume !(0 == ~E_6~0); 3093#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2912#L346 assume !(1 == ~m_pc~0); 2913#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3135#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3128#L861 assume !(0 != activate_threads_~tmp~1#1); 3444#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2946#L365 assume 1 == ~t1_pc~0; 2947#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3079#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2896#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2936#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3359#L384 assume !(1 == ~t2_pc~0); 3353#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3354#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2854#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2855#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3210#L403 assume 1 == ~t3_pc~0; 3098#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3099#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2825#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3203#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3204#L422 assume 1 == ~t4_pc~0; 2849#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2850#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3000#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3282#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2868#L441 assume !(1 == ~t5_pc~0); 2869#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3440#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3139#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3291#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3292#L460 assume 1 == ~t6_pc~0; 2809#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2810#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3314#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3403#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3270#L774 assume !(1 == ~M_E~0); 3271#L774-2 assume !(1 == ~T1_E~0); 3420#L779-1 assume !(1 == ~T2_E~0); 3181#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3182#L789-1 assume !(1 == ~T4_E~0); 2931#L794-1 assume !(1 == ~T5_E~0); 2932#L799-1 assume !(1 == ~T6_E~0); 3485#L804-1 assume !(1 == ~E_M~0); 3486#L809-1 assume !(1 == ~E_1~0); 3258#L814-1 assume !(1 == ~E_2~0); 2828#L819-1 assume !(1 == ~E_3~0); 2829#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3320#L829-1 assume !(1 == ~E_5~0); 3410#L834-1 assume !(1 == ~E_6~0); 3080#L839-1 assume { :end_inline_reset_delta_events } true; 3066#L1065-2 [2024-11-13 15:43:16,742 INFO L747 eck$LassoCheckResult]: Loop: 3066#L1065-2 assume !false; 3067#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3037#L671-1 assume !false; 3385#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3390#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2903#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3346#L582 assume !(0 != eval_~tmp~0#1); 3013#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3014#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3113#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3160#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3161#L706-3 assume !(0 == ~T3_E~0); 3472#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3466#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3142#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3143#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3308#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3309#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3090#L746-3 assume !(0 == ~E_4~0); 3091#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3208#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2954#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2955#L346-24 assume 1 == ~m_pc~0; 2989#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3086#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3033#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3034#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3418#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3025#L365-24 assume !(1 == ~t1_pc~0); 3026#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 3316#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3463#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3381#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3382#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2974#L384-24 assume !(1 == ~t2_pc~0); 2976#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2996#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3493#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3299#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3003#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3004#L403-24 assume 1 == ~t3_pc~0; 3123#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3164#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3165#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3256#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3257#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3063#L422-24 assume !(1 == ~t4_pc~0); 3064#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 3011#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3012#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3447#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 3426#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3081#L441-24 assume 1 == ~t5_pc~0; 3082#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3276#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3227#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2937#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2938#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3360#L460-24 assume !(1 == ~t6_pc~0); 3361#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 3421#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3119#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3120#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3355#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3356#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3293#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3141#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2852#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2853#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2830#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2831#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2949#L804-3 assume !(1 == ~E_M~0); 3274#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2944#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2945#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3104#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3088#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3089#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2929#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2930#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2927#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2863#L1084 assume !(0 == start_simulation_~tmp~3#1); 2865#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3117#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2833#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2894#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2960#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2961#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3129#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3066#L1065-2 [2024-11-13 15:43:16,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:16,743 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2024-11-13 15:43:16,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:16,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437506940] [2024-11-13 15:43:16,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:16,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:16,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:16,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:16,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:16,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437506940] [2024-11-13 15:43:16,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437506940] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:16,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:16,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:16,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080288167] [2024-11-13 15:43:16,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:16,847 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:16,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:16,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1658511267, now seen corresponding path program 1 times [2024-11-13 15:43:16,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:16,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495913426] [2024-11-13 15:43:16,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:16,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:16,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:16,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:16,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:16,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495913426] [2024-11-13 15:43:16,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495913426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:16,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:16,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:16,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279442637] [2024-11-13 15:43:16,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:16,954 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:16,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:16,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:16,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:16,955 INFO L87 Difference]: Start difference. First operand 693 states and 1034 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:16,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:16,997 INFO L93 Difference]: Finished difference Result 693 states and 1033 transitions. [2024-11-13 15:43:16,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1033 transitions. [2024-11-13 15:43:17,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1033 transitions. [2024-11-13 15:43:17,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:17,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:17,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1033 transitions. [2024-11-13 15:43:17,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:17,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-11-13 15:43:17,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1033 transitions. [2024-11-13 15:43:17,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:17,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4906204906204905) internal successors, (1033), 692 states have internal predecessors, (1033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1033 transitions. [2024-11-13 15:43:17,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-11-13 15:43:17,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:17,027 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1033 transitions. [2024-11-13 15:43:17,027 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:43:17,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1033 transitions. [2024-11-13 15:43:17,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:17,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:17,036 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,036 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,036 INFO L745 eck$LassoCheckResult]: Stem: 4555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4855#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4454#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4455#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4284#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4285#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4259#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4260#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4428#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4588#L696 assume !(0 == ~M_E~0); 4589#L696-2 assume !(0 == ~T1_E~0); 4858#L701-1 assume !(0 == ~T2_E~0); 4860#L706-1 assume !(0 == ~T3_E~0); 4696#L711-1 assume !(0 == ~T4_E~0); 4489#L716-1 assume !(0 == ~T5_E~0); 4490#L721-1 assume !(0 == ~T6_E~0); 4654#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4655#L731-1 assume !(0 == ~E_1~0); 4624#L736-1 assume !(0 == ~E_2~0); 4625#L741-1 assume !(0 == ~E_3~0); 4705#L746-1 assume !(0 == ~E_4~0); 4514#L751-1 assume !(0 == ~E_5~0); 4515#L756-1 assume !(0 == ~E_6~0); 4486#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4305#L346 assume !(1 == ~m_pc~0); 4306#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4528#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4520#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4521#L861 assume !(0 != activate_threads_~tmp~1#1); 4837#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4340#L365 assume 1 == ~t1_pc~0; 4341#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4472#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4329#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L384 assume !(1 == ~t2_pc~0); 4746#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4747#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4247#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4248#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4603#L403 assume 1 == ~t3_pc~0; 4491#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4218#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4596#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L422 assume 1 == ~t4_pc~0; 4244#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4245#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4392#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4675#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4261#L441 assume !(1 == ~t5_pc~0); 4262#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4833#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4531#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4532#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L460 assume 1 == ~t6_pc~0; 4202#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4203#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4707#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4796#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L774 assume !(1 == ~M_E~0); 4664#L774-2 assume !(1 == ~T1_E~0); 4813#L779-1 assume !(1 == ~T2_E~0); 4574#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4575#L789-1 assume !(1 == ~T4_E~0); 4324#L794-1 assume !(1 == ~T5_E~0); 4325#L799-1 assume !(1 == ~T6_E~0); 4878#L804-1 assume !(1 == ~E_M~0); 4879#L809-1 assume !(1 == ~E_1~0); 4651#L814-1 assume !(1 == ~E_2~0); 4223#L819-1 assume !(1 == ~E_3~0); 4224#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L829-1 assume !(1 == ~E_5~0); 4803#L834-1 assume !(1 == ~E_6~0); 4473#L839-1 assume { :end_inline_reset_delta_events } true; 4459#L1065-2 [2024-11-13 15:43:17,037 INFO L747 eck$LassoCheckResult]: Loop: 4459#L1065-2 assume !false; 4460#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4430#L671-1 assume !false; 4778#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4296#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4739#L582 assume !(0 != eval_~tmp~0#1); 4406#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4505#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4553#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4554#L706-3 assume !(0 == ~T3_E~0); 4865#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4859#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4708#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4535#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4536#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4701#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4702#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4483#L746-3 assume !(0 == ~E_4~0); 4484#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4601#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4347#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4348#L346-24 assume 1 == ~m_pc~0; 4382#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4479#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4426#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4427#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4811#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4420#L365-24 assume !(1 == ~t1_pc~0); 4421#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4709#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4856#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4774#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4775#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4369#L384-24 assume 1 == ~t2_pc~0; 4370#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4389#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4886#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4692#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4396#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4397#L403-24 assume 1 == ~t3_pc~0; 4516#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4557#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4558#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4649#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4650#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4456#L422-24 assume !(1 == ~t4_pc~0); 4457#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 4404#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4405#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4840#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 4819#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4474#L441-24 assume 1 == ~t5_pc~0; 4475#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4669#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4620#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4330#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4331#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4753#L460-24 assume !(1 == ~t6_pc~0); 4754#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4814#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4512#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4513#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4748#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4749#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4686#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4534#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4221#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4222#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4339#L804-3 assume !(1 == ~E_M~0); 4667#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4332#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4333#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4495#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4480#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4481#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4322#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4323#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4320#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4414#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4256#L1084 assume !(0 == start_simulation_~tmp~3#1); 4258#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4510#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4226#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4282#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4283#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4349#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4350#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4522#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4459#L1065-2 [2024-11-13 15:43:17,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,037 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2024-11-13 15:43:17,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482790094] [2024-11-13 15:43:17,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482790094] [2024-11-13 15:43:17,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482790094] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779501242] [2024-11-13 15:43:17,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,152 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:17,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,152 INFO L85 PathProgramCache]: Analyzing trace with hash -1898778596, now seen corresponding path program 1 times [2024-11-13 15:43:17,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420116362] [2024-11-13 15:43:17,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420116362] [2024-11-13 15:43:17,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420116362] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,284 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076124902] [2024-11-13 15:43:17,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,285 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:17,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:17,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:17,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:17,286 INFO L87 Difference]: Start difference. First operand 693 states and 1033 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:17,320 INFO L93 Difference]: Finished difference Result 693 states and 1032 transitions. [2024-11-13 15:43:17,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1032 transitions. [2024-11-13 15:43:17,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1032 transitions. [2024-11-13 15:43:17,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:17,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:17,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1032 transitions. [2024-11-13 15:43:17,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:17,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-11-13 15:43:17,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1032 transitions. [2024-11-13 15:43:17,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:17,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4891774891774892) internal successors, (1032), 692 states have internal predecessors, (1032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1032 transitions. [2024-11-13 15:43:17,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-11-13 15:43:17,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:17,367 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1032 transitions. [2024-11-13 15:43:17,368 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:43:17,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1032 transitions. [2024-11-13 15:43:17,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:17,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:17,380 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,381 INFO L745 eck$LassoCheckResult]: Stem: 5950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6248#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5847#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5848#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5679#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5680#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5652#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5821#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5981#L696 assume !(0 == ~M_E~0); 5982#L696-2 assume !(0 == ~T1_E~0); 6251#L701-1 assume !(0 == ~T2_E~0); 6254#L706-1 assume !(0 == ~T3_E~0); 6089#L711-1 assume !(0 == ~T4_E~0); 5882#L716-1 assume !(0 == ~T5_E~0); 5883#L721-1 assume !(0 == ~T6_E~0); 6047#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6048#L731-1 assume !(0 == ~E_1~0); 6017#L736-1 assume !(0 == ~E_2~0); 6018#L741-1 assume !(0 == ~E_3~0); 6098#L746-1 assume !(0 == ~E_4~0); 5907#L751-1 assume !(0 == ~E_5~0); 5908#L756-1 assume !(0 == ~E_6~0); 5879#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5700#L346 assume !(1 == ~m_pc~0); 5701#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5921#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5914#L861 assume !(0 != activate_threads_~tmp~1#1); 6230#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5733#L365 assume 1 == ~t1_pc~0; 5734#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5868#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5686#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5687#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5722#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6145#L384 assume !(1 == ~t2_pc~0); 6141#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6142#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5642#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5643#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5997#L403 assume 1 == ~t3_pc~0; 5884#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5885#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5610#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5611#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5992#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5993#L422 assume 1 == ~t4_pc~0; 5637#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5638#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5785#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5786#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6068#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5654#L441 assume !(1 == ~t5_pc~0); 5655#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6227#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5926#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6078#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6079#L460 assume 1 == ~t6_pc~0; 5598#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5599#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5662#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6100#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6189#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6056#L774 assume !(1 == ~M_E~0); 6057#L774-2 assume !(1 == ~T1_E~0); 6206#L779-1 assume !(1 == ~T2_E~0); 5967#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5968#L789-1 assume !(1 == ~T4_E~0); 5717#L794-1 assume !(1 == ~T5_E~0); 5718#L799-1 assume !(1 == ~T6_E~0); 6271#L804-1 assume !(1 == ~E_M~0); 6272#L809-1 assume !(1 == ~E_1~0); 6045#L814-1 assume !(1 == ~E_2~0); 5616#L819-1 assume !(1 == ~E_3~0); 5617#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6106#L829-1 assume !(1 == ~E_5~0); 6196#L834-1 assume !(1 == ~E_6~0); 5869#L839-1 assume { :end_inline_reset_delta_events } true; 5856#L1065-2 [2024-11-13 15:43:17,381 INFO L747 eck$LassoCheckResult]: Loop: 5856#L1065-2 assume !false; 5857#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5823#L671-1 assume !false; 6175#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6176#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5689#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5703#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6133#L582 assume !(0 != eval_~tmp~0#1); 5801#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5898#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5899#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5946#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5947#L706-3 assume !(0 == ~T3_E~0); 6258#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6252#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6102#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5928#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5929#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6094#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6095#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5876#L746-3 assume !(0 == ~E_4~0); 5877#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5994#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5740#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5741#L346-24 assume !(1 == ~m_pc~0); 5776#L346-26 is_master_triggered_~__retres1~0#1 := 0; 5870#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5819#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5820#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6204#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5811#L365-24 assume !(1 == ~t1_pc~0); 5812#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6101#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6249#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6168#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5760#L384-24 assume 1 == ~t2_pc~0; 5761#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5780#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6279#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6085#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5789#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5790#L403-24 assume 1 == ~t3_pc~0; 5909#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5948#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5949#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6042#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6043#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5849#L422-24 assume !(1 == ~t4_pc~0); 5850#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5796#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5797#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6233#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 6212#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5865#L441-24 assume 1 == ~t5_pc~0; 5866#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6061#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6013#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5723#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5724#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6146#L460-24 assume !(1 == ~t6_pc~0); 6147#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 6207#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5905#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5906#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6139#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6140#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6077#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5927#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5636#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5614#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5615#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5732#L804-3 assume !(1 == ~E_M~0); 6060#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5730#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5731#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5890#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5874#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5875#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5715#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5716#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5713#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5649#L1084 assume !(0 == start_simulation_~tmp~3#1); 5651#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5903#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5619#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5678#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5746#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5747#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5915#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5856#L1065-2 [2024-11-13 15:43:17,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2024-11-13 15:43:17,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184523612] [2024-11-13 15:43:17,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184523612] [2024-11-13 15:43:17,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184523612] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093128393] [2024-11-13 15:43:17,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,482 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:17,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,482 INFO L85 PathProgramCache]: Analyzing trace with hash -761149731, now seen corresponding path program 2 times [2024-11-13 15:43:17,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339112797] [2024-11-13 15:43:17,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339112797] [2024-11-13 15:43:17,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339112797] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512262012] [2024-11-13 15:43:17,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,590 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:17,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:17,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:17,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:17,591 INFO L87 Difference]: Start difference. First operand 693 states and 1032 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:17,617 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2024-11-13 15:43:17,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2024-11-13 15:43:17,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1031 transitions. [2024-11-13 15:43:17,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:17,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:17,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1031 transitions. [2024-11-13 15:43:17,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:17,631 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-11-13 15:43:17,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1031 transitions. [2024-11-13 15:43:17,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:17,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4877344877344878) internal successors, (1031), 692 states have internal predecessors, (1031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1031 transitions. [2024-11-13 15:43:17,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-11-13 15:43:17,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:17,663 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1031 transitions. [2024-11-13 15:43:17,663 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:43:17,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1031 transitions. [2024-11-13 15:43:17,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:17,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:17,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,671 INFO L745 eck$LassoCheckResult]: Stem: 7341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7641#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7240#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7241#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7068#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7069#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7045#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7046#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7214#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7374#L696 assume !(0 == ~M_E~0); 7375#L696-2 assume !(0 == ~T1_E~0); 7644#L701-1 assume !(0 == ~T2_E~0); 7646#L706-1 assume !(0 == ~T3_E~0); 7482#L711-1 assume !(0 == ~T4_E~0); 7275#L716-1 assume !(0 == ~T5_E~0); 7276#L721-1 assume !(0 == ~T6_E~0); 7440#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7441#L731-1 assume !(0 == ~E_1~0); 7410#L736-1 assume !(0 == ~E_2~0); 7411#L741-1 assume !(0 == ~E_3~0); 7491#L746-1 assume !(0 == ~E_4~0); 7300#L751-1 assume !(0 == ~E_5~0); 7301#L756-1 assume !(0 == ~E_6~0); 7272#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7091#L346 assume !(1 == ~m_pc~0); 7092#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7314#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7306#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7307#L861 assume !(0 != activate_threads_~tmp~1#1); 7623#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7125#L365 assume 1 == ~t1_pc~0; 7126#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7258#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7075#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7115#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7538#L384 assume !(1 == ~t2_pc~0); 7532#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7533#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7505#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L877 assume !(0 != activate_threads_~tmp___1~0#1); 7034#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7389#L403 assume 1 == ~t3_pc~0; 7277#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7278#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7004#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7382#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7383#L422 assume 1 == ~t4_pc~0; 7028#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7029#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7179#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7461#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7047#L441 assume !(1 == ~t5_pc~0); 7048#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7619#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7317#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7318#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7470#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7471#L460 assume 1 == ~t6_pc~0; 6988#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6989#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7582#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7449#L774 assume !(1 == ~M_E~0); 7450#L774-2 assume !(1 == ~T1_E~0); 7599#L779-1 assume !(1 == ~T2_E~0); 7360#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7361#L789-1 assume !(1 == ~T4_E~0); 7110#L794-1 assume !(1 == ~T5_E~0); 7111#L799-1 assume !(1 == ~T6_E~0); 7664#L804-1 assume !(1 == ~E_M~0); 7665#L809-1 assume !(1 == ~E_1~0); 7437#L814-1 assume !(1 == ~E_2~0); 7007#L819-1 assume !(1 == ~E_3~0); 7008#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7499#L829-1 assume !(1 == ~E_5~0); 7589#L834-1 assume !(1 == ~E_6~0); 7259#L839-1 assume { :end_inline_reset_delta_events } true; 7245#L1065-2 [2024-11-13 15:43:17,671 INFO L747 eck$LassoCheckResult]: Loop: 7245#L1065-2 assume !false; 7246#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7216#L671-1 assume !false; 7564#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7569#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7096#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7525#L582 assume !(0 != eval_~tmp~0#1); 7192#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7291#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7292#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7339#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L706-3 assume !(0 == ~T3_E~0); 7651#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7645#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7494#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7321#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7322#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7487#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7269#L746-3 assume !(0 == ~E_4~0); 7270#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7387#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7133#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7134#L346-24 assume 1 == ~m_pc~0; 7168#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7265#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7212#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7213#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7597#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7204#L365-24 assume !(1 == ~t1_pc~0); 7205#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 7495#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7560#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7561#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7153#L384-24 assume 1 == ~t2_pc~0; 7154#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7175#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7672#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7478#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7182#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7183#L403-24 assume 1 == ~t3_pc~0; 7302#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7343#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7344#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7435#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7436#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7242#L422-24 assume !(1 == ~t4_pc~0); 7243#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 7190#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7626#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 7605#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7260#L441-24 assume 1 == ~t5_pc~0; 7261#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7455#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7406#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7116#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7117#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7539#L460-24 assume !(1 == ~t6_pc~0); 7540#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7600#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7298#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7534#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7535#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7472#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7320#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7031#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7032#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7009#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7010#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7128#L804-3 assume !(1 == ~E_M~0); 7453#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7123#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7124#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7283#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7267#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7268#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7108#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7109#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7106#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7042#L1084 assume !(0 == start_simulation_~tmp~3#1); 7044#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7296#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7073#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7139#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7140#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7245#L1065-2 [2024-11-13 15:43:17,673 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,673 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2024-11-13 15:43:17,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129586075] [2024-11-13 15:43:17,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129586075] [2024-11-13 15:43:17,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129586075] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130698255] [2024-11-13 15:43:17,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,764 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:17,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1898778596, now seen corresponding path program 2 times [2024-11-13 15:43:17,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016422772] [2024-11-13 15:43:17,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:17,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:17,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:17,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016422772] [2024-11-13 15:43:17,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016422772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:17,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:17,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:17,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089748263] [2024-11-13 15:43:17,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:17,848 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:17,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:17,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:17,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:17,848 INFO L87 Difference]: Start difference. First operand 693 states and 1031 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:17,872 INFO L93 Difference]: Finished difference Result 693 states and 1030 transitions. [2024-11-13 15:43:17,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1030 transitions. [2024-11-13 15:43:17,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1030 transitions. [2024-11-13 15:43:17,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2024-11-13 15:43:17,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2024-11-13 15:43:17,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1030 transitions. [2024-11-13 15:43:17,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:17,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-11-13 15:43:17,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1030 transitions. [2024-11-13 15:43:17,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2024-11-13 15:43:17,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4862914862914862) internal successors, (1030), 692 states have internal predecessors, (1030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:17,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1030 transitions. [2024-11-13 15:43:17,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-11-13 15:43:17,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:17,907 INFO L424 stractBuchiCegarLoop]: Abstraction has 693 states and 1030 transitions. [2024-11-13 15:43:17,907 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:43:17,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1030 transitions. [2024-11-13 15:43:17,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2024-11-13 15:43:17,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:17,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:17,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:17,915 INFO L745 eck$LassoCheckResult]: Stem: 8734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9034#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8633#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8634#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8465#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8466#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8438#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8439#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8607#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8767#L696 assume !(0 == ~M_E~0); 8768#L696-2 assume !(0 == ~T1_E~0); 9037#L701-1 assume !(0 == ~T2_E~0); 9039#L706-1 assume !(0 == ~T3_E~0); 8875#L711-1 assume !(0 == ~T4_E~0); 8668#L716-1 assume !(0 == ~T5_E~0); 8669#L721-1 assume !(0 == ~T6_E~0); 8833#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8834#L731-1 assume !(0 == ~E_1~0); 8803#L736-1 assume !(0 == ~E_2~0); 8804#L741-1 assume !(0 == ~E_3~0); 8884#L746-1 assume !(0 == ~E_4~0); 8693#L751-1 assume !(0 == ~E_5~0); 8694#L756-1 assume !(0 == ~E_6~0); 8665#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8484#L346 assume !(1 == ~m_pc~0); 8485#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8707#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8699#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8700#L861 assume !(0 != activate_threads_~tmp~1#1); 9016#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8519#L365 assume 1 == ~t1_pc~0; 8520#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8654#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8470#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8508#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8931#L384 assume !(1 == ~t2_pc~0); 8927#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8928#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8426#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8427#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8782#L403 assume 1 == ~t3_pc~0; 8670#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8671#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8397#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8775#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8776#L422 assume 1 == ~t4_pc~0; 8423#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8424#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8572#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8854#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L441 assume !(1 == ~t5_pc~0); 8441#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9012#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8711#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8864#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8865#L460 assume 1 == ~t6_pc~0; 8381#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8382#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8886#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8975#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8842#L774 assume !(1 == ~M_E~0); 8843#L774-2 assume !(1 == ~T1_E~0); 8992#L779-1 assume !(1 == ~T2_E~0); 8753#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8754#L789-1 assume !(1 == ~T4_E~0); 8503#L794-1 assume !(1 == ~T5_E~0); 8504#L799-1 assume !(1 == ~T6_E~0); 9057#L804-1 assume !(1 == ~E_M~0); 9058#L809-1 assume !(1 == ~E_1~0); 8830#L814-1 assume !(1 == ~E_2~0); 8402#L819-1 assume !(1 == ~E_3~0); 8403#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8892#L829-1 assume !(1 == ~E_5~0); 8982#L834-1 assume !(1 == ~E_6~0); 8655#L839-1 assume { :end_inline_reset_delta_events } true; 8638#L1065-2 [2024-11-13 15:43:17,916 INFO L747 eck$LassoCheckResult]: Loop: 8638#L1065-2 assume !false; 8639#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8609#L671-1 assume !false; 8957#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8962#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8475#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8489#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8918#L582 assume !(0 != eval_~tmp~0#1); 8585#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8586#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8684#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8685#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8732#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8733#L706-3 assume !(0 == ~T3_E~0); 9044#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9038#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8887#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8714#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8715#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8881#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8662#L746-3 assume !(0 == ~E_4~0); 8663#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8780#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8526#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8527#L346-24 assume 1 == ~m_pc~0; 8561#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8658#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8605#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8606#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8990#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8599#L365-24 assume !(1 == ~t1_pc~0); 8600#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 8888#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9035#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8953#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8954#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8548#L384-24 assume 1 == ~t2_pc~0; 8549#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8568#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9065#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8872#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8575#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8576#L403-24 assume 1 == ~t3_pc~0; 8695#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8736#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8737#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8828#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8829#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8635#L422-24 assume !(1 == ~t4_pc~0); 8636#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 8583#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8584#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9019#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 8998#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8651#L441-24 assume 1 == ~t5_pc~0; 8652#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8847#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8799#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8509#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8510#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8932#L460-24 assume !(1 == ~t6_pc~0); 8933#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8993#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8691#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8692#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8925#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8926#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8863#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8713#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8421#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8422#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8400#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8401#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8518#L804-3 assume !(1 == ~E_M~0); 8846#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8513#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8514#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8674#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8659#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8660#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8501#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8502#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8499#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8593#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8435#L1084 assume !(0 == start_simulation_~tmp~3#1); 8437#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8689#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8405#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8463#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8464#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8528#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8529#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8701#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8638#L1065-2 [2024-11-13 15:43:17,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:17,917 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2024-11-13 15:43:17,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:17,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994814439] [2024-11-13 15:43:17,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:17,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:17,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:18,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:18,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:18,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994814439] [2024-11-13 15:43:18,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994814439] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:18,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:18,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:18,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627261255] [2024-11-13 15:43:18,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:18,017 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:18,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:18,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1898778596, now seen corresponding path program 3 times [2024-11-13 15:43:18,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:18,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649684197] [2024-11-13 15:43:18,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:18,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:18,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:18,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:18,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:18,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649684197] [2024-11-13 15:43:18,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649684197] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:18,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:18,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:18,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643414247] [2024-11-13 15:43:18,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:18,091 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:18,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:18,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:43:18,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:43:18,091 INFO L87 Difference]: Start difference. First operand 693 states and 1030 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:18,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:18,321 INFO L93 Difference]: Finished difference Result 1194 states and 1770 transitions. [2024-11-13 15:43:18,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1770 transitions. [2024-11-13 15:43:18,331 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2024-11-13 15:43:18,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1770 transitions. [2024-11-13 15:43:18,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2024-11-13 15:43:18,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2024-11-13 15:43:18,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1770 transitions. [2024-11-13 15:43:18,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:18,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1194 states and 1770 transitions. [2024-11-13 15:43:18,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1770 transitions. [2024-11-13 15:43:18,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 1193. [2024-11-13 15:43:18,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1193 states, 1193 states have (on average 1.4828164291701593) internal successors, (1769), 1192 states have internal predecessors, (1769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:18,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1769 transitions. [2024-11-13 15:43:18,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2024-11-13 15:43:18,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:43:18,406 INFO L424 stractBuchiCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2024-11-13 15:43:18,408 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:43:18,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1769 transitions. [2024-11-13 15:43:18,416 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2024-11-13 15:43:18,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:18,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:18,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:18,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:18,419 INFO L745 eck$LassoCheckResult]: Stem: 10637#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10972#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10533#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10534#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10358#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10359#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10335#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10336#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10507#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10671#L696 assume !(0 == ~M_E~0); 10672#L696-2 assume !(0 == ~T1_E~0); 10977#L701-1 assume !(0 == ~T2_E~0); 10979#L706-1 assume !(0 == ~T3_E~0); 10784#L711-1 assume !(0 == ~T4_E~0); 10568#L716-1 assume !(0 == ~T5_E~0); 10569#L721-1 assume !(0 == ~T6_E~0); 10737#L726-1 assume !(0 == ~E_M~0); 10738#L731-1 assume !(0 == ~E_1~0); 10707#L736-1 assume !(0 == ~E_2~0); 10708#L741-1 assume !(0 == ~E_3~0); 10793#L746-1 assume !(0 == ~E_4~0); 10595#L751-1 assume !(0 == ~E_5~0); 10596#L756-1 assume !(0 == ~E_6~0); 10565#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10381#L346 assume !(1 == ~m_pc~0); 10382#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10610#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10602#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10603#L861 assume !(0 != activate_threads_~tmp~1#1); 10951#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10416#L365 assume 1 == ~t1_pc~0; 10417#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10551#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10364#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10365#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10406#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10849#L384 assume !(1 == ~t2_pc~0); 10843#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10844#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10323#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10324#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10686#L403 assume 1 == ~t3_pc~0; 10570#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10571#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10293#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10294#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10679#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10680#L422 assume 1 == ~t4_pc~0; 10318#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10319#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10471#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10472#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10761#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10337#L441 assume !(1 == ~t5_pc~0); 10338#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10947#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10613#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10614#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10772#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10773#L460 assume 1 == ~t6_pc~0; 10278#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10795#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10902#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10747#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10748#L774-2 assume !(1 == ~T1_E~0); 11062#L779-1 assume !(1 == ~T2_E~0); 11061#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11060#L789-1 assume !(1 == ~T4_E~0); 11059#L794-1 assume !(1 == ~T5_E~0); 11058#L799-1 assume !(1 == ~T6_E~0); 11057#L804-1 assume !(1 == ~E_M~0); 11006#L809-1 assume !(1 == ~E_1~0); 11056#L814-1 assume !(1 == ~E_2~0); 11055#L819-1 assume !(1 == ~E_3~0); 11054#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11052#L829-1 assume !(1 == ~E_5~0); 11050#L834-1 assume !(1 == ~E_6~0); 11048#L839-1 assume { :end_inline_reset_delta_events } true; 11047#L1065-2 [2024-11-13 15:43:18,419 INFO L747 eck$LassoCheckResult]: Loop: 11047#L1065-2 assume !false; 10817#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10509#L671-1 assume !false; 10882#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10992#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10386#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10387#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11025#L582 assume !(0 != eval_~tmp~0#1); 11026#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10960#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10961#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11000#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10635#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10636#L706-3 assume !(0 == ~T3_E~0); 10984#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10978#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10797#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10617#L726-3 assume !(0 == ~E_M~0); 10618#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10789#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10790#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10562#L746-3 assume !(0 == ~E_4~0); 10563#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10684#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10424#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10425#L346-24 assume 1 == ~m_pc~0; 10460#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10558#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10505#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10506#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10920#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10921#L365-24 assume !(1 == ~t1_pc~0); 10800#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 10799#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10973#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10878#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10879#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11002#L384-24 assume !(1 == ~t2_pc~0); 10467#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 10468#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11021#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10780#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10475#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10476#L403-24 assume 1 == ~t3_pc~0; 11014#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10639#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10640#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10732#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10733#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10996#L422-24 assume 1 == ~t4_pc~0; 10993#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10483#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10484#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10954#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 10929#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10930#L441-24 assume 1 == ~t5_pc~0; 10852#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10755#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10703#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10407#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10408#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10853#L460-24 assume !(1 == ~t6_pc~0); 10854#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10924#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10593#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10594#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10845#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10846#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10774#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10616#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10321#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10322#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10299#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10300#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10419#L804-3 assume !(1 == ~E_M~0); 10753#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10414#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10415#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10670#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10560#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10561#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10399#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10400#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11077#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11076#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11073#L1084 assume !(0 == start_simulation_~tmp~3#1); 10938#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11067#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11063#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10363#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10430#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10431#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10964#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 11047#L1065-2 [2024-11-13 15:43:18,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:18,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2024-11-13 15:43:18,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:18,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170006446] [2024-11-13 15:43:18,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:18,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:18,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:18,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:18,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:18,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170006446] [2024-11-13 15:43:18,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170006446] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:18,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:18,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:18,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659957635] [2024-11-13 15:43:18,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:18,537 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:18,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:18,538 INFO L85 PathProgramCache]: Analyzing trace with hash -757967970, now seen corresponding path program 1 times [2024-11-13 15:43:18,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:18,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533492791] [2024-11-13 15:43:18,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:18,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:18,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:18,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:18,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:18,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533492791] [2024-11-13 15:43:18,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533492791] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:18,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:18,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:18,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403555040] [2024-11-13 15:43:18,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:18,613 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:18,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:18,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:18,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:18,614 INFO L87 Difference]: Start difference. First operand 1193 states and 1769 transitions. cyclomatic complexity: 578 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:18,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:18,744 INFO L93 Difference]: Finished difference Result 2162 states and 3179 transitions. [2024-11-13 15:43:18,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3179 transitions. [2024-11-13 15:43:18,763 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2054 [2024-11-13 15:43:18,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3179 transitions. [2024-11-13 15:43:18,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2024-11-13 15:43:18,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2024-11-13 15:43:18,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3179 transitions. [2024-11-13 15:43:18,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:18,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2162 states and 3179 transitions. [2024-11-13 15:43:18,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3179 transitions. [2024-11-13 15:43:18,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2158. [2024-11-13 15:43:18,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2158 states, 2158 states have (on average 1.4712696941612604) internal successors, (3175), 2157 states have internal predecessors, (3175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:18,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2158 states to 2158 states and 3175 transitions. [2024-11-13 15:43:18,848 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2024-11-13 15:43:18,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:18,851 INFO L424 stractBuchiCegarLoop]: Abstraction has 2158 states and 3175 transitions. [2024-11-13 15:43:18,851 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:43:18,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2158 states and 3175 transitions. [2024-11-13 15:43:18,868 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2050 [2024-11-13 15:43:18,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:18,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:18,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:18,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:18,871 INFO L745 eck$LassoCheckResult]: Stem: 13995#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14173#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14174#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14347#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 13890#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13891#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13723#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13724#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13696#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13697#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13865#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14026#L696 assume !(0 == ~M_E~0); 14027#L696-2 assume !(0 == ~T1_E~0); 14355#L701-1 assume !(0 == ~T2_E~0); 14357#L706-1 assume !(0 == ~T3_E~0); 14148#L711-1 assume !(0 == ~T4_E~0); 13925#L716-1 assume !(0 == ~T5_E~0); 13926#L721-1 assume !(0 == ~T6_E~0); 14098#L726-1 assume !(0 == ~E_M~0); 14099#L731-1 assume !(0 == ~E_1~0); 14065#L736-1 assume !(0 == ~E_2~0); 14066#L741-1 assume !(0 == ~E_3~0); 14159#L746-1 assume !(0 == ~E_4~0); 13950#L751-1 assume !(0 == ~E_5~0); 13951#L756-1 assume !(0 == ~E_6~0); 13922#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13744#L346 assume !(1 == ~m_pc~0); 13745#L346-2 is_master_triggered_~__retres1~0#1 := 0; 13966#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13958#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13959#L861 assume !(0 != activate_threads_~tmp~1#1); 14322#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13778#L365 assume !(1 == ~t1_pc~0); 13779#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14338#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13730#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13731#L869 assume !(0 != activate_threads_~tmp___0~0#1); 13767#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14215#L384 assume !(1 == ~t2_pc~0); 14211#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14212#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14179#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13686#L877 assume !(0 != activate_threads_~tmp___1~0#1); 13687#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14044#L403 assume 1 == ~t3_pc~0; 13927#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13928#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13654#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13655#L885 assume !(0 != activate_threads_~tmp___2~0#1); 14039#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14040#L422 assume 1 == ~t4_pc~0; 13681#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13682#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13829#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13830#L893 assume !(0 != activate_threads_~tmp___3~0#1); 14126#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13698#L441 assume !(1 == ~t5_pc~0); 13699#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14319#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13970#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13971#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14137#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14138#L460 assume 1 == ~t6_pc~0; 13643#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13644#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13708#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14162#L909 assume !(0 != activate_threads_~tmp___5~0#1); 14270#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14110#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 14111#L774-2 assume !(1 == ~T1_E~0); 15357#L779-1 assume !(1 == ~T2_E~0); 15356#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15355#L789-1 assume !(1 == ~T4_E~0); 15354#L794-1 assume !(1 == ~T5_E~0); 15353#L799-1 assume !(1 == ~T6_E~0); 15352#L804-1 assume !(1 == ~E_M~0); 14394#L809-1 assume !(1 == ~E_1~0); 15351#L814-1 assume !(1 == ~E_2~0); 15350#L819-1 assume !(1 == ~E_3~0); 15349#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15348#L829-1 assume !(1 == ~E_5~0); 15347#L834-1 assume !(1 == ~E_6~0); 13912#L839-1 assume { :end_inline_reset_delta_events } true; 13898#L1065-2 [2024-11-13 15:43:18,871 INFO L747 eck$LassoCheckResult]: Loop: 13898#L1065-2 assume !false; 13899#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14251#L671-1 assume !false; 14252#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14380#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13747#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13748#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15310#L582 assume !(0 != eval_~tmp~0#1); 15309#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14332#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15308#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15792#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14425#L706-3 assume !(0 == ~T3_E~0); 14362#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14354#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14163#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13973#L726-3 assume !(0 == ~E_M~0); 13974#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14154#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14155#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13919#L746-3 assume !(0 == ~E_4~0); 13920#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14041#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13784#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13785#L346-24 assume 1 == ~m_pc~0; 13822#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13913#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13863#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13864#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14287#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13858#L365-24 assume !(1 == ~t1_pc~0); 13859#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 14431#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15771#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15770#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15769#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15768#L384-24 assume 1 == ~t2_pc~0; 15766#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15765#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15764#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15763#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15762#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15761#L403-24 assume 1 == ~t3_pc~0; 15760#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15758#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15757#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15755#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15753#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15751#L422-24 assume 1 == ~t4_pc~0; 15748#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15745#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15743#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15741#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 15739#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13909#L441-24 assume 1 == ~t5_pc~0; 13910#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14118#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14061#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13768#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13769#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14218#L460-24 assume !(1 == ~t6_pc~0); 14219#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 14292#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13948#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13949#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14209#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14210#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14136#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13972#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13679#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13680#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13658#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13659#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13777#L804-3 assume !(1 == ~E_M~0); 14117#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13775#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13776#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13933#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13917#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13918#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13760#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13761#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15433#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15431#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15429#L1084 assume !(0 == start_simulation_~tmp~3#1); 14309#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14333#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15325#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15324#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 15323#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15322#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15321#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13960#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 13898#L1065-2 [2024-11-13 15:43:18,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:18,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2024-11-13 15:43:18,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:18,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643559578] [2024-11-13 15:43:18,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:18,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:18,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:18,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:18,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:18,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643559578] [2024-11-13 15:43:18,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643559578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:18,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:18,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:18,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786305697] [2024-11-13 15:43:18,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:18,980 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:18,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:18,981 INFO L85 PathProgramCache]: Analyzing trace with hash -998235299, now seen corresponding path program 1 times [2024-11-13 15:43:18,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:18,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132577499] [2024-11-13 15:43:18,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:18,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:19,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:19,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:19,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:19,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132577499] [2024-11-13 15:43:19,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132577499] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:19,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:19,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:19,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252246475] [2024-11-13 15:43:19,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:19,048 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:19,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:19,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:19,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:19,049 INFO L87 Difference]: Start difference. First operand 2158 states and 3175 transitions. cyclomatic complexity: 1021 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:19,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:19,207 INFO L93 Difference]: Finished difference Result 3975 states and 5808 transitions. [2024-11-13 15:43:19,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3975 states and 5808 transitions. [2024-11-13 15:43:19,244 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3860 [2024-11-13 15:43:19,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3975 states to 3975 states and 5808 transitions. [2024-11-13 15:43:19,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3975 [2024-11-13 15:43:19,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3975 [2024-11-13 15:43:19,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3975 states and 5808 transitions. [2024-11-13 15:43:19,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:19,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3975 states and 5808 transitions. [2024-11-13 15:43:19,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3975 states and 5808 transitions. [2024-11-13 15:43:19,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3975 to 3967. [2024-11-13 15:43:19,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4620620115956642) internal successors, (5800), 3966 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:19,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5800 transitions. [2024-11-13 15:43:19,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2024-11-13 15:43:19,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:19,441 INFO L424 stractBuchiCegarLoop]: Abstraction has 3967 states and 5800 transitions. [2024-11-13 15:43:19,441 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:43:19,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5800 transitions. [2024-11-13 15:43:19,460 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3852 [2024-11-13 15:43:19,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:19,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:19,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:19,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:19,462 INFO L745 eck$LassoCheckResult]: Stem: 20124#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20458#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 20026#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20027#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19861#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19862#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19834#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19835#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20004#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20158#L696 assume !(0 == ~M_E~0); 20159#L696-2 assume !(0 == ~T1_E~0); 20465#L701-1 assume !(0 == ~T2_E~0); 20467#L706-1 assume !(0 == ~T3_E~0); 20273#L711-1 assume !(0 == ~T4_E~0); 20059#L716-1 assume !(0 == ~T5_E~0); 20060#L721-1 assume !(0 == ~T6_E~0); 20230#L726-1 assume !(0 == ~E_M~0); 20231#L731-1 assume !(0 == ~E_1~0); 20195#L736-1 assume !(0 == ~E_2~0); 20196#L741-1 assume !(0 == ~E_3~0); 20282#L746-1 assume !(0 == ~E_4~0); 20081#L751-1 assume !(0 == ~E_5~0); 20082#L756-1 assume !(0 == ~E_6~0); 20056#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19881#L346 assume !(1 == ~m_pc~0); 19882#L346-2 is_master_triggered_~__retres1~0#1 := 0; 20097#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20087#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20088#L861 assume !(0 != activate_threads_~tmp~1#1); 20434#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19914#L365 assume !(1 == ~t1_pc~0); 19915#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20447#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19868#L869 assume !(0 != activate_threads_~tmp___0~0#1); 19903#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20332#L384 assume !(1 == ~t2_pc~0); 20328#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20329#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20302#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19824#L877 assume !(0 != activate_threads_~tmp___1~0#1); 19825#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20174#L403 assume !(1 == ~t3_pc~0); 20175#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20369#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19794#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19795#L885 assume !(0 != activate_threads_~tmp___2~0#1); 20168#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20169#L422 assume 1 == ~t4_pc~0; 19819#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19820#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19967#L893 assume !(0 != activate_threads_~tmp___3~0#1); 20252#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19836#L441 assume !(1 == ~t5_pc~0); 19837#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20430#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20100#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20262#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20263#L460 assume 1 == ~t6_pc~0; 19783#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19784#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20284#L909 assume !(0 != activate_threads_~tmp___5~0#1); 20382#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20239#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 20240#L774-2 assume !(1 == ~T1_E~0); 20403#L779-1 assume !(1 == ~T2_E~0); 20142#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20143#L789-1 assume !(1 == ~T4_E~0); 19898#L794-1 assume !(1 == ~T5_E~0); 19899#L799-1 assume !(1 == ~T6_E~0); 22541#L804-1 assume !(1 == ~E_M~0); 20508#L809-1 assume !(1 == ~E_1~0); 20532#L814-1 assume !(1 == ~E_2~0); 19800#L819-1 assume !(1 == ~E_3~0); 19801#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20530#L829-1 assume !(1 == ~E_5~0); 20531#L834-1 assume !(1 == ~E_6~0); 20046#L839-1 assume { :end_inline_reset_delta_events } true; 20036#L1065-2 [2024-11-13 15:43:19,462 INFO L747 eck$LassoCheckResult]: Loop: 20036#L1065-2 assume !false; 20037#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20002#L671-1 assume !false; 20361#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20370#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19870#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19887#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20319#L582 assume !(0 != eval_~tmp~0#1); 20545#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22487#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22486#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22485#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22484#L706-3 assume !(0 == ~T3_E~0); 22483#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22482#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22481#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22480#L726-3 assume !(0 == ~E_M~0); 22479#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22478#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22477#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22476#L746-3 assume !(0 == ~E_4~0); 22475#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22474#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22472#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22471#L346-24 assume 1 == ~m_pc~0; 22469#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22468#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22467#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22465#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22466#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22794#L365-24 assume !(1 == ~t1_pc~0); 22792#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22790#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22788#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22786#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22784#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22782#L384-24 assume 1 == ~t2_pc~0; 22779#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22777#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22776#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22432#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22433#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22426#L403-24 assume !(1 == ~t3_pc~0); 22427#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22754#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22750#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22746#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22742#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22739#L422-24 assume 1 == ~t4_pc~0; 22734#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22729#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22725#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22721#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 22717#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22713#L441-24 assume 1 == ~t5_pc~0; 22707#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22702#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22698#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22694#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22690#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22686#L460-24 assume 1 == ~t6_pc~0; 22680#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20543#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20079#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20080#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20326#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20327#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20261#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20101#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19817#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19818#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19798#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19799#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19913#L804-3 assume !(1 == ~E_M~0); 20244#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23516#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23515#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23514#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23513#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23512#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23511#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20414#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19894#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19989#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 19831#L1084 assume !(0 == start_simulation_~tmp~3#1); 19833#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20077#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19803#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19859#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 19860#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19926#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19927#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 20089#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 20036#L1065-2 [2024-11-13 15:43:19,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:19,463 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2024-11-13 15:43:19,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:19,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932984175] [2024-11-13 15:43:19,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:19,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:19,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:19,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:19,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:19,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932984175] [2024-11-13 15:43:19,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932984175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:19,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:19,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:19,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806066506] [2024-11-13 15:43:19,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:19,542 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:19,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:19,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1522518755, now seen corresponding path program 1 times [2024-11-13 15:43:19,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:19,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145516878] [2024-11-13 15:43:19,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:19,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:19,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:19,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:19,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:19,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145516878] [2024-11-13 15:43:19,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145516878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:19,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:19,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:19,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621905276] [2024-11-13 15:43:19,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:19,639 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:19,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:19,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:19,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:19,641 INFO L87 Difference]: Start difference. First operand 3967 states and 5800 transitions. cyclomatic complexity: 1841 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:19,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:19,819 INFO L93 Difference]: Finished difference Result 7374 states and 10725 transitions. [2024-11-13 15:43:19,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7374 states and 10725 transitions. [2024-11-13 15:43:19,872 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7232 [2024-11-13 15:43:19,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7374 states to 7374 states and 10725 transitions. [2024-11-13 15:43:19,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7374 [2024-11-13 15:43:19,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7374 [2024-11-13 15:43:19,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7374 states and 10725 transitions. [2024-11-13 15:43:19,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:19,938 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7374 states and 10725 transitions. [2024-11-13 15:43:19,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7374 states and 10725 transitions. [2024-11-13 15:43:20,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7374 to 7358. [2024-11-13 15:43:20,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7358 states, 7358 states have (on average 1.4554226692035879) internal successors, (10709), 7357 states have internal predecessors, (10709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:20,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7358 states to 7358 states and 10709 transitions. [2024-11-13 15:43:20,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2024-11-13 15:43:20,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:20,257 INFO L424 stractBuchiCegarLoop]: Abstraction has 7358 states and 10709 transitions. [2024-11-13 15:43:20,257 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:43:20,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7358 states and 10709 transitions. [2024-11-13 15:43:20,296 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7216 [2024-11-13 15:43:20,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:20,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:20,298 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:20,298 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:20,298 INFO L745 eck$LassoCheckResult]: Stem: 31471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31662#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31663#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31832#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 31367#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31368#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31200#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31201#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31177#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31178#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31342#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31507#L696 assume !(0 == ~M_E~0); 31508#L696-2 assume !(0 == ~T1_E~0); 31844#L701-1 assume !(0 == ~T2_E~0); 31846#L706-1 assume !(0 == ~T3_E~0); 31632#L711-1 assume !(0 == ~T4_E~0); 31401#L716-1 assume !(0 == ~T5_E~0); 31402#L721-1 assume !(0 == ~T6_E~0); 31586#L726-1 assume !(0 == ~E_M~0); 31587#L731-1 assume !(0 == ~E_1~0); 31548#L736-1 assume !(0 == ~E_2~0); 31549#L741-1 assume !(0 == ~E_3~0); 31643#L746-1 assume !(0 == ~E_4~0); 31427#L751-1 assume !(0 == ~E_5~0); 31428#L756-1 assume !(0 == ~E_6~0); 31398#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31222#L346 assume !(1 == ~m_pc~0); 31223#L346-2 is_master_triggered_~__retres1~0#1 := 0; 31442#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31434#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31435#L861 assume !(0 != activate_threads_~tmp~1#1); 31805#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31257#L365 assume !(1 == ~t1_pc~0); 31258#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31819#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31207#L869 assume !(0 != activate_threads_~tmp___0~0#1); 31247#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31698#L384 assume !(1 == ~t2_pc~0); 31693#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31694#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31664#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31166#L877 assume !(0 != activate_threads_~tmp___1~0#1); 31167#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31525#L403 assume !(1 == ~t3_pc~0); 31526#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31739#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31141#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31142#L885 assume !(0 != activate_threads_~tmp___2~0#1); 31517#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31518#L422 assume !(1 == ~t4_pc~0); 31660#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31661#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31310#L893 assume !(0 != activate_threads_~tmp___3~0#1); 31611#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31179#L441 assume !(1 == ~t5_pc~0); 31180#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 31800#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31445#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31446#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31620#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31621#L460 assume 1 == ~t6_pc~0; 31128#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31129#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31645#L909 assume !(0 != activate_threads_~tmp___5~0#1); 31753#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31596#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 31597#L774-2 assume !(1 == ~T1_E~0); 31773#L779-1 assume !(1 == ~T2_E~0); 31491#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31492#L789-1 assume !(1 == ~T4_E~0); 31241#L794-1 assume !(1 == ~T5_E~0); 31242#L799-1 assume !(1 == ~T6_E~0); 36709#L804-1 assume !(1 == ~E_M~0); 31898#L809-1 assume !(1 == ~E_1~0); 36705#L814-1 assume !(1 == ~E_2~0); 36703#L819-1 assume !(1 == ~E_3~0); 36701#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36699#L829-1 assume !(1 == ~E_5~0); 31761#L834-1 assume !(1 == ~E_6~0); 31762#L839-1 assume { :end_inline_reset_delta_events } true; 31371#L1065-2 [2024-11-13 15:43:20,299 INFO L747 eck$LassoCheckResult]: Loop: 31371#L1065-2 assume !false; 31372#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31344#L671-1 assume !false; 31733#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31740#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31213#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31227#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31686#L582 assume !(0 != eval_~tmp~0#1); 31941#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36828#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36538#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36533#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36531#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36529#L706-3 assume !(0 == ~T3_E~0); 36528#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36527#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36526#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36525#L726-3 assume !(0 == ~E_M~0); 36517#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36516#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36515#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36513#L746-3 assume !(0 == ~E_4~0); 36511#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36508#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36509#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36499#L346-24 assume 1 == ~m_pc~0; 36500#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36811#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36810#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36809#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36808#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36807#L365-24 assume !(1 == ~t1_pc~0); 36806#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 36805#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36804#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36803#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36802#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36801#L384-24 assume 1 == ~t2_pc~0; 36469#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36467#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36463#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36460#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36458#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36456#L403-24 assume !(1 == ~t3_pc~0); 36454#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 36452#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36450#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36447#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36445#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36443#L422-24 assume !(1 == ~t4_pc~0); 36441#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 36439#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36437#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36434#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 36432#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36430#L441-24 assume 1 == ~t5_pc~0; 36427#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36425#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34815#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34813#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34811#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34809#L460-24 assume 1 == ~t6_pc~0; 34806#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34804#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34802#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34800#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34798#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34796#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34794#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34792#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34790#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34788#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34786#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31259#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31260#L804-3 assume !(1 == ~E_M~0); 31601#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31255#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31256#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31407#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31393#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31394#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36754#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 36740#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 36732#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31174#L1084 assume !(0 == start_simulation_~tmp~3#1); 31176#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31423#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31150#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31204#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31205#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31270#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31271#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31820#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 31371#L1065-2 [2024-11-13 15:43:20,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:20,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2024-11-13 15:43:20,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:20,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980081279] [2024-11-13 15:43:20,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:20,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:20,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:20,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:20,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:20,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980081279] [2024-11-13 15:43:20,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980081279] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:20,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:20,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:20,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255980027] [2024-11-13 15:43:20,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:20,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:20,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:20,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1898970846, now seen corresponding path program 1 times [2024-11-13 15:43:20,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:20,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842884854] [2024-11-13 15:43:20,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:20,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:20,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:20,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:20,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:20,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842884854] [2024-11-13 15:43:20,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842884854] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:20,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:20,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:20,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987709998] [2024-11-13 15:43:20,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:20,558 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:20,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:20,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:20,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:20,560 INFO L87 Difference]: Start difference. First operand 7358 states and 10709 transitions. cyclomatic complexity: 3367 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:20,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:20,971 INFO L93 Difference]: Finished difference Result 7673 states and 11024 transitions. [2024-11-13 15:43:20,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7673 states and 11024 transitions. [2024-11-13 15:43:21,013 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7528 [2024-11-13 15:43:21,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7673 states to 7673 states and 11024 transitions. [2024-11-13 15:43:21,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7673 [2024-11-13 15:43:21,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7673 [2024-11-13 15:43:21,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7673 states and 11024 transitions. [2024-11-13 15:43:21,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:21,067 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-11-13 15:43:21,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7673 states and 11024 transitions. [2024-11-13 15:43:21,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7673 to 7673. [2024-11-13 15:43:21,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7673 states, 7673 states have (on average 1.4367261827186237) internal successors, (11024), 7672 states have internal predecessors, (11024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:21,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7673 states to 7673 states and 11024 transitions. [2024-11-13 15:43:21,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-11-13 15:43:21,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:21,425 INFO L424 stractBuchiCegarLoop]: Abstraction has 7673 states and 11024 transitions. [2024-11-13 15:43:21,425 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:43:21,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7673 states and 11024 transitions. [2024-11-13 15:43:21,465 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7528 [2024-11-13 15:43:21,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:21,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:21,468 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:21,468 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:21,468 INFO L745 eck$LassoCheckResult]: Stem: 46511#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 46512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 46699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46866#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 46407#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46408#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46240#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46241#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46217#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46218#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46381#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46548#L696 assume !(0 == ~M_E~0); 46549#L696-2 assume !(0 == ~T1_E~0); 46877#L701-1 assume !(0 == ~T2_E~0); 46879#L706-1 assume !(0 == ~T3_E~0); 46672#L711-1 assume !(0 == ~T4_E~0); 46441#L716-1 assume !(0 == ~T5_E~0); 46442#L721-1 assume !(0 == ~T6_E~0); 46622#L726-1 assume !(0 == ~E_M~0); 46623#L731-1 assume !(0 == ~E_1~0); 46588#L736-1 assume !(0 == ~E_2~0); 46589#L741-1 assume !(0 == ~E_3~0); 46682#L746-1 assume !(0 == ~E_4~0); 46466#L751-1 assume !(0 == ~E_5~0); 46467#L756-1 assume !(0 == ~E_6~0); 46438#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46262#L346 assume !(1 == ~m_pc~0); 46263#L346-2 is_master_triggered_~__retres1~0#1 := 0; 46481#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46473#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46474#L861 assume !(0 != activate_threads_~tmp~1#1); 46842#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46296#L365 assume !(1 == ~t1_pc~0); 46297#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46854#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46247#L869 assume !(0 != activate_threads_~tmp___0~0#1); 46286#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46739#L384 assume !(1 == ~t2_pc~0); 46733#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46734#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46701#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46206#L877 assume !(0 != activate_threads_~tmp___1~0#1); 46207#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46565#L403 assume !(1 == ~t3_pc~0); 46566#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46779#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46181#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46182#L885 assume !(0 != activate_threads_~tmp___2~0#1); 46558#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46559#L422 assume !(1 == ~t4_pc~0); 46697#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46698#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46349#L893 assume !(0 != activate_threads_~tmp___3~0#1); 46647#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46219#L441 assume !(1 == ~t5_pc~0); 46220#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46837#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46980#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46975#L901 assume !(0 != activate_threads_~tmp___4~0#1); 46658#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46659#L460 assume 1 == ~t6_pc~0; 46168#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46169#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46227#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46684#L909 assume !(0 != activate_threads_~tmp___5~0#1); 46795#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46632#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 46633#L774-2 assume !(1 == ~T1_E~0); 50260#L779-1 assume !(1 == ~T2_E~0); 50259#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50258#L789-1 assume !(1 == ~T4_E~0); 50256#L794-1 assume !(1 == ~T5_E~0); 50255#L799-1 assume !(1 == ~T6_E~0); 50247#L804-1 assume !(1 == ~E_M~0); 46932#L809-1 assume !(1 == ~E_1~0); 50244#L814-1 assume !(1 == ~E_2~0); 46185#L819-1 assume !(1 == ~E_3~0); 46186#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46692#L829-1 assume !(1 == ~E_5~0); 46960#L834-1 assume !(1 == ~E_6~0); 46424#L839-1 assume { :end_inline_reset_delta_events } true; 46411#L1065-2 [2024-11-13 15:43:21,469 INFO L747 eck$LassoCheckResult]: Loop: 46411#L1065-2 assume !false; 46412#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46383#L671-1 assume !false; 46772#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 50193#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 50187#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 50185#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50181#L582 assume !(0 != eval_~tmp~0#1); 50182#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53835#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53834#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53833#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53832#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53831#L706-3 assume !(0 == ~T3_E~0); 53830#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53829#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53828#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53827#L726-3 assume !(0 == ~E_M~0); 53826#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53825#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53824#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53823#L746-3 assume !(0 == ~E_4~0); 53822#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53821#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53820#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53819#L346-24 assume 1 == ~m_pc~0; 46789#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46431#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46379#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46380#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46813#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46374#L365-24 assume !(1 == ~t1_pc~0); 46375#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 46962#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46872#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46767#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46768#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46321#L384-24 assume 1 == ~t2_pc~0; 46322#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46343#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46957#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46967#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46352#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46353#L403-24 assume !(1 == ~t3_pc~0); 46468#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 46513#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46514#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46613#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46614#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46409#L422-24 assume !(1 == ~t4_pc~0); 46410#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 46360#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46361#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46845#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 46822#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46425#L441-24 assume 1 == ~t5_pc~0; 46426#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46740#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53767#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53761#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53741#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46741#L460-24 assume !(1 == ~t6_pc~0); 46742#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 46817#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46464#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46465#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46735#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46736#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46660#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46661#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46204#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46205#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46187#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46188#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46298#L804-3 assume !(1 == ~E_M~0); 46637#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46865#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53464#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53462#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53460#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53459#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46279#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46280#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46277#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46370#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 46214#L1084 assume !(0 == start_simulation_~tmp~3#1); 46216#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46462#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46190#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46244#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 46245#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46308#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46309#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 46475#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 46411#L1065-2 [2024-11-13 15:43:21,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:21,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2024-11-13 15:43:21,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:21,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458777569] [2024-11-13 15:43:21,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:21,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:21,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:21,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:21,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:21,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458777569] [2024-11-13 15:43:21,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458777569] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:21,556 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:21,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:21,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219119012] [2024-11-13 15:43:21,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:21,557 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:21,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:21,559 INFO L85 PathProgramCache]: Analyzing trace with hash 322413087, now seen corresponding path program 1 times [2024-11-13 15:43:21,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:21,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635685527] [2024-11-13 15:43:21,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:21,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:21,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:21,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:21,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:21,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635685527] [2024-11-13 15:43:21,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635685527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:21,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:21,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:21,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321386617] [2024-11-13 15:43:21,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:21,633 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:21,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:21,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:21,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:21,634 INFO L87 Difference]: Start difference. First operand 7673 states and 11024 transitions. cyclomatic complexity: 3367 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:21,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:21,841 INFO L93 Difference]: Finished difference Result 14708 states and 21001 transitions. [2024-11-13 15:43:21,841 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14708 states and 21001 transitions. [2024-11-13 15:43:21,949 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14492 [2024-11-13 15:43:22,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14708 states to 14708 states and 21001 transitions. [2024-11-13 15:43:22,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14708 [2024-11-13 15:43:22,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14708 [2024-11-13 15:43:22,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14708 states and 21001 transitions. [2024-11-13 15:43:22,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:22,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14708 states and 21001 transitions. [2024-11-13 15:43:22,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14708 states and 21001 transitions. [2024-11-13 15:43:22,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14708 to 14676. [2024-11-13 15:43:22,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14676 states, 14676 states have (on average 1.4287953120741346) internal successors, (20969), 14675 states have internal predecessors, (20969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:22,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14676 states to 14676 states and 20969 transitions. [2024-11-13 15:43:22,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2024-11-13 15:43:22,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:22,481 INFO L424 stractBuchiCegarLoop]: Abstraction has 14676 states and 20969 transitions. [2024-11-13 15:43:22,482 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:43:22,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14676 states and 20969 transitions. [2024-11-13 15:43:22,531 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14460 [2024-11-13 15:43:22,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:22,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:22,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:22,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:22,533 INFO L745 eck$LassoCheckResult]: Stem: 68897#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 68898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 69081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69082#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69249#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 68797#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68798#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68631#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68632#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68605#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68606#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68771#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68931#L696 assume !(0 == ~M_E~0); 68932#L696-2 assume !(0 == ~T1_E~0); 69255#L701-1 assume !(0 == ~T2_E~0); 69257#L706-1 assume !(0 == ~T3_E~0); 69054#L711-1 assume !(0 == ~T4_E~0); 68832#L716-1 assume !(0 == ~T5_E~0); 68833#L721-1 assume !(0 == ~T6_E~0); 69008#L726-1 assume !(0 == ~E_M~0); 69009#L731-1 assume !(0 == ~E_1~0); 68971#L736-1 assume !(0 == ~E_2~0); 68972#L741-1 assume !(0 == ~E_3~0); 69064#L746-1 assume !(0 == ~E_4~0); 68854#L751-1 assume !(0 == ~E_5~0); 68855#L756-1 assume !(0 == ~E_6~0); 68829#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68649#L346 assume !(1 == ~m_pc~0); 68650#L346-2 is_master_triggered_~__retres1~0#1 := 0; 68869#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68859#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68860#L861 assume !(0 != activate_threads_~tmp~1#1); 69227#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68684#L365 assume !(1 == ~t1_pc~0); 68685#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69240#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68635#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68636#L869 assume !(0 != activate_threads_~tmp___0~0#1); 68673#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69120#L384 assume !(1 == ~t2_pc~0); 69116#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69117#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68593#L877 assume !(0 != activate_threads_~tmp___1~0#1); 68594#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68950#L403 assume !(1 == ~t3_pc~0); 68951#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69162#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68568#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68569#L885 assume !(0 != activate_threads_~tmp___2~0#1); 68943#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68944#L422 assume !(1 == ~t4_pc~0); 69079#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69080#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68737#L893 assume !(0 != activate_threads_~tmp___3~0#1); 69033#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68607#L441 assume !(1 == ~t5_pc~0); 68608#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69223#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68872#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68873#L901 assume !(0 != activate_threads_~tmp___4~0#1); 69043#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69044#L460 assume !(1 == ~t6_pc~0); 69184#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68614#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68615#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69066#L909 assume !(0 != activate_threads_~tmp___5~0#1); 69181#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69018#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 69019#L774-2 assume !(1 == ~T1_E~0); 69200#L779-1 assume !(1 == ~T2_E~0); 68916#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68917#L789-1 assume !(1 == ~T4_E~0); 69285#L794-1 assume !(1 == ~T5_E~0); 74715#L799-1 assume !(1 == ~T6_E~0); 74712#L804-1 assume !(1 == ~E_M~0); 69296#L809-1 assume !(1 == ~E_1~0); 74709#L814-1 assume !(1 == ~E_2~0); 74707#L819-1 assume !(1 == ~E_3~0); 74705#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 74703#L829-1 assume !(1 == ~E_5~0); 74701#L834-1 assume !(1 == ~E_6~0); 74665#L839-1 assume { :end_inline_reset_delta_events } true; 74663#L1065-2 [2024-11-13 15:43:22,534 INFO L747 eck$LassoCheckResult]: Loop: 74663#L1065-2 assume !false; 74661#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74656#L671-1 assume !false; 74654#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 74649#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 74643#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 74640#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 74638#L582 assume !(0 != eval_~tmp~0#1); 74639#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75402#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75399#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 75397#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75395#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75393#L706-3 assume !(0 == ~T3_E~0); 75391#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75389#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75387#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75385#L726-3 assume !(0 == ~E_M~0); 75383#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75381#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75379#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75377#L746-3 assume !(0 == ~E_4~0); 75375#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 75373#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 75371#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75369#L346-24 assume !(1 == ~m_pc~0); 75367#L346-26 is_master_triggered_~__retres1~0#1 := 0; 75362#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75360#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75358#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75356#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75353#L365-24 assume !(1 == ~t1_pc~0); 75351#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 75349#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75347#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75345#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75343#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75341#L384-24 assume !(1 == ~t2_pc~0); 75339#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 75336#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75332#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75331#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75328#L403-24 assume !(1 == ~t3_pc~0); 75324#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 75320#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75316#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75312#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75308#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75307#L422-24 assume !(1 == ~t4_pc~0); 75306#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 75305#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75304#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75303#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 75302#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75301#L441-24 assume !(1 == ~t5_pc~0); 75299#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 75297#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75295#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75294#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 75292#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75284#L460-24 assume !(1 == ~t6_pc~0); 75282#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 75280#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75278#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75276#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75274#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75272#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 75132#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75269#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75267#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75265#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75264#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75263#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75114#L804-3 assume !(1 == ~E_M~0); 75112#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75110#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75108#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75106#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75104#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75102#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75100#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 75097#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75089#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 75087#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 75063#L1084 assume !(0 == start_simulation_~tmp~3#1); 75058#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 74684#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 74677#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 74675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 74673#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74671#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74668#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 74666#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 74663#L1065-2 [2024-11-13 15:43:22,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:22,535 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2024-11-13 15:43:22,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:22,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158251269] [2024-11-13 15:43:22,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:22,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:22,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:22,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:22,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:22,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158251269] [2024-11-13 15:43:22,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158251269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:22,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:22,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:43:22,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572393721] [2024-11-13 15:43:22,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:22,601 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:22,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:22,601 INFO L85 PathProgramCache]: Analyzing trace with hash -100624604, now seen corresponding path program 1 times [2024-11-13 15:43:22,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:22,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241767544] [2024-11-13 15:43:22,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:22,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:22,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:22,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:22,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:22,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241767544] [2024-11-13 15:43:22,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241767544] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:22,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:22,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:22,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74970487] [2024-11-13 15:43:22,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:22,683 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:22,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:22,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:22,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:22,684 INFO L87 Difference]: Start difference. First operand 14676 states and 20969 transitions. cyclomatic complexity: 6325 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:22,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:22,914 INFO L93 Difference]: Finished difference Result 21861 states and 31258 transitions. [2024-11-13 15:43:22,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21861 states and 31258 transitions. [2024-11-13 15:43:23,010 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2024-11-13 15:43:23,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21861 states to 21861 states and 31258 transitions. [2024-11-13 15:43:23,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21861 [2024-11-13 15:43:23,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21861 [2024-11-13 15:43:23,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21861 states and 31258 transitions. [2024-11-13 15:43:23,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:23,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21861 states and 31258 transitions. [2024-11-13 15:43:23,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21861 states and 31258 transitions. [2024-11-13 15:43:23,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21861 to 15306. [2024-11-13 15:43:23,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4321834574676597) internal successors, (21921), 15305 states have internal predecessors, (21921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:23,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21921 transitions. [2024-11-13 15:43:23,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2024-11-13 15:43:23,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:23,669 INFO L424 stractBuchiCegarLoop]: Abstraction has 15306 states and 21921 transitions. [2024-11-13 15:43:23,669 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:43:23,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21921 transitions. [2024-11-13 15:43:23,740 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-11-13 15:43:23,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:23,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:23,743 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:23,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:23,743 INFO L745 eck$LassoCheckResult]: Stem: 105450#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 105451#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 105639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105830#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 105344#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105345#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105177#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105178#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105151#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105152#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105321#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105483#L696 assume !(0 == ~M_E~0); 105484#L696-2 assume !(0 == ~T1_E~0); 105835#L701-1 assume !(0 == ~T2_E~0); 105837#L706-1 assume !(0 == ~T3_E~0); 105609#L711-1 assume !(0 == ~T4_E~0); 105379#L716-1 assume !(0 == ~T5_E~0); 105380#L721-1 assume !(0 == ~T6_E~0); 105554#L726-1 assume !(0 == ~E_M~0); 105555#L731-1 assume !(0 == ~E_1~0); 105520#L736-1 assume !(0 == ~E_2~0); 105521#L741-1 assume !(0 == ~E_3~0); 105620#L746-1 assume !(0 == ~E_4~0); 105403#L751-1 assume !(0 == ~E_5~0); 105404#L756-1 assume !(0 == ~E_6~0); 105376#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105198#L346 assume !(1 == ~m_pc~0); 105199#L346-2 is_master_triggered_~__retres1~0#1 := 0; 105420#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105409#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105410#L861 assume !(0 != activate_threads_~tmp~1#1); 105802#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105232#L365 assume !(1 == ~t1_pc~0); 105233#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105819#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105184#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105185#L869 assume !(0 != activate_threads_~tmp___0~0#1); 105221#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105682#L384 assume !(1 == ~t2_pc~0); 105678#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105679#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105141#L877 assume !(0 != activate_threads_~tmp___1~0#1); 105142#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105499#L403 assume !(1 == ~t3_pc~0); 105500#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105729#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105112#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105113#L885 assume !(0 != activate_threads_~tmp___2~0#1); 105493#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105494#L422 assume !(1 == ~t4_pc~0); 105637#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105638#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105285#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 105286#L893 assume !(0 != activate_threads_~tmp___3~0#1); 105582#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105153#L441 assume !(1 == ~t5_pc~0); 105154#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 105797#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105423#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105424#L901 assume !(0 != activate_threads_~tmp___4~0#1); 105596#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105597#L460 assume !(1 == ~t6_pc~0); 105755#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105162#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105163#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105622#L909 assume !(0 != activate_threads_~tmp___5~0#1); 105750#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105568#L774 assume !(1 == ~M_E~0); 105569#L774-2 assume !(1 == ~T1_E~0); 105771#L779-1 assume !(1 == ~T2_E~0); 105467#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105468#L789-1 assume !(1 == ~T4_E~0); 105215#L794-1 assume !(1 == ~T5_E~0); 105216#L799-1 assume !(1 == ~T6_E~0); 105879#L804-1 assume !(1 == ~E_M~0); 105880#L809-1 assume !(1 == ~E_1~0); 105552#L814-1 assume !(1 == ~E_2~0); 105118#L819-1 assume !(1 == ~E_3~0); 105119#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 105630#L829-1 assume !(1 == ~E_5~0); 105758#L834-1 assume !(1 == ~E_6~0); 105364#L839-1 assume { :end_inline_reset_delta_events } true; 105365#L1065-2 [2024-11-13 15:43:23,744 INFO L747 eck$LassoCheckResult]: Loop: 105365#L1065-2 assume !false; 114837#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114832#L671-1 assume !false; 114830#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 114825#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 114819#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 114816#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 114814#L582 assume !(0 != eval_~tmp~0#1); 114815#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120242#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120241#L696-3 assume !(0 == ~M_E~0); 120239#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 120238#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120237#L706-3 assume !(0 == ~T3_E~0); 120233#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 120231#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 120229#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 120227#L726-3 assume !(0 == ~E_M~0); 120224#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 120222#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 120220#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 120218#L746-3 assume !(0 == ~E_4~0); 120216#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 120214#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120212#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 120210#L346-24 assume !(1 == ~m_pc~0); 120059#L346-26 is_master_triggered_~__retres1~0#1 := 0; 119815#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119814#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119813#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119812#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119810#L365-24 assume !(1 == ~t1_pc~0); 119809#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 119808#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119807#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119806#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119805#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119804#L384-24 assume !(1 == ~t2_pc~0); 119803#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 119801#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119800#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119799#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119798#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119797#L403-24 assume !(1 == ~t3_pc~0); 119796#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 119795#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119794#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119793#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119791#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119790#L422-24 assume !(1 == ~t4_pc~0); 119789#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 119788#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119786#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119784#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 119782#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119780#L441-24 assume !(1 == ~t5_pc~0); 119776#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 119774#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119772#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119770#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 119767#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119765#L460-24 assume !(1 == ~t6_pc~0); 119763#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 119761#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119759#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119757#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119755#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119753#L774-3 assume !(1 == ~M_E~0); 110677#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119749#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119747#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119745#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119743#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119741#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 119739#L804-3 assume !(1 == ~E_M~0); 119736#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119734#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119732#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119730#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119728#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119726#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119723#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119720#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119712#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119399#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 110752#L1084 assume !(0 == start_simulation_~tmp~3#1); 110753#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 114858#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 114851#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 114849#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 114847#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114845#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 114842#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 114840#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 105365#L1065-2 [2024-11-13 15:43:23,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:23,744 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2024-11-13 15:43:23,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:23,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665914667] [2024-11-13 15:43:23,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:23,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:23,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:23,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:23,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:23,938 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665914667] [2024-11-13 15:43:23,938 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665914667] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:23,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:23,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:23,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706537473] [2024-11-13 15:43:23,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:23,939 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:23,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:23,939 INFO L85 PathProgramCache]: Analyzing trace with hash -56527516, now seen corresponding path program 1 times [2024-11-13 15:43:23,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:23,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674520401] [2024-11-13 15:43:23,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:23,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:23,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:24,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:24,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:24,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674520401] [2024-11-13 15:43:24,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674520401] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:24,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:24,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:24,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788979842] [2024-11-13 15:43:24,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:24,059 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:24,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:24,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:43:24,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:43:24,060 INFO L87 Difference]: Start difference. First operand 15306 states and 21921 transitions. cyclomatic complexity: 6631 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:24,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:24,279 INFO L93 Difference]: Finished difference Result 24428 states and 34861 transitions. [2024-11-13 15:43:24,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24428 states and 34861 transitions. [2024-11-13 15:43:24,411 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24096 [2024-11-13 15:43:24,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24428 states to 24428 states and 34861 transitions. [2024-11-13 15:43:24,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24428 [2024-11-13 15:43:24,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24428 [2024-11-13 15:43:24,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24428 states and 34861 transitions. [2024-11-13 15:43:24,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:24,603 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24428 states and 34861 transitions. [2024-11-13 15:43:24,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24428 states and 34861 transitions. [2024-11-13 15:43:25,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24428 to 17449. [2024-11-13 15:43:25,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.4309129463006476) internal successors, (24968), 17448 states have internal predecessors, (24968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:25,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24968 transitions. [2024-11-13 15:43:25,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2024-11-13 15:43:25,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:43:25,110 INFO L424 stractBuchiCegarLoop]: Abstraction has 17449 states and 24968 transitions. [2024-11-13 15:43:25,110 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:43:25,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24968 transitions. [2024-11-13 15:43:25,165 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2024-11-13 15:43:25,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:25,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:25,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:25,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:25,167 INFO L745 eck$LassoCheckResult]: Stem: 145187#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 145188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 145364#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145365#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145544#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 145086#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145087#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144922#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144923#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144896#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144897#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 145064#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145220#L696 assume !(0 == ~M_E~0); 145221#L696-2 assume !(0 == ~T1_E~0); 145551#L701-1 assume !(0 == ~T2_E~0); 145553#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 145337#L711-1 assume !(0 == ~T4_E~0); 145120#L716-1 assume !(0 == ~T5_E~0); 145121#L721-1 assume !(0 == ~T6_E~0); 145292#L726-1 assume !(0 == ~E_M~0); 145293#L731-1 assume !(0 == ~E_1~0); 145257#L736-1 assume !(0 == ~E_2~0); 145258#L741-1 assume !(0 == ~E_3~0); 145615#L746-1 assume !(0 == ~E_4~0); 145616#L751-1 assume !(0 == ~E_5~0); 145688#L756-1 assume !(0 == ~E_6~0); 145117#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144942#L346 assume !(1 == ~m_pc~0); 144943#L346-2 is_master_triggered_~__retres1~0#1 := 0; 145160#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145149#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145150#L861 assume !(0 != activate_threads_~tmp~1#1); 145682#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144975#L365 assume !(1 == ~t1_pc~0); 144976#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145529#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145679#L869 assume !(0 != activate_threads_~tmp___0~0#1); 145678#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145677#L384 assume !(1 == ~t2_pc~0); 145675#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 145617#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144886#L877 assume !(0 != activate_threads_~tmp___1~0#1); 144887#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145237#L403 assume !(1 == ~t3_pc~0); 145238#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145443#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144860#L885 assume !(0 != activate_threads_~tmp___2~0#1); 145230#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145231#L422 assume !(1 == ~t4_pc~0); 145362#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 145363#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 145028#L893 assume !(0 != activate_threads_~tmp___3~0#1); 145495#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145662#L441 assume !(1 == ~t5_pc~0); 145560#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 145661#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145658#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 145655#L901 assume !(0 != activate_threads_~tmp___4~0#1); 145326#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145327#L460 assume !(1 == ~t6_pc~0); 145468#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 145653#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145652#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 145651#L909 assume !(0 != activate_threads_~tmp___5~0#1); 145566#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145567#L774 assume !(1 == ~M_E~0); 145650#L774-2 assume !(1 == ~T1_E~0); 145649#L779-1 assume !(1 == ~T2_E~0); 145648#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145205#L789-1 assume !(1 == ~T4_E~0); 144959#L794-1 assume !(1 == ~T5_E~0); 144960#L799-1 assume !(1 == ~T6_E~0); 145598#L804-1 assume !(1 == ~E_M~0); 145599#L809-1 assume !(1 == ~E_1~0); 145288#L814-1 assume !(1 == ~E_2~0); 144865#L819-1 assume !(1 == ~E_3~0); 144866#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 145357#L829-1 assume !(1 == ~E_5~0); 145472#L834-1 assume !(1 == ~E_6~0); 145106#L839-1 assume { :end_inline_reset_delta_events } true; 145107#L1065-2 [2024-11-13 15:43:25,168 INFO L747 eck$LassoCheckResult]: Loop: 145107#L1065-2 assume !false; 150756#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 150751#L671-1 assume !false; 150749#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 150736#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 150729#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 150727#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 150724#L582 assume !(0 != eval_~tmp~0#1); 150722#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 150720#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150718#L696-3 assume !(0 == ~M_E~0); 150716#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 150715#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 150712#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150711#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 150710#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150709#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 150708#L726-3 assume !(0 == ~E_M~0); 150707#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 150706#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 150705#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 150704#L746-3 assume !(0 == ~E_4~0); 150703#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150702#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 150701#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150700#L346-24 assume 1 == ~m_pc~0; 150698#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 150697#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150696#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 150695#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150694#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150693#L365-24 assume !(1 == ~t1_pc~0); 150692#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 150691#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150690#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150689#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150688#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150687#L384-24 assume !(1 == ~t2_pc~0); 150686#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 150684#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150683#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 150682#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 150681#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150680#L403-24 assume !(1 == ~t3_pc~0); 150679#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 150678#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150677#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 150676#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 150675#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150674#L422-24 assume !(1 == ~t4_pc~0); 150673#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 150672#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150671#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 150670#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 150669#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150668#L441-24 assume 1 == ~t5_pc~0; 150666#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 150664#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150662#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 150660#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 150659#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150658#L460-24 assume !(1 == ~t6_pc~0); 150657#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 150656#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150655#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 150654#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150653#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150652#L774-3 assume !(1 == ~M_E~0); 148870#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 150651#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 150649#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 150647#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 150645#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150643#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 150641#L804-3 assume !(1 == ~E_M~0); 150639#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 150501#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 150491#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 150483#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 150477#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 150406#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 150402#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 150360#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 150343#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 150281#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 149031#L1084 assume !(0 == start_simulation_~tmp~3#1); 149032#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 150774#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 150769#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 150767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 150765#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 150763#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 150761#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 150759#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 145107#L1065-2 [2024-11-13 15:43:25,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:25,169 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2024-11-13 15:43:25,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:25,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481450733] [2024-11-13 15:43:25,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:25,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:25,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:25,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:25,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:25,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481450733] [2024-11-13 15:43:25,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481450733] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:25,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:25,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:25,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910560013] [2024-11-13 15:43:25,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:25,254 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:25,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:25,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1664615582, now seen corresponding path program 1 times [2024-11-13 15:43:25,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:25,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202092079] [2024-11-13 15:43:25,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:25,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:25,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:25,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:25,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:25,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202092079] [2024-11-13 15:43:25,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202092079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:25,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:25,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:25,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136825453] [2024-11-13 15:43:25,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:25,331 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:25,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:25,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:43:25,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:43:25,332 INFO L87 Difference]: Start difference. First operand 17449 states and 24968 transitions. cyclomatic complexity: 7535 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:25,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:25,476 INFO L93 Difference]: Finished difference Result 22274 states and 31679 transitions. [2024-11-13 15:43:25,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22274 states and 31679 transitions. [2024-11-13 15:43:25,571 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22016 [2024-11-13 15:43:25,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22274 states to 22274 states and 31679 transitions. [2024-11-13 15:43:25,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22274 [2024-11-13 15:43:25,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22274 [2024-11-13 15:43:25,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22274 states and 31679 transitions. [2024-11-13 15:43:25,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:25,721 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22274 states and 31679 transitions. [2024-11-13 15:43:25,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22274 states and 31679 transitions. [2024-11-13 15:43:26,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22274 to 15306. [2024-11-13 15:43:26,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.42578073957925) internal successors, (21823), 15305 states have internal predecessors, (21823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:26,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21823 transitions. [2024-11-13 15:43:26,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2024-11-13 15:43:26,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:43:26,179 INFO L424 stractBuchiCegarLoop]: Abstraction has 15306 states and 21823 transitions. [2024-11-13 15:43:26,179 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:43:26,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21823 transitions. [2024-11-13 15:43:26,227 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-11-13 15:43:26,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:26,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:26,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:26,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:26,229 INFO L745 eck$LassoCheckResult]: Stem: 184921#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 184922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 185102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 185266#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 184820#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184821#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184656#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184657#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184629#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 184630#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 184797#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184957#L696 assume !(0 == ~M_E~0); 184958#L696-2 assume !(0 == ~T1_E~0); 185270#L701-1 assume !(0 == ~T2_E~0); 185272#L706-1 assume !(0 == ~T3_E~0); 185073#L711-1 assume !(0 == ~T4_E~0); 184854#L716-1 assume !(0 == ~T5_E~0); 184855#L721-1 assume !(0 == ~T6_E~0); 185029#L726-1 assume !(0 == ~E_M~0); 185030#L731-1 assume !(0 == ~E_1~0); 184993#L736-1 assume !(0 == ~E_2~0); 184994#L741-1 assume !(0 == ~E_3~0); 185083#L746-1 assume !(0 == ~E_4~0); 184877#L751-1 assume !(0 == ~E_5~0); 184878#L756-1 assume !(0 == ~E_6~0); 184851#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184676#L346 assume !(1 == ~m_pc~0); 184677#L346-2 is_master_triggered_~__retres1~0#1 := 0; 184893#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184883#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 184884#L861 assume !(0 != activate_threads_~tmp~1#1); 185239#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184709#L365 assume !(1 == ~t1_pc~0); 184710#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185252#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184662#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 184663#L869 assume !(0 != activate_threads_~tmp___0~0#1); 184698#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185139#L384 assume !(1 == ~t2_pc~0); 185135#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185136#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185108#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 184619#L877 assume !(0 != activate_threads_~tmp___1~0#1); 184620#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184972#L403 assume !(1 == ~t3_pc~0); 184973#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185175#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184592#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 184593#L885 assume !(0 != activate_threads_~tmp___2~0#1); 184967#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184968#L422 assume !(1 == ~t4_pc~0); 185100#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185101#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184760#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 184761#L893 assume !(0 != activate_threads_~tmp___3~0#1); 185052#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 184631#L441 assume !(1 == ~t5_pc~0); 184632#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185235#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184895#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 184896#L901 assume !(0 != activate_threads_~tmp___4~0#1); 185062#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185063#L460 assume !(1 == ~t6_pc~0); 185199#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 184640#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184641#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 185085#L909 assume !(0 != activate_threads_~tmp___5~0#1); 185193#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185039#L774 assume !(1 == ~M_E~0); 185040#L774-2 assume !(1 == ~T1_E~0); 185212#L779-1 assume !(1 == ~T2_E~0); 184939#L784-1 assume !(1 == ~T3_E~0); 184940#L789-1 assume !(1 == ~T4_E~0); 184693#L794-1 assume !(1 == ~T5_E~0); 184694#L799-1 assume !(1 == ~T6_E~0); 185305#L804-1 assume !(1 == ~E_M~0); 185306#L809-1 assume !(1 == ~E_1~0); 185025#L814-1 assume !(1 == ~E_2~0); 184598#L819-1 assume !(1 == ~E_3~0); 184599#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 185091#L829-1 assume !(1 == ~E_5~0); 185202#L834-1 assume !(1 == ~E_6~0); 184840#L839-1 assume { :end_inline_reset_delta_events } true; 184841#L1065-2 [2024-11-13 15:43:26,230 INFO L747 eck$LassoCheckResult]: Loop: 184841#L1065-2 assume !false; 189731#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189720#L671-1 assume !false; 189715#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189709#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189702#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189700#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 189697#L582 assume !(0 != eval_~tmp~0#1); 189695#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 189694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189683#L696-3 assume !(0 == ~M_E~0); 189678#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189673#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 189667#L706-3 assume !(0 == ~T3_E~0); 189662#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 189657#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 189652#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 189645#L726-3 assume !(0 == ~E_M~0); 189640#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189635#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 189629#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189624#L746-3 assume !(0 == ~E_4~0); 189619#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189613#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189608#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189603#L346-24 assume !(1 == ~m_pc~0); 189598#L346-26 is_master_triggered_~__retres1~0#1 := 0; 189592#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189587#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189580#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189575#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189570#L365-24 assume !(1 == ~t1_pc~0); 189563#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 189558#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189553#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189548#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189543#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189538#L384-24 assume 1 == ~t2_pc~0; 189530#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 189525#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189520#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189515#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189510#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189505#L403-24 assume !(1 == ~t3_pc~0); 189499#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 189494#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189489#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189482#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189475#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189468#L422-24 assume !(1 == ~t4_pc~0); 189459#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 189453#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189447#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189440#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 189435#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189430#L441-24 assume 1 == ~t5_pc~0; 189424#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189418#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189412#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189408#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189403#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189398#L460-24 assume !(1 == ~t6_pc~0); 189392#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 189386#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189381#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 189380#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189377#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189375#L774-3 assume !(1 == ~M_E~0); 188218#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189372#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 189370#L784-3 assume !(1 == ~T3_E~0); 189368#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189366#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189364#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189362#L804-3 assume !(1 == ~E_M~0); 189361#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189359#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 189357#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189352#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189347#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189341#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189335#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189330#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189320#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189319#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 188583#L1084 assume !(0 == start_simulation_~tmp~3#1); 188584#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189966#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189955#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189950#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 189948#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189947#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189946#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 189807#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 184841#L1065-2 [2024-11-13 15:43:26,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:26,231 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2024-11-13 15:43:26,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:26,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383907079] [2024-11-13 15:43:26,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:26,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:26,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:26,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:26,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:26,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383907079] [2024-11-13 15:43:26,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383907079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:26,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:26,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:26,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017489280] [2024-11-13 15:43:26,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:26,321 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:26,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:26,322 INFO L85 PathProgramCache]: Analyzing trace with hash 1370125534, now seen corresponding path program 1 times [2024-11-13 15:43:26,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:26,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681707962] [2024-11-13 15:43:26,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:26,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:26,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:26,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:26,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:26,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681707962] [2024-11-13 15:43:26,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681707962] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:26,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:26,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:26,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343979641] [2024-11-13 15:43:26,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:26,555 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:26,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:26,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:43:26,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:43:26,556 INFO L87 Difference]: Start difference. First operand 15306 states and 21823 transitions. cyclomatic complexity: 6533 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:26,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:26,886 INFO L93 Difference]: Finished difference Result 24188 states and 34235 transitions. [2024-11-13 15:43:26,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34235 transitions. [2024-11-13 15:43:27,024 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2024-11-13 15:43:27,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34235 transitions. [2024-11-13 15:43:27,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2024-11-13 15:43:27,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2024-11-13 15:43:27,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34235 transitions. [2024-11-13 15:43:27,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:27,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34235 transitions. [2024-11-13 15:43:27,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34235 transitions. [2024-11-13 15:43:27,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17449. [2024-11-13 15:43:27,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17449 states, 17449 states have (on average 1.41933635165339) internal successors, (24766), 17448 states have internal predecessors, (24766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:27,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17449 states to 17449 states and 24766 transitions. [2024-11-13 15:43:27,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2024-11-13 15:43:27,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:43:27,586 INFO L424 stractBuchiCegarLoop]: Abstraction has 17449 states and 24766 transitions. [2024-11-13 15:43:27,586 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:43:27,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17449 states and 24766 transitions. [2024-11-13 15:43:27,644 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17184 [2024-11-13 15:43:27,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:27,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:27,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:27,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:27,648 INFO L745 eck$LassoCheckResult]: Stem: 224431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 224432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 224616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224794#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 224327#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224328#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224158#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224159#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224135#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224136#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 224302#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 224467#L696 assume !(0 == ~M_E~0); 224468#L696-2 assume !(0 == ~T1_E~0); 224802#L701-1 assume !(0 == ~T2_E~0); 224804#L706-1 assume !(0 == ~T3_E~0); 224586#L711-1 assume !(0 == ~T4_E~0); 224365#L716-1 assume !(0 == ~T5_E~0); 224366#L721-1 assume !(0 == ~T6_E~0); 224541#L726-1 assume !(0 == ~E_M~0); 224542#L731-1 assume !(0 == ~E_1~0); 224507#L736-1 assume !(0 == ~E_2~0); 224508#L741-1 assume !(0 == ~E_3~0); 224596#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 224863#L751-1 assume !(0 == ~E_5~0); 224925#L756-1 assume !(0 == ~E_6~0); 224361#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224362#L346 assume !(1 == ~m_pc~0); 224401#L346-2 is_master_triggered_~__retres1~0#1 := 0; 224402#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224716#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224821#L861 assume !(0 != activate_threads_~tmp~1#1); 224768#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224769#L365 assume !(1 == ~t1_pc~0); 224922#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 224921#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224164#L869 assume !(0 != activate_threads_~tmp___0~0#1); 224203#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224919#L384 assume !(1 == ~t2_pc~0); 224650#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224651#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224618#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224619#L877 assume !(0 != activate_threads_~tmp___1~0#1); 224918#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224917#L403 assume !(1 == ~t3_pc~0); 224916#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224888#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224098#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224099#L885 assume !(0 != activate_threads_~tmp___2~0#1); 224476#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224477#L422 assume !(1 == ~t4_pc~0); 224795#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224911#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224910#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224909#L893 assume !(0 != activate_threads_~tmp___3~0#1); 224564#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224137#L441 assume !(1 == ~t5_pc~0); 224138#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 224860#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 224406#L901 assume !(0 != activate_threads_~tmp___4~0#1); 224893#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224901#L460 assume !(1 == ~t6_pc~0); 224800#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224144#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 224899#L909 assume !(0 != activate_threads_~tmp___5~0#1); 224818#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224819#L774 assume !(1 == ~M_E~0); 224848#L774-2 assume !(1 == ~T1_E~0); 224736#L779-1 assume !(1 == ~T2_E~0); 224452#L784-1 assume !(1 == ~T3_E~0); 224453#L789-1 assume !(1 == ~T4_E~0); 224896#L794-1 assume !(1 == ~T5_E~0); 224884#L799-1 assume !(1 == ~T6_E~0); 224885#L804-1 assume !(1 == ~E_M~0); 224880#L809-1 assume !(1 == ~E_1~0); 224881#L814-1 assume !(1 == ~E_2~0); 224102#L819-1 assume !(1 == ~E_3~0); 224103#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 224608#L829-1 assume !(1 == ~E_5~0); 224726#L834-1 assume !(1 == ~E_6~0); 224345#L839-1 assume { :end_inline_reset_delta_events } true; 224346#L1065-2 [2024-11-13 15:43:27,649 INFO L747 eck$LassoCheckResult]: Loop: 224346#L1065-2 assume !false; 231516#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 231511#L671-1 assume !false; 231509#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 231504#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 231494#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 231489#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 231482#L582 assume !(0 != eval_~tmp~0#1); 231483#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 233094#L696-3 assume !(0 == ~M_E~0); 233092#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 233091#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 233089#L706-3 assume !(0 == ~T3_E~0); 233087#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 233085#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 233083#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 233081#L726-3 assume !(0 == ~E_M~0); 233079#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 233077#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 233075#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 233072#L746-3 assume !(0 == ~E_4~0); 233073#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 233145#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 233144#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233143#L346-24 assume !(1 == ~m_pc~0); 233142#L346-26 is_master_triggered_~__retres1~0#1 := 0; 233140#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233139#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233138#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 233137#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233136#L365-24 assume !(1 == ~t1_pc~0); 233135#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 233134#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233133#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 233132#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 233131#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233130#L384-24 assume !(1 == ~t2_pc~0); 233129#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 233127#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233126#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233125#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233124#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233123#L403-24 assume !(1 == ~t3_pc~0); 233122#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 233121#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233120#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233119#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 233118#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233117#L422-24 assume !(1 == ~t4_pc~0); 233116#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 233115#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233114#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 233113#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 233112#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 233111#L441-24 assume !(1 == ~t5_pc~0); 233110#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 233108#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233106#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 233104#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 233102#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233101#L460-24 assume !(1 == ~t6_pc~0); 233100#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 233099#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 233098#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 233097#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 233095#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 233093#L774-3 assume !(1 == ~M_E~0); 227296#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 233090#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 233088#L784-3 assume !(1 == ~T3_E~0); 233086#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 233084#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 233082#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 233080#L804-3 assume !(1 == ~E_M~0); 233078#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 233076#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 233074#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 232767#L824-3 assume !(1 == ~E_4~0); 232757#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 232753#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 232750#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232747#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232738#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 227446#L1084 assume !(0 == start_simulation_~tmp~3#1); 227447#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 231534#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 231529#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 231527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 231525#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 231523#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 231521#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 231519#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 224346#L1065-2 [2024-11-13 15:43:27,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:27,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2024-11-13 15:43:27,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:27,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773134604] [2024-11-13 15:43:27,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:27,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:27,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:27,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:27,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:27,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773134604] [2024-11-13 15:43:27,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773134604] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:27,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:27,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:27,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841284762] [2024-11-13 15:43:27,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:27,736 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:43:27,737 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:27,737 INFO L85 PathProgramCache]: Analyzing trace with hash -1211609376, now seen corresponding path program 1 times [2024-11-13 15:43:27,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:27,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877507462] [2024-11-13 15:43:27,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:27,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:27,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:27,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:27,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:27,820 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877507462] [2024-11-13 15:43:27,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877507462] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:27,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:27,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:27,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320697209] [2024-11-13 15:43:27,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:27,821 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:27,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:27,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:43:27,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:43:27,822 INFO L87 Difference]: Start difference. First operand 17449 states and 24766 transitions. cyclomatic complexity: 7333 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:28,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:28,008 INFO L93 Difference]: Finished difference Result 21862 states and 30841 transitions. [2024-11-13 15:43:28,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21862 states and 30841 transitions. [2024-11-13 15:43:28,095 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21596 [2024-11-13 15:43:28,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21862 states to 21862 states and 30841 transitions. [2024-11-13 15:43:28,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21862 [2024-11-13 15:43:28,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21862 [2024-11-13 15:43:28,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21862 states and 30841 transitions. [2024-11-13 15:43:28,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:28,204 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21862 states and 30841 transitions. [2024-11-13 15:43:28,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21862 states and 30841 transitions. [2024-11-13 15:43:28,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21862 to 15306. [2024-11-13 15:43:28,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15306 states, 15306 states have (on average 1.4125833006664053) internal successors, (21621), 15305 states have internal predecessors, (21621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:28,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15306 states to 15306 states and 21621 transitions. [2024-11-13 15:43:28,601 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2024-11-13 15:43:28,601 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:43:28,602 INFO L424 stractBuchiCegarLoop]: Abstraction has 15306 states and 21621 transitions. [2024-11-13 15:43:28,602 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:43:28,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15306 states and 21621 transitions. [2024-11-13 15:43:28,650 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15104 [2024-11-13 15:43:28,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:28,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:28,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:28,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:28,652 INFO L745 eck$LassoCheckResult]: Stem: 263758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 263759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 263929#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 263930#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264086#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 263654#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263655#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263484#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263485#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263459#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263460#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 263628#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263792#L696 assume !(0 == ~M_E~0); 263793#L696-2 assume !(0 == ~T1_E~0); 264092#L701-1 assume !(0 == ~T2_E~0); 264095#L706-1 assume !(0 == ~T3_E~0); 263905#L711-1 assume !(0 == ~T4_E~0); 263689#L716-1 assume !(0 == ~T5_E~0); 263690#L721-1 assume !(0 == ~T6_E~0); 263860#L726-1 assume !(0 == ~E_M~0); 263861#L731-1 assume !(0 == ~E_1~0); 263829#L736-1 assume !(0 == ~E_2~0); 263830#L741-1 assume !(0 == ~E_3~0); 263915#L746-1 assume !(0 == ~E_4~0); 263713#L751-1 assume !(0 == ~E_5~0); 263714#L756-1 assume !(0 == ~E_6~0); 263686#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 263505#L346 assume !(1 == ~m_pc~0); 263506#L346-2 is_master_triggered_~__retres1~0#1 := 0; 263727#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 263719#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 263720#L861 assume !(0 != activate_threads_~tmp~1#1); 264066#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263540#L365 assume !(1 == ~t1_pc~0); 263541#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264078#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263490#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 263491#L869 assume !(0 != activate_threads_~tmp___0~0#1); 263529#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263969#L384 assume !(1 == ~t2_pc~0); 263966#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 263967#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 263933#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263448#L877 assume !(0 != activate_threads_~tmp___1~0#1); 263449#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263808#L403 assume !(1 == ~t3_pc~0); 263809#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264004#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263421#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 263422#L885 assume !(0 != activate_threads_~tmp___2~0#1); 263804#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263805#L422 assume !(1 == ~t4_pc~0); 263927#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 263928#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 263593#L893 assume !(0 != activate_threads_~tmp___3~0#1); 263884#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263461#L441 assume !(1 == ~t5_pc~0); 263462#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264062#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 263730#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 263731#L901 assume !(0 != activate_threads_~tmp___4~0#1); 263894#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 263895#L460 assume !(1 == ~t6_pc~0); 264022#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 263468#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 263469#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 263917#L909 assume !(0 != activate_threads_~tmp___5~0#1); 264019#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263871#L774 assume !(1 == ~M_E~0); 263872#L774-2 assume !(1 == ~T1_E~0); 264037#L779-1 assume !(1 == ~T2_E~0); 263777#L784-1 assume !(1 == ~T3_E~0); 263778#L789-1 assume !(1 == ~T4_E~0); 263524#L794-1 assume !(1 == ~T5_E~0); 263525#L799-1 assume !(1 == ~T6_E~0); 264127#L804-1 assume !(1 == ~E_M~0); 264128#L809-1 assume !(1 == ~E_1~0); 263857#L814-1 assume !(1 == ~E_2~0); 263427#L819-1 assume !(1 == ~E_3~0); 263428#L824-1 assume !(1 == ~E_4~0); 263923#L829-1 assume !(1 == ~E_5~0); 264027#L834-1 assume !(1 == ~E_6~0); 263674#L839-1 assume { :end_inline_reset_delta_events } true; 263675#L1065-2 [2024-11-13 15:43:28,653 INFO L747 eck$LassoCheckResult]: Loop: 263675#L1065-2 assume !false; 268433#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 268429#L671-1 assume !false; 268428#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 268426#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 268420#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 268419#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 268417#L582 assume !(0 != eval_~tmp~0#1); 268416#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 268408#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 268406#L696-3 assume !(0 == ~M_E~0); 268404#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 268401#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 268399#L706-3 assume !(0 == ~T3_E~0); 268397#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 268395#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 268393#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 268391#L726-3 assume !(0 == ~E_M~0); 268389#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 268387#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 268385#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 268383#L746-3 assume !(0 == ~E_4~0); 268381#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 268379#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 268377#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 268375#L346-24 assume 1 == ~m_pc~0; 268372#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 268370#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268368#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 268366#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 268364#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 268361#L365-24 assume !(1 == ~t1_pc~0); 268359#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 268357#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 268355#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 268353#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 268351#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 268350#L384-24 assume 1 == ~t2_pc~0; 268348#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 268345#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268343#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268341#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 268339#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 268337#L403-24 assume !(1 == ~t3_pc~0); 268335#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 268332#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268330#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268328#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 268326#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 268324#L422-24 assume !(1 == ~t4_pc~0); 268322#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 268320#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268318#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 268316#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 268314#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 268312#L441-24 assume 1 == ~t5_pc~0; 268308#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 268306#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268304#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268300#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 268298#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 268294#L460-24 assume !(1 == ~t6_pc~0); 268292#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 268290#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268288#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268285#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 268283#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268281#L774-3 assume !(1 == ~M_E~0); 267433#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 268277#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 268275#L784-3 assume !(1 == ~T3_E~0); 268273#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 268271#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 268269#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 268268#L804-3 assume !(1 == ~E_M~0); 268266#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 268264#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 268262#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 268260#L824-3 assume !(1 == ~E_4~0); 268258#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268256#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 268254#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 268251#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 268243#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 268207#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 268204#L1084 assume !(0 == start_simulation_~tmp~3#1); 268205#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 268460#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 268456#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 268453#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 268449#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 268445#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 268441#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 268437#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 263675#L1065-2 [2024-11-13 15:43:28,653 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:28,653 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2024-11-13 15:43:28,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:28,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743793682] [2024-11-13 15:43:28,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:28,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:28,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:28,838 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:28,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:28,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:28,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:28,985 INFO L85 PathProgramCache]: Analyzing trace with hash -788571685, now seen corresponding path program 1 times [2024-11-13 15:43:28,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:28,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460220309] [2024-11-13 15:43:28,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:28,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:29,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:29,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:29,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:29,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460220309] [2024-11-13 15:43:29,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460220309] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:29,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:29,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:29,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323126948] [2024-11-13 15:43:29,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:29,143 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:29,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:29,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:29,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:29,143 INFO L87 Difference]: Start difference. First operand 15306 states and 21621 transitions. cyclomatic complexity: 6331 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:29,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:29,465 INFO L93 Difference]: Finished difference Result 28407 states and 39618 transitions. [2024-11-13 15:43:29,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28407 states and 39618 transitions. [2024-11-13 15:43:29,616 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28040 [2024-11-13 15:43:29,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28407 states to 28407 states and 39618 transitions. [2024-11-13 15:43:29,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28407 [2024-11-13 15:43:29,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28407 [2024-11-13 15:43:29,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28407 states and 39618 transitions. [2024-11-13 15:43:29,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:29,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28407 states and 39618 transitions. [2024-11-13 15:43:29,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28407 states and 39618 transitions. [2024-11-13 15:43:30,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28407 to 28391. [2024-11-13 15:43:30,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28391 states, 28391 states have (on average 1.3948786587298792) internal successors, (39602), 28390 states have internal predecessors, (39602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:30,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28391 states to 28391 states and 39602 transitions. [2024-11-13 15:43:30,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28391 states and 39602 transitions. [2024-11-13 15:43:30,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:30,240 INFO L424 stractBuchiCegarLoop]: Abstraction has 28391 states and 39602 transitions. [2024-11-13 15:43:30,240 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:43:30,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28391 states and 39602 transitions. [2024-11-13 15:43:30,328 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28024 [2024-11-13 15:43:30,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:30,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:30,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:30,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:30,330 INFO L745 eck$LassoCheckResult]: Stem: 307468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 307469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 307653#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307654#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 307836#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 307369#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307370#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307199#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307200#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307176#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 307177#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 307343#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307503#L696 assume !(0 == ~M_E~0); 307504#L696-2 assume !(0 == ~T1_E~0); 307845#L701-1 assume !(0 == ~T2_E~0); 307847#L706-1 assume !(0 == ~T3_E~0); 307624#L711-1 assume !(0 == ~T4_E~0); 307402#L716-1 assume !(0 == ~T5_E~0); 307403#L721-1 assume !(0 == ~T6_E~0); 307576#L726-1 assume !(0 == ~E_M~0); 307577#L731-1 assume !(0 == ~E_1~0); 307542#L736-1 assume !(0 == ~E_2~0); 307543#L741-1 assume !(0 == ~E_3~0); 307633#L746-1 assume !(0 == ~E_4~0); 307426#L751-1 assume !(0 == ~E_5~0); 307427#L756-1 assume !(0 == ~E_6~0); 307399#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307221#L346 assume !(1 == ~m_pc~0); 307222#L346-2 is_master_triggered_~__retres1~0#1 := 0; 307440#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307752#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 307864#L861 assume !(0 != activate_threads_~tmp~1#1); 307805#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307806#L365 assume !(1 == ~t1_pc~0); 307972#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 307971#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307205#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307206#L869 assume !(0 != activate_threads_~tmp___0~0#1); 307246#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307969#L384 assume !(1 == ~t2_pc~0); 307689#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 307690#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307655#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307656#L877 assume !(0 != activate_threads_~tmp___1~0#1); 307968#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307967#L403 assume !(1 == ~t3_pc~0); 307966#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 307932#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307933#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 307965#L885 assume !(0 != activate_threads_~tmp___2~0#1); 307964#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307963#L422 assume !(1 == ~t4_pc~0); 307651#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 307652#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307307#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 307308#L893 assume !(0 != activate_threads_~tmp___3~0#1); 307784#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307959#L441 assume !(1 == ~t5_pc~0); 307800#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 307801#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307957#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 307954#L901 assume !(0 != activate_threads_~tmp___4~0#1); 307611#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 307612#L460 assume !(1 == ~t6_pc~0); 307756#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 307951#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 307636#L909 assume !(0 != activate_threads_~tmp___5~0#1); 307753#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307587#L774 assume !(1 == ~M_E~0); 307588#L774-2 assume !(1 == ~T1_E~0); 307949#L779-1 assume !(1 == ~T2_E~0); 307948#L784-1 assume !(1 == ~T3_E~0); 307888#L789-1 assume !(1 == ~T4_E~0); 307241#L794-1 assume !(1 == ~T5_E~0); 307242#L799-1 assume !(1 == ~T6_E~0); 307945#L804-1 assume !(1 == ~E_M~0); 307895#L809-1 assume !(1 == ~E_1~0); 307571#L814-1 assume !(1 == ~E_2~0); 307144#L819-1 assume !(1 == ~E_3~0); 307145#L824-1 assume !(1 == ~E_4~0); 307643#L829-1 assume !(1 == ~E_5~0); 307762#L834-1 assume !(1 == ~E_6~0); 307385#L839-1 assume { :end_inline_reset_delta_events } true; 307386#L1065-2 [2024-11-13 15:43:30,331 INFO L747 eck$LassoCheckResult]: Loop: 307386#L1065-2 assume !false; 319549#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 319545#L671-1 assume !false; 319544#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 319542#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 319536#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 319535#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 319533#L582 assume !(0 != eval_~tmp~0#1); 319532#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 319531#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319530#L696-3 assume !(0 == ~M_E~0); 319529#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 319527#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 319525#L706-3 assume !(0 == ~T3_E~0); 319523#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319521#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 319519#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 319517#L726-3 assume !(0 == ~E_M~0); 319515#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 319513#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 319511#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 319509#L746-3 assume !(0 == ~E_4~0); 319507#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 319505#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 319503#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319501#L346-24 assume 1 == ~m_pc~0; 319500#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 319490#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 319488#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319486#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 319484#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319482#L365-24 assume !(1 == ~t1_pc~0); 319480#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 319478#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319476#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 319474#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 319471#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319469#L384-24 assume 1 == ~t2_pc~0; 319466#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 319464#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319462#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 319460#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 319458#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319456#L403-24 assume !(1 == ~t3_pc~0); 319454#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 319452#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 319450#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 319448#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 319446#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319444#L422-24 assume !(1 == ~t4_pc~0); 319442#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 319440#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319438#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 319434#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 319432#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319430#L441-24 assume 1 == ~t5_pc~0; 319428#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 319429#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319760#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 319418#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 319416#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 319414#L460-24 assume !(1 == ~t6_pc~0); 319412#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 319410#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319408#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 319406#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 319405#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319403#L774-3 assume !(1 == ~M_E~0); 319107#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 319400#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 319398#L784-3 assume !(1 == ~T3_E~0); 319396#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 319395#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 319394#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 319392#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 319390#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 319389#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 319388#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 319387#L824-3 assume !(1 == ~E_4~0); 319386#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 319385#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 319384#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 319383#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 319376#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 319375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 319372#L1084 assume !(0 == start_simulation_~tmp~3#1); 319373#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 319576#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 319572#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 319569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 319565#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 319561#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319557#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 319553#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 307386#L1065-2 [2024-11-13 15:43:30,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:30,332 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2024-11-13 15:43:30,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:30,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676765249] [2024-11-13 15:43:30,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:30,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:30,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:30,348 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:30,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:30,387 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:30,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:30,388 INFO L85 PathProgramCache]: Analyzing trace with hash 29076765, now seen corresponding path program 1 times [2024-11-13 15:43:30,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:30,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347784969] [2024-11-13 15:43:30,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:30,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:30,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:30,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:30,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:30,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347784969] [2024-11-13 15:43:30,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347784969] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:30,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:30,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:30,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321005486] [2024-11-13 15:43:30,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:30,480 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:30,480 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:30,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:30,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:30,481 INFO L87 Difference]: Start difference. First operand 28391 states and 39602 transitions. cyclomatic complexity: 11227 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:30,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:30,885 INFO L93 Difference]: Finished difference Result 28711 states and 39922 transitions. [2024-11-13 15:43:30,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28711 states and 39922 transitions. [2024-11-13 15:43:30,998 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28344 [2024-11-13 15:43:31,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28711 states to 28711 states and 39922 transitions. [2024-11-13 15:43:31,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28711 [2024-11-13 15:43:31,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28711 [2024-11-13 15:43:31,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28711 states and 39922 transitions. [2024-11-13 15:43:31,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:31,120 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28711 states and 39922 transitions. [2024-11-13 15:43:31,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28711 states and 39922 transitions. [2024-11-13 15:43:31,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28711 to 28583. [2024-11-13 15:43:31,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28583 states, 28583 states have (on average 1.392226148409894) internal successors, (39794), 28582 states have internal predecessors, (39794), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:31,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28583 states to 28583 states and 39794 transitions. [2024-11-13 15:43:31,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28583 states and 39794 transitions. [2024-11-13 15:43:31,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:31,671 INFO L424 stractBuchiCegarLoop]: Abstraction has 28583 states and 39794 transitions. [2024-11-13 15:43:31,671 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:43:31,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28583 states and 39794 transitions. [2024-11-13 15:43:31,875 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28216 [2024-11-13 15:43:31,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:31,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:31,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:31,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:31,879 INFO L745 eck$LassoCheckResult]: Stem: 364597#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 364598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 364810#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364811#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 365057#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 364485#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364486#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364309#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364310#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364286#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364287#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364459#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364637#L696 assume !(0 == ~M_E~0); 364638#L696-2 assume !(0 == ~T1_E~0); 365068#L701-1 assume !(0 == ~T2_E~0); 365070#L706-1 assume !(0 == ~T3_E~0); 364769#L711-1 assume !(0 == ~T4_E~0); 364524#L716-1 assume !(0 == ~T5_E~0); 364525#L721-1 assume !(0 == ~T6_E~0); 364715#L726-1 assume !(0 == ~E_M~0); 364716#L731-1 assume !(0 == ~E_1~0); 364677#L736-1 assume !(0 == ~E_2~0); 364678#L741-1 assume !(0 == ~E_3~0); 364784#L746-1 assume !(0 == ~E_4~0); 364547#L751-1 assume !(0 == ~E_5~0); 364548#L756-1 assume !(0 == ~E_6~0); 364521#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364330#L346 assume !(1 == ~m_pc~0); 364331#L346-2 is_master_triggered_~__retres1~0#1 := 0; 364566#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364947#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 365092#L861 assume !(0 != activate_threads_~tmp~1#1); 365017#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365018#L365 assume !(1 == ~t1_pc~0); 365249#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 365248#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364314#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 364315#L869 assume !(0 != activate_threads_~tmp___0~0#1); 364357#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365246#L384 assume !(1 == ~t2_pc~0); 364857#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 364858#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364813#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364814#L877 assume !(0 != activate_threads_~tmp___1~0#1); 365245#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365244#L403 assume !(1 == ~t3_pc~0); 365243#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 365203#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365204#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 365242#L885 assume !(0 != activate_threads_~tmp___2~0#1); 365241#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365240#L422 assume !(1 == ~t4_pc~0); 364808#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 364809#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 364425#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 364426#L893 assume !(0 != activate_threads_~tmp___3~0#1); 364988#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365236#L441 assume !(1 == ~t5_pc~0); 365078#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 365235#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365232#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 365229#L901 assume !(0 != activate_threads_~tmp___4~0#1); 364756#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364757#L460 assume !(1 == ~t6_pc~0); 364951#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 365227#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 364787#L909 assume !(0 != activate_threads_~tmp___5~0#1); 364948#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 364729#L774 assume !(1 == ~M_E~0); 364730#L774-2 assume !(1 == ~T1_E~0); 365225#L779-1 assume !(1 == ~T2_E~0); 365224#L784-1 assume !(1 == ~T3_E~0); 365128#L789-1 assume !(1 == ~T4_E~0); 364351#L794-1 assume !(1 == ~T5_E~0); 364352#L799-1 assume !(1 == ~T6_E~0); 365221#L804-1 assume !(1 == ~E_M~0); 365141#L809-1 assume !(1 == ~E_1~0); 364709#L814-1 assume !(1 == ~E_2~0); 364253#L819-1 assume !(1 == ~E_3~0); 364254#L824-1 assume !(1 == ~E_4~0); 364797#L829-1 assume !(1 == ~E_5~0); 364956#L834-1 assume !(1 == ~E_6~0); 364503#L839-1 assume { :end_inline_reset_delta_events } true; 364504#L1065-2 [2024-11-13 15:43:31,879 INFO L747 eck$LassoCheckResult]: Loop: 364504#L1065-2 assume !false; 376598#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 374620#L671-1 assume !false; 376595#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 376102#L530 assume !(0 == ~m_st~0); 376103#L534 assume !(0 == ~t1_st~0); 376098#L538 assume !(0 == ~t2_st~0); 376099#L542 assume !(0 == ~t3_st~0); 376101#L546 assume !(0 == ~t4_st~0); 376096#L550 assume !(0 == ~t5_st~0); 376097#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 376100#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 375766#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 375767#L582 assume !(0 != eval_~tmp~0#1); 378337#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 378335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 378333#L696-3 assume !(0 == ~M_E~0); 378331#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 378329#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 378327#L706-3 assume !(0 == ~T3_E~0); 378325#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 378323#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 378321#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 378318#L726-3 assume !(0 == ~E_M~0); 378315#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 378312#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 378309#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 378306#L746-3 assume !(0 == ~E_4~0); 378303#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 378300#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 378296#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 378234#L346-24 assume !(1 == ~m_pc~0); 378226#L346-26 is_master_triggered_~__retres1~0#1 := 0; 378222#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378218#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 378214#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 378210#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 378206#L365-24 assume !(1 == ~t1_pc~0); 378202#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 378198#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 378194#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 378190#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 378186#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 378182#L384-24 assume !(1 == ~t2_pc~0); 378176#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 378170#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378166#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 378162#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 378158#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378154#L403-24 assume !(1 == ~t3_pc~0); 378150#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 378146#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378142#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 378138#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 378134#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378130#L422-24 assume !(1 == ~t4_pc~0); 378126#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 378122#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 378118#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 378114#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 378110#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378106#L441-24 assume !(1 == ~t5_pc~0); 378100#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 378092#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 378084#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 378076#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 378070#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 378066#L460-24 assume !(1 == ~t6_pc~0); 378062#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 378058#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378054#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378050#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 378046#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 378041#L774-3 assume !(1 == ~M_E~0); 378037#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 378035#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 378033#L784-3 assume !(1 == ~T3_E~0); 378031#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 378029#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 378027#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 378025#L804-3 assume !(1 == ~E_M~0); 378024#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 378023#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 378022#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 378021#L824-3 assume !(1 == ~E_4~0); 378020#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 378019#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 378018#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 378017#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 377892#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 377879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 377876#L1084 assume !(0 == start_simulation_~tmp~3#1); 377874#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 377870#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 377862#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 376611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 376610#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 376609#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 376607#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 376606#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 364504#L1065-2 [2024-11-13 15:43:31,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:31,880 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2024-11-13 15:43:31,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:31,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561804677] [2024-11-13 15:43:31,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:31,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:31,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:31,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:31,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:31,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:31,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:31,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1534565457, now seen corresponding path program 1 times [2024-11-13 15:43:31,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:31,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697657028] [2024-11-13 15:43:31,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:31,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:31,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:32,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:32,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:32,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697657028] [2024-11-13 15:43:32,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697657028] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:32,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:32,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:32,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147560600] [2024-11-13 15:43:32,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:32,054 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:32,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:32,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:32,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:32,054 INFO L87 Difference]: Start difference. First operand 28583 states and 39794 transitions. cyclomatic complexity: 11227 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:32,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:32,389 INFO L93 Difference]: Finished difference Result 29159 states and 40177 transitions. [2024-11-13 15:43:32,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29159 states and 40177 transitions. [2024-11-13 15:43:32,655 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28792 [2024-11-13 15:43:32,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29159 states to 29159 states and 40177 transitions. [2024-11-13 15:43:32,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29159 [2024-11-13 15:43:32,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29159 [2024-11-13 15:43:32,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29159 states and 40177 transitions. [2024-11-13 15:43:32,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:32,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29159 states and 40177 transitions. [2024-11-13 15:43:32,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29159 states and 40177 transitions. [2024-11-13 15:43:33,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29159 to 29159. [2024-11-13 15:43:33,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29159 states, 29159 states have (on average 1.3778593230220515) internal successors, (40177), 29158 states have internal predecessors, (40177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:33,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29159 states to 29159 states and 40177 transitions. [2024-11-13 15:43:33,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29159 states and 40177 transitions. [2024-11-13 15:43:33,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:33,377 INFO L424 stractBuchiCegarLoop]: Abstraction has 29159 states and 40177 transitions. [2024-11-13 15:43:33,377 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 15:43:33,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29159 states and 40177 transitions. [2024-11-13 15:43:33,464 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28792 [2024-11-13 15:43:33,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:33,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:33,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:33,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:33,467 INFO L745 eck$LassoCheckResult]: Stem: 422343#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 422344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 422526#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422527#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422737#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 422233#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 422234#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 422064#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 422065#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422038#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422039#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 422210#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 422377#L696 assume !(0 == ~M_E~0); 422378#L696-2 assume !(0 == ~T1_E~0); 422748#L701-1 assume !(0 == ~T2_E~0); 422750#L706-1 assume !(0 == ~T3_E~0); 422497#L711-1 assume !(0 == ~T4_E~0); 422270#L716-1 assume !(0 == ~T5_E~0); 422271#L721-1 assume !(0 == ~T6_E~0); 422447#L726-1 assume !(0 == ~E_M~0); 422448#L731-1 assume !(0 == ~E_1~0); 422412#L736-1 assume !(0 == ~E_2~0); 422413#L741-1 assume !(0 == ~E_3~0); 422508#L746-1 assume !(0 == ~E_4~0); 422294#L751-1 assume !(0 == ~E_5~0); 422295#L756-1 assume !(0 == ~E_6~0); 422267#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 422084#L346 assume !(1 == ~m_pc~0); 422085#L346-2 is_master_triggered_~__retres1~0#1 := 0; 422311#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 422301#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 422302#L861 assume !(0 != activate_threads_~tmp~1#1); 422886#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422120#L365 assume !(1 == ~t1_pc~0); 422121#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 422721#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422735#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 422883#L869 assume !(0 != activate_threads_~tmp___0~0#1); 422882#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422881#L384 assume !(1 == ~t2_pc~0); 422879#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422815#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 422816#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422878#L877 assume !(0 != activate_threads_~tmp___1~0#1); 422877#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422876#L403 assume !(1 == ~t3_pc~0); 422875#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422874#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 422000#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 422001#L885 assume !(0 != activate_threads_~tmp___2~0#1); 422387#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422388#L422 assume !(1 == ~t4_pc~0); 422524#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 422525#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 422172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 422173#L893 assume !(0 != activate_threads_~tmp___3~0#1); 422678#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422868#L441 assume !(1 == ~t5_pc~0); 422699#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422700#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422866#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422863#L901 assume !(0 != activate_threads_~tmp___4~0#1); 422485#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422486#L460 assume !(1 == ~t6_pc~0); 422650#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 422049#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422050#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422858#L909 assume !(0 != activate_threads_~tmp___5~0#1); 422760#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422761#L774 assume !(1 == ~M_E~0); 422856#L774-2 assume !(1 == ~T1_E~0); 422855#L779-1 assume !(1 == ~T2_E~0); 422854#L784-1 assume !(1 == ~T3_E~0); 422853#L789-1 assume !(1 == ~T4_E~0); 422852#L794-1 assume !(1 == ~T5_E~0); 422851#L799-1 assume !(1 == ~T6_E~0); 422850#L804-1 assume !(1 == ~E_M~0); 422797#L809-1 assume !(1 == ~E_1~0); 422443#L814-1 assume !(1 == ~E_2~0); 422006#L819-1 assume !(1 == ~E_3~0); 422007#L824-1 assume !(1 == ~E_4~0); 422518#L829-1 assume !(1 == ~E_5~0); 422653#L834-1 assume !(1 == ~E_6~0); 422255#L839-1 assume { :end_inline_reset_delta_events } true; 422256#L1065-2 [2024-11-13 15:43:33,467 INFO L747 eck$LassoCheckResult]: Loop: 422256#L1065-2 assume !false; 432605#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 432597#L671-1 assume !false; 432576#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 432563#L530 assume !(0 == ~m_st~0); 432558#L534 assume !(0 == ~t1_st~0); 432556#L538 assume !(0 == ~t2_st~0); 432554#L542 assume !(0 == ~t3_st~0); 432552#L546 assume !(0 == ~t4_st~0); 432550#L550 assume !(0 == ~t5_st~0); 432547#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 432545#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 432543#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 432541#L582 assume !(0 != eval_~tmp~0#1); 432538#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 432536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 432534#L696-3 assume !(0 == ~M_E~0); 432532#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 432530#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 432528#L706-3 assume !(0 == ~T3_E~0); 432526#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 432524#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 432522#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 432520#L726-3 assume !(0 == ~E_M~0); 432518#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 432516#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 432514#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 432512#L746-3 assume !(0 == ~E_4~0); 432510#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 432508#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 432485#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 431087#L346-24 assume 1 == ~m_pc~0; 431085#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 431086#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 431349#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 431257#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 431256#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 431253#L365-24 assume !(1 == ~t1_pc~0); 431252#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 431251#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 431249#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 431248#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 431247#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431246#L384-24 assume 1 == ~t2_pc~0; 431244#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 431243#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 431242#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 431241#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 431239#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431237#L403-24 assume !(1 == ~t3_pc~0); 431235#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 431234#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 431232#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 431231#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 431230#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 431228#L422-24 assume !(1 == ~t4_pc~0); 431226#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 431220#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 431218#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 431216#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 431213#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 431211#L441-24 assume 1 == ~t5_pc~0; 431208#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 431206#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 431205#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 430715#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 430713#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 430712#L460-24 assume !(1 == ~t6_pc~0); 429494#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 429493#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429491#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 429489#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 429487#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 429484#L774-3 assume !(1 == ~M_E~0); 427958#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 429483#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 429049#L784-3 assume !(1 == ~T3_E~0); 429045#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 429044#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 429041#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 429039#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 428160#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 428156#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 428154#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 428152#L824-3 assume !(1 == ~E_4~0); 428151#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 428142#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 428140#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 428137#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 428130#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 428128#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 428125#L1084 assume !(0 == start_simulation_~tmp~3#1); 428126#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 432666#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 432661#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 432659#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 432657#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 432655#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 432653#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 432651#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 422256#L1065-2 [2024-11-13 15:43:33,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:33,468 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2024-11-13 15:43:33,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:33,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278551971] [2024-11-13 15:43:33,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:33,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:33,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:33,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:33,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:33,513 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:33,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:33,515 INFO L85 PathProgramCache]: Analyzing trace with hash -293879316, now seen corresponding path program 1 times [2024-11-13 15:43:33,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:33,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387604829] [2024-11-13 15:43:33,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:33,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:33,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:33,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:33,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:33,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387604829] [2024-11-13 15:43:33,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387604829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:33,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:33,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:33,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968506867] [2024-11-13 15:43:33,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:33,626 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:33,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:33,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:33,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:33,627 INFO L87 Difference]: Start difference. First operand 29159 states and 40177 transitions. cyclomatic complexity: 11034 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:33,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:33,962 INFO L93 Difference]: Finished difference Result 29807 states and 40639 transitions. [2024-11-13 15:43:33,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29807 states and 40639 transitions. [2024-11-13 15:43:34,249 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29440 [2024-11-13 15:43:34,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29807 states to 29807 states and 40639 transitions. [2024-11-13 15:43:34,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29807 [2024-11-13 15:43:34,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29807 [2024-11-13 15:43:34,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29807 states and 40639 transitions. [2024-11-13 15:43:34,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:34,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29807 states and 40639 transitions. [2024-11-13 15:43:34,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29807 states and 40639 transitions. [2024-11-13 15:43:34,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29807 to 29807. [2024-11-13 15:43:34,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29807 states, 29807 states have (on average 1.3634045693964505) internal successors, (40639), 29806 states have internal predecessors, (40639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:34,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29807 states to 29807 states and 40639 transitions. [2024-11-13 15:43:34,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29807 states and 40639 transitions. [2024-11-13 15:43:34,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:34,958 INFO L424 stractBuchiCegarLoop]: Abstraction has 29807 states and 40639 transitions. [2024-11-13 15:43:34,959 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 15:43:34,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29807 states and 40639 transitions. [2024-11-13 15:43:35,052 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29440 [2024-11-13 15:43:35,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:35,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:35,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:35,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:35,057 INFO L745 eck$LassoCheckResult]: Stem: 481316#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 481317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 481502#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 481503#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 481699#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 481209#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481210#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 481038#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 481039#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 481012#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 481013#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 481186#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 481349#L696 assume !(0 == ~M_E~0); 481350#L696-2 assume !(0 == ~T1_E~0); 481708#L701-1 assume !(0 == ~T2_E~0); 481710#L706-1 assume !(0 == ~T3_E~0); 481469#L711-1 assume !(0 == ~T4_E~0); 481245#L716-1 assume !(0 == ~T5_E~0); 481246#L721-1 assume !(0 == ~T6_E~0); 481419#L726-1 assume !(0 == ~E_M~0); 481420#L731-1 assume !(0 == ~E_1~0); 481385#L736-1 assume !(0 == ~E_2~0); 481386#L741-1 assume !(0 == ~E_3~0); 481479#L746-1 assume !(0 == ~E_4~0); 481269#L751-1 assume !(0 == ~E_5~0); 481270#L756-1 assume !(0 == ~E_6~0); 481242#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 481059#L346 assume !(1 == ~m_pc~0); 481060#L346-2 is_master_triggered_~__retres1~0#1 := 0; 481286#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 481276#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 481277#L861 assume !(0 != activate_threads_~tmp~1#1); 481868#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 481095#L365 assume !(1 == ~t1_pc~0); 481096#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 481689#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 481697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 481865#L869 assume !(0 != activate_threads_~tmp___0~0#1); 481864#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 481863#L384 assume !(1 == ~t2_pc~0); 481861#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 481786#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 481787#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 481860#L877 assume !(0 != activate_threads_~tmp___1~0#1); 481859#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 481858#L403 assume !(1 == ~t3_pc~0); 481857#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 481856#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 480975#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 480976#L885 assume !(0 != activate_threads_~tmp___2~0#1); 481359#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 481360#L422 assume !(1 == ~t4_pc~0); 481500#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 481501#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481146#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 481147#L893 assume !(0 != activate_threads_~tmp___3~0#1); 481649#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 481850#L441 assume !(1 == ~t5_pc~0); 481668#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 481669#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 481845#L901 assume !(0 != activate_threads_~tmp___4~0#1); 481457#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 481458#L460 assume !(1 == ~t6_pc~0); 481619#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 481023#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 481024#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 481840#L909 assume !(0 != activate_threads_~tmp___5~0#1); 481721#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 481722#L774 assume !(1 == ~M_E~0); 481838#L774-2 assume !(1 == ~T1_E~0); 481837#L779-1 assume !(1 == ~T2_E~0); 481836#L784-1 assume !(1 == ~T3_E~0); 481835#L789-1 assume !(1 == ~T4_E~0); 481834#L794-1 assume !(1 == ~T5_E~0); 481833#L799-1 assume !(1 == ~T6_E~0); 481832#L804-1 assume !(1 == ~E_M~0); 481764#L809-1 assume !(1 == ~E_1~0); 481415#L814-1 assume !(1 == ~E_2~0); 480981#L819-1 assume !(1 == ~E_3~0); 480982#L824-1 assume !(1 == ~E_4~0); 481491#L829-1 assume !(1 == ~E_5~0); 481623#L834-1 assume !(1 == ~E_6~0); 481229#L839-1 assume { :end_inline_reset_delta_events } true; 481230#L1065-2 [2024-11-13 15:43:35,058 INFO L747 eck$LassoCheckResult]: Loop: 481230#L1065-2 assume !false; 489913#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 487860#L671-1 assume !false; 489912#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 489911#L530 assume !(0 == ~m_st~0); 489910#L534 assume !(0 == ~t1_st~0); 489909#L538 assume !(0 == ~t2_st~0); 489908#L542 assume !(0 == ~t3_st~0); 489907#L546 assume !(0 == ~t4_st~0); 489906#L550 assume !(0 == ~t5_st~0); 489904#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 489903#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 489902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 489901#L582 assume !(0 != eval_~tmp~0#1); 489899#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489897#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 489895#L696-3 assume !(0 == ~M_E~0); 489893#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 489891#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 489889#L706-3 assume !(0 == ~T3_E~0); 489887#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 489885#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 489883#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 489881#L726-3 assume !(0 == ~E_M~0); 489879#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 489877#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 489875#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 489873#L746-3 assume !(0 == ~E_4~0); 489871#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 489869#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 489867#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 489862#L346-24 assume 1 == ~m_pc~0; 489861#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 489856#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 489853#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 489850#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 489848#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 489846#L365-24 assume !(1 == ~t1_pc~0); 489844#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 489842#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 489840#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 489838#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 489836#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 489834#L384-24 assume 1 == ~t2_pc~0; 489831#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 489828#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 489826#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 489824#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 489822#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 489820#L403-24 assume !(1 == ~t3_pc~0); 489818#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 489816#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 489813#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 489809#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 489806#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 489800#L422-24 assume !(1 == ~t4_pc~0); 489791#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 489787#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 489783#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 489779#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 489774#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 489770#L441-24 assume !(1 == ~t5_pc~0); 489763#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 489756#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 489748#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 489741#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 489734#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 489729#L460-24 assume !(1 == ~t6_pc~0); 489724#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 489719#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 489714#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 489709#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 489702#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 489695#L774-3 assume !(1 == ~M_E~0); 489126#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 489684#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 489677#L784-3 assume !(1 == ~T3_E~0); 489671#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 489665#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 489659#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 489653#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 489647#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 489640#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 489634#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 489627#L824-3 assume !(1 == ~E_4~0); 489619#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 489614#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 489610#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 489464#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 489456#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 489454#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 489451#L1084 assume !(0 == start_simulation_~tmp~3#1); 489452#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 489923#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 489919#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 489918#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 489917#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 489916#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 489915#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 489914#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 481230#L1065-2 [2024-11-13 15:43:35,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:35,059 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2024-11-13 15:43:35,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:35,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625997804] [2024-11-13 15:43:35,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:35,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:35,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:35,076 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:35,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:35,110 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:35,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:35,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1534113423, now seen corresponding path program 1 times [2024-11-13 15:43:35,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:35,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922645511] [2024-11-13 15:43:35,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:35,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:35,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:35,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:35,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:35,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922645511] [2024-11-13 15:43:35,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922645511] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:35,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:35,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:35,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070279473] [2024-11-13 15:43:35,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:35,222 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:35,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:35,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:35,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:35,223 INFO L87 Difference]: Start difference. First operand 29807 states and 40639 transitions. cyclomatic complexity: 10848 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:35,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:35,546 INFO L93 Difference]: Finished difference Result 30455 states and 41101 transitions. [2024-11-13 15:43:35,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30455 states and 41101 transitions. [2024-11-13 15:43:35,853 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30088 [2024-11-13 15:43:35,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30455 states to 30455 states and 41101 transitions. [2024-11-13 15:43:35,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30455 [2024-11-13 15:43:35,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30455 [2024-11-13 15:43:35,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30455 states and 41101 transitions. [2024-11-13 15:43:36,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:36,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30455 states and 41101 transitions. [2024-11-13 15:43:36,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30455 states and 41101 transitions. [2024-11-13 15:43:36,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30455 to 30455. [2024-11-13 15:43:36,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30455 states, 30455 states have (on average 1.3495649318666885) internal successors, (41101), 30454 states have internal predecessors, (41101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:36,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30455 states to 30455 states and 41101 transitions. [2024-11-13 15:43:36,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30455 states and 41101 transitions. [2024-11-13 15:43:36,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:36,490 INFO L424 stractBuchiCegarLoop]: Abstraction has 30455 states and 41101 transitions. [2024-11-13 15:43:36,490 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 15:43:36,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30455 states and 41101 transitions. [2024-11-13 15:43:36,717 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30088 [2024-11-13 15:43:36,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:36,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:36,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:36,719 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:36,720 INFO L745 eck$LassoCheckResult]: Stem: 541579#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 541580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 541764#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 541765#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 541958#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 541474#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 541475#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 541309#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 541310#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 541281#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 541282#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 541452#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 541613#L696 assume !(0 == ~M_E~0); 541614#L696-2 assume !(0 == ~T1_E~0); 541967#L701-1 assume !(0 == ~T2_E~0); 541969#L706-1 assume !(0 == ~T3_E~0); 541732#L711-1 assume !(0 == ~T4_E~0); 541511#L716-1 assume !(0 == ~T5_E~0); 541512#L721-1 assume !(0 == ~T6_E~0); 541687#L726-1 assume !(0 == ~E_M~0); 541688#L731-1 assume !(0 == ~E_1~0); 541651#L736-1 assume !(0 == ~E_2~0); 541652#L741-1 assume !(0 == ~E_3~0); 541741#L746-1 assume !(0 == ~E_4~0); 541535#L751-1 assume !(0 == ~E_5~0); 541536#L756-1 assume !(0 == ~E_6~0); 541508#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 541329#L346 assume !(1 == ~m_pc~0); 541330#L346-2 is_master_triggered_~__retres1~0#1 := 0; 541551#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 541541#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 541542#L861 assume !(0 != activate_threads_~tmp~1#1); 542116#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 541362#L365 assume !(1 == ~t1_pc~0); 541363#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 541943#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 541955#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 542113#L869 assume !(0 != activate_threads_~tmp___0~0#1); 542112#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 542111#L384 assume !(1 == ~t2_pc~0); 542109#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 542040#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 542041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 542108#L877 assume !(0 != activate_threads_~tmp___1~0#1); 542107#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 542106#L403 assume !(1 == ~t3_pc~0); 542105#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 542104#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 541244#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 541245#L885 assume !(0 != activate_threads_~tmp___2~0#1); 541623#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 541624#L422 assume !(1 == ~t4_pc~0); 541762#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 541763#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 541414#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 541415#L893 assume !(0 != activate_threads_~tmp___3~0#1); 541907#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 542098#L441 assume !(1 == ~t5_pc~0); 541923#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 541924#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 542096#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 542093#L901 assume !(0 != activate_threads_~tmp___4~0#1); 541720#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 541721#L460 assume !(1 == ~t6_pc~0); 541877#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 541292#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 541293#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 542088#L909 assume !(0 != activate_threads_~tmp___5~0#1); 541983#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 541984#L774 assume !(1 == ~M_E~0); 542086#L774-2 assume !(1 == ~T1_E~0); 542085#L779-1 assume !(1 == ~T2_E~0); 542084#L784-1 assume !(1 == ~T3_E~0); 542083#L789-1 assume !(1 == ~T4_E~0); 542082#L794-1 assume !(1 == ~T5_E~0); 542081#L799-1 assume !(1 == ~T6_E~0); 542080#L804-1 assume !(1 == ~E_M~0); 542023#L809-1 assume !(1 == ~E_1~0); 541683#L814-1 assume !(1 == ~E_2~0); 541250#L819-1 assume !(1 == ~E_3~0); 541251#L824-1 assume !(1 == ~E_4~0); 541753#L829-1 assume !(1 == ~E_5~0); 541881#L834-1 assume !(1 == ~E_6~0); 541494#L839-1 assume { :end_inline_reset_delta_events } true; 541495#L1065-2 [2024-11-13 15:43:36,720 INFO L747 eck$LassoCheckResult]: Loop: 541495#L1065-2 assume !false; 556059#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 556056#L671-1 assume !false; 556055#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 556054#L530 assume !(0 == ~m_st~0); 556053#L534 assume !(0 == ~t1_st~0); 556052#L538 assume !(0 == ~t2_st~0); 556050#L542 assume !(0 == ~t3_st~0); 556049#L546 assume !(0 == ~t4_st~0); 556048#L550 assume !(0 == ~t5_st~0); 556046#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 556045#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 556044#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 556043#L582 assume !(0 != eval_~tmp~0#1); 556041#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 556039#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 556037#L696-3 assume !(0 == ~M_E~0); 556035#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 556033#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 556031#L706-3 assume !(0 == ~T3_E~0); 556029#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 556027#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 556025#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 556023#L726-3 assume !(0 == ~E_M~0); 556021#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 556019#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 556017#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 556015#L746-3 assume !(0 == ~E_4~0); 556013#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 556011#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 556009#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 556007#L346-24 assume !(1 == ~m_pc~0); 556003#L346-26 is_master_triggered_~__retres1~0#1 := 0; 556000#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 555998#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 555996#L861-24 assume !(0 != activate_threads_~tmp~1#1); 555994#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555991#L365-24 assume !(1 == ~t1_pc~0); 555989#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 555987#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 555985#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 555983#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 555981#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 555979#L384-24 assume 1 == ~t2_pc~0; 555976#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 555974#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 555971#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 555969#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 555967#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 555965#L403-24 assume !(1 == ~t3_pc~0); 555963#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 555961#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 555959#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 555957#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 555955#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 555953#L422-24 assume !(1 == ~t4_pc~0); 555951#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 555949#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 555947#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555945#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 555943#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 555941#L441-24 assume !(1 == ~t5_pc~0); 555937#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 555933#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555931#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 555929#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 555926#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555923#L460-24 assume !(1 == ~t6_pc~0); 555921#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 555919#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 555917#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 555915#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 555913#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 555911#L774-3 assume !(1 == ~M_E~0); 555655#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 555908#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 555907#L784-3 assume !(1 == ~T3_E~0); 555905#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 555903#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 555901#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 555897#L804-3 assume !(1 == ~E_M~0); 555895#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 555894#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 555893#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 555892#L824-3 assume !(1 == ~E_4~0); 555891#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 555890#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 555889#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 555887#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 555880#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 555879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 555877#L1084 assume !(0 == start_simulation_~tmp~3#1); 555878#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 556074#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 556069#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 556067#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 556065#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 556064#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 556062#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 556060#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 541495#L1065-2 [2024-11-13 15:43:36,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:36,722 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2024-11-13 15:43:36,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:36,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27687092] [2024-11-13 15:43:36,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:36,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:36,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:36,737 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:36,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:36,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:36,762 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:36,762 INFO L85 PathProgramCache]: Analyzing trace with hash 1041566068, now seen corresponding path program 1 times [2024-11-13 15:43:36,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:36,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115713475] [2024-11-13 15:43:36,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:36,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:36,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:36,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:36,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:36,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115713475] [2024-11-13 15:43:36,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115713475] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:36,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:36,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:36,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014224388] [2024-11-13 15:43:36,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:36,818 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:36,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:36,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:36,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:36,819 INFO L87 Difference]: Start difference. First operand 30455 states and 41101 transitions. cyclomatic complexity: 10662 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:37,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:37,043 INFO L93 Difference]: Finished difference Result 53695 states and 71533 transitions. [2024-11-13 15:43:37,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53695 states and 71533 transitions. [2024-11-13 15:43:37,259 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53104 [2024-11-13 15:43:37,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53695 states to 53695 states and 71533 transitions. [2024-11-13 15:43:37,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53695 [2024-11-13 15:43:37,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53695 [2024-11-13 15:43:37,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53695 states and 71533 transitions. [2024-11-13 15:43:37,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:37,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53695 states and 71533 transitions. [2024-11-13 15:43:37,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53695 states and 71533 transitions. [2024-11-13 15:43:38,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53695 to 52159. [2024-11-13 15:43:38,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52159 states, 52159 states have (on average 1.3343238942464388) internal successors, (69597), 52158 states have internal predecessors, (69597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:38,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52159 states to 52159 states and 69597 transitions. [2024-11-13 15:43:38,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52159 states and 69597 transitions. [2024-11-13 15:43:38,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:38,424 INFO L424 stractBuchiCegarLoop]: Abstraction has 52159 states and 69597 transitions. [2024-11-13 15:43:38,424 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 15:43:38,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52159 states and 69597 transitions. [2024-11-13 15:43:38,586 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51568 [2024-11-13 15:43:38,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:38,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:38,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:38,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:38,589 INFO L745 eck$LassoCheckResult]: Stem: 625749#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 625750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 625946#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 625947#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 626157#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 625636#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 625637#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 625460#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 625461#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 625437#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 625438#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 625610#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 625785#L696 assume !(0 == ~M_E~0); 625786#L696-2 assume !(0 == ~T1_E~0); 626171#L701-1 assume !(0 == ~T2_E~0); 626174#L706-1 assume !(0 == ~T3_E~0); 625918#L711-1 assume !(0 == ~T4_E~0); 625671#L716-1 assume !(0 == ~T5_E~0); 625672#L721-1 assume !(0 == ~T6_E~0); 625862#L726-1 assume !(0 == ~E_M~0); 625863#L731-1 assume !(0 == ~E_1~0); 625825#L736-1 assume !(0 == ~E_2~0); 625826#L741-1 assume !(0 == ~E_3~0); 625930#L746-1 assume !(0 == ~E_4~0); 625696#L751-1 assume !(0 == ~E_5~0); 625697#L756-1 assume !(0 == ~E_6~0); 625668#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 625484#L346 assume !(1 == ~m_pc~0); 625485#L346-2 is_master_triggered_~__retres1~0#1 := 0; 625715#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 626058#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 626194#L861 assume !(0 != activate_threads_~tmp~1#1); 626116#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 626117#L365 assume !(1 == ~t1_pc~0); 626342#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 626341#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 625467#L869 assume !(0 != activate_threads_~tmp___0~0#1); 625510#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 626339#L384 assume !(1 == ~t2_pc~0); 625988#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 625989#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 625949#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 625950#L877 assume !(0 != activate_threads_~tmp___1~0#1); 626338#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 626337#L403 assume !(1 == ~t3_pc~0); 626336#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 626300#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 626301#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 626335#L885 assume !(0 != activate_threads_~tmp___2~0#1); 626334#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 626333#L422 assume !(1 == ~t4_pc~0); 625944#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 625945#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 625574#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 625575#L893 assume !(0 != activate_threads_~tmp___3~0#1); 626091#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 626329#L441 assume !(1 == ~t5_pc~0); 626182#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 626328#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 626325#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 626322#L901 assume !(0 != activate_threads_~tmp___4~0#1); 625904#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 625905#L460 assume !(1 == ~t6_pc~0); 626062#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 626320#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 625932#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 625933#L909 assume !(0 != activate_threads_~tmp___5~0#1); 626059#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 625874#L774 assume !(1 == ~M_E~0); 625875#L774-2 assume !(1 == ~T1_E~0); 626318#L779-1 assume !(1 == ~T2_E~0); 626317#L784-1 assume !(1 == ~T3_E~0); 626225#L789-1 assume !(1 == ~T4_E~0); 625504#L794-1 assume !(1 == ~T5_E~0); 625505#L799-1 assume !(1 == ~T6_E~0); 626314#L804-1 assume !(1 == ~E_M~0); 626238#L809-1 assume !(1 == ~E_1~0); 625858#L814-1 assume !(1 == ~E_2~0); 625404#L819-1 assume !(1 == ~E_3~0); 625405#L824-1 assume !(1 == ~E_4~0); 625939#L829-1 assume !(1 == ~E_5~0); 626069#L834-1 assume !(1 == ~E_6~0); 625652#L839-1 assume { :end_inline_reset_delta_events } true; 625653#L1065-2 [2024-11-13 15:43:38,589 INFO L747 eck$LassoCheckResult]: Loop: 625653#L1065-2 assume !false; 630062#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630057#L671-1 assume !false; 630055#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 630051#L530 assume !(0 == ~m_st~0); 630052#L534 assume !(0 == ~t1_st~0); 649028#L538 assume !(0 == ~t2_st~0); 649029#L542 assume !(0 == ~t3_st~0); 649031#L546 assume !(0 == ~t4_st~0); 649026#L550 assume !(0 == ~t5_st~0); 649027#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 649030#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 649274#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 649267#L582 assume !(0 != eval_~tmp~0#1); 649263#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 649261#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 649258#L696-3 assume !(0 == ~M_E~0); 649256#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 649255#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 649253#L706-3 assume !(0 == ~T3_E~0); 649250#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 649248#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 649244#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 649242#L726-3 assume !(0 == ~E_M~0); 649240#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 649238#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 649235#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 649233#L746-3 assume !(0 == ~E_4~0); 649231#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 649228#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 649226#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 649222#L346-24 assume 1 == ~m_pc~0; 649223#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 630216#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630214#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 630211#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630209#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630207#L365-24 assume !(1 == ~t1_pc~0); 630205#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 630202#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630200#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 630198#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 630196#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630194#L384-24 assume !(1 == ~t2_pc~0); 630189#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 630186#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630184#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630182#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 630180#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630178#L403-24 assume !(1 == ~t3_pc~0); 630176#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 630174#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630172#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630170#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 630166#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 630164#L422-24 assume !(1 == ~t4_pc~0); 630162#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 630160#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630157#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 630155#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 630153#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630151#L441-24 assume !(1 == ~t5_pc~0); 630147#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 630145#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630143#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630141#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 630139#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630138#L460-24 assume !(1 == ~t6_pc~0); 630137#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 630133#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630131#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630129#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 630127#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 630125#L774-3 assume !(1 == ~M_E~0); 630121#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 630119#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 630117#L784-3 assume !(1 == ~T3_E~0); 630115#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 630113#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 630111#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 630109#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 630107#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 630104#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 630102#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 630100#L824-3 assume !(1 == ~E_4~0); 630098#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 630096#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 630094#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 630091#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 630089#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 630087#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 630084#L1084 assume !(0 == start_simulation_~tmp~3#1); 630081#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 630078#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 630076#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 630074#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 630072#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 630070#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630068#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 630067#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 625653#L1065-2 [2024-11-13 15:43:38,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:38,590 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2024-11-13 15:43:38,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:38,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94423704] [2024-11-13 15:43:38,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:38,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:38,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:38,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:38,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:38,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:38,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:38,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1646934476, now seen corresponding path program 1 times [2024-11-13 15:43:38,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:38,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940862542] [2024-11-13 15:43:38,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:38,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:38,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:38,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:38,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:38,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940862542] [2024-11-13 15:43:38,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940862542] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:38,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:38,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:38,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074022034] [2024-11-13 15:43:38,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:38,732 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:38,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:38,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:38,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:38,733 INFO L87 Difference]: Start difference. First operand 52159 states and 69597 transitions. cyclomatic complexity: 17454 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:39,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:39,164 INFO L93 Difference]: Finished difference Result 54277 states and 71715 transitions. [2024-11-13 15:43:39,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54277 states and 71715 transitions. [2024-11-13 15:43:39,726 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53680 [2024-11-13 15:43:39,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54277 states to 54277 states and 71715 transitions. [2024-11-13 15:43:39,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54277 [2024-11-13 15:43:39,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54277 [2024-11-13 15:43:39,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54277 states and 71715 transitions. [2024-11-13 15:43:39,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:39,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54277 states and 71715 transitions. [2024-11-13 15:43:40,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54277 states and 71715 transitions. [2024-11-13 15:43:40,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54277 to 54277. [2024-11-13 15:43:40,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54277 states, 54277 states have (on average 1.321277889345395) internal successors, (71715), 54276 states have internal predecessors, (71715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:41,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54277 states to 54277 states and 71715 transitions. [2024-11-13 15:43:41,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54277 states and 71715 transitions. [2024-11-13 15:43:41,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:41,122 INFO L424 stractBuchiCegarLoop]: Abstraction has 54277 states and 71715 transitions. [2024-11-13 15:43:41,122 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 15:43:41,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54277 states and 71715 transitions. [2024-11-13 15:43:41,277 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53680 [2024-11-13 15:43:41,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:41,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:41,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:41,279 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:41,279 INFO L745 eck$LassoCheckResult]: Stem: 732188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 732189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 732382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 732383#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 732586#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 732081#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 732082#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 731904#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 731905#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 731881#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 731882#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 732055#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 732227#L696 assume !(0 == ~M_E~0); 732228#L696-2 assume !(0 == ~T1_E~0); 732594#L701-1 assume !(0 == ~T2_E~0); 732597#L706-1 assume !(0 == ~T3_E~0); 732352#L711-1 assume !(0 == ~T4_E~0); 732118#L716-1 assume !(0 == ~T5_E~0); 732119#L721-1 assume !(0 == ~T6_E~0); 732304#L726-1 assume !(0 == ~E_M~0); 732305#L731-1 assume !(0 == ~E_1~0); 732267#L736-1 assume !(0 == ~E_2~0); 732268#L741-1 assume !(0 == ~E_3~0); 732364#L746-1 assume !(0 == ~E_4~0); 732141#L751-1 assume !(0 == ~E_5~0); 732142#L756-1 assume !(0 == ~E_6~0); 732115#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 731927#L346 assume !(1 == ~m_pc~0); 731928#L346-2 is_master_triggered_~__retres1~0#1 := 0; 732157#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 732495#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 732619#L861 assume !(0 != activate_threads_~tmp~1#1); 732553#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 732554#L365 assume !(1 == ~t1_pc~0); 732756#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 732755#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 731910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 731911#L869 assume !(0 != activate_threads_~tmp___0~0#1); 731952#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 732428#L384 assume !(1 == ~t2_pc~0); 732422#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 732423#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732384#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 731870#L877 assume !(0 != activate_threads_~tmp___1~0#1); 731871#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 732245#L403 assume !(1 == ~t3_pc~0); 732246#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 732476#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 731844#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 731845#L885 assume !(0 != activate_threads_~tmp___2~0#1); 732237#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 732238#L422 assume !(1 == ~t4_pc~0); 732587#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 732735#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 732734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 732732#L893 assume !(0 != activate_threads_~tmp___3~0#1); 732329#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 732330#L441 assume !(1 == ~t5_pc~0); 732606#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 732731#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 732729#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 732727#L901 assume !(0 != activate_threads_~tmp___4~0#1); 732339#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 732340#L460 assume !(1 == ~t6_pc~0); 732500#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 732725#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 732366#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 732367#L909 assume !(0 != activate_threads_~tmp___5~0#1); 732496#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 732315#L774 assume !(1 == ~M_E~0); 732316#L774-2 assume !(1 == ~T1_E~0); 732723#L779-1 assume !(1 == ~T2_E~0); 732722#L784-1 assume !(1 == ~T3_E~0); 732650#L789-1 assume !(1 == ~T4_E~0); 731947#L794-1 assume !(1 == ~T5_E~0); 731948#L799-1 assume !(1 == ~T6_E~0); 732719#L804-1 assume !(1 == ~E_M~0); 732655#L809-1 assume !(1 == ~E_1~0); 732299#L814-1 assume !(1 == ~E_2~0); 731848#L819-1 assume !(1 == ~E_3~0); 731849#L824-1 assume !(1 == ~E_4~0); 732374#L829-1 assume !(1 == ~E_5~0); 732506#L834-1 assume !(1 == ~E_6~0); 732098#L839-1 assume { :end_inline_reset_delta_events } true; 732099#L1065-2 [2024-11-13 15:43:41,280 INFO L747 eck$LassoCheckResult]: Loop: 732099#L1065-2 assume !false; 736075#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 736070#L671-1 assume !false; 736068#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 736065#L530 assume !(0 == ~m_st~0); 736066#L534 assume !(0 == ~t1_st~0); 759320#L538 assume !(0 == ~t2_st~0); 759321#L542 assume !(0 == ~t3_st~0); 759323#L546 assume !(0 == ~t4_st~0); 759318#L550 assume !(0 == ~t5_st~0); 759319#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 759322#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 772458#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 765006#L582 assume !(0 != eval_~tmp~0#1); 765003#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 765004#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 764997#L696-3 assume !(0 == ~M_E~0); 764998#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 764991#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 764992#L706-3 assume !(0 == ~T3_E~0); 764985#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 764986#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 764979#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 764980#L726-3 assume !(0 == ~E_M~0); 764973#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 764974#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 764967#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 764968#L746-3 assume !(0 == ~E_4~0); 764960#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 764961#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 764952#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 764953#L346-24 assume 1 == ~m_pc~0; 767375#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 736227#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 736225#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 736222#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 736220#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 736218#L365-24 assume !(1 == ~t1_pc~0); 736216#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 736214#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 736212#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 736210#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 736208#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 736206#L384-24 assume !(1 == ~t2_pc~0); 736202#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 736198#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 736196#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 736194#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 736191#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 736188#L403-24 assume !(1 == ~t3_pc~0); 736186#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 736184#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 736182#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 736180#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 736178#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 736176#L422-24 assume !(1 == ~t4_pc~0); 736174#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 736173#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 736172#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 736170#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 736169#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 736168#L441-24 assume 1 == ~t5_pc~0; 736166#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 736167#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 736171#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 736157#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 736155#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 736153#L460-24 assume !(1 == ~t6_pc~0); 736151#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 736149#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 736147#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 736145#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 736143#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 736141#L774-3 assume !(1 == ~M_E~0); 736137#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 736135#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 736131#L784-3 assume !(1 == ~T3_E~0); 736129#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 736127#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 736125#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 736122#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 736120#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 736118#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 736116#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 736114#L824-3 assume !(1 == ~E_4~0); 736112#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 736110#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 736108#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 736105#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 736103#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 736101#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 736098#L1084 assume !(0 == start_simulation_~tmp~3#1); 736095#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 736092#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 736091#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 736087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 736085#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 736083#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 736081#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 736078#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 732099#L1065-2 [2024-11-13 15:43:41,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:41,281 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2024-11-13 15:43:41,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:41,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409789751] [2024-11-13 15:43:41,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:41,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:41,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:41,296 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:41,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:41,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:41,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:41,315 INFO L85 PathProgramCache]: Analyzing trace with hash 597900083, now seen corresponding path program 1 times [2024-11-13 15:43:41,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:41,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831074473] [2024-11-13 15:43:41,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:41,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:41,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:41,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:41,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:41,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831074473] [2024-11-13 15:43:41,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831074473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:41,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:41,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:43:41,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918530043] [2024-11-13 15:43:41,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:41,403 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:41,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:41,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:43:41,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:43:41,405 INFO L87 Difference]: Start difference. First operand 54277 states and 71715 transitions. cyclomatic complexity: 17454 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:41,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:41,792 INFO L93 Difference]: Finished difference Result 55381 states and 72481 transitions. [2024-11-13 15:43:41,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55381 states and 72481 transitions. [2024-11-13 15:43:42,013 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54784 [2024-11-13 15:43:42,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55381 states to 55381 states and 72481 transitions. [2024-11-13 15:43:42,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55381 [2024-11-13 15:43:42,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55381 [2024-11-13 15:43:42,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55381 states and 72481 transitions. [2024-11-13 15:43:42,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:43:42,542 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55381 states and 72481 transitions. [2024-11-13 15:43:42,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55381 states and 72481 transitions. [2024-11-13 15:43:42,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55381 to 55381. [2024-11-13 15:43:43,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55381 states, 55381 states have (on average 1.3087701558296168) internal successors, (72481), 55380 states have internal predecessors, (72481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:43,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55381 states to 55381 states and 72481 transitions. [2024-11-13 15:43:43,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55381 states and 72481 transitions. [2024-11-13 15:43:43,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:43:43,092 INFO L424 stractBuchiCegarLoop]: Abstraction has 55381 states and 72481 transitions. [2024-11-13 15:43:43,092 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 15:43:43,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55381 states and 72481 transitions. [2024-11-13 15:43:43,250 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54784 [2024-11-13 15:43:43,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:43,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:43,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:43,251 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:43,252 INFO L745 eck$LassoCheckResult]: Stem: 841855#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 841856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 842039#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 842040#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 842239#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 841749#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 841750#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 841575#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 841576#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 841548#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 841549#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 841726#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 841889#L696 assume !(0 == ~M_E~0); 841890#L696-2 assume !(0 == ~T1_E~0); 842252#L701-1 assume !(0 == ~T2_E~0); 842254#L706-1 assume !(0 == ~T3_E~0); 842011#L711-1 assume !(0 == ~T4_E~0); 841786#L716-1 assume !(0 == ~T5_E~0); 841787#L721-1 assume !(0 == ~T6_E~0); 841961#L726-1 assume !(0 == ~E_M~0); 841962#L731-1 assume !(0 == ~E_1~0); 841925#L736-1 assume !(0 == ~E_2~0); 841926#L741-1 assume !(0 == ~E_3~0); 842021#L746-1 assume !(0 == ~E_4~0); 841809#L751-1 assume !(0 == ~E_5~0); 841810#L756-1 assume !(0 == ~E_6~0); 841783#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 841597#L346 assume !(1 == ~m_pc~0); 841598#L346-2 is_master_triggered_~__retres1~0#1 := 0; 841826#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842150#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 842271#L861 assume !(0 != activate_threads_~tmp~1#1); 842206#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 842207#L365 assume !(1 == ~t1_pc~0); 842396#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842395#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 841582#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 841583#L869 assume !(0 != activate_threads_~tmp___0~0#1); 841620#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 842084#L384 assume !(1 == ~t2_pc~0); 842079#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 842080#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 842045#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 841538#L877 assume !(0 != activate_threads_~tmp___1~0#1); 841539#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 841904#L403 assume !(1 == ~t3_pc~0); 841905#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 842129#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 841510#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 841511#L885 assume !(0 != activate_threads_~tmp___2~0#1); 841899#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 841900#L422 assume !(1 == ~t4_pc~0); 842037#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 842038#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 841683#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 841684#L893 assume !(0 != activate_threads_~tmp___3~0#1); 842183#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 842373#L441 assume !(1 == ~t5_pc~0); 842201#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 842202#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 842371#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 842368#L901 assume !(0 != activate_threads_~tmp___4~0#1); 841998#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 841999#L460 assume !(1 == ~t6_pc~0); 842156#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 842365#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 842024#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 842025#L909 assume !(0 != activate_threads_~tmp___5~0#1); 842151#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 841973#L774 assume !(1 == ~M_E~0); 841974#L774-2 assume !(1 == ~T1_E~0); 842363#L779-1 assume !(1 == ~T2_E~0); 842362#L784-1 assume !(1 == ~T3_E~0); 842298#L789-1 assume !(1 == ~T4_E~0); 841614#L794-1 assume !(1 == ~T5_E~0); 841615#L799-1 assume !(1 == ~T6_E~0); 842359#L804-1 assume !(1 == ~E_M~0); 842309#L809-1 assume !(1 == ~E_1~0); 841959#L814-1 assume !(1 == ~E_2~0); 841516#L819-1 assume !(1 == ~E_3~0); 841517#L824-1 assume !(1 == ~E_4~0); 842031#L829-1 assume !(1 == ~E_5~0); 842160#L834-1 assume !(1 == ~E_6~0); 841771#L839-1 assume { :end_inline_reset_delta_events } true; 841772#L1065-2 [2024-11-13 15:43:43,252 INFO L747 eck$LassoCheckResult]: Loop: 841772#L1065-2 assume !false; 851110#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 851105#L671-1 assume !false; 851103#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 851100#L530 assume !(0 == ~m_st~0); 851101#L534 assume !(0 == ~t1_st~0); 856298#L538 assume !(0 == ~t2_st~0); 856296#L542 assume !(0 == ~t3_st~0); 856292#L546 assume !(0 == ~t4_st~0); 856290#L550 assume !(0 == ~t5_st~0); 856287#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 856285#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 856282#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 856280#L582 assume !(0 != eval_~tmp~0#1); 856276#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 856274#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 856272#L696-3 assume !(0 == ~M_E~0); 856270#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 856268#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 856266#L706-3 assume !(0 == ~T3_E~0); 856264#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 856262#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 856263#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 866220#L726-3 assume !(0 == ~E_M~0); 866218#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 856256#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 856254#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 856255#L746-3 assume !(0 == ~E_4~0); 856249#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 856250#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 856245#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 856246#L346-24 assume 1 == ~m_pc~0; 866172#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 850111#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 850109#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 850106#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 850104#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 850102#L365-24 assume !(1 == ~t1_pc~0); 850100#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 850098#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 850096#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 850094#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 850092#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 850090#L384-24 assume 1 == ~t2_pc~0; 850088#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 850089#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 850118#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 850078#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 850074#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 850072#L403-24 assume !(1 == ~t3_pc~0); 850069#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 850067#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 850065#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 850063#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 850062#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 850061#L422-24 assume !(1 == ~t4_pc~0); 850059#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 850057#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 850055#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 850053#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 850052#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 850051#L441-24 assume !(1 == ~t5_pc~0); 850048#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 850046#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 850045#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 850043#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 850040#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 850038#L460-24 assume !(1 == ~t6_pc~0); 850033#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 850031#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 850029#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 850027#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 850025#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 850023#L774-3 assume !(1 == ~M_E~0); 849798#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 850020#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 850016#L784-3 assume !(1 == ~T3_E~0); 850014#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 850012#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 850010#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 850007#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 850005#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 850003#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 850001#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 849999#L824-3 assume !(1 == ~E_4~0); 849997#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 849995#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 849993#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 849990#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 849988#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 849986#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 849983#L1084 assume !(0 == start_simulation_~tmp~3#1); 849984#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 851127#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 851126#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 851122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 851120#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 851118#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 851116#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 851113#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 841772#L1065-2 [2024-11-13 15:43:43,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:43,252 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2024-11-13 15:43:43,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:43,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083412295] [2024-11-13 15:43:43,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:43,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:43,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:43,268 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:43,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:43,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:43,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:43,294 INFO L85 PathProgramCache]: Analyzing trace with hash -500998411, now seen corresponding path program 1 times [2024-11-13 15:43:43,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:43,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774167677] [2024-11-13 15:43:43,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:43,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:43,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:43,310 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:43,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:43,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:43,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:43,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1204610115, now seen corresponding path program 1 times [2024-11-13 15:43:43,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:43,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407580897] [2024-11-13 15:43:43,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:43,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:43,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:43,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:43,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:43,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407580897] [2024-11-13 15:43:43,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407580897] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:43,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:43,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:43,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421875701] [2024-11-13 15:43:43,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:45,575 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:43:45,575 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:43:45,576 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:43:45,576 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:43:45,577 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 15:43:45,577 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:45,577 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:43:45,577 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:43:45,578 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-1.c_Iteration26_Loop [2024-11-13 15:43:45,578 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:43:45,578 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:43:45,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,805 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,867 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:45,899 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:46,490 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:43:46,492 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 15:43:46,494 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,495 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,497 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,499 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 15:43:46,501 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,501 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,526 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,526 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,544 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 15:43:46,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,546 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 15:43:46,548 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,548 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,563 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,563 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,577 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 15:43:46,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,579 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 15:43:46,581 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,581 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,598 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,598 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,611 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 15:43:46,611 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,611 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,613 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 15:43:46,614 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,614 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,627 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,627 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,640 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 15:43:46,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,642 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 15:43:46,644 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,644 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,661 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,661 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,679 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 15:43:46,680 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,680 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,682 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 15:43:46,685 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,685 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,711 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,711 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,866 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:46,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,869 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 15:43:46,871 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,871 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,884 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,884 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,896 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 15:43:46,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,898 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 15:43:46,900 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,900 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,912 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,912 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,925 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 15:43:46,925 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,927 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,931 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 15:43:46,933 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,933 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:46,959 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:46,959 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-8} Honda state: {~E_4~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:46,977 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-13 15:43:46,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:46,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:46,980 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:46,981 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 15:43:46,983 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:46,983 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,000 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,000 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,015 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 15:43:47,016 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,016 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,018 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,019 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 15:43:47,019 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,019 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,032 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,032 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,044 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 15:43:47,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,045 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 15:43:47,047 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,047 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,067 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,068 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,079 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 15:43:47,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,080 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,081 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 15:43:47,083 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,083 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,102 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,102 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,115 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-13 15:43:47,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,116 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,117 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 15:43:47,119 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,119 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,131 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,131 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,143 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-13 15:43:47,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,145 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 15:43:47,147 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,147 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,162 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,162 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,177 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 15:43:47,177 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,177 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,178 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 15:43:47,180 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,180 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,202 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,202 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=4} Honda state: {~t5_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,220 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:47,221 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,221 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,222 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 15:43:47,225 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,225 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,238 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,238 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,250 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 15:43:47,250 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,250 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,252 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,253 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 15:43:47,253 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,253 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,265 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,266 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,278 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 15:43:47,278 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,280 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,281 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 15:43:47,282 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,282 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,295 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,295 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,309 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 15:43:47,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,310 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,311 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,313 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 15:43:47,314 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,314 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,328 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,328 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,341 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 15:43:47,341 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,342 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,344 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 15:43:47,346 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,346 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,359 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,359 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,371 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 15:43:47,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,373 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 15:43:47,376 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,376 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,391 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,391 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,403 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-13 15:43:47,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,404 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,405 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 15:43:47,407 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,407 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,423 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,423 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,436 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-13 15:43:47,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,438 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,439 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 15:43:47,440 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,440 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,452 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,452 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,464 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 15:43:47,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,465 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,467 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 15:43:47,468 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,468 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,481 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,481 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,493 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-13 15:43:47,494 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,494 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,495 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 15:43:47,497 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,497 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,509 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,510 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,521 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 15:43:47,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,523 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,524 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-13 15:43:47,525 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,525 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,537 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:43:47,537 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:43:47,550 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-13 15:43:47,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,552 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-13 15:43:47,554 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:43:47,554 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,580 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-13 15:43:47,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:47,582 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:47,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-13 15:43:47,583 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 15:43:47,584 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:43:47,600 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 15:43:47,618 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-13 15:43:47,618 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:43:47,619 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:43:47,619 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:43:47,619 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:43:47,619 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 15:43:47,619 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:47,619 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:43:47,620 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:43:47,620 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-1.c_Iteration26_Loop [2024-11-13 15:43:47,620 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:43:47,620 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:43:47,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,899 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:47,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:43:48,592 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:43:48,596 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 15:43:48,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,600 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-13 15:43:48,610 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,626 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,627 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,627 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,627 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,627 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,637 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,637 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,641 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,660 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:48,660 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,662 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,663 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-13 15:43:48,664 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,676 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,676 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,676 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,676 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,677 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,677 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,679 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,699 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-13 15:43:48,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,701 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-13 15:43:48,705 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,720 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,721 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,721 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,721 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,721 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,721 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,722 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,723 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,744 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:48,747 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,748 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,751 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-13 15:43:48,755 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,772 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,773 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,773 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,773 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,773 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,774 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,775 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,777 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,798 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:48,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,801 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,804 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-13 15:43:48,805 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,822 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,823 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,823 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,823 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:43:48,823 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,824 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:43:48,824 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,828 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,850 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2024-11-13 15:43:48,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,850 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,853 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-13 15:43:48,857 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,871 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,872 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,872 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,874 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,887 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:48,888 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,888 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,889 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-13 15:43:48,891 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,904 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,904 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,904 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,904 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,904 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,905 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,905 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,909 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,924 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2024-11-13 15:43:48,924 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,924 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,926 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-13 15:43:48,929 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,942 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,942 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,942 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,942 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:48,942 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,943 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:48,943 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,945 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,960 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-11-13 15:43:48,960 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,960 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,963 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-13 15:43:48,965 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:48,978 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:48,978 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:48,978 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:48,978 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:43:48,978 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:48,979 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:43:48,979 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:48,982 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:48,994 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2024-11-13 15:43:48,995 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:48,995 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:48,997 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:48,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-13 15:43:48,999 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,014 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,014 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,015 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,015 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,015 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,015 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,016 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,017 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,031 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2024-11-13 15:43:49,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,031 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,033 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,035 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-13 15:43:49,037 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,052 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,052 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,052 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,052 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,052 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,053 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,053 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,055 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2024-11-13 15:43:49,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,068 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,070 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,071 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-13 15:43:49,072 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,085 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,085 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,085 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,085 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,085 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,086 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,086 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,088 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,102 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2024-11-13 15:43:49,102 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,102 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,104 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-13 15:43:49,106 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,119 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,119 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,119 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,119 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,119 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,120 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,120 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,123 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,144 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2024-11-13 15:43:49,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,146 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-13 15:43:49,149 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,163 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,163 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,163 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,163 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:43:49,163 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,164 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:43:49,164 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,166 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,179 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-13 15:43:49,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,180 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,182 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-13 15:43:49,184 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,197 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,197 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,197 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:43:49,197 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,198 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:43:49,198 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,200 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,215 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2024-11-13 15:43:49,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,215 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,217 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,218 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-13 15:43:49,218 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,231 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,231 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,231 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,231 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,231 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,232 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,232 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,234 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,248 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-11-13 15:43:49,248 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,250 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,251 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-13 15:43:49,252 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,263 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,264 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,264 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,264 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:43:49,264 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,265 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:43:49,265 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,267 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,280 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-11-13 15:43:49,280 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,280 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,282 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,283 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-13 15:43:49,284 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,296 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,296 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,296 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,296 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,296 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,297 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,297 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,298 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,311 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2024-11-13 15:43:49,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,313 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,315 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-11-13 15:43:49,316 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,329 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,329 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,329 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,329 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,329 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,330 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,330 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,331 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,345 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2024-11-13 15:43:49,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,346 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,348 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-11-13 15:43:49,349 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,363 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,363 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,363 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,363 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,363 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,363 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,364 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,365 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,379 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2024-11-13 15:43:49,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,382 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,383 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-11-13 15:43:49,384 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,396 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,397 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,397 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,397 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,397 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,397 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,397 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,399 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:49,412 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,414 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-11-13 15:43:49,418 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,435 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,435 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,435 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,435 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,435 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,436 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,436 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,438 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,459 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2024-11-13 15:43:49,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,463 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-11-13 15:43:49,467 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,482 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,482 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,482 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,482 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,482 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,483 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,483 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,485 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,505 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:49,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,508 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,510 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-11-13 15:43:49,511 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,527 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,527 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,527 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,527 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,527 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,528 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,528 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,531 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,552 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-11-13 15:43:49,552 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,552 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,554 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,556 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-11-13 15:43:49,561 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,595 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,595 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,595 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,595 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,595 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,596 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,596 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,599 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,633 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Ended with exit code 0 [2024-11-13 15:43:49,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,634 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,637 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-11-13 15:43:49,644 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,663 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,664 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,664 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,664 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,664 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,665 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,665 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,667 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,685 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:49,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,688 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,689 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-11-13 15:43:49,689 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,706 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,706 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,706 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,706 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,706 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,709 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,709 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,711 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,746 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2024-11-13 15:43:49,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,747 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,750 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-11-13 15:43:49,754 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,771 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,771 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,771 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,771 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,772 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,772 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,772 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,774 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:43:49,816 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Forceful destruction successful, exit code 0 [2024-11-13 15:43:49,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,816 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,818 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-11-13 15:43:49,820 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:43:49,831 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:43:49,832 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:43:49,832 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:43:49,832 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:43:49,832 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:43:49,833 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:43:49,833 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:43:49,835 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 15:43:49,838 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 15:43:49,842 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 15:43:49,844 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:43:49,844 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:43:49,846 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:43:49,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-11-13 15:43:49,848 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 15:43:49,848 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 15:43:49,848 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 15:43:49,849 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2024-11-13 15:43:49,862 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-11-13 15:43:49,865 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 15:43:49,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:49,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:49,997 INFO L255 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 15:43:50,001 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:43:50,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:50,254 INFO L255 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 15:43:50,258 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:43:50,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:50,630 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 15:43:50,632 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 55381 states and 72481 transitions. cyclomatic complexity: 17116 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:50,967 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_200f5577-3e6a-4805-9e6d-fb34e02540f4/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2024-11-13 15:43:51,738 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 55381 states and 72481 transitions. cyclomatic complexity: 17116. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 111191 states and 146020 transitions. Complement of second has 4 states. [2024-11-13 15:43:51,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 15:43:51,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:51,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 999 transitions. [2024-11-13 15:43:51,749 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 999 transitions. Stem has 84 letters. Loop has 100 letters. [2024-11-13 15:43:51,754 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:43:51,758 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 999 transitions. Stem has 184 letters. Loop has 100 letters. [2024-11-13 15:43:51,760 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:43:51,760 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 999 transitions. Stem has 84 letters. Loop has 200 letters. [2024-11-13 15:43:51,762 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:43:51,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111191 states and 146020 transitions. [2024-11-13 15:43:52,507 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54784 [2024-11-13 15:43:53,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111191 states to 111191 states and 146020 transitions. [2024-11-13 15:43:53,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55382 [2024-11-13 15:43:53,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55671 [2024-11-13 15:43:53,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111191 states and 146020 transitions. [2024-11-13 15:43:53,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:43:53,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111191 states and 146020 transitions. [2024-11-13 15:43:53,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111191 states and 146020 transitions. [2024-11-13 15:43:54,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111191 to 110902. [2024-11-13 15:43:54,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110902 states, 110902 states have (on average 1.3131864168364862) internal successors, (145635), 110901 states have internal predecessors, (145635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:55,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110902 states to 110902 states and 145635 transitions. [2024-11-13 15:43:55,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110902 states and 145635 transitions. [2024-11-13 15:43:55,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:55,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:55,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:55,162 INFO L87 Difference]: Start difference. First operand 110902 states and 145635 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:55,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:55,633 INFO L93 Difference]: Finished difference Result 114262 states and 149379 transitions. [2024-11-13 15:43:55,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114262 states and 149379 transitions. [2024-11-13 15:43:56,035 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 56464 [2024-11-13 15:43:56,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114262 states to 114262 states and 149379 transitions. [2024-11-13 15:43:56,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57062 [2024-11-13 15:43:56,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57062 [2024-11-13 15:43:56,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114262 states and 149379 transitions. [2024-11-13 15:43:56,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:43:56,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 114262 states and 149379 transitions. [2024-11-13 15:43:57,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114262 states and 149379 transitions. [2024-11-13 15:43:58,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114262 to 110902. [2024-11-13 15:43:58,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110902 states, 110902 states have (on average 1.3097239003805161) internal successors, (145251), 110901 states have internal predecessors, (145251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:58,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110902 states to 110902 states and 145251 transitions. [2024-11-13 15:43:58,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110902 states and 145251 transitions. [2024-11-13 15:43:58,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:43:58,407 INFO L424 stractBuchiCegarLoop]: Abstraction has 110902 states and 145251 transitions. [2024-11-13 15:43:58,407 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 15:43:58,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110902 states and 145251 transitions. [2024-11-13 15:43:58,626 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54784 [2024-11-13 15:43:58,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:43:58,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:43:58,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:58,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:43:58,629 INFO L745 eck$LassoCheckResult]: Stem: 1234485#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1234486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1234861#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1234862#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1235284#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1234280#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1234281#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1233944#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1233945#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1233903#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1233904#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1234231#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1234553#L696 assume !(0 == ~M_E~0); 1234554#L696-2 assume !(0 == ~T1_E~0); 1235300#L701-1 assume !(0 == ~T2_E~0); 1235304#L706-1 assume !(0 == ~T3_E~0); 1234803#L711-1 assume !(0 == ~T4_E~0); 1234350#L716-1 assume !(0 == ~T5_E~0); 1234351#L721-1 assume !(0 == ~T6_E~0); 1234699#L726-1 assume !(0 == ~E_M~0); 1234700#L731-1 assume !(0 == ~E_1~0); 1234631#L736-1 assume !(0 == ~E_2~0); 1234632#L741-1 assume !(0 == ~E_3~0); 1234824#L746-1 assume !(0 == ~E_4~0); 1234399#L751-1 assume !(0 == ~E_5~0); 1234400#L756-1 assume !(0 == ~E_6~0); 1234345#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1233985#L346 assume !(1 == ~m_pc~0); 1233986#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1234426#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1235090#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1235346#L861 assume !(0 != activate_threads_~tmp~1#1); 1235347#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1235599#L365 assume !(1 == ~t1_pc~0); 1235598#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1235597#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1233954#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1233955#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1234031#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1234956#L384 assume !(1 == ~t2_pc~0); 1234943#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1234944#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1235600#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1233882#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1233883#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1234585#L403 assume !(1 == ~t3_pc~0); 1234586#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1235048#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1233834#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1233835#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1234571#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234572#L422 assume !(1 == ~t4_pc~0); 1235285#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1235579#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1235578#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1235577#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1234752#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1233905#L441 assume !(1 == ~t5_pc~0); 1233906#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1235574#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1235571#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1235568#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1234774#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1234775#L460 assume !(1 == ~t6_pc~0); 1235096#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1233916#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1233917#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1235564#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1235563#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1235562#L774 assume !(1 == ~M_E~0); 1235411#L774-2 assume !(1 == ~T1_E~0); 1235136#L779-1 assume !(1 == ~T2_E~0); 1234520#L784-1 assume !(1 == ~T3_E~0); 1234521#L789-1 assume !(1 == ~T4_E~0); 1235558#L794-1 assume !(1 == ~T5_E~0); 1235557#L799-1 assume !(1 == ~T6_E~0); 1235556#L804-1 assume !(1 == ~E_M~0); 1235431#L809-1 assume !(1 == ~E_1~0); 1234692#L814-1 assume !(1 == ~E_2~0); 1233840#L819-1 assume !(1 == ~E_3~0); 1233841#L824-1 assume !(1 == ~E_4~0); 1234847#L829-1 assume !(1 == ~E_5~0); 1235108#L834-1 assume !(1 == ~E_6~0); 1234312#L839-1 assume { :end_inline_reset_delta_events } true; 1234313#L1065-2 assume !false; 1250774#L1066 [2024-11-13 15:43:58,630 INFO L747 eck$LassoCheckResult]: Loop: 1250774#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1296455#L671-1 assume !false; 1296453#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1296452#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1296449#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1296448#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1296446#L582 assume 0 != eval_~tmp~0#1; 1296445#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1296443#L590 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1296444#L74 assume 0 == ~m_pc~0; 1314562#L110 assume !false; 1314558#L86 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1314556#L346-3 assume !(1 == ~m_pc~0); 1314552#L346-5 is_master_triggered_~__retres1~0#1 := 0; 1314551#L357-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1314548#is_master_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1314547#L861-3 assume !(0 != activate_threads_~tmp~1#1); 1314546#L861-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1314544#L365-3 assume !(1 == ~t1_pc~0); 1314543#L365-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1314542#L376-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1314540#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1314539#L869-3 assume !(0 != activate_threads_~tmp___0~0#1); 1314538#L869-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1314537#L384-3 assume !(1 == ~t2_pc~0); 1314534#L384-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1314532#L395-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1314531#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1314530#L877-3 assume !(0 != activate_threads_~tmp___1~0#1); 1314527#L877-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1314526#L403-3 assume !(1 == ~t3_pc~0); 1314525#L403-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1314523#L414-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1314522#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1314521#L885-3 assume !(0 != activate_threads_~tmp___2~0#1); 1314520#L885-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1314519#L422-3 assume !(1 == ~t4_pc~0); 1314518#L422-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1314514#L433-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314512#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1314510#L893-3 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1314508#L893-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1314506#L441-3 assume !(1 == ~t5_pc~0); 1314502#L441-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1314498#L452-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1314496#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1314494#L901-3 assume !(0 != activate_threads_~tmp___4~0#1); 1314491#L901-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1314488#L460-3 assume !(1 == ~t6_pc~0); 1314486#L460-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1314482#L471-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1314480#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1314478#L909-3 assume !(0 != activate_threads_~tmp___5~0#1); 1314476#L909-5 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true; 1314473#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1314471#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 1314453#L590-2 havoc eval_~tmp_ndt_1~0#1; 1314450#L587-1 assume !(0 == ~t1_st~0); 1314451#L601-1 assume !(0 == ~t2_st~0); 1321660#L615-1 assume !(0 == ~t3_st~0); 1321656#L629-1 assume !(0 == ~t4_st~0); 1321644#L643-1 assume !(0 == ~t5_st~0); 1321634#L657-1 assume !(0 == ~t6_st~0); 1321635#L671-1 assume !false; 1339552#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1336728#L530 assume !(0 == ~m_st~0); 1327082#L534 assume !(0 == ~t1_st~0); 1327078#L538 assume !(0 == ~t2_st~0); 1327079#L542 assume !(0 == ~t3_st~0); 1327081#L546 assume !(0 == ~t4_st~0); 1327076#L550 assume !(0 == ~t5_st~0); 1327077#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1327080#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1327133#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1327132#L582 assume !(0 != eval_~tmp~0#1); 1327126#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1327125#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1327123#L696-3 assume !(0 == ~M_E~0); 1327122#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1327121#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1327120#L706-3 assume !(0 == ~T3_E~0); 1327119#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1327118#L716-3 assume !(0 == ~T5_E~0); 1327116#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1327114#L726-3 assume !(0 == ~E_M~0); 1327112#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1327104#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1327102#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1327100#L746-3 assume !(0 == ~E_4~0); 1327096#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1327092#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1327089#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1327084#L346-24 assume 1 == ~m_pc~0; 1327085#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1308557#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1308555#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1308553#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1308552#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1308550#L365-24 assume !(1 == ~t1_pc~0); 1308549#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1308548#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1308547#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1308545#L869-24 assume !(0 != activate_threads_~tmp___0~0#1); 1308544#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1308543#L384-24 assume !(1 == ~t2_pc~0); 1308541#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1311388#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1310909#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1308529#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1308526#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1308523#L403-24 assume !(1 == ~t3_pc~0); 1308521#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1308517#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1308515#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1308513#L885-24 assume !(0 != activate_threads_~tmp___2~0#1); 1308511#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304713#L422-24 assume !(1 == ~t4_pc~0); 1304710#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1304706#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1304702#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1304700#L893-24 assume !(0 != activate_threads_~tmp___3~0#1); 1304698#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1304696#L441-24 assume !(1 == ~t5_pc~0); 1304693#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1304743#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1296563#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1296557#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1296551#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1296547#L460-24 assume !(1 == ~t6_pc~0); 1296543#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1296540#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1296537#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1296533#L909-24 assume !(0 != activate_threads_~tmp___5~0#1); 1296529#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1296525#L774-3 assume !(1 == ~M_E~0); 1296520#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1296518#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1296516#L784-3 assume !(1 == ~T3_E~0); 1296514#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1296512#L794-3 assume !(1 == ~T5_E~0); 1296510#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1296508#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1296506#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1296503#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1296501#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1296499#L824-3 assume !(1 == ~E_4~0); 1296497#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1296495#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1296493#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1296492#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1296488#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1296486#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1296483#L1084 assume !(0 == start_simulation_~tmp~3#1); 1296480#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1296477#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1296475#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1296473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1296471#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1296469#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1296467#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1296465#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1296463#L1065-2 assume !false; 1250774#L1066 [2024-11-13 15:43:58,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:58,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793377, now seen corresponding path program 1 times [2024-11-13 15:43:58,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:58,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429663984] [2024-11-13 15:43:58,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:58,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:58,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:58,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:43:58,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:43:58,670 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:43:58,671 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:43:58,671 INFO L85 PathProgramCache]: Analyzing trace with hash -1958260430, now seen corresponding path program 1 times [2024-11-13 15:43:58,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:43:58,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544089658] [2024-11-13 15:43:58,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:43:58,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:43:58,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:43:58,721 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:43:58,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:43:58,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544089658] [2024-11-13 15:43:58,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544089658] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:43:58,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:43:58,722 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:43:58,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204834924] [2024-11-13 15:43:58,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:43:58,722 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:43:58,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:43:58,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:43:58,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:43:58,723 INFO L87 Difference]: Start difference. First operand 110902 states and 145251 transitions. cyclomatic complexity: 34381 Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:43:59,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:43:59,220 INFO L93 Difference]: Finished difference Result 127016 states and 165141 transitions. [2024-11-13 15:43:59,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127016 states and 165141 transitions. [2024-11-13 15:44:00,203 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 62568 [2024-11-13 15:44:00,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127016 states to 127016 states and 165141 transitions. [2024-11-13 15:44:00,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63455 [2024-11-13 15:44:00,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63455 [2024-11-13 15:44:00,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127016 states and 165141 transitions. [2024-11-13 15:44:00,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:44:00,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127016 states and 165141 transitions. [2024-11-13 15:44:00,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127016 states and 165141 transitions. [2024-11-13 15:44:01,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127016 to 124200. [2024-11-13 15:44:02,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124200 states, 124200 states have (on average 1.3023268921095008) internal successors, (161749), 124199 states have internal predecessors, (161749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:44:02,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124200 states to 124200 states and 161749 transitions. [2024-11-13 15:44:02,213 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124200 states and 161749 transitions. [2024-11-13 15:44:02,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:44:02,217 INFO L424 stractBuchiCegarLoop]: Abstraction has 124200 states and 161749 transitions. [2024-11-13 15:44:02,218 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 15:44:02,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124200 states and 161749 transitions. [2024-11-13 15:44:02,471 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 61160 [2024-11-13 15:44:02,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:44:02,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:44:02,472 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:02,472 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:02,472 INFO L745 eck$LassoCheckResult]: Stem: 1472404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1472405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1472778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1472779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1473168#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1472204#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472205#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1471868#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1471869#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1471828#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1471829#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1472152#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1472476#L696 assume !(0 == ~M_E~0); 1472477#L696-2 assume !(0 == ~T1_E~0); 1473190#L701-1 assume !(0 == ~T2_E~0); 1473197#L706-1 assume !(0 == ~T3_E~0); 1472725#L711-1 assume !(0 == ~T4_E~0); 1472272#L716-1 assume !(0 == ~T5_E~0); 1472273#L721-1 assume !(0 == ~T6_E~0); 1472631#L726-1 assume !(0 == ~E_M~0); 1472632#L731-1 assume !(0 == ~E_1~0); 1472555#L736-1 assume !(0 == ~E_2~0); 1472556#L741-1 assume !(0 == ~E_3~0); 1472744#L746-1 assume !(0 == ~E_4~0); 1472321#L751-1 assume !(0 == ~E_5~0); 1472322#L756-1 assume !(0 == ~E_6~0); 1472267#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471907#L346 assume !(1 == ~m_pc~0); 1471908#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1472348#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1472333#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1472334#L861 assume !(0 != activate_threads_~tmp~1#1); 1473472#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1473471#L365 assume !(1 == ~t1_pc~0); 1473470#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1473469#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1471878#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1471879#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1471954#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1473467#L384 assume !(1 == ~t2_pc~0); 1473466#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1473464#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1473462#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1473460#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1473458#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1473457#L403 assume !(1 == ~t3_pc~0); 1473456#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1473404#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1473405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1473455#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1473454#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1473453#L422 assume !(1 == ~t4_pc~0); 1472776#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1472777#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1473036#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1473451#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1472683#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1471830#L441 assume !(1 == ~t5_pc~0); 1471831#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1473448#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1473446#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1473443#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1472700#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1472701#L460 assume !(1 == ~t6_pc~0); 1473002#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1471841#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1471842#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1473438#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1473437#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1473436#L774 assume !(1 == ~M_E~0); 1473294#L774-2 assume !(1 == ~T1_E~0); 1473041#L779-1 assume !(1 == ~T2_E~0); 1472440#L784-1 assume !(1 == ~T3_E~0); 1472441#L789-1 assume !(1 == ~T4_E~0); 1473432#L794-1 assume !(1 == ~T5_E~0); 1473431#L799-1 assume !(1 == ~T6_E~0); 1473430#L804-1 assume !(1 == ~E_M~0); 1473304#L809-1 assume !(1 == ~E_1~0); 1472620#L814-1 assume !(1 == ~E_2~0); 1471765#L819-1 assume !(1 == ~E_3~0); 1471766#L824-1 assume !(1 == ~E_4~0); 1472765#L829-1 assume !(1 == ~E_5~0); 1473015#L834-1 assume !(1 == ~E_6~0); 1472237#L839-1 assume { :end_inline_reset_delta_events } true; 1472238#L1065-2 assume !false; 1523379#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1544260#L671-1 [2024-11-13 15:44:02,473 INFO L747 eck$LassoCheckResult]: Loop: 1544260#L671-1 assume !false; 1544245#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1544232#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1544224#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1544213#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1544206#L582 assume 0 != eval_~tmp~0#1; 1544198#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1544187#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1544181#L590-2 havoc eval_~tmp_ndt_1~0#1; 1544170#L587-1 assume !(0 == ~t1_st~0); 1544161#L601-1 assume !(0 == ~t2_st~0); 1544162#L615-1 assume !(0 == ~t3_st~0); 1545418#L629-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1545420#L646 assume !(0 != eval_~tmp_ndt_5~0#1); 1545342#L646-2 havoc eval_~tmp_ndt_5~0#1; 1545309#L643-1 assume !(0 == ~t5_st~0); 1544335#L657-1 assume !(0 == ~t6_st~0); 1544260#L671-1 [2024-11-13 15:44:02,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:02,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052149, now seen corresponding path program 1 times [2024-11-13 15:44:02,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:02,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439112108] [2024-11-13 15:44:02,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:02,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:02,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:02,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:44:02,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:02,504 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:44:02,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:02,505 INFO L85 PathProgramCache]: Analyzing trace with hash 1378613308, now seen corresponding path program 1 times [2024-11-13 15:44:02,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:02,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267594014] [2024-11-13 15:44:02,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:02,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:02,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:02,509 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:44:02,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:02,513 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:44:02,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:02,513 INFO L85 PathProgramCache]: Analyzing trace with hash -641574414, now seen corresponding path program 1 times [2024-11-13 15:44:02,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:02,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654450983] [2024-11-13 15:44:02,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:02,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:02,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:44:02,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:44:02,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:44:02,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654450983] [2024-11-13 15:44:02,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654450983] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:44:02,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:44:02,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:44:02,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670440227] [2024-11-13 15:44:02,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:44:02,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:44:02,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:44:02,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:44:02,635 INFO L87 Difference]: Start difference. First operand 124200 states and 161749 transitions. cyclomatic complexity: 37597 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:44:03,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:44:03,799 INFO L93 Difference]: Finished difference Result 234778 states and 303419 transitions. [2024-11-13 15:44:03,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234778 states and 303419 transitions. [2024-11-13 15:44:05,277 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 112936 [2024-11-13 15:44:05,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234778 states to 234778 states and 303419 transitions. [2024-11-13 15:44:05,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117328 [2024-11-13 15:44:05,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117328 [2024-11-13 15:44:05,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234778 states and 303419 transitions. [2024-11-13 15:44:05,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:44:05,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 234778 states and 303419 transitions. [2024-11-13 15:44:05,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234778 states and 303419 transitions. [2024-11-13 15:44:08,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234778 to 227290. [2024-11-13 15:44:08,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227290 states, 227290 states have (on average 1.2943948259932245) internal successors, (294203), 227289 states have internal predecessors, (294203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:44:09,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227290 states to 227290 states and 294203 transitions. [2024-11-13 15:44:09,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227290 states and 294203 transitions. [2024-11-13 15:44:09,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:44:09,137 INFO L424 stractBuchiCegarLoop]: Abstraction has 227290 states and 294203 transitions. [2024-11-13 15:44:09,137 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 15:44:09,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227290 states and 294203 transitions. [2024-11-13 15:44:09,700 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 109192 [2024-11-13 15:44:09,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:44:09,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:44:09,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:09,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:09,702 INFO L745 eck$LassoCheckResult]: Stem: 1831396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1831397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1831787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1831788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1832221#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1831191#L487-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1831192#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1830856#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1830857#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1830817#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1830818#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1831141#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1831465#L696 assume !(0 == ~M_E~0); 1831466#L696-2 assume !(0 == ~T1_E~0); 1832239#L701-1 assume !(0 == ~T2_E~0); 1832246#L706-1 assume !(0 == ~T3_E~0); 1831720#L711-1 assume !(0 == ~T4_E~0); 1831262#L716-1 assume !(0 == ~T5_E~0); 1831263#L721-1 assume !(0 == ~T6_E~0); 1831621#L726-1 assume !(0 == ~E_M~0); 1831622#L731-1 assume !(0 == ~E_1~0); 1831546#L736-1 assume !(0 == ~E_2~0); 1831547#L741-1 assume !(0 == ~E_3~0); 1831747#L746-1 assume !(0 == ~E_4~0); 1831308#L751-1 assume !(0 == ~E_5~0); 1831309#L756-1 assume !(0 == ~E_6~0); 1831257#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830893#L346 assume !(1 == ~m_pc~0); 1830894#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1831335#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1832014#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1832283#L861 assume !(0 != activate_threads_~tmp~1#1); 1832284#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1832583#L365 assume !(1 == ~t1_pc~0); 1832582#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1832581#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1830865#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1830866#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1840683#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1840676#L384 assume !(1 == ~t2_pc~0); 1840675#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1840674#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1840673#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1840672#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1840670#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1840669#L403 assume !(1 == ~t3_pc~0); 1840668#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1840667#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1840666#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1840665#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1840664#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1840663#L422 assume !(1 == ~t4_pc~0); 1840662#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1840661#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1840660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1840659#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1840658#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1840657#L441 assume !(1 == ~t5_pc~0); 1840654#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1840653#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1840652#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1840649#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1840648#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1840647#L460 assume !(1 == ~t6_pc~0); 1840646#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1840645#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1840644#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1840643#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1840642#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1840641#L774 assume !(1 == ~M_E~0); 1840640#L774-2 assume !(1 == ~T1_E~0); 1832054#L779-1 assume !(1 == ~T2_E~0); 1832055#L784-1 assume !(1 == ~T3_E~0); 1832533#L789-1 assume !(1 == ~T4_E~0); 1832534#L794-1 assume !(1 == ~T5_E~0); 1832529#L799-1 assume !(1 == ~T6_E~0); 1832530#L804-1 assume !(1 == ~E_M~0); 1832461#L809-1 assume !(1 == ~E_1~0); 1831612#L814-1 assume !(1 == ~E_2~0); 1830751#L819-1 assume !(1 == ~E_3~0); 1830752#L824-1 assume !(1 == ~E_4~0); 1840599#L829-1 assume !(1 == ~E_5~0); 1840597#L834-1 assume !(1 == ~E_6~0); 1840595#L839-1 assume { :end_inline_reset_delta_events } true; 1840588#L1065-2 assume !false; 1840589#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1895289#L671-1 [2024-11-13 15:44:09,702 INFO L747 eck$LassoCheckResult]: Loop: 1895289#L671-1 assume !false; 1895287#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1895285#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1895283#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1895281#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1895277#L582 assume 0 != eval_~tmp~0#1; 1895275#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1895272#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1895271#L590-2 havoc eval_~tmp_ndt_1~0#1; 1895267#L587-1 assume !(0 == ~t1_st~0); 1895265#L601-1 assume !(0 == ~t2_st~0); 1895262#L615-1 assume !(0 == ~t3_st~0); 1895257#L629-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1895252#L646 assume !(0 != eval_~tmp_ndt_5~0#1); 1895253#L646-2 havoc eval_~tmp_ndt_5~0#1; 1901064#L643-1 assume !(0 == ~t5_st~0); 1895292#L657-1 assume !(0 == ~t6_st~0); 1895289#L671-1 [2024-11-13 15:44:09,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:09,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1466077069, now seen corresponding path program 1 times [2024-11-13 15:44:09,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:09,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7748120] [2024-11-13 15:44:09,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:09,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:09,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:44:09,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:44:09,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:44:09,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7748120] [2024-11-13 15:44:09,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7748120] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:44:09,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:44:09,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:44:09,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224088014] [2024-11-13 15:44:09,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:44:09,729 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:44:09,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:09,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1378613308, now seen corresponding path program 2 times [2024-11-13 15:44:09,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:09,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143217370] [2024-11-13 15:44:09,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:09,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:09,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:09,734 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:44:09,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:09,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:44:09,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:44:09,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:44:09,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:44:09,818 INFO L87 Difference]: Start difference. First operand 227290 states and 294203 transitions. cyclomatic complexity: 67009 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:44:10,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:44:10,952 INFO L93 Difference]: Finished difference Result 150152 states and 194696 transitions. [2024-11-13 15:44:10,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150152 states and 194696 transitions. [2024-11-13 15:44:11,428 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 73696 [2024-11-13 15:44:11,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150152 states to 150152 states and 194696 transitions. [2024-11-13 15:44:11,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75031 [2024-11-13 15:44:11,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75031 [2024-11-13 15:44:11,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150152 states and 194696 transitions. [2024-11-13 15:44:11,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:44:11,743 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150152 states and 194696 transitions. [2024-11-13 15:44:11,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150152 states and 194696 transitions. [2024-11-13 15:44:13,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150152 to 150152. [2024-11-13 15:44:13,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150152 states, 150152 states have (on average 1.2966593851563748) internal successors, (194696), 150151 states have internal predecessors, (194696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:44:13,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150152 states to 150152 states and 194696 transitions. [2024-11-13 15:44:13,620 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150152 states and 194696 transitions. [2024-11-13 15:44:13,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:44:13,621 INFO L424 stractBuchiCegarLoop]: Abstraction has 150152 states and 194696 transitions. [2024-11-13 15:44:13,621 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 15:44:13,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150152 states and 194696 transitions. [2024-11-13 15:44:14,569 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 73696 [2024-11-13 15:44:14,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:44:14,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:44:14,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:14,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:44:14,571 INFO L745 eck$LassoCheckResult]: Stem: 2208838#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2208839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2209211#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2209212#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2209601#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2208638#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2208639#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2208310#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2208311#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2208263#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2208264#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2208594#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2208913#L696 assume !(0 == ~M_E~0); 2208914#L696-2 assume !(0 == ~T1_E~0); 2209623#L701-1 assume !(0 == ~T2_E~0); 2209626#L706-1 assume !(0 == ~T3_E~0); 2209149#L711-1 assume !(0 == ~T4_E~0); 2208708#L716-1 assume !(0 == ~T5_E~0); 2208709#L721-1 assume !(0 == ~T6_E~0); 2209057#L726-1 assume !(0 == ~E_M~0); 2209058#L731-1 assume !(0 == ~E_1~0); 2208985#L736-1 assume !(0 == ~E_2~0); 2208986#L741-1 assume !(0 == ~E_3~0); 2209173#L746-1 assume !(0 == ~E_4~0); 2208757#L751-1 assume !(0 == ~E_5~0); 2208758#L756-1 assume !(0 == ~E_6~0); 2208703#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2208345#L346 assume !(1 == ~m_pc~0); 2208346#L346-2 is_master_triggered_~__retres1~0#1 := 0; 2208785#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2209419#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2209878#L861 assume !(0 != activate_threads_~tmp~1#1); 2209876#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2209875#L365 assume !(1 == ~t1_pc~0); 2209874#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2209873#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2208321#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2208322#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2208386#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2209871#L384 assume !(1 == ~t2_pc~0); 2209870#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2209868#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2209866#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2209864#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2209862#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2209861#L403 assume !(1 == ~t3_pc~0); 2209860#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2209814#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2209815#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2209859#L885 assume !(0 != activate_threads_~tmp___2~0#1); 2209858#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2209857#L422 assume !(1 == ~t4_pc~0); 2209209#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2209210#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2209462#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2209855#L893 assume !(0 != activate_threads_~tmp___3~0#1); 2209107#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2208265#L441 assume !(1 == ~t5_pc~0); 2208266#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2209531#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2208789#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2208790#L901 assume !(0 != activate_threads_~tmp___4~0#1); 2209127#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2209128#L460 assume !(1 == ~t6_pc~0); 2209429#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2208280#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2208281#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2209841#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2209840#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2209839#L774 assume !(1 == ~M_E~0); 2209710#L774-2 assume !(1 == ~T1_E~0); 2209465#L779-1 assume !(1 == ~T2_E~0); 2208872#L784-1 assume !(1 == ~T3_E~0); 2208873#L789-1 assume !(1 == ~T4_E~0); 2209836#L794-1 assume !(1 == ~T5_E~0); 2209835#L799-1 assume !(1 == ~T6_E~0); 2209834#L804-1 assume !(1 == ~E_M~0); 2209720#L809-1 assume !(1 == ~E_1~0); 2209052#L814-1 assume !(1 == ~E_2~0); 2208204#L819-1 assume !(1 == ~E_3~0); 2208205#L824-1 assume !(1 == ~E_4~0); 2209195#L829-1 assume !(1 == ~E_5~0); 2209440#L834-1 assume !(1 == ~E_6~0); 2208678#L839-1 assume { :end_inline_reset_delta_events } true; 2208679#L1065-2 assume !false; 2228615#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2298372#L671-1 [2024-11-13 15:44:14,571 INFO L747 eck$LassoCheckResult]: Loop: 2298372#L671-1 assume !false; 2298370#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2298368#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2298365#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2298363#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2298361#L582 assume 0 != eval_~tmp~0#1; 2298359#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2298356#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 2298354#L590-2 havoc eval_~tmp_ndt_1~0#1; 2298352#L587-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2298349#L604 assume !(0 != eval_~tmp_ndt_2~0#1); 2298348#L604-2 havoc eval_~tmp_ndt_2~0#1; 2298344#L601-1 assume !(0 == ~t2_st~0); 2298340#L615-1 assume !(0 == ~t3_st~0); 2298337#L629-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 2298334#L646 assume !(0 != eval_~tmp_ndt_5~0#1); 2298335#L646-2 havoc eval_~tmp_ndt_5~0#1; 2316932#L643-1 assume !(0 == ~t5_st~0); 2298375#L657-1 assume !(0 == ~t6_st~0); 2298372#L671-1 [2024-11-13 15:44:14,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:14,571 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052149, now seen corresponding path program 2 times [2024-11-13 15:44:14,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:14,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53047788] [2024-11-13 15:44:14,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:14,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:14,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:14,588 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:44:14,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:14,615 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:44:14,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:14,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1808737154, now seen corresponding path program 1 times [2024-11-13 15:44:14,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:14,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369556651] [2024-11-13 15:44:14,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:14,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:14,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:14,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:44:14,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:44:14,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:44:14,627 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:44:14,627 INFO L85 PathProgramCache]: Analyzing trace with hash 1733554104, now seen corresponding path program 1 times [2024-11-13 15:44:14,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:44:14,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218425669] [2024-11-13 15:44:14,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:44:14,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:44:14,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:44:14,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:44:14,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:44:14,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218425669] [2024-11-13 15:44:14,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218425669] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:44:14,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:44:14,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:44:14,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118719975] [2024-11-13 15:44:14,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:44:14,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:44:14,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:44:14,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:44:14,783 INFO L87 Difference]: Start difference. First operand 150152 states and 194696 transitions. cyclomatic complexity: 44600 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)