./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 15:45:11,974 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 15:45:12,057 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 15:45:12,062 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 15:45:12,062 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 15:45:12,104 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 15:45:12,105 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 15:45:12,105 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 15:45:12,106 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 15:45:12,106 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 15:45:12,106 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 15:45:12,106 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 15:45:12,107 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 15:45:12,107 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 15:45:12,107 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 15:45:12,108 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 15:45:12,109 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 15:45:12,109 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 15:45:12,109 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 15:45:12,110 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 15:45:12,110 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 15:45:12,111 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 15:45:12,111 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 15:45:12,111 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 15:45:12,111 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 15:45:12,112 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 15:45:12,112 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2024-11-13 15:45:12,412 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 15:45:12,421 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 15:45:12,423 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 15:45:12,424 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 15:45:12,425 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 15:45:12,426 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c Unable to find full path for "g++" [2024-11-13 15:45:14,276 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 15:45:14,641 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 15:45:14,645 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2024-11-13 15:45:14,664 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/data/5726844f4/274ec35fa24242c3a829d6f1743dad0e/FLAG65c105a0b [2024-11-13 15:45:14,688 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/data/5726844f4/274ec35fa24242c3a829d6f1743dad0e [2024-11-13 15:45:14,690 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 15:45:14,692 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 15:45:14,696 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 15:45:14,697 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 15:45:14,702 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 15:45:14,703 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:45:14" (1/1) ... [2024-11-13 15:45:14,705 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@264a7bf7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:14, skipping insertion in model container [2024-11-13 15:45:14,706 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 03:45:14" (1/1) ... [2024-11-13 15:45:14,754 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 15:45:15,070 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:45:15,092 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 15:45:15,185 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 15:45:15,212 INFO L204 MainTranslator]: Completed translation [2024-11-13 15:45:15,213 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15 WrapperNode [2024-11-13 15:45:15,213 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 15:45:15,214 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 15:45:15,214 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 15:45:15,214 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 15:45:15,222 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,236 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,337 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1656 [2024-11-13 15:45:15,338 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 15:45:15,338 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 15:45:15,338 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 15:45:15,338 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 15:45:15,352 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,352 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,359 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,409 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 15:45:15,409 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,409 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,435 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,473 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,479 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,482 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,497 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 15:45:15,497 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 15:45:15,498 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 15:45:15,498 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 15:45:15,498 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (1/1) ... [2024-11-13 15:45:15,513 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:15,533 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:15,552 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:15,556 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 15:45:15,581 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 15:45:15,581 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 15:45:15,581 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 15:45:15,581 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 15:45:15,681 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 15:45:15,683 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 15:45:17,492 INFO L? ?]: Removed 318 outVars from TransFormulas that were not future-live. [2024-11-13 15:45:17,493 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 15:45:17,534 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 15:45:17,534 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-11-13 15:45:17,535 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:45:17 BoogieIcfgContainer [2024-11-13 15:45:17,535 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 15:45:17,537 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 15:45:17,537 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 15:45:17,549 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 15:45:17,550 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:45:17,550 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 03:45:14" (1/3) ... [2024-11-13 15:45:17,551 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4a0e2411 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:45:17, skipping insertion in model container [2024-11-13 15:45:17,551 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:45:17,551 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 03:45:15" (2/3) ... [2024-11-13 15:45:17,552 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4a0e2411 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 03:45:17, skipping insertion in model container [2024-11-13 15:45:17,552 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 15:45:17,552 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 03:45:17" (3/3) ... [2024-11-13 15:45:17,555 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2024-11-13 15:45:17,658 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 15:45:17,658 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 15:45:17,658 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 15:45:17,659 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 15:45:17,659 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 15:45:17,659 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 15:45:17,659 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 15:45:17,659 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 15:45:17,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:17,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-13 15:45:17,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:17,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:17,720 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:17,720 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:17,721 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 15:45:17,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:17,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-13 15:45:17,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:17,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:17,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:17,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:17,752 INFO L745 eck$LassoCheckResult]: Stem: 216#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 324#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 573#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 561#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 323#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 628#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 263#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 80#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L684true assume !(0 == ~M_E~0); 451#L684-2true assume !(0 == ~T1_E~0); 291#L689-1true assume !(0 == ~T2_E~0); 671#L694-1true assume !(0 == ~T3_E~0); 290#L699-1true assume !(0 == ~T4_E~0); 445#L704-1true assume !(0 == ~T5_E~0); 249#L709-1true assume !(0 == ~T6_E~0); 205#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 410#L719-1true assume !(0 == ~E_1~0); 595#L724-1true assume !(0 == ~E_2~0); 65#L729-1true assume !(0 == ~E_3~0); 569#L734-1true assume !(0 == ~E_4~0); 503#L739-1true assume !(0 == ~E_5~0); 179#L744-1true assume !(0 == ~E_6~0); 411#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43#L334true assume !(1 == ~m_pc~0); 244#L334-2true is_master_triggered_~__retres1~0#1 := 0; 514#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161#L849true assume !(0 != activate_threads_~tmp~1#1); 375#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125#L353true assume 1 == ~t1_pc~0; 603#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302#L857true assume !(0 != activate_threads_~tmp___0~0#1); 94#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567#L372true assume !(1 == ~t2_pc~0); 167#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 240#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 488#L865true assume !(0 != activate_threads_~tmp___1~0#1); 38#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463#L391true assume 1 == ~t3_pc~0; 586#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401#L873true assume !(0 != activate_threads_~tmp___2~0#1); 164#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485#L410true assume 1 == ~t4_pc~0; 602#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 380#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 490#L881true assume !(0 != activate_threads_~tmp___3~0#1); 169#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 284#L429true assume !(1 == ~t5_pc~0); 68#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 660#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 372#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159#L448true assume 1 == ~t6_pc~0; 88#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 346#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 541#L897true assume !(0 != activate_threads_~tmp___5~0#1); 648#L897-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 640#L762true assume !(1 == ~M_E~0); 193#L762-2true assume !(1 == ~T1_E~0); 600#L767-1true assume !(1 == ~T2_E~0); 550#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 373#L777-1true assume !(1 == ~T4_E~0); 276#L782-1true assume !(1 == ~T5_E~0); 83#L787-1true assume !(1 == ~T6_E~0); 82#L792-1true assume !(1 == ~E_M~0); 106#L797-1true assume !(1 == ~E_1~0); 429#L802-1true assume !(1 == ~E_2~0); 247#L807-1true assume !(1 == ~E_3~0); 498#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 619#L817-1true assume !(1 == ~E_5~0); 292#L822-1true assume !(1 == ~E_6~0); 512#L827-1true assume { :end_inline_reset_delta_events } true; 162#L1053-2true [2024-11-13 15:45:17,754 INFO L747 eck$LassoCheckResult]: Loop: 162#L1053-2true assume !false; 487#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376#L659-1true assume false; 110#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 507#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 266#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 438#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 191#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 28#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 359#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 492#L709-3true assume !(0 == ~T6_E~0); 337#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 186#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 318#L729-3true assume 0 == ~E_3~0;~E_3~0 := 1; 382#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 542#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 494#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L334-24true assume 1 == ~m_pc~0; 310#L335-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 332#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361#L353-24true assume !(1 == ~t1_pc~0); 634#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 556#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 553#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72#L372-24true assume 1 == ~t2_pc~0; 22#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 230#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 535#L865-24true assume !(0 != activate_threads_~tmp___1~0#1); 662#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207#L391-24true assume !(1 == ~t3_pc~0); 633#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 412#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277#L873-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 254#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141#L410-24true assume !(1 == ~t4_pc~0); 63#L410-26true is_transmit4_triggered_~__retres1~4#1 := 0; 386#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 493#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139#L429-24true assume 1 == ~t5_pc~0; 282#L430-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 385#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79#L448-24true assume 1 == ~t6_pc~0; 112#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285#L897-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 251#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 580#L767-3true assume !(1 == ~T2_E~0); 668#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 546#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 69#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 647#L787-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 394#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 206#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 453#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 664#L807-3true assume !(1 == ~E_3~0); 315#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 404#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 388#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 221#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 389#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 301#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 620#L1072true assume !(0 == start_simulation_~tmp~3#1); 151#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 502#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 605#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524#stop_simulation_returnLabel#1true start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 407#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 162#L1053-2true [2024-11-13 15:45:17,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:17,759 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2024-11-13 15:45:17,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:17,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894744054] [2024-11-13 15:45:17,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:17,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:17,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:18,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:18,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:18,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894744054] [2024-11-13 15:45:18,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894744054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:18,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:18,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:18,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367554282] [2024-11-13 15:45:18,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:18,099 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:18,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:18,100 INFO L85 PathProgramCache]: Analyzing trace with hash -44443139, now seen corresponding path program 1 times [2024-11-13 15:45:18,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:18,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075074132] [2024-11-13 15:45:18,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:18,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:18,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:18,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:18,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:18,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075074132] [2024-11-13 15:45:18,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075074132] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:18,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:18,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:18,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704894483] [2024-11-13 15:45:18,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:18,192 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:18,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:18,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:18,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:18,224 INFO L87 Difference]: Start difference. First operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:18,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:18,311 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2024-11-13 15:45:18,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2024-11-13 15:45:18,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:18,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 688 states and 1026 transitions. [2024-11-13 15:45:18,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:18,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:18,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1026 transitions. [2024-11-13 15:45:18,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:18,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-13 15:45:18,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1026 transitions. [2024-11-13 15:45:18,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:18,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4912790697674418) internal successors, (1026), 687 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:18,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1026 transitions. [2024-11-13 15:45:18,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-13 15:45:18,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:18,436 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-13 15:45:18,438 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 15:45:18,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1026 transitions. [2024-11-13 15:45:18,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:18,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:18,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:18,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:18,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:18,452 INFO L745 eck$LassoCheckResult]: Stem: 1789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1583#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1584#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1911#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1912#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1843#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1637#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1638#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1561#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1562#L684 assume !(0 == ~M_E~0); 2013#L684-2 assume !(0 == ~T1_E~0); 1872#L689-1 assume !(0 == ~T2_E~0); 1873#L694-1 assume !(0 == ~T3_E~0); 1870#L699-1 assume !(0 == ~T4_E~0); 1871#L704-1 assume !(0 == ~T5_E~0); 1828#L709-1 assume !(0 == ~T6_E~0); 1767#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1768#L719-1 assume !(0 == ~E_1~0); 1987#L724-1 assume !(0 == ~E_2~0); 1533#L729-1 assume !(0 == ~E_3~0); 1534#L734-1 assume !(0 == ~E_4~0); 2040#L739-1 assume !(0 == ~E_5~0); 1730#L744-1 assume !(0 == ~E_6~0); 1731#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490#L334 assume !(1 == ~m_pc~0); 1491#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1820#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1701#L849 assume !(0 != activate_threads_~tmp~1#1); 1702#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1634#L353 assume 1 == ~t1_pc~0; 1635#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1917#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1505#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1506#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1586#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L372 assume !(1 == ~t2_pc~0); 1690#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1689#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1918#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1479#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480#L391 assume 1 == ~t3_pc~0; 2024#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1402#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1428#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1429#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1708#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1709#L410 assume 1 == ~t4_pc~0; 2031#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1932#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1601#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1717#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1718#L429 assume !(1 == ~t5_pc~0); 1539#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1540#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1743#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1744#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1935#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1700#L448 assume 1 == ~t6_pc~0; 1574#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1575#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1903#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1904#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2059#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082#L762 assume !(1 == ~M_E~0); 1747#L762-2 assume !(1 == ~T1_E~0); 1748#L767-1 assume !(1 == ~T2_E~0); 2064#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1963#L777-1 assume !(1 == ~T4_E~0); 1858#L782-1 assume !(1 == ~T5_E~0); 1565#L787-1 assume !(1 == ~T6_E~0); 1563#L792-1 assume !(1 == ~E_M~0); 1564#L797-1 assume !(1 == ~E_1~0); 1606#L802-1 assume !(1 == ~E_2~0); 1824#L807-1 assume !(1 == ~E_3~0); 1825#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2035#L817-1 assume !(1 == ~E_5~0); 1876#L822-1 assume !(1 == ~E_6~0); 1877#L827-1 assume { :end_inline_reset_delta_events } true; 1703#L1053-2 [2024-11-13 15:45:18,452 INFO L747 eck$LassoCheckResult]: Loop: 1703#L1053-2 assume !false; 1704#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1680#L659-1 assume !false; 1668#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1669#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1937#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1938#L570 assume !(0 != eval_~tmp~0#1); 1611#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1849#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1850#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1397#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1457#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1458#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1944#L709-3 assume !(0 == ~T6_E~0); 1929#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1742#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1450#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1451#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1908#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1950#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1951#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2033#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1464#L334-24 assume 1 == ~m_pc~0; 1465#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1604#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1629#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1434#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1435#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1947#L353-24 assume 1 == ~t1_pc~0; 1948#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1975#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2065#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1481#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1482#L372-24 assume 1 == ~t2_pc~0; 1443#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1444#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1803#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2052#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 2053#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1772#L391-24 assume 1 == ~t3_pc~0; 1773#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1988#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1945#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1859#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1834#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1667#L410-24 assume 1 == ~t4_pc~0; 1605#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1531#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1968#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1713#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1559#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L429-24 assume !(1 == ~t5_pc~0); 1664#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1863#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1835#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1609#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1610#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1554#L448-24 assume !(1 == ~t6_pc~0); 1555#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1548#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1724#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1866#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1867#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1832#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1833#L767-3 assume !(1 == ~T2_E~0); 2071#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2061#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1541#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1542#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1976#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1769#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1770#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2015#L807-3 assume !(1 == ~E_3~0); 1901#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1902#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1982#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1972#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1796#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1441#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1889#L1072 assume !(0 == start_simulation_~tmp~3#1); 1684#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1685#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1550#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1469#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1470#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2047#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1985#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1703#L1053-2 [2024-11-13 15:45:18,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:18,453 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2024-11-13 15:45:18,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:18,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964176243] [2024-11-13 15:45:18,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:18,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:18,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:18,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:18,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:18,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964176243] [2024-11-13 15:45:18,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964176243] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:18,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:18,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:18,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971730562] [2024-11-13 15:45:18,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:18,586 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:18,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:18,587 INFO L85 PathProgramCache]: Analyzing trace with hash -92887877, now seen corresponding path program 1 times [2024-11-13 15:45:18,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:18,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670214560] [2024-11-13 15:45:18,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:18,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:18,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:18,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:18,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:18,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670214560] [2024-11-13 15:45:18,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670214560] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:18,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:18,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:18,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446577540] [2024-11-13 15:45:18,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:18,776 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:18,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:18,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:18,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:18,777 INFO L87 Difference]: Start difference. First operand 688 states and 1026 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:18,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:18,809 INFO L93 Difference]: Finished difference Result 688 states and 1025 transitions. [2024-11-13 15:45:18,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1025 transitions. [2024-11-13 15:45:18,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:18,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1025 transitions. [2024-11-13 15:45:18,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:18,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:18,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1025 transitions. [2024-11-13 15:45:18,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:18,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-13 15:45:18,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1025 transitions. [2024-11-13 15:45:18,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:18,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.489825581395349) internal successors, (1025), 687 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:18,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1025 transitions. [2024-11-13 15:45:18,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-13 15:45:18,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:18,865 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-13 15:45:18,867 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 15:45:18,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1025 transitions. [2024-11-13 15:45:18,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:18,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:18,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:18,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:18,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:18,882 INFO L745 eck$LassoCheckResult]: Stem: 3170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2964#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2965#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3294#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3295#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3226#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3020#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3021#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2942#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943#L684 assume !(0 == ~M_E~0); 3396#L684-2 assume !(0 == ~T1_E~0); 3255#L689-1 assume !(0 == ~T2_E~0); 3256#L694-1 assume !(0 == ~T3_E~0); 3253#L699-1 assume !(0 == ~T4_E~0); 3254#L704-1 assume !(0 == ~T5_E~0); 3211#L709-1 assume !(0 == ~T6_E~0); 3150#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3151#L719-1 assume !(0 == ~E_1~0); 3370#L724-1 assume !(0 == ~E_2~0); 2916#L729-1 assume !(0 == ~E_3~0); 2917#L734-1 assume !(0 == ~E_4~0); 3423#L739-1 assume !(0 == ~E_5~0); 3113#L744-1 assume !(0 == ~E_6~0); 3114#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2873#L334 assume !(1 == ~m_pc~0); 2874#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3203#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3115#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3084#L849 assume !(0 != activate_threads_~tmp~1#1); 3085#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3017#L353 assume 1 == ~t1_pc~0; 3018#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3300#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2889#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2969#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2970#L372 assume !(1 == ~t2_pc~0); 3073#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3072#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3301#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2862#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2863#L391 assume 1 == ~t3_pc~0; 3405#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2785#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2812#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3091#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3092#L410 assume 1 == ~t4_pc~0; 3413#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3314#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2983#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2984#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3097#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3098#L429 assume !(1 == ~t5_pc~0); 2922#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2923#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3126#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3127#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3318#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3083#L448 assume 1 == ~t6_pc~0; 2957#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2958#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3285#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3442#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3465#L762 assume !(1 == ~M_E~0); 3130#L762-2 assume !(1 == ~T1_E~0); 3131#L767-1 assume !(1 == ~T2_E~0); 3447#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3346#L777-1 assume !(1 == ~T4_E~0); 3241#L782-1 assume !(1 == ~T5_E~0); 2948#L787-1 assume !(1 == ~T6_E~0); 2946#L792-1 assume !(1 == ~E_M~0); 2947#L797-1 assume !(1 == ~E_1~0); 2988#L802-1 assume !(1 == ~E_2~0); 3207#L807-1 assume !(1 == ~E_3~0); 3208#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3418#L817-1 assume !(1 == ~E_5~0); 3257#L822-1 assume !(1 == ~E_6~0); 3258#L827-1 assume { :end_inline_reset_delta_events } true; 3086#L1053-2 [2024-11-13 15:45:18,882 INFO L747 eck$LassoCheckResult]: Loop: 3086#L1053-2 assume !false; 3087#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3063#L659-1 assume !false; 3051#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3052#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3054#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3320#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3321#L570 assume !(0 != eval_~tmp~0#1); 2994#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2995#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3230#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3231#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2780#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2781#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2840#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2841#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3327#L709-3 assume !(0 == ~T6_E~0); 3310#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3120#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2833#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2834#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3290#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3334#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3416#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2847#L334-24 assume 1 == ~m_pc~0; 2848#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2987#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3012#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2815#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2816#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L353-24 assume 1 == ~t1_pc~0; 3330#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3358#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3448#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3449#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2864#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2865#L372-24 assume 1 == ~t2_pc~0; 2826#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2827#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3186#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3436#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 3437#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L391-24 assume 1 == ~t3_pc~0; 3156#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3371#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3242#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3220#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410-24 assume !(1 == ~t4_pc~0); 2913#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3351#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3096#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2944#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2945#L429-24 assume 1 == ~t5_pc~0; 3046#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3246#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3221#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2992#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2993#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2939#L448-24 assume !(1 == ~t6_pc~0); 2940#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2931#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2932#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3107#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3249#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3250#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3215#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3216#L767-3 assume !(1 == ~T2_E~0); 3454#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3444#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2925#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3359#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3152#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3153#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3398#L807-3 assume !(1 == ~E_3~0); 3286#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3365#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3355#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3179#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2824#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3272#L1072 assume !(0 == start_simulation_~tmp~3#1); 3067#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3068#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2933#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2854#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2855#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3430#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3368#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3086#L1053-2 [2024-11-13 15:45:18,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:18,883 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2024-11-13 15:45:18,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:18,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764675589] [2024-11-13 15:45:18,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:18,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:18,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:18,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:18,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:18,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764675589] [2024-11-13 15:45:18,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764675589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:18,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:18,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:18,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657683439] [2024-11-13 15:45:18,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:18,981 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:18,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:18,982 INFO L85 PathProgramCache]: Analyzing trace with hash -9437189, now seen corresponding path program 1 times [2024-11-13 15:45:18,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:18,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687536288] [2024-11-13 15:45:18,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:18,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687536288] [2024-11-13 15:45:19,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687536288] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185744270] [2024-11-13 15:45:19,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,119 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:19,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:19,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:19,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:19,120 INFO L87 Difference]: Start difference. First operand 688 states and 1025 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:19,156 INFO L93 Difference]: Finished difference Result 688 states and 1024 transitions. [2024-11-13 15:45:19,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1024 transitions. [2024-11-13 15:45:19,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1024 transitions. [2024-11-13 15:45:19,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:19,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:19,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1024 transitions. [2024-11-13 15:45:19,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:19,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-13 15:45:19,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1024 transitions. [2024-11-13 15:45:19,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:19,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4883720930232558) internal successors, (1024), 687 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1024 transitions. [2024-11-13 15:45:19,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-13 15:45:19,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:19,203 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-13 15:45:19,204 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 15:45:19,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1024 transitions. [2024-11-13 15:45:19,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:19,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:19,210 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,210 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,210 INFO L745 eck$LassoCheckResult]: Stem: 4553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4347#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4348#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4677#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4678#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4609#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4403#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4404#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4325#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4326#L684 assume !(0 == ~M_E~0); 4779#L684-2 assume !(0 == ~T1_E~0); 4638#L689-1 assume !(0 == ~T2_E~0); 4639#L694-1 assume !(0 == ~T3_E~0); 4636#L699-1 assume !(0 == ~T4_E~0); 4637#L704-1 assume !(0 == ~T5_E~0); 4594#L709-1 assume !(0 == ~T6_E~0); 4533#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4534#L719-1 assume !(0 == ~E_1~0); 4753#L724-1 assume !(0 == ~E_2~0); 4299#L729-1 assume !(0 == ~E_3~0); 4300#L734-1 assume !(0 == ~E_4~0); 4806#L739-1 assume !(0 == ~E_5~0); 4496#L744-1 assume !(0 == ~E_6~0); 4497#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4256#L334 assume !(1 == ~m_pc~0); 4257#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4586#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4498#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4467#L849 assume !(0 != activate_threads_~tmp~1#1); 4468#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4400#L353 assume 1 == ~t1_pc~0; 4401#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4683#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4272#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4352#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4353#L372 assume !(1 == ~t2_pc~0); 4456#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4455#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4684#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4245#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4246#L391 assume 1 == ~t3_pc~0; 4788#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4168#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4194#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4195#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4474#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4475#L410 assume 1 == ~t4_pc~0; 4797#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4697#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4367#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4480#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4481#L429 assume !(1 == ~t5_pc~0); 4305#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4306#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4510#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4701#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4466#L448 assume 1 == ~t6_pc~0; 4340#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4341#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4825#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4848#L762 assume !(1 == ~M_E~0); 4513#L762-2 assume !(1 == ~T1_E~0); 4514#L767-1 assume !(1 == ~T2_E~0); 4830#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4729#L777-1 assume !(1 == ~T4_E~0); 4624#L782-1 assume !(1 == ~T5_E~0); 4331#L787-1 assume !(1 == ~T6_E~0); 4329#L792-1 assume !(1 == ~E_M~0); 4330#L797-1 assume !(1 == ~E_1~0); 4371#L802-1 assume !(1 == ~E_2~0); 4590#L807-1 assume !(1 == ~E_3~0); 4591#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4801#L817-1 assume !(1 == ~E_5~0); 4642#L822-1 assume !(1 == ~E_6~0); 4643#L827-1 assume { :end_inline_reset_delta_events } true; 4469#L1053-2 [2024-11-13 15:45:19,210 INFO L747 eck$LassoCheckResult]: Loop: 4469#L1053-2 assume !false; 4470#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4446#L659-1 assume !false; 4434#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4435#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4437#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4704#L570 assume !(0 != eval_~tmp~0#1); 4377#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4615#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4616#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4163#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4164#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4223#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4224#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4710#L709-3 assume !(0 == ~T6_E~0); 4693#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4503#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4216#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4217#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4673#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4716#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4717#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4799#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4230#L334-24 assume 1 == ~m_pc~0; 4231#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4370#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4395#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4198#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4199#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4712#L353-24 assume 1 == ~t1_pc~0; 4713#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4741#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4832#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4247#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4248#L372-24 assume 1 == ~t2_pc~0; 4209#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4569#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4819#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 4820#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L391-24 assume 1 == ~t3_pc~0; 4539#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4754#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4715#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4625#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4603#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4433#L410-24 assume 1 == ~t4_pc~0; 4372#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4297#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4734#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4479#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4327#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4328#L429-24 assume 1 == ~t5_pc~0; 4429#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4629#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4604#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4375#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4376#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4322#L448-24 assume !(1 == ~t6_pc~0); 4323#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4314#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4315#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4490#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4632#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4633#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4598#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4599#L767-3 assume !(1 == ~T2_E~0); 4837#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4827#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4307#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4308#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4742#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4535#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4536#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4781#L807-3 assume !(1 == ~E_3~0); 4669#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4670#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4748#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4738#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4562#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4207#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4654#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4655#L1072 assume !(0 == start_simulation_~tmp~3#1); 4450#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4451#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4316#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4237#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4238#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4813#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4751#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L1053-2 [2024-11-13 15:45:19,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,211 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2024-11-13 15:45:19,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63095866] [2024-11-13 15:45:19,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63095866] [2024-11-13 15:45:19,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63095866] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237943559] [2024-11-13 15:45:19,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,300 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:19,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,301 INFO L85 PathProgramCache]: Analyzing trace with hash 864040506, now seen corresponding path program 1 times [2024-11-13 15:45:19,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713580613] [2024-11-13 15:45:19,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713580613] [2024-11-13 15:45:19,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713580613] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,391 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106247851] [2024-11-13 15:45:19,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,392 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:19,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:19,393 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:19,393 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:19,393 INFO L87 Difference]: Start difference. First operand 688 states and 1024 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:19,420 INFO L93 Difference]: Finished difference Result 688 states and 1023 transitions. [2024-11-13 15:45:19,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1023 transitions. [2024-11-13 15:45:19,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1023 transitions. [2024-11-13 15:45:19,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:19,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:19,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1023 transitions. [2024-11-13 15:45:19,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:19,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-13 15:45:19,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1023 transitions. [2024-11-13 15:45:19,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:19,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4869186046511629) internal successors, (1023), 687 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1023 transitions. [2024-11-13 15:45:19,467 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-13 15:45:19,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:19,468 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-13 15:45:19,468 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 15:45:19,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1023 transitions. [2024-11-13 15:45:19,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:19,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:19,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,477 INFO L745 eck$LassoCheckResult]: Stem: 5938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5733#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5734#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6060#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6061#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5992#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5786#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5787#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5711#L684 assume !(0 == ~M_E~0); 6163#L684-2 assume !(0 == ~T1_E~0); 6021#L689-1 assume !(0 == ~T2_E~0); 6022#L694-1 assume !(0 == ~T3_E~0); 6019#L699-1 assume !(0 == ~T4_E~0); 6020#L704-1 assume !(0 == ~T5_E~0); 5977#L709-1 assume !(0 == ~T6_E~0); 5916#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5917#L719-1 assume !(0 == ~E_1~0); 6136#L724-1 assume !(0 == ~E_2~0); 5682#L729-1 assume !(0 == ~E_3~0); 5683#L734-1 assume !(0 == ~E_4~0); 6189#L739-1 assume !(0 == ~E_5~0); 5879#L744-1 assume !(0 == ~E_6~0); 5880#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5639#L334 assume !(1 == ~m_pc~0); 5640#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5969#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5882#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5850#L849 assume !(0 != activate_threads_~tmp~1#1); 5851#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5783#L353 assume 1 == ~t1_pc~0; 5784#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6066#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5655#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5735#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5736#L372 assume !(1 == ~t2_pc~0); 5839#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5838#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6067#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5628#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5629#L391 assume 1 == ~t3_pc~0; 6173#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5551#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5577#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5578#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5857#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5858#L410 assume 1 == ~t4_pc~0; 6180#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6081#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5749#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5750#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5866#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5867#L429 assume !(1 == ~t5_pc~0); 5688#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5689#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5893#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6084#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5849#L448 assume 1 == ~t6_pc~0; 5723#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5724#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6208#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6231#L762 assume !(1 == ~M_E~0); 5896#L762-2 assume !(1 == ~T1_E~0); 5897#L767-1 assume !(1 == ~T2_E~0); 6213#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6112#L777-1 assume !(1 == ~T4_E~0); 6007#L782-1 assume !(1 == ~T5_E~0); 5714#L787-1 assume !(1 == ~T6_E~0); 5712#L792-1 assume !(1 == ~E_M~0); 5713#L797-1 assume !(1 == ~E_1~0); 5755#L802-1 assume !(1 == ~E_2~0); 5973#L807-1 assume !(1 == ~E_3~0); 5974#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6184#L817-1 assume !(1 == ~E_5~0); 6025#L822-1 assume !(1 == ~E_6~0); 6026#L827-1 assume { :end_inline_reset_delta_events } true; 5852#L1053-2 [2024-11-13 15:45:19,478 INFO L747 eck$LassoCheckResult]: Loop: 5852#L1053-2 assume !false; 5853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5829#L659-1 assume !false; 5817#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5818#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5820#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6087#L570 assume !(0 != eval_~tmp~0#1); 5762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5998#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5999#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5546#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5547#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5606#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5607#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6093#L709-3 assume !(0 == ~T6_E~0); 6078#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5891#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5599#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5600#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6057#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6099#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6100#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6182#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5613#L334-24 assume 1 == ~m_pc~0; 5614#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5753#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5778#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5581#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5582#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6094#L353-24 assume !(1 == ~t1_pc~0); 6096#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6124#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6214#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6215#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5630#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5631#L372-24 assume 1 == ~t2_pc~0; 5592#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5593#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5952#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6201#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 6202#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5921#L391-24 assume 1 == ~t3_pc~0; 5922#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6137#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6097#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6008#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5983#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5816#L410-24 assume 1 == ~t4_pc~0; 5754#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5680#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6117#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5862#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5708#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5709#L429-24 assume 1 == ~t5_pc~0; 5812#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6012#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5984#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5758#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5759#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5703#L448-24 assume !(1 == ~t6_pc~0); 5704#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 5697#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5698#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5873#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5981#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5982#L767-3 assume !(1 == ~T2_E~0); 6220#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6210#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5690#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5691#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6125#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5918#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5919#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6164#L807-3 assume !(1 == ~E_3~0); 6050#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6051#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6131#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6121#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5945#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5590#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6037#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6038#L1072 assume !(0 == start_simulation_~tmp~3#1); 5833#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5834#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5699#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5653#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5620#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5621#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6196#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6134#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5852#L1053-2 [2024-11-13 15:45:19,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2024-11-13 15:45:19,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181912862] [2024-11-13 15:45:19,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181912862] [2024-11-13 15:45:19,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181912862] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662228500] [2024-11-13 15:45:19,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,544 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:19,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1440969147, now seen corresponding path program 1 times [2024-11-13 15:45:19,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142963322] [2024-11-13 15:45:19,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142963322] [2024-11-13 15:45:19,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142963322] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841073375] [2024-11-13 15:45:19,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,636 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:19,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:19,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:19,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:19,636 INFO L87 Difference]: Start difference. First operand 688 states and 1023 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:19,662 INFO L93 Difference]: Finished difference Result 688 states and 1022 transitions. [2024-11-13 15:45:19,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1022 transitions. [2024-11-13 15:45:19,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1022 transitions. [2024-11-13 15:45:19,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:19,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:19,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1022 transitions. [2024-11-13 15:45:19,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:19,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-13 15:45:19,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1022 transitions. [2024-11-13 15:45:19,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:19,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4854651162790697) internal successors, (1022), 687 states have internal predecessors, (1022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1022 transitions. [2024-11-13 15:45:19,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-13 15:45:19,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:19,695 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-13 15:45:19,695 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 15:45:19,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1022 transitions. [2024-11-13 15:45:19,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:19,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:19,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,703 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,703 INFO L745 eck$LassoCheckResult]: Stem: 7319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7113#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7114#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7443#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7444#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7375#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7169#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7170#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7091#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7092#L684 assume !(0 == ~M_E~0); 7545#L684-2 assume !(0 == ~T1_E~0); 7404#L689-1 assume !(0 == ~T2_E~0); 7405#L694-1 assume !(0 == ~T3_E~0); 7402#L699-1 assume !(0 == ~T4_E~0); 7403#L704-1 assume !(0 == ~T5_E~0); 7360#L709-1 assume !(0 == ~T6_E~0); 7299#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7300#L719-1 assume !(0 == ~E_1~0); 7519#L724-1 assume !(0 == ~E_2~0); 7065#L729-1 assume !(0 == ~E_3~0); 7066#L734-1 assume !(0 == ~E_4~0); 7572#L739-1 assume !(0 == ~E_5~0); 7262#L744-1 assume !(0 == ~E_6~0); 7263#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7022#L334 assume !(1 == ~m_pc~0); 7023#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7352#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7233#L849 assume !(0 != activate_threads_~tmp~1#1); 7234#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7166#L353 assume 1 == ~t1_pc~0; 7167#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7449#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7038#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7118#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7119#L372 assume !(1 == ~t2_pc~0); 7222#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7221#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7450#L865 assume !(0 != activate_threads_~tmp___1~0#1); 7011#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L391 assume 1 == ~t3_pc~0; 7554#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6934#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6961#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7240#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7241#L410 assume 1 == ~t4_pc~0; 7562#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7463#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7133#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7246#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L429 assume !(1 == ~t5_pc~0); 7071#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7072#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7276#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7467#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7232#L448 assume 1 == ~t6_pc~0; 7106#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7107#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7434#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7591#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7614#L762 assume !(1 == ~M_E~0); 7279#L762-2 assume !(1 == ~T1_E~0); 7280#L767-1 assume !(1 == ~T2_E~0); 7596#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7495#L777-1 assume !(1 == ~T4_E~0); 7390#L782-1 assume !(1 == ~T5_E~0); 7097#L787-1 assume !(1 == ~T6_E~0); 7095#L792-1 assume !(1 == ~E_M~0); 7096#L797-1 assume !(1 == ~E_1~0); 7137#L802-1 assume !(1 == ~E_2~0); 7356#L807-1 assume !(1 == ~E_3~0); 7357#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L817-1 assume !(1 == ~E_5~0); 7406#L822-1 assume !(1 == ~E_6~0); 7407#L827-1 assume { :end_inline_reset_delta_events } true; 7235#L1053-2 [2024-11-13 15:45:19,704 INFO L747 eck$LassoCheckResult]: Loop: 7235#L1053-2 assume !false; 7236#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7212#L659-1 assume !false; 7200#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7201#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7203#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7469#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7470#L570 assume !(0 != eval_~tmp~0#1); 7143#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7144#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7379#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7380#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6929#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6930#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6989#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7476#L709-3 assume !(0 == ~T6_E~0); 7459#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7269#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6982#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6983#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7439#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7482#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7483#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7565#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6996#L334-24 assume 1 == ~m_pc~0; 6997#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7136#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7161#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6964#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6965#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7478#L353-24 assume 1 == ~t1_pc~0; 7479#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7507#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7597#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7598#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7013#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7014#L372-24 assume !(1 == ~t2_pc~0); 6977#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6976#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7585#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 7586#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7304#L391-24 assume 1 == ~t3_pc~0; 7305#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7520#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7481#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7391#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7369#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7199#L410-24 assume 1 == ~t4_pc~0; 7138#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7063#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7500#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7245#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7093#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7094#L429-24 assume 1 == ~t5_pc~0; 7195#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7370#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7141#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7142#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7088#L448-24 assume !(1 == ~t6_pc~0); 7089#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7080#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7081#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7256#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7398#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7399#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7364#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7365#L767-3 assume !(1 == ~T2_E~0); 7603#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7593#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7073#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7074#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7508#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7301#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7302#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7547#L807-3 assume !(1 == ~E_3~0); 7435#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7436#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7514#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7504#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7328#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6973#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7421#L1072 assume !(0 == start_simulation_~tmp~3#1); 7216#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7036#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 7003#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7004#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7579#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7517#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7235#L1053-2 [2024-11-13 15:45:19,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,705 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2024-11-13 15:45:19,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599798084] [2024-11-13 15:45:19,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599798084] [2024-11-13 15:45:19,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599798084] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936024713] [2024-11-13 15:45:19,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,769 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:19,769 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1104307835, now seen corresponding path program 1 times [2024-11-13 15:45:19,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972186702] [2024-11-13 15:45:19,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:19,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:19,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:19,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972186702] [2024-11-13 15:45:19,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972186702] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:19,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:19,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:19,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848617587] [2024-11-13 15:45:19,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:19,853 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:19,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:19,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:19,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:19,854 INFO L87 Difference]: Start difference. First operand 688 states and 1022 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:19,881 INFO L93 Difference]: Finished difference Result 688 states and 1021 transitions. [2024-11-13 15:45:19,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1021 transitions. [2024-11-13 15:45:19,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1021 transitions. [2024-11-13 15:45:19,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-13 15:45:19,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-13 15:45:19,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1021 transitions. [2024-11-13 15:45:19,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:19,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-13 15:45:19,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1021 transitions. [2024-11-13 15:45:19,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-13 15:45:19,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4840116279069768) internal successors, (1021), 687 states have internal predecessors, (1021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:19,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1021 transitions. [2024-11-13 15:45:19,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-13 15:45:19,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:19,917 INFO L424 stractBuchiCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-13 15:45:19,917 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 15:45:19,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1021 transitions. [2024-11-13 15:45:19,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-13 15:45:19,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:19,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:19,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:19,924 INFO L745 eck$LassoCheckResult]: Stem: 8702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8496#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8497#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8826#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8827#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8758#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8552#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8553#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8474#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8475#L684 assume !(0 == ~M_E~0); 8928#L684-2 assume !(0 == ~T1_E~0); 8787#L689-1 assume !(0 == ~T2_E~0); 8788#L694-1 assume !(0 == ~T3_E~0); 8785#L699-1 assume !(0 == ~T4_E~0); 8786#L704-1 assume !(0 == ~T5_E~0); 8743#L709-1 assume !(0 == ~T6_E~0); 8682#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8683#L719-1 assume !(0 == ~E_1~0); 8902#L724-1 assume !(0 == ~E_2~0); 8448#L729-1 assume !(0 == ~E_3~0); 8449#L734-1 assume !(0 == ~E_4~0); 8955#L739-1 assume !(0 == ~E_5~0); 8645#L744-1 assume !(0 == ~E_6~0); 8646#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8405#L334 assume !(1 == ~m_pc~0); 8406#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8735#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8647#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8616#L849 assume !(0 != activate_threads_~tmp~1#1); 8617#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8549#L353 assume 1 == ~t1_pc~0; 8550#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8832#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8421#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8501#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8502#L372 assume !(1 == ~t2_pc~0); 8605#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8604#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8833#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8394#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8395#L391 assume 1 == ~t3_pc~0; 8937#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8344#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8623#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8624#L410 assume 1 == ~t4_pc~0; 8946#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8846#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8516#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8630#L429 assume !(1 == ~t5_pc~0); 8454#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8455#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8658#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8659#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8850#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8615#L448 assume 1 == ~t6_pc~0; 8489#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8490#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8819#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8974#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8997#L762 assume !(1 == ~M_E~0); 8662#L762-2 assume !(1 == ~T1_E~0); 8663#L767-1 assume !(1 == ~T2_E~0); 8979#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8878#L777-1 assume !(1 == ~T4_E~0); 8773#L782-1 assume !(1 == ~T5_E~0); 8480#L787-1 assume !(1 == ~T6_E~0); 8478#L792-1 assume !(1 == ~E_M~0); 8479#L797-1 assume !(1 == ~E_1~0); 8520#L802-1 assume !(1 == ~E_2~0); 8739#L807-1 assume !(1 == ~E_3~0); 8740#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8950#L817-1 assume !(1 == ~E_5~0); 8791#L822-1 assume !(1 == ~E_6~0); 8792#L827-1 assume { :end_inline_reset_delta_events } true; 8618#L1053-2 [2024-11-13 15:45:19,924 INFO L747 eck$LassoCheckResult]: Loop: 8618#L1053-2 assume !false; 8619#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8595#L659-1 assume !false; 8583#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8584#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8586#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8853#L570 assume !(0 != eval_~tmp~0#1); 8526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8764#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8765#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8312#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8313#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8372#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8373#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8859#L709-3 assume !(0 == ~T6_E~0); 8842#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8652#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8365#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8366#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8822#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8865#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8866#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8948#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8379#L334-24 assume 1 == ~m_pc~0; 8380#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8519#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8544#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8347#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8348#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8861#L353-24 assume 1 == ~t1_pc~0; 8862#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8890#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8980#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8981#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8396#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8397#L372-24 assume 1 == ~t2_pc~0; 8358#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8359#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8718#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8968#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 8969#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8687#L391-24 assume 1 == ~t3_pc~0; 8688#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8903#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8864#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8774#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8752#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8582#L410-24 assume 1 == ~t4_pc~0; 8521#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8446#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8883#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8628#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8476#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8477#L429-24 assume 1 == ~t5_pc~0; 8578#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8778#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8753#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8522#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8523#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8468#L448-24 assume !(1 == ~t6_pc~0); 8469#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8463#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8464#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8781#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8782#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8747#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8748#L767-3 assume !(1 == ~T2_E~0); 8986#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8456#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8457#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8891#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8684#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8685#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8930#L807-3 assume !(1 == ~E_3~0); 8816#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8897#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8887#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8710#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8354#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8804#L1072 assume !(0 == start_simulation_~tmp~3#1); 8599#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8600#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8465#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8384#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8385#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8962#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8900#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8618#L1053-2 [2024-11-13 15:45:19,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:19,924 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2024-11-13 15:45:19,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:19,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797613318] [2024-11-13 15:45:19,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:19,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:19,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797613318] [2024-11-13 15:45:20,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797613318] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:20,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059134112] [2024-11-13 15:45:20,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,041 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:20,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:20,042 INFO L85 PathProgramCache]: Analyzing trace with hash 864040506, now seen corresponding path program 2 times [2024-11-13 15:45:20,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:20,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397325671] [2024-11-13 15:45:20,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:20,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:20,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397325671] [2024-11-13 15:45:20,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397325671] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:20,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925121098] [2024-11-13 15:45:20,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,116 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:20,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:20,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:20,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:20,117 INFO L87 Difference]: Start difference. First operand 688 states and 1021 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:20,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:20,352 INFO L93 Difference]: Finished difference Result 1184 states and 1752 transitions. [2024-11-13 15:45:20,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1184 states and 1752 transitions. [2024-11-13 15:45:20,361 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2024-11-13 15:45:20,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1184 states to 1184 states and 1752 transitions. [2024-11-13 15:45:20,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1184 [2024-11-13 15:45:20,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1184 [2024-11-13 15:45:20,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1752 transitions. [2024-11-13 15:45:20,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:20,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1752 transitions. [2024-11-13 15:45:20,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1752 transitions. [2024-11-13 15:45:20,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 1183. [2024-11-13 15:45:20,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1183 states have (on average 1.4801352493660187) internal successors, (1751), 1182 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:20,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 1751 transitions. [2024-11-13 15:45:20,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2024-11-13 15:45:20,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:20,414 INFO L424 stractBuchiCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2024-11-13 15:45:20,414 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 15:45:20,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1183 states and 1751 transitions. [2024-11-13 15:45:20,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2024-11-13 15:45:20,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:20,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:20,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:20,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:20,423 INFO L745 eck$LassoCheckResult]: Stem: 10586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10380#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10381#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10715#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10716#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10646#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10436#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10437#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10356#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10357#L684 assume !(0 == ~M_E~0); 10824#L684-2 assume !(0 == ~T1_E~0); 10676#L689-1 assume !(0 == ~T2_E~0); 10677#L694-1 assume !(0 == ~T3_E~0); 10674#L699-1 assume !(0 == ~T4_E~0); 10675#L704-1 assume !(0 == ~T5_E~0); 10631#L709-1 assume !(0 == ~T6_E~0); 10566#L714-1 assume !(0 == ~E_M~0); 10567#L719-1 assume !(0 == ~E_1~0); 10797#L724-1 assume !(0 == ~E_2~0); 10330#L729-1 assume !(0 == ~E_3~0); 10331#L734-1 assume !(0 == ~E_4~0); 10855#L739-1 assume !(0 == ~E_5~0); 10529#L744-1 assume !(0 == ~E_6~0); 10530#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10287#L334 assume !(1 == ~m_pc~0); 10288#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10531#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10500#L849 assume !(0 != activate_threads_~tmp~1#1); 10501#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10433#L353 assume 1 == ~t1_pc~0; 10434#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10721#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10302#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10303#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10385#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L372 assume !(1 == ~t2_pc~0); 10489#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10488#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10722#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10276#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10277#L391 assume 1 == ~t3_pc~0; 10833#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10199#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10226#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10507#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10508#L410 assume 1 == ~t4_pc~0; 10843#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10735#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10400#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10513#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10514#L429 assume !(1 == ~t5_pc~0); 10336#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10337#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10543#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10739#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10499#L448 assume 1 == ~t6_pc~0; 10373#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10374#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10706#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10874#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10903#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10904#L762-2 assume !(1 == ~T1_E~0); 11360#L767-1 assume !(1 == ~T2_E~0); 10879#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10768#L777-1 assume !(1 == ~T4_E~0); 10662#L782-1 assume !(1 == ~T5_E~0); 10363#L787-1 assume !(1 == ~T6_E~0); 10364#L792-1 assume !(1 == ~E_M~0); 10361#L797-1 assume !(1 == ~E_1~0); 10970#L802-1 assume !(1 == ~E_2~0); 10968#L807-1 assume !(1 == ~E_3~0); 10966#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10948#L817-1 assume !(1 == ~E_5~0); 10940#L822-1 assume !(1 == ~E_6~0); 10934#L827-1 assume { :end_inline_reset_delta_events } true; 10928#L1053-2 [2024-11-13 15:45:20,424 INFO L747 eck$LassoCheckResult]: Loop: 10928#L1053-2 assume !false; 10845#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10479#L659-1 assume !false; 10467#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10468#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10470#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10742#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10743#L570 assume !(0 != eval_~tmp~0#1); 10790#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10911#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10912#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11365#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11364#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11363#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11362#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11361#L709-3 assume !(0 == ~T6_E~0); 11359#L714-3 assume !(0 == ~E_M~0); 11358#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11357#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11356#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11355#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11354#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11353#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11352#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11351#L334-24 assume 1 == ~m_pc~0; 11349#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11348#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11347#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11346#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11345#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11344#L353-24 assume !(1 == ~t1_pc~0); 11342#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11340#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11337#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11335#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11333#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11331#L372-24 assume !(1 == ~t2_pc~0); 11328#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11324#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11322#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11320#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 11319#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10571#L391-24 assume 1 == ~t3_pc~0; 10572#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10798#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10754#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10663#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10640#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10466#L410-24 assume 1 == ~t4_pc~0; 10405#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10328#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10773#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10512#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10358#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10359#L429-24 assume 1 == ~t5_pc~0; 10462#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10667#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10641#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10408#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10409#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10353#L448-24 assume !(1 == ~t6_pc~0); 10354#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10345#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10346#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10523#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10670#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10671#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10635#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10636#L767-3 assume !(1 == ~T2_E~0); 10886#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10876#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10338#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10339#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10784#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10785#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11200#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11199#L807-3 assume !(1 == ~E_3~0); 11198#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11197#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11196#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11195#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10595#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10238#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10693#L1072 assume !(0 == start_simulation_~tmp~3#1); 10483#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10484#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10971#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10969#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10967#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10949#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10941#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10935#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10928#L1053-2 [2024-11-13 15:45:20,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:20,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2024-11-13 15:45:20,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:20,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016289942] [2024-11-13 15:45:20,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:20,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:20,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016289942] [2024-11-13 15:45:20,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016289942] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:20,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668075165] [2024-11-13 15:45:20,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,502 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:20,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:20,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1708302078, now seen corresponding path program 1 times [2024-11-13 15:45:20,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:20,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29978654] [2024-11-13 15:45:20,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:20,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:20,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29978654] [2024-11-13 15:45:20,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29978654] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:20,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195361733] [2024-11-13 15:45:20,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,569 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:20,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:20,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:20,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:20,569 INFO L87 Difference]: Start difference. First operand 1183 states and 1751 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:20,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:20,691 INFO L93 Difference]: Finished difference Result 2142 states and 3143 transitions. [2024-11-13 15:45:20,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2142 states and 3143 transitions. [2024-11-13 15:45:20,734 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2034 [2024-11-13 15:45:20,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2142 states to 2142 states and 3143 transitions. [2024-11-13 15:45:20,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2142 [2024-11-13 15:45:20,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2142 [2024-11-13 15:45:20,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2142 states and 3143 transitions. [2024-11-13 15:45:20,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:20,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2142 states and 3143 transitions. [2024-11-13 15:45:20,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2142 states and 3143 transitions. [2024-11-13 15:45:20,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2142 to 2138. [2024-11-13 15:45:20,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2138 states, 2138 states have (on average 1.4681945743685687) internal successors, (3139), 2137 states have internal predecessors, (3139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:20,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2138 states to 2138 states and 3139 transitions. [2024-11-13 15:45:20,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2024-11-13 15:45:20,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:20,809 INFO L424 stractBuchiCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2024-11-13 15:45:20,809 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 15:45:20,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2138 states and 3139 transitions. [2024-11-13 15:45:20,820 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2030 [2024-11-13 15:45:20,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:20,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:20,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:20,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:20,822 INFO L745 eck$LassoCheckResult]: Stem: 13938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14082#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14083#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13713#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 13714#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14078#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14079#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13770#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13771#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13691#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13692#L684 assume !(0 == ~M_E~0); 14205#L684-2 assume !(0 == ~T1_E~0); 14035#L689-1 assume !(0 == ~T2_E~0); 14036#L694-1 assume !(0 == ~T3_E~0); 14033#L699-1 assume !(0 == ~T4_E~0); 14034#L704-1 assume !(0 == ~T5_E~0); 13980#L709-1 assume !(0 == ~T6_E~0); 13914#L714-1 assume !(0 == ~E_M~0); 13915#L719-1 assume !(0 == ~E_1~0); 14167#L724-1 assume !(0 == ~E_2~0); 13663#L729-1 assume !(0 == ~E_3~0); 13664#L734-1 assume !(0 == ~E_4~0); 14244#L739-1 assume !(0 == ~E_5~0); 13872#L744-1 assume !(0 == ~E_6~0); 13873#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13618#L334 assume !(1 == ~m_pc~0); 13619#L334-2 is_master_triggered_~__retres1~0#1 := 0; 13972#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13877#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13842#L849 assume !(0 != activate_threads_~tmp~1#1); 13843#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13768#L353 assume !(1 == ~t1_pc~0); 13769#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14086#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13634#L857 assume !(0 != activate_threads_~tmp___0~0#1); 13717#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13718#L372 assume !(1 == ~t2_pc~0); 13828#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13827#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13967#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14087#L865 assume !(0 != activate_threads_~tmp___1~0#1); 13607#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13608#L391 assume 1 == ~t3_pc~0; 14221#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13531#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13557#L873 assume !(0 != activate_threads_~tmp___2~0#1); 13849#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13850#L410 assume 1 == ~t4_pc~0; 14230#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14101#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13733#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13734#L881 assume !(0 != activate_threads_~tmp___3~0#1); 13858#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13859#L429 assume !(1 == ~t5_pc~0); 13669#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13670#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13888#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13889#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14105#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13839#L448 assume 1 == ~t6_pc~0; 13704#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13705#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14070#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14071#L897 assume !(0 != activate_threads_~tmp___5~0#1); 14272#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14328#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 13895#L762-2 assume !(1 == ~T1_E~0); 13896#L767-1 assume !(1 == ~T2_E~0); 14278#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14134#L777-1 assume !(1 == ~T4_E~0); 14016#L782-1 assume !(1 == ~T5_E~0); 13695#L787-1 assume !(1 == ~T6_E~0); 13693#L792-1 assume !(1 == ~E_M~0); 13694#L797-1 assume !(1 == ~E_1~0); 13739#L802-1 assume !(1 == ~E_2~0); 13976#L807-1 assume !(1 == ~E_3~0); 13977#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14238#L817-1 assume !(1 == ~E_5~0); 14039#L822-1 assume !(1 == ~E_6~0); 14040#L827-1 assume { :end_inline_reset_delta_events } true; 14249#L1053-2 [2024-11-13 15:45:20,822 INFO L747 eck$LassoCheckResult]: Loop: 14249#L1053-2 assume !false; 14231#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13818#L659-1 assume !false; 13804#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13805#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13807#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14108#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14109#L570 assume !(0 != eval_~tmp~0#1); 14811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14806#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14805#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14804#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14803#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14802#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14801#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14800#L709-3 assume !(0 == ~T6_E~0); 14799#L714-3 assume !(0 == ~E_M~0); 14798#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14797#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14796#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14795#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14794#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14793#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14791#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14792#L334-24 assume 1 == ~m_pc~0; 14785#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14786#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14781#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14782#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14321#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14117#L353-24 assume !(1 == ~t1_pc~0); 14118#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15370#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15368#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15365#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15363#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15361#L372-24 assume 1 == ~t2_pc~0; 15358#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15356#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15354#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15351#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 15349#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15347#L391-24 assume 1 == ~t3_pc~0; 15344#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15343#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15342#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15329#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15327#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15326#L410-24 assume !(1 == ~t4_pc~0); 15324#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 15323#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15321#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15320#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15319#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15318#L429-24 assume 1 == ~t5_pc~0; 14021#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14022#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13987#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13742#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13743#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13684#L448-24 assume !(1 == ~t6_pc~0); 13685#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13678#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13679#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13866#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14026#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14027#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13984#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13985#L767-3 assume !(1 == ~T2_E~0); 14770#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14769#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14768#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14767#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14766#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13916#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13917#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14207#L807-3 assume !(1 == ~E_3~0); 14068#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14069#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14161#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14144#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14145#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14640#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14319#L1072 assume !(0 == start_simulation_~tmp~3#1); 14320#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14700#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14699#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14698#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 14697#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14696#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14695#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14694#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 14249#L1053-2 [2024-11-13 15:45:20,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:20,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2024-11-13 15:45:20,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:20,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058975215] [2024-11-13 15:45:20,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:20,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:20,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058975215] [2024-11-13 15:45:20,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058975215] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:20,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140462261] [2024-11-13 15:45:20,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,896 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:20,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:20,898 INFO L85 PathProgramCache]: Analyzing trace with hash 594557054, now seen corresponding path program 1 times [2024-11-13 15:45:20,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:20,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140649000] [2024-11-13 15:45:20,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:20,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:20,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:20,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:20,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140649000] [2024-11-13 15:45:20,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140649000] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:20,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:20,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:20,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685024346] [2024-11-13 15:45:20,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:20,952 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:20,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:20,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:20,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:20,952 INFO L87 Difference]: Start difference. First operand 2138 states and 3139 transitions. cyclomatic complexity: 1005 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:21,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:21,091 INFO L93 Difference]: Finished difference Result 3935 states and 5736 transitions. [2024-11-13 15:45:21,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3935 states and 5736 transitions. [2024-11-13 15:45:21,120 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3820 [2024-11-13 15:45:21,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3935 states to 3935 states and 5736 transitions. [2024-11-13 15:45:21,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3935 [2024-11-13 15:45:21,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3935 [2024-11-13 15:45:21,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3935 states and 5736 transitions. [2024-11-13 15:45:21,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:21,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3935 states and 5736 transitions. [2024-11-13 15:45:21,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3935 states and 5736 transitions. [2024-11-13 15:45:21,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3935 to 3927. [2024-11-13 15:45:21,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3927 states, 3927 states have (on average 1.458619811560988) internal successors, (5728), 3926 states have internal predecessors, (5728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:21,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3927 states to 3927 states and 5728 transitions. [2024-11-13 15:45:21,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2024-11-13 15:45:21,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:21,257 INFO L424 stractBuchiCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2024-11-13 15:45:21,257 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 15:45:21,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3927 states and 5728 transitions. [2024-11-13 15:45:21,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3812 [2024-11-13 15:45:21,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:21,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:21,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:21,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:21,274 INFO L745 eck$LassoCheckResult]: Stem: 20016#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20150#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19796#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 19797#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20146#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20147#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20069#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19850#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19851#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19771#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19772#L684 assume !(0 == ~M_E~0); 20270#L684-2 assume !(0 == ~T1_E~0); 20104#L689-1 assume !(0 == ~T2_E~0); 20105#L694-1 assume !(0 == ~T3_E~0); 20102#L699-1 assume !(0 == ~T4_E~0); 20103#L704-1 assume !(0 == ~T5_E~0); 20057#L709-1 assume !(0 == ~T6_E~0); 19993#L714-1 assume !(0 == ~E_M~0); 19994#L719-1 assume !(0 == ~E_1~0); 20235#L724-1 assume !(0 == ~E_2~0); 19743#L729-1 assume !(0 == ~E_3~0); 19744#L734-1 assume !(0 == ~E_4~0); 20307#L739-1 assume !(0 == ~E_5~0); 19946#L744-1 assume !(0 == ~E_6~0); 19947#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19698#L334 assume !(1 == ~m_pc~0); 19699#L334-2 is_master_triggered_~__retres1~0#1 := 0; 20046#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19951#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19915#L849 assume !(0 != activate_threads_~tmp~1#1); 19916#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19846#L353 assume !(1 == ~t1_pc~0); 19847#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20153#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19714#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19715#L857 assume !(0 != activate_threads_~tmp___0~0#1); 19798#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19799#L372 assume !(1 == ~t2_pc~0); 19902#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19901#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20041#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20154#L865 assume !(0 != activate_threads_~tmp___1~0#1); 19687#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19688#L391 assume !(1 == ~t3_pc~0); 19610#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19611#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19637#L873 assume !(0 != activate_threads_~tmp___2~0#1); 19922#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19923#L410 assume 1 == ~t4_pc~0; 20294#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20170#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19812#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19813#L881 assume !(0 != activate_threads_~tmp___3~0#1); 19933#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19934#L429 assume !(1 == ~t5_pc~0); 19749#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19750#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19962#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19963#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20173#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19914#L448 assume 1 == ~t6_pc~0; 19786#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19787#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20139#L897 assume !(0 != activate_threads_~tmp___5~0#1); 20333#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20386#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 20387#L762-2 assume !(1 == ~T1_E~0); 20362#L767-1 assume !(1 == ~T2_E~0); 20363#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20202#L777-1 assume !(1 == ~T4_E~0); 20203#L782-1 assume !(1 == ~T5_E~0); 19776#L787-1 assume !(1 == ~T6_E~0); 19777#L792-1 assume !(1 == ~E_M~0); 19774#L797-1 assume !(1 == ~E_1~0); 19818#L802-1 assume !(1 == ~E_2~0); 20050#L807-1 assume !(1 == ~E_3~0); 20051#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20378#L817-1 assume !(1 == ~E_5~0); 20379#L822-1 assume !(1 == ~E_6~0); 20312#L827-1 assume { :end_inline_reset_delta_events } true; 19917#L1053-2 [2024-11-13 15:45:21,274 INFO L747 eck$LassoCheckResult]: Loop: 19917#L1053-2 assume !false; 19918#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19892#L659-1 assume !false; 20204#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22060#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20399#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20175#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20176#L570 assume !(0 != eval_~tmp~0#1); 20228#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22517#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22516#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22515#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22514#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22513#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22512#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22511#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22509#L709-3 assume !(0 == ~T6_E~0); 22507#L714-3 assume !(0 == ~E_M~0); 22505#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22503#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22501#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22498#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22496#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22494#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22492#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22490#L334-24 assume 1 == ~m_pc~0; 22487#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22485#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22483#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22481#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22479#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22477#L353-24 assume !(1 == ~t1_pc~0); 22475#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22472#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22470#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22468#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22466#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22464#L372-24 assume 1 == ~t2_pc~0; 22461#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22458#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22456#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22359#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 22358#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22357#L391-24 assume !(1 == ~t3_pc~0); 22356#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22353#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22351#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22349#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22347#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22345#L410-24 assume !(1 == ~t4_pc~0); 22343#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 22342#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22341#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21343#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21344#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21325#L429-24 assume 1 == ~t5_pc~0; 21321#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21318#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21315#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21312#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21306#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21305#L448-24 assume 1 == ~t6_pc~0; 21296#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20993#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20982#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20935#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20934#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20933#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20932#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20931#L767-3 assume !(1 == ~T2_E~0); 20930#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20929#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20928#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20920#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20918#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20916#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20914#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20912#L807-3 assume !(1 == ~E_3~0); 20909#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20910#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22304#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20902#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20903#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20793#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20792#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 20778#L1072 assume !(0 == start_simulation_~tmp~3#1); 19895#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19896#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19760#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 19713#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22170#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20317#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20233#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 19917#L1053-2 [2024-11-13 15:45:21,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:21,274 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2024-11-13 15:45:21,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:21,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308292955] [2024-11-13 15:45:21,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:21,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:21,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:21,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:21,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:21,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308292955] [2024-11-13 15:45:21,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308292955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:21,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:21,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:21,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454357676] [2024-11-13 15:45:21,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:21,350 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:21,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:21,351 INFO L85 PathProgramCache]: Analyzing trace with hash 70273598, now seen corresponding path program 1 times [2024-11-13 15:45:21,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:21,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185636079] [2024-11-13 15:45:21,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:21,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:21,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:21,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:21,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:21,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185636079] [2024-11-13 15:45:21,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185636079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:21,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:21,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:21,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939345352] [2024-11-13 15:45:21,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:21,406 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:21,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:21,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:21,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:21,407 INFO L87 Difference]: Start difference. First operand 3927 states and 5728 transitions. cyclomatic complexity: 1809 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:21,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:21,550 INFO L93 Difference]: Finished difference Result 7294 states and 10581 transitions. [2024-11-13 15:45:21,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7294 states and 10581 transitions. [2024-11-13 15:45:21,595 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7152 [2024-11-13 15:45:21,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7294 states to 7294 states and 10581 transitions. [2024-11-13 15:45:21,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7294 [2024-11-13 15:45:21,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7294 [2024-11-13 15:45:21,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7294 states and 10581 transitions. [2024-11-13 15:45:21,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:21,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7294 states and 10581 transitions. [2024-11-13 15:45:21,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7294 states and 10581 transitions. [2024-11-13 15:45:21,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7294 to 7278. [2024-11-13 15:45:21,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7278 states, 7278 states have (on average 1.4516350645781808) internal successors, (10565), 7277 states have internal predecessors, (10565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:21,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7278 states to 7278 states and 10565 transitions. [2024-11-13 15:45:21,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2024-11-13 15:45:21,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:21,827 INFO L424 stractBuchiCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2024-11-13 15:45:21,827 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 15:45:21,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7278 states and 10565 transitions. [2024-11-13 15:45:21,854 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7136 [2024-11-13 15:45:21,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:21,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:21,855 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:21,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:21,856 INFO L745 eck$LassoCheckResult]: Stem: 31235#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31019#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 31020#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31367#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31368#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31297#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31076#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31077#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30996#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30997#L684 assume !(0 == ~M_E~0); 31479#L684-2 assume !(0 == ~T1_E~0); 31326#L689-1 assume !(0 == ~T2_E~0); 31327#L694-1 assume !(0 == ~T3_E~0); 31324#L699-1 assume !(0 == ~T4_E~0); 31325#L704-1 assume !(0 == ~T5_E~0); 31281#L709-1 assume !(0 == ~T6_E~0); 31214#L714-1 assume !(0 == ~E_M~0); 31215#L719-1 assume !(0 == ~E_1~0); 31450#L724-1 assume !(0 == ~E_2~0); 30970#L729-1 assume !(0 == ~E_3~0); 30971#L734-1 assume !(0 == ~E_4~0); 31513#L739-1 assume !(0 == ~E_5~0); 31175#L744-1 assume !(0 == ~E_6~0); 31176#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30926#L334 assume !(1 == ~m_pc~0); 30927#L334-2 is_master_triggered_~__retres1~0#1 := 0; 31273#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31177#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31146#L849 assume !(0 != activate_threads_~tmp~1#1); 31147#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31074#L353 assume !(1 == ~t1_pc~0); 31075#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31373#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30941#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30942#L857 assume !(0 != activate_threads_~tmp___0~0#1); 31024#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31025#L372 assume !(1 == ~t2_pc~0); 31133#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31132#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31268#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31374#L865 assume !(0 != activate_threads_~tmp___1~0#1); 30915#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30916#L391 assume !(1 == ~t3_pc~0); 30838#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30839#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30865#L873 assume !(0 != activate_threads_~tmp___2~0#1); 31153#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31154#L410 assume !(1 == ~t4_pc~0); 31387#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31388#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31039#L881 assume !(0 != activate_threads_~tmp___3~0#1); 31159#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31160#L429 assume !(1 == ~t5_pc~0); 30976#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30977#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31189#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31190#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31393#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31143#L448 assume 1 == ~t6_pc~0; 31012#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31013#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31357#L897 assume !(0 != activate_threads_~tmp___5~0#1); 31543#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31581#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 31582#L762-2 assume !(1 == ~T1_E~0); 35123#L767-1 assume !(1 == ~T2_E~0); 35122#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35121#L777-1 assume !(1 == ~T4_E~0); 35120#L782-1 assume !(1 == ~T5_E~0); 35119#L787-1 assume !(1 == ~T6_E~0); 35118#L792-1 assume !(1 == ~E_M~0); 31001#L797-1 assume !(1 == ~E_1~0); 35117#L802-1 assume !(1 == ~E_2~0); 35116#L807-1 assume !(1 == ~E_3~0); 35115#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35114#L817-1 assume !(1 == ~E_5~0); 35113#L822-1 assume !(1 == ~E_6~0); 31520#L827-1 assume { :end_inline_reset_delta_events } true; 31521#L1053-2 [2024-11-13 15:45:21,856 INFO L747 eck$LassoCheckResult]: Loop: 31521#L1053-2 assume !false; 36053#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36050#L659-1 assume !false; 36048#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 35978#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 35971#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 35969#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 35966#L570 assume !(0 != eval_~tmp~0#1); 35967#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36376#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36374#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36372#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36370#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36368#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36365#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36363#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36361#L709-3 assume !(0 == ~T6_E~0); 36359#L714-3 assume !(0 == ~E_M~0); 36357#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36355#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36352#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36350#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36348#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36346#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36344#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36342#L334-24 assume 1 == ~m_pc~0; 36339#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36337#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36335#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36333#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36331#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36329#L353-24 assume !(1 == ~t1_pc~0); 36327#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 36325#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36323#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36321#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36319#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36317#L372-24 assume 1 == ~t2_pc~0; 36314#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36313#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36312#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36311#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 36310#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36309#L391-24 assume !(1 == ~t3_pc~0); 36308#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 36307#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36306#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36305#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36304#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36303#L410-24 assume !(1 == ~t4_pc~0); 36302#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 36299#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36297#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36295#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36293#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36290#L429-24 assume !(1 == ~t5_pc~0); 36288#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 36285#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36283#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36281#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36279#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36277#L448-24 assume !(1 == ~t6_pc~0); 36274#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 36272#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36270#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36268#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36266#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36263#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35259#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36260#L767-3 assume !(1 == ~T2_E~0); 36258#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36256#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36254#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36252#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36250#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35243#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36247#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36245#L807-3 assume !(1 == ~E_3~0); 36243#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36241#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36239#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36237#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 36232#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 36224#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 36222#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 36220#L1072 assume !(0 == start_simulation_~tmp~3#1); 36217#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 36201#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 36200#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 36197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 36196#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36195#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36194#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 36193#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 31521#L1053-2 [2024-11-13 15:45:21,856 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:21,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2024-11-13 15:45:21,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:21,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691368728] [2024-11-13 15:45:21,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:21,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:21,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:21,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:21,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:21,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691368728] [2024-11-13 15:45:21,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [691368728] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:21,930 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:21,930 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:21,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482693691] [2024-11-13 15:45:21,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:21,930 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:21,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:21,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1831754752, now seen corresponding path program 1 times [2024-11-13 15:45:21,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:21,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658992656] [2024-11-13 15:45:21,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:21,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:21,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:22,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:22,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:22,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658992656] [2024-11-13 15:45:22,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658992656] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:22,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:22,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:22,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342530199] [2024-11-13 15:45:22,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:22,017 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:22,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:22,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:22,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:22,017 INFO L87 Difference]: Start difference. First operand 7278 states and 10565 transitions. cyclomatic complexity: 3303 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:22,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:22,293 INFO L93 Difference]: Finished difference Result 7593 states and 10880 transitions. [2024-11-13 15:45:22,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7593 states and 10880 transitions. [2024-11-13 15:45:22,327 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7448 [2024-11-13 15:45:22,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7593 states to 7593 states and 10880 transitions. [2024-11-13 15:45:22,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7593 [2024-11-13 15:45:22,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7593 [2024-11-13 15:45:22,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7593 states and 10880 transitions. [2024-11-13 15:45:22,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:22,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-13 15:45:22,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7593 states and 10880 transitions. [2024-11-13 15:45:22,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7593 to 7593. [2024-11-13 15:45:22,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7593 states, 7593 states have (on average 1.4328987225075727) internal successors, (10880), 7592 states have internal predecessors, (10880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:22,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7593 states to 7593 states and 10880 transitions. [2024-11-13 15:45:22,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-13 15:45:22,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:22,524 INFO L424 stractBuchiCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-13 15:45:22,524 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 15:45:22,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7593 states and 10880 transitions. [2024-11-13 15:45:22,551 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7448 [2024-11-13 15:45:22,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:22,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:22,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:22,553 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:22,553 INFO L745 eck$LassoCheckResult]: Stem: 46109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 46110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 46249#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46250#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45900#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 45901#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46247#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46248#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46174#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45955#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45956#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45877#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45878#L684 assume !(0 == ~M_E~0); 46371#L684-2 assume !(0 == ~T1_E~0); 46204#L689-1 assume !(0 == ~T2_E~0); 46205#L694-1 assume !(0 == ~T3_E~0); 46202#L699-1 assume !(0 == ~T4_E~0); 46203#L704-1 assume !(0 == ~T5_E~0); 46157#L709-1 assume !(0 == ~T6_E~0); 46089#L714-1 assume !(0 == ~E_M~0); 46090#L719-1 assume !(0 == ~E_1~0); 46339#L724-1 assume !(0 == ~E_2~0); 45851#L729-1 assume !(0 == ~E_3~0); 45852#L734-1 assume !(0 == ~E_4~0); 46408#L739-1 assume !(0 == ~E_5~0); 46049#L744-1 assume !(0 == ~E_6~0); 46050#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45807#L334 assume !(1 == ~m_pc~0); 45808#L334-2 is_master_triggered_~__retres1~0#1 := 0; 46149#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46051#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46019#L849 assume !(0 != activate_threads_~tmp~1#1); 46020#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45953#L353 assume !(1 == ~t1_pc~0); 45954#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46253#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45822#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45823#L857 assume !(0 != activate_threads_~tmp___0~0#1); 45905#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45906#L372 assume !(1 == ~t2_pc~0); 46007#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46006#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46142#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46254#L865 assume !(0 != activate_threads_~tmp___1~0#1); 45796#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45797#L391 assume !(1 == ~t3_pc~0); 45718#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45719#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45745#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45746#L873 assume !(0 != activate_threads_~tmp___2~0#1); 46026#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46027#L410 assume !(1 == ~t4_pc~0); 46268#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46269#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45919#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45920#L881 assume !(0 != activate_threads_~tmp___3~0#1); 46032#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46033#L429 assume !(1 == ~t5_pc~0); 45857#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45858#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46063#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46064#L889 assume !(0 != activate_threads_~tmp___4~0#1); 46274#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46018#L448 assume 1 == ~t6_pc~0; 45893#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45894#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46236#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46237#L897 assume !(0 != activate_threads_~tmp___5~0#1); 46438#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46484#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 46485#L762-2 assume !(1 == ~T1_E~0); 49606#L767-1 assume !(1 == ~T2_E~0); 49605#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49604#L777-1 assume !(1 == ~T4_E~0); 49603#L782-1 assume !(1 == ~T5_E~0); 49602#L787-1 assume !(1 == ~T6_E~0); 49601#L792-1 assume !(1 == ~E_M~0); 45882#L797-1 assume !(1 == ~E_1~0); 49600#L802-1 assume !(1 == ~E_2~0); 49599#L807-1 assume !(1 == ~E_3~0); 49598#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49596#L817-1 assume !(1 == ~E_5~0); 49594#L822-1 assume !(1 == ~E_6~0); 48816#L827-1 assume { :end_inline_reset_delta_events } true; 48814#L1053-2 [2024-11-13 15:45:22,553 INFO L747 eck$LassoCheckResult]: Loop: 48814#L1053-2 assume !false; 48692#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48690#L659-1 assume !false; 48688#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48683#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48676#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48673#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48670#L570 assume !(0 != eval_~tmp~0#1); 48671#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49577#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49575#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49573#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49571#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49569#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49567#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49565#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49561#L709-3 assume !(0 == ~T6_E~0); 49559#L714-3 assume !(0 == ~E_M~0); 49557#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49555#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49552#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49550#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49548#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49545#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49543#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49541#L334-24 assume 1 == ~m_pc~0; 49538#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49536#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49534#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49532#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49530#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49528#L353-24 assume !(1 == ~t1_pc~0); 49526#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 49524#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49522#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49520#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49518#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49516#L372-24 assume 1 == ~t2_pc~0; 49513#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49511#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49509#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49507#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 49506#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49505#L391-24 assume !(1 == ~t3_pc~0); 49504#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 49503#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49502#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49501#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49500#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49499#L410-24 assume !(1 == ~t4_pc~0); 49497#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 49496#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49495#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49494#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49493#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49491#L429-24 assume 1 == ~t5_pc~0; 49489#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49490#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49498#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49479#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49477#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49475#L448-24 assume !(1 == ~t6_pc~0); 49472#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 49470#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49468#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49466#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49464#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49462#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49133#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49458#L767-3 assume !(1 == ~T2_E~0); 49456#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49454#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49452#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49450#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49448#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49125#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49445#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49443#L807-3 assume !(1 == ~E_3~0); 49441#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49439#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49437#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49435#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48870#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48863#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48861#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 48859#L1072 assume !(0 == start_simulation_~tmp~3#1); 48856#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48830#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48828#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48825#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 48823#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48821#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48819#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 48817#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 48814#L1053-2 [2024-11-13 15:45:22,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:22,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2024-11-13 15:45:22,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:22,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719736271] [2024-11-13 15:45:22,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:22,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:22,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:22,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:22,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:22,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719736271] [2024-11-13 15:45:22,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719736271] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:22,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:22,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:22,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342644090] [2024-11-13 15:45:22,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:22,606 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:22,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:22,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1506284161, now seen corresponding path program 1 times [2024-11-13 15:45:22,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:22,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246766046] [2024-11-13 15:45:22,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:22,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:22,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:22,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:22,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:22,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246766046] [2024-11-13 15:45:22,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246766046] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:22,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:22,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:22,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544437878] [2024-11-13 15:45:22,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:22,659 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:22,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:22,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:22,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:22,660 INFO L87 Difference]: Start difference. First operand 7593 states and 10880 transitions. cyclomatic complexity: 3303 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:22,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:22,825 INFO L93 Difference]: Finished difference Result 14548 states and 20713 transitions. [2024-11-13 15:45:22,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14548 states and 20713 transitions. [2024-11-13 15:45:22,898 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14332 [2024-11-13 15:45:22,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14548 states to 14548 states and 20713 transitions. [2024-11-13 15:45:22,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14548 [2024-11-13 15:45:22,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14548 [2024-11-13 15:45:22,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14548 states and 20713 transitions. [2024-11-13 15:45:23,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:23,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14548 states and 20713 transitions. [2024-11-13 15:45:23,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14548 states and 20713 transitions. [2024-11-13 15:45:23,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14548 to 14516. [2024-11-13 15:45:23,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14516 states, 14516 states have (on average 1.424703775144668) internal successors, (20681), 14515 states have internal predecessors, (20681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:23,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14516 states to 14516 states and 20681 transitions. [2024-11-13 15:45:23,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2024-11-13 15:45:23,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:23,393 INFO L424 stractBuchiCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2024-11-13 15:45:23,393 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 15:45:23,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14516 states and 20681 transitions. [2024-11-13 15:45:23,445 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14300 [2024-11-13 15:45:23,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:23,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:23,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:23,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:23,448 INFO L745 eck$LassoCheckResult]: Stem: 68260#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 68261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 68405#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68406#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68042#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 68043#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68403#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68404#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68326#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68105#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68106#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68023#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68024#L684 assume !(0 == ~M_E~0); 68532#L684-2 assume !(0 == ~T1_E~0); 68360#L689-1 assume !(0 == ~T2_E~0); 68361#L694-1 assume !(0 == ~T3_E~0); 68358#L699-1 assume !(0 == ~T4_E~0); 68359#L704-1 assume !(0 == ~T5_E~0); 68310#L709-1 assume !(0 == ~T6_E~0); 68239#L714-1 assume !(0 == ~E_M~0); 68240#L719-1 assume !(0 == ~E_1~0); 68500#L724-1 assume !(0 == ~E_2~0); 67996#L729-1 assume !(0 == ~E_3~0); 67997#L734-1 assume !(0 == ~E_4~0); 68565#L739-1 assume !(0 == ~E_5~0); 68199#L744-1 assume !(0 == ~E_6~0); 68200#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67952#L334 assume !(1 == ~m_pc~0); 67953#L334-2 is_master_triggered_~__retres1~0#1 := 0; 68302#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68201#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68170#L849 assume !(0 != activate_threads_~tmp~1#1); 68171#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68103#L353 assume !(1 == ~t1_pc~0); 68104#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68409#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67968#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67969#L857 assume !(0 != activate_threads_~tmp___0~0#1); 68047#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68048#L372 assume !(1 == ~t2_pc~0); 68159#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68158#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68294#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68410#L865 assume !(0 != activate_threads_~tmp___1~0#1); 67941#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67942#L391 assume !(1 == ~t3_pc~0); 67866#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67867#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67891#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67892#L873 assume !(0 != activate_threads_~tmp___2~0#1); 68177#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68178#L410 assume !(1 == ~t4_pc~0); 68423#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68424#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68061#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68062#L881 assume !(0 != activate_threads_~tmp___3~0#1); 68183#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68184#L429 assume !(1 == ~t5_pc~0); 68002#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68003#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68212#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68213#L889 assume !(0 != activate_threads_~tmp___4~0#1); 68429#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68169#L448 assume !(1 == ~t6_pc~0); 68086#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68087#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68394#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68395#L897 assume !(0 != activate_threads_~tmp___5~0#1); 68592#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68642#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 68643#L762-2 assume !(1 == ~T1_E~0); 70578#L767-1 assume !(1 == ~T2_E~0); 70577#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68461#L777-1 assume !(1 == ~T4_E~0); 68345#L782-1 assume !(1 == ~T5_E~0); 68029#L787-1 assume !(1 == ~T6_E~0); 68027#L792-1 assume !(1 == ~E_M~0); 68028#L797-1 assume !(1 == ~E_1~0); 68514#L802-1 assume !(1 == ~E_2~0); 68515#L807-1 assume !(1 == ~E_3~0); 68559#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 68560#L817-1 assume !(1 == ~E_5~0); 68364#L822-1 assume !(1 == ~E_6~0); 68365#L827-1 assume { :end_inline_reset_delta_events } true; 70529#L1053-2 [2024-11-13 15:45:23,448 INFO L747 eck$LassoCheckResult]: Loop: 70529#L1053-2 assume !false; 70525#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70359#L659-1 assume !false; 70512#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 70431#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 70421#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 70415#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70406#L570 assume !(0 != eval_~tmp~0#1); 70407#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70857#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70855#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70852#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70850#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70848#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70846#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70844#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70842#L709-3 assume !(0 == ~T6_E~0); 70840#L714-3 assume !(0 == ~E_M~0); 70838#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70836#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70834#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70832#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70830#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70828#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70826#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70824#L334-24 assume 1 == ~m_pc~0; 70821#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 70819#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70817#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70815#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70812#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70810#L353-24 assume !(1 == ~t1_pc~0); 70808#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 70806#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70804#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70802#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70800#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70798#L372-24 assume 1 == ~t2_pc~0; 70795#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70793#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70791#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70789#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 70786#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70784#L391-24 assume !(1 == ~t3_pc~0); 70782#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 70780#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70778#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70776#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70774#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70772#L410-24 assume !(1 == ~t4_pc~0); 70770#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 70767#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70764#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70761#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70758#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70755#L429-24 assume !(1 == ~t5_pc~0); 70752#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 70738#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70733#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70728#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 70722#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70720#L448-24 assume !(1 == ~t6_pc~0); 70717#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 70713#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70710#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70707#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70704#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70701#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70697#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70694#L767-3 assume !(1 == ~T2_E~0); 70691#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70688#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70685#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70682#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70680#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70675#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70673#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70671#L807-3 assume !(1 == ~E_3~0); 70669#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70667#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70665#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70663#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 70660#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 70653#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 70649#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 70583#L1072 assume !(0 == start_simulation_~tmp~3#1); 70580#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 70570#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 70553#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 70549#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 70545#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70541#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70537#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 70533#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 70529#L1053-2 [2024-11-13 15:45:23,449 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:23,449 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2024-11-13 15:45:23,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:23,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528376911] [2024-11-13 15:45:23,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:23,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:23,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:23,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:23,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:23,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528376911] [2024-11-13 15:45:23,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528376911] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:23,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:23,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 15:45:23,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955351098] [2024-11-13 15:45:23,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:23,513 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:23,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:23,513 INFO L85 PathProgramCache]: Analyzing trace with hash 987749250, now seen corresponding path program 1 times [2024-11-13 15:45:23,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:23,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863586787] [2024-11-13 15:45:23,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:23,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:23,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:23,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:23,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:23,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863586787] [2024-11-13 15:45:23,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863586787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:23,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:23,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:23,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378891165] [2024-11-13 15:45:23,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:23,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:23,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:23,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:23,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:23,564 INFO L87 Difference]: Start difference. First operand 14516 states and 20681 transitions. cyclomatic complexity: 6197 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:23,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:23,712 INFO L93 Difference]: Finished difference Result 21621 states and 30826 transitions. [2024-11-13 15:45:23,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21621 states and 30826 transitions. [2024-11-13 15:45:23,820 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2024-11-13 15:45:23,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21621 states to 21621 states and 30826 transitions. [2024-11-13 15:45:23,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21621 [2024-11-13 15:45:23,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21621 [2024-11-13 15:45:23,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21621 states and 30826 transitions. [2024-11-13 15:45:23,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:23,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21621 states and 30826 transitions. [2024-11-13 15:45:23,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21621 states and 30826 transitions. [2024-11-13 15:45:24,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21621 to 15146. [2024-11-13 15:45:24,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4282979004357585) internal successors, (21633), 15145 states have internal predecessors, (21633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:24,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21633 transitions. [2024-11-13 15:45:24,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2024-11-13 15:45:24,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:24,635 INFO L424 stractBuchiCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2024-11-13 15:45:24,635 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 15:45:24,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21633 transitions. [2024-11-13 15:45:24,679 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-13 15:45:24,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:24,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:24,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:24,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:24,682 INFO L745 eck$LassoCheckResult]: Stem: 104416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 104417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 104553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104190#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 104191#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104549#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104550#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104474#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104249#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 104250#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104169#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104170#L684 assume !(0 == ~M_E~0); 104685#L684-2 assume !(0 == ~T1_E~0); 104503#L689-1 assume !(0 == ~T2_E~0); 104504#L694-1 assume !(0 == ~T3_E~0); 104501#L699-1 assume !(0 == ~T4_E~0); 104502#L704-1 assume !(0 == ~T5_E~0); 104459#L709-1 assume !(0 == ~T6_E~0); 104393#L714-1 assume !(0 == ~E_M~0); 104394#L719-1 assume !(0 == ~E_1~0); 104645#L724-1 assume !(0 == ~E_2~0); 104141#L729-1 assume !(0 == ~E_3~0); 104142#L734-1 assume !(0 == ~E_4~0); 104722#L739-1 assume !(0 == ~E_5~0); 104345#L744-1 assume !(0 == ~E_6~0); 104346#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104097#L334 assume !(1 == ~m_pc~0); 104098#L334-2 is_master_triggered_~__retres1~0#1 := 0; 104448#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104351#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104315#L849 assume !(0 != activate_threads_~tmp~1#1); 104316#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104245#L353 assume !(1 == ~t1_pc~0); 104246#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104555#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104112#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104113#L857 assume !(0 != activate_threads_~tmp___0~0#1); 104192#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104193#L372 assume !(1 == ~t2_pc~0); 104302#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104301#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104442#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104556#L865 assume !(0 != activate_threads_~tmp___1~0#1); 104086#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104087#L391 assume !(1 == ~t3_pc~0); 104010#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 104011#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104036#L873 assume !(0 != activate_threads_~tmp___2~0#1); 104322#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104323#L410 assume !(1 == ~t4_pc~0); 104570#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104571#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104207#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104208#L881 assume !(0 != activate_threads_~tmp___3~0#1); 104332#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104333#L429 assume !(1 == ~t5_pc~0); 104147#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104148#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104363#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104364#L889 assume !(0 != activate_threads_~tmp___4~0#1); 104576#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104314#L448 assume !(1 == ~t6_pc~0); 104228#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 104229#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104539#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 104540#L897 assume !(0 != activate_threads_~tmp___5~0#1); 104757#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104813#L762 assume !(1 == ~M_E~0); 104372#L762-2 assume !(1 == ~T1_E~0); 104373#L767-1 assume !(1 == ~T2_E~0); 104763#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104608#L777-1 assume !(1 == ~T4_E~0); 104489#L782-1 assume !(1 == ~T5_E~0); 104173#L787-1 assume !(1 == ~T6_E~0); 104171#L792-1 assume !(1 == ~E_M~0); 104172#L797-1 assume !(1 == ~E_1~0); 104213#L802-1 assume !(1 == ~E_2~0); 104452#L807-1 assume !(1 == ~E_3~0); 104453#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 104718#L817-1 assume !(1 == ~E_5~0); 104505#L822-1 assume !(1 == ~E_6~0); 104506#L827-1 assume { :end_inline_reset_delta_events } true; 104733#L1053-2 [2024-11-13 15:45:24,682 INFO L747 eck$LassoCheckResult]: Loop: 104733#L1053-2 assume !false; 107877#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107872#L659-1 assume !false; 107870#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107860#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107853#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 107851#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 107847#L570 assume !(0 != eval_~tmp~0#1); 107845#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107841#L684-3 assume !(0 == ~M_E~0); 107839#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107837#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107835#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107833#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107831#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107829#L709-3 assume !(0 == ~T6_E~0); 107827#L714-3 assume !(0 == ~E_M~0); 107825#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107823#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107821#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107819#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 107817#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107815#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 107813#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107811#L334-24 assume !(1 == ~m_pc~0); 107808#L334-26 is_master_triggered_~__retres1~0#1 := 0; 107805#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107803#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107801#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 107799#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107797#L353-24 assume !(1 == ~t1_pc~0); 107795#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 107793#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107791#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107789#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107787#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107785#L372-24 assume 1 == ~t2_pc~0; 107781#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 107779#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107777#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107775#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 107773#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107771#L391-24 assume !(1 == ~t3_pc~0); 107769#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 107767#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107765#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107763#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107761#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107759#L410-24 assume !(1 == ~t4_pc~0); 107757#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 107755#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107753#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 107751#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 107749#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107747#L429-24 assume !(1 == ~t5_pc~0); 107744#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 107740#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107736#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107732#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 107729#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107727#L448-24 assume !(1 == ~t6_pc~0); 107724#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 107722#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107720#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 107718#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107716#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107714#L762-3 assume !(1 == ~M_E~0); 107548#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107712#L767-3 assume !(1 == ~T2_E~0); 107710#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107708#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107706#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107704#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107702#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107700#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107698#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107696#L807-3 assume !(1 == ~E_3~0); 107694#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107692#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107690#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107688#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107686#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107673#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 107671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 107651#L1072 assume !(0 == start_simulation_~tmp~3#1); 107652#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107972#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107953#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 107943#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 107923#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107903#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107902#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 107898#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 104733#L1053-2 [2024-11-13 15:45:24,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:24,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2024-11-13 15:45:24,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:24,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637560558] [2024-11-13 15:45:24,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:24,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:24,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:24,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:24,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:24,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637560558] [2024-11-13 15:45:24,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637560558] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:24,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:24,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:24,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572136335] [2024-11-13 15:45:24,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:24,779 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:24,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:24,780 INFO L85 PathProgramCache]: Analyzing trace with hash -2125492093, now seen corresponding path program 1 times [2024-11-13 15:45:24,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:24,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919076024] [2024-11-13 15:45:24,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:24,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:24,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:24,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:24,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:24,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919076024] [2024-11-13 15:45:24,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919076024] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:24,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:24,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:24,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593038379] [2024-11-13 15:45:24,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:24,863 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:24,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:24,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:24,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:24,865 INFO L87 Difference]: Start difference. First operand 15146 states and 21633 transitions. cyclomatic complexity: 6503 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:25,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:25,135 INFO L93 Difference]: Finished difference Result 24188 states and 34429 transitions. [2024-11-13 15:45:25,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34429 transitions. [2024-11-13 15:45:25,262 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2024-11-13 15:45:25,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34429 transitions. [2024-11-13 15:45:25,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2024-11-13 15:45:25,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2024-11-13 15:45:25,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34429 transitions. [2024-11-13 15:45:25,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:25,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34429 transitions. [2024-11-13 15:45:25,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34429 transitions. [2024-11-13 15:45:25,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17289. [2024-11-13 15:45:25,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.427497252588351) internal successors, (24680), 17288 states have internal predecessors, (24680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:25,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24680 transitions. [2024-11-13 15:45:25,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2024-11-13 15:45:25,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:25,756 INFO L424 stractBuchiCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2024-11-13 15:45:25,756 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 15:45:25,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24680 transitions. [2024-11-13 15:45:25,893 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-13 15:45:25,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:25,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:25,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:25,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:25,895 INFO L745 eck$LassoCheckResult]: Stem: 143752#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 143753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 143884#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143533#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 143534#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143880#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143881#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143809#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143592#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 143593#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 143513#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143514#L684 assume !(0 == ~M_E~0); 144005#L684-2 assume !(0 == ~T1_E~0); 143839#L689-1 assume !(0 == ~T2_E~0); 143840#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143837#L699-1 assume !(0 == ~T4_E~0); 143838#L704-1 assume !(0 == ~T5_E~0); 143796#L709-1 assume !(0 == ~T6_E~0); 143797#L714-1 assume !(0 == ~E_M~0); 144164#L719-1 assume !(0 == ~E_1~0); 144103#L724-1 assume !(0 == ~E_2~0); 144104#L729-1 assume !(0 == ~E_3~0); 144091#L734-1 assume !(0 == ~E_4~0); 144040#L739-1 assume !(0 == ~E_5~0); 144041#L744-1 assume !(0 == ~E_6~0); 144162#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143443#L334 assume !(1 == ~m_pc~0); 143444#L334-2 is_master_triggered_~__retres1~0#1 := 0; 143785#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144046#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143656#L849 assume !(0 != activate_threads_~tmp~1#1); 143657#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144158#L353 assume !(1 == ~t1_pc~0); 144157#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 143886#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143458#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 143459#L857 assume !(0 != activate_threads_~tmp___0~0#1); 143535#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143536#L372 assume !(1 == ~t2_pc~0); 143645#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143644#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143780#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144154#L865 assume !(0 != activate_threads_~tmp___1~0#1); 143432#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143433#L391 assume !(1 == ~t3_pc~0); 144017#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144152#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144151#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144150#L873 assume !(0 != activate_threads_~tmp___2~0#1); 143663#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143664#L410 assume !(1 == ~t4_pc~0); 144028#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 143945#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 143550#L881 assume !(0 != activate_threads_~tmp___3~0#1); 144032#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143831#L429 assume !(1 == ~t5_pc~0); 143492#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 143493#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143701#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 143702#L889 assume !(0 != activate_threads_~tmp___4~0#1); 143907#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143655#L448 assume !(1 == ~t6_pc~0); 143571#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 143572#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143872#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 143873#L897 assume !(0 != activate_threads_~tmp___5~0#1); 144126#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144127#L762 assume !(1 == ~M_E~0); 144138#L762-2 assume !(1 == ~T1_E~0); 144106#L767-1 assume !(1 == ~T2_E~0); 144107#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143939#L777-1 assume !(1 == ~T4_E~0); 143824#L782-1 assume !(1 == ~T5_E~0); 143517#L787-1 assume !(1 == ~T6_E~0); 143515#L792-1 assume !(1 == ~E_M~0); 143516#L797-1 assume !(1 == ~E_1~0); 143555#L802-1 assume !(1 == ~E_2~0); 143789#L807-1 assume !(1 == ~E_3~0); 143790#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 144037#L817-1 assume !(1 == ~E_5~0); 143843#L822-1 assume !(1 == ~E_6~0); 143844#L827-1 assume { :end_inline_reset_delta_events } true; 144045#L1053-2 [2024-11-13 15:45:25,896 INFO L747 eck$LassoCheckResult]: Loop: 144045#L1053-2 assume !false; 151614#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 150488#L659-1 assume !false; 151610#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 151539#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 151527#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 151521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 151515#L570 assume !(0 != eval_~tmp~0#1); 151516#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 152220#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151808#L684-3 assume !(0 == ~M_E~0); 151807#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 151802#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 148853#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148851#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148849#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 148846#L709-3 assume !(0 == ~T6_E~0); 148844#L714-3 assume !(0 == ~E_M~0); 148842#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 148840#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 148838#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 148836#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 148833#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 148831#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 148829#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148827#L334-24 assume 1 == ~m_pc~0; 148823#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 148814#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148810#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 148806#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148801#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148795#L353-24 assume !(1 == ~t1_pc~0); 148791#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 148784#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148778#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148773#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148768#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148762#L372-24 assume 1 == ~t2_pc~0; 148756#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 148751#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148746#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 148742#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 148738#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148734#L391-24 assume !(1 == ~t3_pc~0); 148723#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 148716#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148711#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 148706#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148700#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148696#L410-24 assume !(1 == ~t4_pc~0); 148690#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 148689#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148688#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 148684#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148682#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148680#L429-24 assume !(1 == ~t5_pc~0); 148678#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 148670#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148664#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 148659#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 148654#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 148650#L448-24 assume !(1 == ~t6_pc~0); 148646#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 148644#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 148641#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 148548#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 148547#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148546#L762-3 assume !(1 == ~M_E~0); 146390#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 148545#L767-3 assume !(1 == ~T2_E~0); 148543#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 148542#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 148540#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 148538#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 148536#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 148534#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 148532#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 148528#L807-3 assume !(1 == ~E_3~0); 148520#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148518#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148516#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 148515#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 148506#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 148499#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 148497#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 146798#L1072 assume !(0 == start_simulation_~tmp~3#1); 146799#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 151663#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 151656#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 151650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 151644#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151638#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151632#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 151626#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 144045#L1053-2 [2024-11-13 15:45:25,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:25,896 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2024-11-13 15:45:25,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:25,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425620865] [2024-11-13 15:45:25,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:25,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:25,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:25,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:25,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:25,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425620865] [2024-11-13 15:45:25,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425620865] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:25,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:25,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:25,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391009325] [2024-11-13 15:45:25,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:25,970 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:25,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:25,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1031846338, now seen corresponding path program 1 times [2024-11-13 15:45:25,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:25,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571130299] [2024-11-13 15:45:25,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:25,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:25,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:26,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:26,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:26,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571130299] [2024-11-13 15:45:26,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571130299] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:26,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:26,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:26,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259853980] [2024-11-13 15:45:26,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:26,020 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:26,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:26,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:26,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:26,021 INFO L87 Difference]: Start difference. First operand 17289 states and 24680 transitions. cyclomatic complexity: 7407 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:26,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:26,203 INFO L93 Difference]: Finished difference Result 22034 states and 31247 transitions. [2024-11-13 15:45:26,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22034 states and 31247 transitions. [2024-11-13 15:45:26,294 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2024-11-13 15:45:26,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22034 states to 22034 states and 31247 transitions. [2024-11-13 15:45:26,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22034 [2024-11-13 15:45:26,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22034 [2024-11-13 15:45:26,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22034 states and 31247 transitions. [2024-11-13 15:45:26,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:26,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22034 states and 31247 transitions. [2024-11-13 15:45:26,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22034 states and 31247 transitions. [2024-11-13 15:45:26,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22034 to 15146. [2024-11-13 15:45:26,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4218275452264624) internal successors, (21535), 15145 states have internal predecessors, (21535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:26,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21535 transitions. [2024-11-13 15:45:26,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2024-11-13 15:45:26,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:26,826 INFO L424 stractBuchiCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2024-11-13 15:45:26,826 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 15:45:26,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21535 transitions. [2024-11-13 15:45:26,873 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-13 15:45:26,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:26,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:26,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:26,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:26,877 INFO L745 eck$LassoCheckResult]: Stem: 183081#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 183082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 183211#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 183212#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182865#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 182866#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 183207#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 183208#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 183137#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 182925#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 182926#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 182845#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 182846#L684 assume !(0 == ~M_E~0); 183325#L684-2 assume !(0 == ~T1_E~0); 183166#L689-1 assume !(0 == ~T2_E~0); 183167#L694-1 assume !(0 == ~T3_E~0); 183164#L699-1 assume !(0 == ~T4_E~0); 183165#L704-1 assume !(0 == ~T5_E~0); 183124#L709-1 assume !(0 == ~T6_E~0); 183059#L714-1 assume !(0 == ~E_M~0); 183060#L719-1 assume !(0 == ~E_1~0); 183292#L724-1 assume !(0 == ~E_2~0); 182818#L729-1 assume !(0 == ~E_3~0); 182819#L734-1 assume !(0 == ~E_4~0); 183353#L739-1 assume !(0 == ~E_5~0); 183021#L744-1 assume !(0 == ~E_6~0); 183022#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 182775#L334 assume !(1 == ~m_pc~0); 182776#L334-2 is_master_triggered_~__retres1~0#1 := 0; 183113#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183025#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 182991#L849 assume !(0 != activate_threads_~tmp~1#1); 182992#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 182921#L353 assume !(1 == ~t1_pc~0); 182922#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 183213#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 182790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 182791#L857 assume !(0 != activate_threads_~tmp___0~0#1); 182867#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182868#L372 assume !(1 == ~t2_pc~0); 182980#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 182979#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183107#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 183214#L865 assume !(0 != activate_threads_~tmp___1~0#1); 182764#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 182765#L391 assume !(1 == ~t3_pc~0); 182687#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 182688#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 182713#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 182714#L873 assume !(0 != activate_threads_~tmp___2~0#1); 182998#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182999#L410 assume !(1 == ~t4_pc~0); 183228#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 183229#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 182881#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 182882#L881 assume !(0 != activate_threads_~tmp___3~0#1); 183008#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 183009#L429 assume !(1 == ~t5_pc~0); 182824#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 182825#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 183035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 183036#L889 assume !(0 != activate_threads_~tmp___4~0#1); 183233#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 182990#L448 assume !(1 == ~t6_pc~0); 182903#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 182904#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 183200#L897 assume !(0 != activate_threads_~tmp___5~0#1); 183375#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183413#L762 assume !(1 == ~M_E~0); 183040#L762-2 assume !(1 == ~T1_E~0); 183041#L767-1 assume !(1 == ~T2_E~0); 183380#L772-1 assume !(1 == ~T3_E~0); 183263#L777-1 assume !(1 == ~T4_E~0); 183152#L782-1 assume !(1 == ~T5_E~0); 182849#L787-1 assume !(1 == ~T6_E~0); 182847#L792-1 assume !(1 == ~E_M~0); 182848#L797-1 assume !(1 == ~E_1~0); 182887#L802-1 assume !(1 == ~E_2~0); 183117#L807-1 assume !(1 == ~E_3~0); 183118#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 183350#L817-1 assume !(1 == ~E_5~0); 183170#L822-1 assume !(1 == ~E_6~0); 183171#L827-1 assume { :end_inline_reset_delta_events } true; 183356#L1053-2 [2024-11-13 15:45:26,877 INFO L747 eck$LassoCheckResult]: Loop: 183356#L1053-2 assume !false; 189291#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189287#L659-1 assume !false; 189283#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189276#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189269#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189267#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 189265#L570 assume !(0 != eval_~tmp~0#1); 189263#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 189261#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189259#L684-3 assume !(0 == ~M_E~0); 189257#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189255#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 189253#L694-3 assume !(0 == ~T3_E~0); 189251#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 189249#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 189247#L709-3 assume !(0 == ~T6_E~0); 189245#L714-3 assume !(0 == ~E_M~0); 189243#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189241#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 189239#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189236#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189234#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189232#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189230#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189228#L334-24 assume !(1 == ~m_pc~0); 189226#L334-26 is_master_triggered_~__retres1~0#1 := 0; 189222#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189220#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189218#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189216#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189214#L353-24 assume !(1 == ~t1_pc~0); 189212#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 189209#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189207#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189205#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189203#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189201#L372-24 assume 1 == ~t2_pc~0; 189198#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 189196#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189194#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189192#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 189190#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189188#L391-24 assume !(1 == ~t3_pc~0); 189186#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 189184#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189182#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189180#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189178#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189176#L410-24 assume !(1 == ~t4_pc~0); 189172#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 189170#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189168#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189166#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189163#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189161#L429-24 assume 1 == ~t5_pc~0; 189159#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189160#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189754#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189149#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189147#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189145#L448-24 assume !(1 == ~t6_pc~0); 189143#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 189142#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189140#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189138#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189136#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189134#L762-3 assume !(1 == ~M_E~0); 185958#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189131#L767-3 assume !(1 == ~T2_E~0); 189129#L772-3 assume !(1 == ~T3_E~0); 189127#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189125#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189123#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189121#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189119#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189117#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 189116#L807-3 assume !(1 == ~E_3~0); 189115#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189114#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189113#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189112#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189110#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189097#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189095#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 186146#L1072 assume !(0 == start_simulation_~tmp~3#1); 186147#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189574#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189572#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 189567#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189565#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189563#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 189561#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 183356#L1053-2 [2024-11-13 15:45:26,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:26,878 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2024-11-13 15:45:26,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:26,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459768541] [2024-11-13 15:45:26,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:26,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:26,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:26,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:26,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:26,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459768541] [2024-11-13 15:45:26,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459768541] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:26,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:26,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:26,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677409370] [2024-11-13 15:45:26,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:26,966 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:26,967 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:26,967 INFO L85 PathProgramCache]: Analyzing trace with hash -1516409792, now seen corresponding path program 1 times [2024-11-13 15:45:26,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:26,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316957775] [2024-11-13 15:45:26,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:26,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:26,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:27,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:27,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:27,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316957775] [2024-11-13 15:45:27,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316957775] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:27,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:27,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:27,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721805876] [2024-11-13 15:45:27,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:27,021 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:27,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:27,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:27,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:27,022 INFO L87 Difference]: Start difference. First operand 15146 states and 21535 transitions. cyclomatic complexity: 6405 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:27,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:27,269 INFO L93 Difference]: Finished difference Result 23948 states and 33803 transitions. [2024-11-13 15:45:27,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23948 states and 33803 transitions. [2024-11-13 15:45:27,500 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23616 [2024-11-13 15:45:27,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23948 states to 23948 states and 33803 transitions. [2024-11-13 15:45:27,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23948 [2024-11-13 15:45:27,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23948 [2024-11-13 15:45:27,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23948 states and 33803 transitions. [2024-11-13 15:45:27,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:27,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23948 states and 33803 transitions. [2024-11-13 15:45:27,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23948 states and 33803 transitions. [2024-11-13 15:45:27,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23948 to 17289. [2024-11-13 15:45:27,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.4158135230493378) internal successors, (24478), 17288 states have internal predecessors, (24478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:28,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24478 transitions. [2024-11-13 15:45:28,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2024-11-13 15:45:28,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:28,049 INFO L424 stractBuchiCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2024-11-13 15:45:28,049 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 15:45:28,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24478 transitions. [2024-11-13 15:45:28,119 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-13 15:45:28,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:28,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:28,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:28,122 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:28,122 INFO L745 eck$LassoCheckResult]: Stem: 222191#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 222192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 222332#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 222333#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221970#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 221971#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222330#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222331#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222251#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222028#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222029#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221950#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221951#L684 assume !(0 == ~M_E~0); 222456#L684-2 assume !(0 == ~T1_E~0); 222287#L689-1 assume !(0 == ~T2_E~0); 222288#L694-1 assume !(0 == ~T3_E~0); 222285#L699-1 assume !(0 == ~T4_E~0); 222286#L704-1 assume !(0 == ~T5_E~0); 222235#L709-1 assume !(0 == ~T6_E~0); 222172#L714-1 assume !(0 == ~E_M~0); 222173#L719-1 assume !(0 == ~E_1~0); 222427#L724-1 assume !(0 == ~E_2~0); 221924#L729-1 assume !(0 == ~E_3~0); 221925#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 222498#L739-1 assume !(0 == ~E_5~0); 222128#L744-1 assume !(0 == ~E_6~0); 222129#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221879#L334 assume !(1 == ~m_pc~0); 221880#L334-2 is_master_triggered_~__retres1~0#1 := 0; 222227#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222131#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 222132#L849 assume !(0 != activate_threads_~tmp~1#1); 222622#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222621#L353 assume !(1 == ~t1_pc~0); 222620#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 222336#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221895#L857 assume !(0 != activate_threads_~tmp___0~0#1); 222618#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222541#L372 assume !(1 == ~t2_pc~0); 222542#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 222617#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222337#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222338#L865 assume !(0 != activate_threads_~tmp___1~0#1); 222484#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222615#L391 assume !(1 == ~t3_pc~0); 221791#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221792#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221818#L873 assume !(0 != activate_threads_~tmp___2~0#1); 222420#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222611#L410 assume !(1 == ~t4_pc~0); 222349#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222350#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221991#L881 assume !(0 != activate_threads_~tmp___3~0#1); 222486#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222275#L429 assume !(1 == ~t5_pc~0); 222276#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 222606#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222604#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222602#L889 assume !(0 != activate_threads_~tmp___4~0#1); 222601#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222094#L448 assume !(1 == ~t6_pc~0); 222009#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 222010#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222354#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 222521#L897 assume !(0 != activate_threads_~tmp___5~0#1); 222522#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222574#L762 assume !(1 == ~M_E~0); 222152#L762-2 assume !(1 == ~T1_E~0); 222153#L767-1 assume !(1 == ~T2_E~0); 222528#L772-1 assume !(1 == ~T3_E~0); 222386#L777-1 assume !(1 == ~T4_E~0); 222387#L782-1 assume !(1 == ~T5_E~0); 221956#L787-1 assume !(1 == ~T6_E~0); 221957#L792-1 assume !(1 == ~E_M~0); 222596#L797-1 assume !(1 == ~E_1~0); 222595#L802-1 assume !(1 == ~E_2~0); 222594#L807-1 assume !(1 == ~E_3~0); 222593#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 222493#L817-1 assume !(1 == ~E_5~0); 222289#L822-1 assume !(1 == ~E_6~0); 222290#L827-1 assume { :end_inline_reset_delta_events } true; 222502#L1053-2 [2024-11-13 15:45:28,122 INFO L747 eck$LassoCheckResult]: Loop: 222502#L1053-2 assume !false; 226330#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 226321#L659-1 assume !false; 226313#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 225323#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 225184#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 225181#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 225178#L570 assume !(0 != eval_~tmp~0#1); 225176#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 225173#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 225171#L684-3 assume !(0 == ~M_E~0); 225169#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 225167#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 225165#L694-3 assume !(0 == ~T3_E~0); 225157#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 225155#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 225153#L709-3 assume !(0 == ~T6_E~0); 225151#L714-3 assume !(0 == ~E_M~0); 225122#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 225112#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 225104#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 225089#L734-3 assume !(0 == ~E_4~0); 225090#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 226012#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 226008#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 226006#L334-24 assume !(1 == ~m_pc~0); 226002#L334-26 is_master_triggered_~__retres1~0#1 := 0; 225998#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 225994#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 225991#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 225987#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 225984#L353-24 assume !(1 == ~t1_pc~0); 225981#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 225978#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 225975#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 225972#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 225969#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 225966#L372-24 assume !(1 == ~t2_pc~0); 225963#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 225959#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 225956#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 225953#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 225949#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 225946#L391-24 assume !(1 == ~t3_pc~0); 225943#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 225940#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 225936#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 225932#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 225926#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 225920#L410-24 assume !(1 == ~t4_pc~0); 225916#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 225912#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 225908#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 225904#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 225854#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 225848#L429-24 assume !(1 == ~t5_pc~0); 225843#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 225837#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 225829#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 225782#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 225779#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 225776#L448-24 assume !(1 == ~t6_pc~0); 225774#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 225772#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 225762#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 225749#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 225605#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 225602#L762-3 assume !(1 == ~M_E~0); 224588#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 225599#L767-3 assume !(1 == ~T2_E~0); 225596#L772-3 assume !(1 == ~T3_E~0); 225575#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 225359#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 225358#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 225150#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 225121#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 225111#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 225103#L807-3 assume !(1 == ~E_3~0); 225027#L812-3 assume !(1 == ~E_4~0); 225020#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 225018#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 225016#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 224969#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 224963#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 224953#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 224803#L1072 assume !(0 == start_simulation_~tmp~3#1); 224804#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 226353#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 226349#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 226343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 226338#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 226337#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 226336#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 226335#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 222502#L1053-2 [2024-11-13 15:45:28,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:28,127 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2024-11-13 15:45:28,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:28,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770744053] [2024-11-13 15:45:28,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:28,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:28,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:28,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:28,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:28,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770744053] [2024-11-13 15:45:28,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770744053] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:28,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:28,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:28,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16890947] [2024-11-13 15:45:28,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:28,211 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:28,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:28,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1714219964, now seen corresponding path program 1 times [2024-11-13 15:45:28,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:28,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579724960] [2024-11-13 15:45:28,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:28,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:28,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:28,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:28,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:28,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579724960] [2024-11-13 15:45:28,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579724960] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:28,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:28,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:28,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983329230] [2024-11-13 15:45:28,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:28,278 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:28,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:28,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:28,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:28,279 INFO L87 Difference]: Start difference. First operand 17289 states and 24478 transitions. cyclomatic complexity: 7205 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:28,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:28,634 INFO L93 Difference]: Finished difference Result 21622 states and 30409 transitions. [2024-11-13 15:45:28,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21622 states and 30409 transitions. [2024-11-13 15:45:28,711 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2024-11-13 15:45:28,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21622 states to 21622 states and 30409 transitions. [2024-11-13 15:45:28,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21622 [2024-11-13 15:45:28,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21622 [2024-11-13 15:45:28,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21622 states and 30409 transitions. [2024-11-13 15:45:28,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:28,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21622 states and 30409 transitions. [2024-11-13 15:45:28,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21622 states and 30409 transitions. [2024-11-13 15:45:28,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21622 to 15146. [2024-11-13 15:45:28,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4084906906113825) internal successors, (21333), 15145 states have internal predecessors, (21333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:29,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21333 transitions. [2024-11-13 15:45:29,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2024-11-13 15:45:29,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:29,025 INFO L424 stractBuchiCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2024-11-13 15:45:29,025 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 15:45:29,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21333 transitions. [2024-11-13 15:45:29,070 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-13 15:45:29,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:29,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:29,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:29,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:29,073 INFO L745 eck$LassoCheckResult]: Stem: 261110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 261111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 261249#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 261250#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 260890#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 260891#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 261247#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 261248#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 261174#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 260950#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 260951#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 260871#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 260872#L684 assume !(0 == ~M_E~0); 261373#L684-2 assume !(0 == ~T1_E~0); 261205#L689-1 assume !(0 == ~T2_E~0); 261206#L694-1 assume !(0 == ~T3_E~0); 261203#L699-1 assume !(0 == ~T4_E~0); 261204#L704-1 assume !(0 == ~T5_E~0); 261158#L709-1 assume !(0 == ~T6_E~0); 261091#L714-1 assume !(0 == ~E_M~0); 261092#L719-1 assume !(0 == ~E_1~0); 261342#L724-1 assume !(0 == ~E_2~0); 260842#L729-1 assume !(0 == ~E_3~0); 260843#L734-1 assume !(0 == ~E_4~0); 261408#L739-1 assume !(0 == ~E_5~0); 261050#L744-1 assume !(0 == ~E_6~0); 261051#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260798#L334 assume !(1 == ~m_pc~0); 260799#L334-2 is_master_triggered_~__retres1~0#1 := 0; 261150#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261054#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 261019#L849 assume !(0 != activate_threads_~tmp~1#1); 261020#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260948#L353 assume !(1 == ~t1_pc~0); 260949#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 261253#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260814#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 260815#L857 assume !(0 != activate_threads_~tmp___0~0#1); 260895#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260896#L372 assume !(1 == ~t2_pc~0); 261008#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 261007#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261142#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261254#L865 assume !(0 != activate_threads_~tmp___1~0#1); 260787#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260788#L391 assume !(1 == ~t3_pc~0); 260712#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 260713#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260737#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 260738#L873 assume !(0 != activate_threads_~tmp___2~0#1); 261026#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261027#L410 assume !(1 == ~t4_pc~0); 261269#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 261270#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 260911#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 260912#L881 assume !(0 != activate_threads_~tmp___3~0#1); 261034#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 261035#L429 assume !(1 == ~t5_pc~0); 260848#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 260849#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 261065#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 261066#L889 assume !(0 != activate_threads_~tmp___4~0#1); 261275#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 261018#L448 assume !(1 == ~t6_pc~0); 260931#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 260932#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 261237#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 261238#L897 assume !(0 != activate_threads_~tmp___5~0#1); 261435#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261483#L762 assume !(1 == ~M_E~0); 261071#L762-2 assume !(1 == ~T1_E~0); 261072#L767-1 assume !(1 == ~T2_E~0); 261440#L772-1 assume !(1 == ~T3_E~0); 261306#L777-1 assume !(1 == ~T4_E~0); 261189#L782-1 assume !(1 == ~T5_E~0); 260877#L787-1 assume !(1 == ~T6_E~0); 260875#L792-1 assume !(1 == ~E_M~0); 260876#L797-1 assume !(1 == ~E_1~0); 260916#L802-1 assume !(1 == ~E_2~0); 261154#L807-1 assume !(1 == ~E_3~0); 261155#L812-1 assume !(1 == ~E_4~0); 261403#L817-1 assume !(1 == ~E_5~0); 261207#L822-1 assume !(1 == ~E_6~0); 261208#L827-1 assume { :end_inline_reset_delta_events } true; 261414#L1053-2 [2024-11-13 15:45:29,074 INFO L747 eck$LassoCheckResult]: Loop: 261414#L1053-2 assume !false; 264421#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 264420#L659-1 assume !false; 264419#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 264417#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 264408#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264406#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 264403#L570 assume !(0 != eval_~tmp~0#1); 264404#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 264821#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 264818#L684-3 assume !(0 == ~M_E~0); 264815#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 264812#L689-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 264809#L694-3 assume !(0 == ~T3_E~0); 264806#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 264803#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 264800#L709-3 assume !(0 == ~T6_E~0); 264797#L714-3 assume !(0 == ~E_M~0); 264793#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 264790#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 264787#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 264785#L734-3 assume !(0 == ~E_4~0); 264783#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 264781#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 264778#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264776#L334-24 assume 1 == ~m_pc~0; 264773#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 264770#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264767#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264764#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 264760#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264757#L353-24 assume !(1 == ~t1_pc~0); 264754#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 264751#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264748#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264745#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 264740#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264736#L372-24 assume !(1 == ~t2_pc~0); 264732#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 264727#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264724#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264721#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 264717#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264714#L391-24 assume !(1 == ~t3_pc~0); 264712#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 264710#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264707#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264703#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 264699#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264696#L410-24 assume !(1 == ~t4_pc~0); 264693#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 264690#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264687#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 264684#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 264681#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264678#L429-24 assume 1 == ~t5_pc~0; 264674#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 264670#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264666#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 264661#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 264657#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264653#L448-24 assume !(1 == ~t6_pc~0); 264649#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 264645#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264642#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 264639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 264636#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264626#L762-3 assume !(1 == ~M_E~0); 263187#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 264625#L767-3 assume !(1 == ~T2_E~0); 264624#L772-3 assume !(1 == ~T3_E~0); 264623#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 264622#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 264621#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 264619#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 264616#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 264614#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 264612#L807-3 assume !(1 == ~E_3~0); 264610#L812-3 assume !(1 == ~E_4~0); 264608#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 264606#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 264603#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 264598#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 264589#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264586#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 264473#L1072 assume !(0 == start_simulation_~tmp~3#1); 264470#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 264448#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 264446#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264444#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 264442#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 264438#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 264436#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 264434#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 261414#L1053-2 [2024-11-13 15:45:29,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:29,074 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2024-11-13 15:45:29,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:29,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308439572] [2024-11-13 15:45:29,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:29,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:29,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:29,089 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:29,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:29,158 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:29,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:29,159 INFO L85 PathProgramCache]: Analyzing trace with hash -1050914944, now seen corresponding path program 1 times [2024-11-13 15:45:29,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:29,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256474717] [2024-11-13 15:45:29,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:29,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:29,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:29,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:29,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:29,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256474717] [2024-11-13 15:45:29,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256474717] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:29,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:29,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:29,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359826484] [2024-11-13 15:45:29,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:29,217 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:29,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:29,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:29,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:29,218 INFO L87 Difference]: Start difference. First operand 15146 states and 21333 transitions. cyclomatic complexity: 6203 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:29,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:29,311 INFO L93 Difference]: Finished difference Result 17289 states and 24330 transitions. [2024-11-13 15:45:29,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17289 states and 24330 transitions. [2024-11-13 15:45:29,378 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-13 15:45:29,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17289 states to 17289 states and 24330 transitions. [2024-11-13 15:45:29,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17289 [2024-11-13 15:45:29,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17289 [2024-11-13 15:45:29,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17289 states and 24330 transitions. [2024-11-13 15:45:29,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:29,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-13 15:45:29,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17289 states and 24330 transitions. [2024-11-13 15:45:29,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17289 to 17289. [2024-11-13 15:45:29,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.407253166753427) internal successors, (24330), 17288 states have internal predecessors, (24330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:29,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24330 transitions. [2024-11-13 15:45:29,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-13 15:45:29,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:29,882 INFO L424 stractBuchiCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-13 15:45:29,882 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 15:45:29,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24330 transitions. [2024-11-13 15:45:29,935 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-13 15:45:29,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:29,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:29,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:29,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:29,938 INFO L745 eck$LassoCheckResult]: Stem: 293544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 293545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 293685#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293686#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 293329#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 293330#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 293683#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 293684#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 293606#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 293389#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 293390#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 293310#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 293311#L684 assume !(0 == ~M_E~0); 293812#L684-2 assume !(0 == ~T1_E~0); 293638#L689-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 293639#L694-1 assume !(0 == ~T3_E~0); 293636#L699-1 assume !(0 == ~T4_E~0); 293637#L704-1 assume !(0 == ~T5_E~0); 293591#L709-1 assume !(0 == ~T6_E~0); 293526#L714-1 assume !(0 == ~E_M~0); 293527#L719-1 assume !(0 == ~E_1~0); 293779#L724-1 assume !(0 == ~E_2~0); 293285#L729-1 assume !(0 == ~E_3~0); 293286#L734-1 assume !(0 == ~E_4~0); 293980#L739-1 assume !(0 == ~E_5~0); 293979#L744-1 assume !(0 == ~E_6~0); 293978#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293242#L334 assume !(1 == ~m_pc~0); 293243#L334-2 is_master_triggered_~__retres1~0#1 := 0; 293582#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293487#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293488#L849 assume !(0 != activate_threads_~tmp~1#1); 293973#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293972#L353 assume !(1 == ~t1_pc~0); 293971#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 293970#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293969#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293661#L857 assume !(0 != activate_threads_~tmp___0~0#1); 293334#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293335#L372 assume !(1 == ~t2_pc~0); 293966#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 293965#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 293963#L865 assume !(0 != activate_threads_~tmp___1~0#1); 293231#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293232#L391 assume !(1 == ~t3_pc~0); 293154#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 293155#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293180#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293181#L873 assume !(0 != activate_threads_~tmp___2~0#1); 293460#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293461#L410 assume !(1 == ~t4_pc~0); 293703#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 293704#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 293349#L881 assume !(0 != activate_threads_~tmp___3~0#1); 293466#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293467#L429 assume !(1 == ~t5_pc~0); 293630#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 293952#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 293944#L889 assume !(0 != activate_threads_~tmp___4~0#1); 293943#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293942#L448 assume !(1 == ~t6_pc~0); 293941#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 293940#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 293939#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 293866#L897 assume !(0 != activate_threads_~tmp___5~0#1); 293867#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293919#L762 assume !(1 == ~M_E~0); 293505#L762-2 assume !(1 == ~T1_E~0); 293506#L767-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 293872#L772-1 assume !(1 == ~T3_E~0); 293743#L777-1 assume !(1 == ~T4_E~0); 293622#L782-1 assume !(1 == ~T5_E~0); 293316#L787-1 assume !(1 == ~T6_E~0); 293314#L792-1 assume !(1 == ~E_M~0); 293315#L797-1 assume !(1 == ~E_1~0); 293353#L802-1 assume !(1 == ~E_2~0); 293586#L807-1 assume !(1 == ~E_3~0); 293587#L812-1 assume !(1 == ~E_4~0); 293839#L817-1 assume !(1 == ~E_5~0); 293641#L822-1 assume !(1 == ~E_6~0); 293642#L827-1 assume { :end_inline_reset_delta_events } true; 293848#L1053-2 [2024-11-13 15:45:29,938 INFO L747 eck$LassoCheckResult]: Loop: 293848#L1053-2 assume !false; 298865#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 297528#L659-1 assume !false; 298864#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 297643#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 297636#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 297634#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 297631#L570 assume !(0 != eval_~tmp~0#1); 297632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 299908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 299906#L684-3 assume !(0 == ~M_E~0); 299904#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 299901#L689-3 assume !(0 == ~T2_E~0); 299902#L694-3 assume !(0 == ~T3_E~0); 299641#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 299633#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 299631#L709-3 assume !(0 == ~T6_E~0); 299629#L714-3 assume !(0 == ~E_M~0); 299627#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 299625#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 299623#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 299620#L734-3 assume !(0 == ~E_4~0); 299618#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 299616#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 299614#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 299612#L334-24 assume 1 == ~m_pc~0; 299609#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 299607#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299605#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 299603#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 299601#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299599#L353-24 assume !(1 == ~t1_pc~0); 299597#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 299594#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 299592#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 299590#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 299588#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299586#L372-24 assume !(1 == ~t2_pc~0); 299584#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 299581#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299579#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299577#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 299575#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299573#L391-24 assume !(1 == ~t3_pc~0); 299571#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 299569#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299567#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 299565#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 299563#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299561#L410-24 assume !(1 == ~t4_pc~0); 299559#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 299556#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299554#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299552#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 299551#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 299550#L429-24 assume !(1 == ~t5_pc~0); 299548#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 299860#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299859#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 299540#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 299536#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 299534#L448-24 assume !(1 == ~t6_pc~0); 299532#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 299530#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299528#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 299526#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 299524#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 299522#L762-3 assume !(1 == ~M_E~0); 295661#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 299519#L767-3 assume !(1 == ~T2_E~0); 299516#L772-3 assume !(1 == ~T3_E~0); 299487#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 299466#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 299462#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 299451#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 299444#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 299440#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 299436#L807-3 assume !(1 == ~E_3~0); 299431#L812-3 assume !(1 == ~E_4~0); 299426#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 299422#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 299413#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 297023#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 297016#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 297014#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 297011#L1072 assume !(0 == start_simulation_~tmp~3#1); 297012#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 298873#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 298871#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 298870#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 298869#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 298868#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 298867#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 298866#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 293848#L1053-2 [2024-11-13 15:45:29,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:29,939 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2024-11-13 15:45:29,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:29,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123574674] [2024-11-13 15:45:29,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:29,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:30,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:30,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:30,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:30,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123574674] [2024-11-13 15:45:30,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123574674] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:30,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:30,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:30,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271236876] [2024-11-13 15:45:30,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:30,154 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:30,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:30,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1285090879, now seen corresponding path program 1 times [2024-11-13 15:45:30,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:30,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473386492] [2024-11-13 15:45:30,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:30,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:30,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:30,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:30,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:30,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473386492] [2024-11-13 15:45:30,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473386492] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:30,213 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:30,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:30,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911246628] [2024-11-13 15:45:30,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:30,213 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:30,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:30,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:30,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:30,214 INFO L87 Difference]: Start difference. First operand 17289 states and 24330 transitions. cyclomatic complexity: 7057 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:30,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:30,376 INFO L93 Difference]: Finished difference Result 22046 states and 30937 transitions. [2024-11-13 15:45:30,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22046 states and 30937 transitions. [2024-11-13 15:45:30,463 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2024-11-13 15:45:30,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22046 states to 22046 states and 30937 transitions. [2024-11-13 15:45:30,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22046 [2024-11-13 15:45:30,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22046 [2024-11-13 15:45:30,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22046 states and 30937 transitions. [2024-11-13 15:45:30,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:30,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22046 states and 30937 transitions. [2024-11-13 15:45:30,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22046 states and 30937 transitions. [2024-11-13 15:45:30,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22046 to 15146. [2024-11-13 15:45:30,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4063118975307012) internal successors, (21300), 15145 states have internal predecessors, (21300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:30,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21300 transitions. [2024-11-13 15:45:30,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2024-11-13 15:45:30,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:30,751 INFO L424 stractBuchiCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2024-11-13 15:45:30,751 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 15:45:30,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21300 transitions. [2024-11-13 15:45:30,794 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-13 15:45:30,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:30,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:30,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:30,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:30,797 INFO L745 eck$LassoCheckResult]: Stem: 332894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 332895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 333023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 332677#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 332678#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333018#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 333019#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 332949#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 332736#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 332737#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 332657#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 332658#L684 assume !(0 == ~M_E~0); 333134#L684-2 assume !(0 == ~T1_E~0); 332979#L689-1 assume !(0 == ~T2_E~0); 332980#L694-1 assume !(0 == ~T3_E~0); 332977#L699-1 assume !(0 == ~T4_E~0); 332978#L704-1 assume !(0 == ~T5_E~0); 332937#L709-1 assume !(0 == ~T6_E~0); 332871#L714-1 assume !(0 == ~E_M~0); 332872#L719-1 assume !(0 == ~E_1~0); 333105#L724-1 assume !(0 == ~E_2~0); 332630#L729-1 assume !(0 == ~E_3~0); 332631#L734-1 assume !(0 == ~E_4~0); 333166#L739-1 assume !(0 == ~E_5~0); 332828#L744-1 assume !(0 == ~E_6~0); 332829#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332586#L334 assume !(1 == ~m_pc~0); 332587#L334-2 is_master_triggered_~__retres1~0#1 := 0; 332926#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 332832#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332798#L849 assume !(0 != activate_threads_~tmp~1#1); 332799#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332732#L353 assume !(1 == ~t1_pc~0); 332733#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 333024#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 332601#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 332602#L857 assume !(0 != activate_threads_~tmp___0~0#1); 332679#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 332680#L372 assume !(1 == ~t2_pc~0); 332787#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 332786#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 332921#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333025#L865 assume !(0 != activate_threads_~tmp___1~0#1); 332575#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 332576#L391 assume !(1 == ~t3_pc~0); 332498#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 332499#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 332524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 332525#L873 assume !(0 != activate_threads_~tmp___2~0#1); 332805#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 332806#L410 assume !(1 == ~t4_pc~0); 333039#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333040#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 332693#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 332694#L881 assume !(0 != activate_threads_~tmp___3~0#1); 332815#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332816#L429 assume !(1 == ~t5_pc~0); 332636#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 332637#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 332843#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 332844#L889 assume !(0 != activate_threads_~tmp___4~0#1); 333043#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 332797#L448 assume !(1 == ~t6_pc~0); 332715#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 332716#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333010#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333011#L897 assume !(0 != activate_threads_~tmp___5~0#1); 333193#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333236#L762 assume !(1 == ~M_E~0); 332852#L762-2 assume !(1 == ~T1_E~0); 332853#L767-1 assume !(1 == ~T2_E~0); 333198#L772-1 assume !(1 == ~T3_E~0); 333072#L777-1 assume !(1 == ~T4_E~0); 332964#L782-1 assume !(1 == ~T5_E~0); 332661#L787-1 assume !(1 == ~T6_E~0); 332659#L792-1 assume !(1 == ~E_M~0); 332660#L797-1 assume !(1 == ~E_1~0); 332699#L802-1 assume !(1 == ~E_2~0); 332930#L807-1 assume !(1 == ~E_3~0); 332931#L812-1 assume !(1 == ~E_4~0); 333163#L817-1 assume !(1 == ~E_5~0); 332981#L822-1 assume !(1 == ~E_6~0); 332982#L827-1 assume { :end_inline_reset_delta_events } true; 333172#L1053-2 [2024-11-13 15:45:30,798 INFO L747 eck$LassoCheckResult]: Loop: 333172#L1053-2 assume !false; 341229#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 341227#L659-1 assume !false; 341225#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 341215#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 341208#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 341206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 341203#L570 assume !(0 != eval_~tmp~0#1); 341204#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 347349#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 347347#L684-3 assume !(0 == ~M_E~0); 347345#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 347343#L689-3 assume !(0 == ~T2_E~0); 347341#L694-3 assume !(0 == ~T3_E~0); 347339#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 347337#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 347335#L709-3 assume !(0 == ~T6_E~0); 347333#L714-3 assume !(0 == ~E_M~0); 347330#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 347328#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 347326#L729-3 assume 0 == ~E_3~0;~E_3~0 := 1; 347324#L734-3 assume !(0 == ~E_4~0); 347322#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 347320#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 347317#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347315#L334-24 assume !(1 == ~m_pc~0); 347313#L334-26 is_master_triggered_~__retres1~0#1 := 0; 347310#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 347308#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 347306#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 347303#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347301#L353-24 assume !(1 == ~t1_pc~0); 347299#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 347297#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 347295#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 347293#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 347291#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 347289#L372-24 assume !(1 == ~t2_pc~0); 347287#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 347284#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 347282#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 347279#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 347277#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 347275#L391-24 assume !(1 == ~t3_pc~0); 347273#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 347271#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 347269#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 347265#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 347263#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 347261#L410-24 assume !(1 == ~t4_pc~0); 347259#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 347256#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 347254#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 347252#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 347249#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 347247#L429-24 assume 1 == ~t5_pc~0; 347245#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 347246#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 347360#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 347236#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 347235#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 347233#L448-24 assume !(1 == ~t6_pc~0); 347231#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 347229#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 347227#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347225#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 347223#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 347221#L762-3 assume !(1 == ~M_E~0); 338460#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 347218#L767-3 assume !(1 == ~T2_E~0); 347216#L772-3 assume !(1 == ~T3_E~0); 347214#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 347212#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 347210#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 347209#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 347208#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 347207#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 347206#L807-3 assume !(1 == ~E_3~0); 347205#L812-3 assume !(1 == ~E_4~0); 347204#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 347203#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 347202#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 345790#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 343066#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 343056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 338594#L1072 assume !(0 == start_simulation_~tmp~3#1); 338595#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 341367#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 341365#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 341364#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 341361#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 341360#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 341359#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 341358#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 333172#L1053-2 [2024-11-13 15:45:30,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:30,799 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2024-11-13 15:45:30,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:30,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393305296] [2024-11-13 15:45:30,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:30,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:30,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:30,815 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:30,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:30,847 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:30,847 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:30,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1653471871, now seen corresponding path program 1 times [2024-11-13 15:45:30,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:30,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083566973] [2024-11-13 15:45:30,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:30,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:30,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:30,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:30,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:30,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083566973] [2024-11-13 15:45:30,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083566973] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:30,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:30,905 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:30,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643187549] [2024-11-13 15:45:30,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:30,905 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:30,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:30,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:30,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:30,906 INFO L87 Difference]: Start difference. First operand 15146 states and 21300 transitions. cyclomatic complexity: 6170 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:31,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:31,245 INFO L93 Difference]: Finished difference Result 22705 states and 31782 transitions. [2024-11-13 15:45:31,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22705 states and 31782 transitions. [2024-11-13 15:45:31,356 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22392 [2024-11-13 15:45:31,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22705 states to 22705 states and 31782 transitions. [2024-11-13 15:45:31,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22705 [2024-11-13 15:45:31,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22705 [2024-11-13 15:45:31,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22705 states and 31782 transitions. [2024-11-13 15:45:31,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:31,473 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22705 states and 31782 transitions. [2024-11-13 15:45:31,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22705 states and 31782 transitions. [2024-11-13 15:45:31,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22705 to 22689. [2024-11-13 15:45:31,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22689 states, 22689 states have (on average 1.4000617039093834) internal successors, (31766), 22688 states have internal predecessors, (31766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:31,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22689 states to 22689 states and 31766 transitions. [2024-11-13 15:45:31,843 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22689 states and 31766 transitions. [2024-11-13 15:45:31,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:31,844 INFO L424 stractBuchiCegarLoop]: Abstraction has 22689 states and 31766 transitions. [2024-11-13 15:45:31,844 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 15:45:31,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22689 states and 31766 transitions. [2024-11-13 15:45:31,905 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22376 [2024-11-13 15:45:31,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:31,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:31,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:31,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:31,907 INFO L745 eck$LassoCheckResult]: Stem: 370748#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 370749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 370889#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 370890#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 370535#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 370536#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 370885#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 370886#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 370812#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 370591#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 370592#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 370515#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 370516#L684 assume !(0 == ~M_E~0); 371018#L684-2 assume !(0 == ~T1_E~0); 370844#L689-1 assume !(0 == ~T2_E~0); 370845#L694-1 assume !(0 == ~T3_E~0); 370842#L699-1 assume !(0 == ~T4_E~0); 370843#L704-1 assume !(0 == ~T5_E~0); 370798#L709-1 assume !(0 == ~T6_E~0); 370725#L714-1 assume !(0 == ~E_M~0); 370726#L719-1 assume !(0 == ~E_1~0); 370985#L724-1 assume !(0 == ~E_2~0); 370486#L729-1 assume 0 == ~E_3~0;~E_3~0 := 1; 370487#L734-1 assume !(0 == ~E_4~0); 371055#L739-1 assume !(0 == ~E_5~0); 371056#L744-1 assume !(0 == ~E_6~0); 371190#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 370443#L334 assume !(1 == ~m_pc~0); 370444#L334-2 is_master_triggered_~__retres1~0#1 := 0; 370787#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 370690#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 370691#L849 assume !(0 != activate_threads_~tmp~1#1); 371185#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371184#L353 assume !(1 == ~t1_pc~0); 371183#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 370891#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 370458#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 370459#L857 assume !(0 != activate_threads_~tmp___0~0#1); 371181#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371104#L372 assume !(1 == ~t2_pc~0); 371105#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 371180#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 370892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 370893#L865 assume !(0 != activate_threads_~tmp___1~0#1); 371041#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371178#L391 assume !(1 == ~t3_pc~0); 371177#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 371176#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371174#L873 assume !(0 != activate_threads_~tmp___2~0#1); 370665#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 370666#L410 assume !(1 == ~t4_pc~0); 371039#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371172#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371171#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 371170#L881 assume !(0 != activate_threads_~tmp___3~0#1); 370674#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370675#L429 assume !(1 == ~t5_pc~0); 370493#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 370494#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 370912#L889 assume !(0 != activate_threads_~tmp___4~0#1); 370913#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 370944#L448 assume !(1 == ~t6_pc~0); 371162#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 371161#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 370877#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 370878#L897 assume !(0 != activate_threads_~tmp___5~0#1); 371139#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371140#L762 assume !(1 == ~M_E~0); 371160#L762-2 assume !(1 == ~T1_E~0); 371121#L767-1 assume !(1 == ~T2_E~0); 371122#L772-1 assume !(1 == ~T3_E~0); 371159#L777-1 assume !(1 == ~T4_E~0); 371158#L782-1 assume !(1 == ~T5_E~0); 370519#L787-1 assume !(1 == ~T6_E~0); 370517#L792-1 assume !(1 == ~E_M~0); 370518#L797-1 assume !(1 == ~E_1~0); 370557#L802-1 assume !(1 == ~E_2~0); 370791#L807-1 assume 1 == ~E_3~0;~E_3~0 := 2; 370792#L812-1 assume !(1 == ~E_4~0); 371052#L817-1 assume !(1 == ~E_5~0); 370846#L822-1 assume !(1 == ~E_6~0); 370847#L827-1 assume { :end_inline_reset_delta_events } true; 371063#L1053-2 [2024-11-13 15:45:31,908 INFO L747 eck$LassoCheckResult]: Loop: 371063#L1053-2 assume !false; 381907#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 381905#L659-1 assume !false; 381902#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 377998#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 377991#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 377989#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 377986#L570 assume !(0 != eval_~tmp~0#1); 377984#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 377982#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 377980#L684-3 assume !(0 == ~M_E~0); 377978#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 377976#L689-3 assume !(0 == ~T2_E~0); 377974#L694-3 assume !(0 == ~T3_E~0); 377972#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 377970#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 377968#L709-3 assume !(0 == ~T6_E~0); 377966#L714-3 assume !(0 == ~E_M~0); 377962#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 377960#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 377957#L729-3 assume !(0 == ~E_3~0); 377958#L734-3 assume !(0 == ~E_4~0); 392537#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 392536#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 392535#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 392534#L334-24 assume !(1 == ~m_pc~0); 392533#L334-26 is_master_triggered_~__retres1~0#1 := 0; 392531#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 392530#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 392529#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 392528#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 392527#L353-24 assume !(1 == ~t1_pc~0); 392526#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 392525#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392524#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 381915#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 381911#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 381906#L372-24 assume !(1 == ~t2_pc~0); 381904#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 378002#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378001#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 378000#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 377992#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 377990#L391-24 assume !(1 == ~t3_pc~0); 377988#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 377985#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 377983#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 377981#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 377979#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 377977#L410-24 assume !(1 == ~t4_pc~0); 377975#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 377973#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 377971#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 377969#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 377967#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 377965#L429-24 assume !(1 == ~t5_pc~0); 377961#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 377959#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377956#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 377954#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 377951#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 377949#L448-24 assume !(1 == ~t6_pc~0); 377947#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 377945#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 377942#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 377940#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 377938#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 377936#L762-3 assume !(1 == ~M_E~0); 374963#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 377933#L767-3 assume !(1 == ~T2_E~0); 377931#L772-3 assume !(1 == ~T3_E~0); 377929#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 377927#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 377925#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 377923#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 377921#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 377918#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 377843#L807-3 assume !(1 == ~E_3~0); 377841#L812-3 assume !(1 == ~E_4~0); 377839#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 377837#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 377835#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 375153#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 375147#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 375146#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 375143#L1072 assume !(0 == start_simulation_~tmp~3#1); 375144#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 381934#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 381932#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 381930#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 381928#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 381926#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 381924#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 381920#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 371063#L1053-2 [2024-11-13 15:45:31,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:31,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2024-11-13 15:45:31,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:31,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475134947] [2024-11-13 15:45:31,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:31,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:31,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:31,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:31,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:31,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475134947] [2024-11-13 15:45:31,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475134947] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:31,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:31,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:31,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029080795] [2024-11-13 15:45:31,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:31,977 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:45:31,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:31,977 INFO L85 PathProgramCache]: Analyzing trace with hash 739760832, now seen corresponding path program 1 times [2024-11-13 15:45:31,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:31,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864182117] [2024-11-13 15:45:31,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:31,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:31,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:32,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:32,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:32,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864182117] [2024-11-13 15:45:32,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864182117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:32,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:32,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:32,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213333945] [2024-11-13 15:45:32,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:32,093 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:32,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:32,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 15:45:32,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 15:45:32,095 INFO L87 Difference]: Start difference. First operand 22689 states and 31766 transitions. cyclomatic complexity: 9093 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:32,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:32,362 INFO L93 Difference]: Finished difference Result 30702 states and 42901 transitions. [2024-11-13 15:45:32,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30702 states and 42901 transitions. [2024-11-13 15:45:32,724 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 29724 [2024-11-13 15:45:32,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30702 states to 30702 states and 42901 transitions. [2024-11-13 15:45:32,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30702 [2024-11-13 15:45:32,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30702 [2024-11-13 15:45:32,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30702 states and 42901 transitions. [2024-11-13 15:45:32,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:32,860 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30702 states and 42901 transitions. [2024-11-13 15:45:32,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30702 states and 42901 transitions. [2024-11-13 15:45:33,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30702 to 21594. [2024-11-13 15:45:33,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21594 states, 21594 states have (on average 1.3984903213855702) internal successors, (30199), 21593 states have internal predecessors, (30199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:33,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21594 states to 21594 states and 30199 transitions. [2024-11-13 15:45:33,246 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21594 states and 30199 transitions. [2024-11-13 15:45:33,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 15:45:33,247 INFO L424 stractBuchiCegarLoop]: Abstraction has 21594 states and 30199 transitions. [2024-11-13 15:45:33,247 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 15:45:33,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21594 states and 30199 transitions. [2024-11-13 15:45:33,306 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21344 [2024-11-13 15:45:33,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:33,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:33,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:33,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:33,308 INFO L745 eck$LassoCheckResult]: Stem: 424152#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 424153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 424289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 424290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 423940#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 423941#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 424285#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 424286#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 424211#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 423995#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 423996#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 423920#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 423921#L684 assume !(0 == ~M_E~0); 424407#L684-2 assume !(0 == ~T1_E~0); 424245#L689-1 assume !(0 == ~T2_E~0); 424246#L694-1 assume !(0 == ~T3_E~0); 424243#L699-1 assume !(0 == ~T4_E~0); 424244#L704-1 assume !(0 == ~T5_E~0); 424199#L709-1 assume !(0 == ~T6_E~0); 424131#L714-1 assume !(0 == ~E_M~0); 424132#L719-1 assume !(0 == ~E_1~0); 424372#L724-1 assume !(0 == ~E_2~0); 423889#L729-1 assume !(0 == ~E_3~0); 423890#L734-1 assume !(0 == ~E_4~0); 424441#L739-1 assume !(0 == ~E_5~0); 424091#L744-1 assume !(0 == ~E_6~0); 424092#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 423846#L334 assume !(1 == ~m_pc~0); 423847#L334-2 is_master_triggered_~__retres1~0#1 := 0; 424188#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 424095#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 424062#L849 assume !(0 != activate_threads_~tmp~1#1); 424063#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 423991#L353 assume !(1 == ~t1_pc~0); 423992#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 424291#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 423862#L857 assume !(0 != activate_threads_~tmp___0~0#1); 423942#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 423943#L372 assume !(1 == ~t2_pc~0); 424051#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 424050#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424183#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 424292#L865 assume !(0 != activate_threads_~tmp___1~0#1); 423835#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423836#L391 assume !(1 == ~t3_pc~0); 423758#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 423759#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423785#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 423786#L873 assume !(0 != activate_threads_~tmp___2~0#1); 424069#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 424070#L410 assume !(1 == ~t4_pc~0); 424305#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 424306#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 423956#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423957#L881 assume !(0 != activate_threads_~tmp___3~0#1); 424078#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 424079#L429 assume !(1 == ~t5_pc~0); 423895#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 423896#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 424104#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 424105#L889 assume !(0 != activate_threads_~tmp___4~0#1); 424310#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424061#L448 assume !(1 == ~t6_pc~0); 423975#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 423976#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 424276#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 424277#L897 assume !(0 != activate_threads_~tmp___5~0#1); 424468#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 424520#L762 assume !(1 == ~M_E~0); 424112#L762-2 assume !(1 == ~T1_E~0); 424113#L767-1 assume !(1 == ~T2_E~0); 424474#L772-1 assume !(1 == ~T3_E~0); 424342#L777-1 assume !(1 == ~T4_E~0); 424227#L782-1 assume !(1 == ~T5_E~0); 423924#L787-1 assume !(1 == ~T6_E~0); 423922#L792-1 assume !(1 == ~E_M~0); 423923#L797-1 assume !(1 == ~E_1~0); 423962#L802-1 assume !(1 == ~E_2~0); 424192#L807-1 assume !(1 == ~E_3~0); 424193#L812-1 assume !(1 == ~E_4~0); 424438#L817-1 assume !(1 == ~E_5~0); 424249#L822-1 assume !(1 == ~E_6~0); 424250#L827-1 assume { :end_inline_reset_delta_events } true; 424447#L1053-2 [2024-11-13 15:45:33,309 INFO L747 eck$LassoCheckResult]: Loop: 424447#L1053-2 assume !false; 431499#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 431497#L659-1 assume !false; 431495#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431465#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 431458#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431456#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 431453#L570 assume !(0 != eval_~tmp~0#1); 431454#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 432127#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 432125#L684-3 assume !(0 == ~M_E~0); 432123#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 432121#L689-3 assume !(0 == ~T2_E~0); 432119#L694-3 assume !(0 == ~T3_E~0); 432117#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 432115#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 432111#L709-3 assume !(0 == ~T6_E~0); 432109#L714-3 assume !(0 == ~E_M~0); 432107#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 432105#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 432102#L729-3 assume !(0 == ~E_3~0); 432100#L734-3 assume !(0 == ~E_4~0); 432098#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 432096#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 432094#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 432092#L334-24 assume !(1 == ~m_pc~0); 432090#L334-26 is_master_triggered_~__retres1~0#1 := 0; 432087#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 432086#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 432085#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 432081#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 432079#L353-24 assume !(1 == ~t1_pc~0); 432077#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 432076#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 432073#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 432072#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 432071#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 432070#L372-24 assume 1 == ~t2_pc~0; 432066#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 432064#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432062#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 432061#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 432058#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 432057#L391-24 assume !(1 == ~t3_pc~0); 432056#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 432053#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432049#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 432045#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 432041#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 432037#L410-24 assume !(1 == ~t4_pc~0); 432035#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 432033#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 432032#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 432024#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 432022#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 430781#L429-24 assume 1 == ~t5_pc~0; 430779#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 430780#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 430783#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 430768#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 430766#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 430764#L448-24 assume !(1 == ~t6_pc~0); 430762#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 430760#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430758#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 430756#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 430754#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 430752#L762-3 assume !(1 == ~M_E~0); 428542#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 430749#L767-3 assume !(1 == ~T2_E~0); 430748#L772-3 assume !(1 == ~T3_E~0); 430747#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 430739#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 430737#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 430735#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 430732#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 430728#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 430724#L807-3 assume !(1 == ~E_3~0); 430721#L812-3 assume !(1 == ~E_4~0); 430718#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 430716#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 430713#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 430417#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 430408#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 430276#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 424677#L1072 assume !(0 == start_simulation_~tmp~3#1); 424678#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431608#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 431606#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431604#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 431602#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 431600#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 431598#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 431594#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 424447#L1053-2 [2024-11-13 15:45:33,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:33,310 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2024-11-13 15:45:33,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:33,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80330632] [2024-11-13 15:45:33,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:33,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:33,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:33,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:33,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:33,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:33,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:33,349 INFO L85 PathProgramCache]: Analyzing trace with hash -1994539908, now seen corresponding path program 1 times [2024-11-13 15:45:33,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:33,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521105835] [2024-11-13 15:45:33,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:33,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:33,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:33,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:33,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:33,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521105835] [2024-11-13 15:45:33,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521105835] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:33,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:33,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:33,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849508256] [2024-11-13 15:45:33,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:33,422 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:33,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:33,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:33,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:33,423 INFO L87 Difference]: Start difference. First operand 21594 states and 30199 transitions. cyclomatic complexity: 8621 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:33,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:33,584 INFO L93 Difference]: Finished difference Result 21866 states and 30471 transitions. [2024-11-13 15:45:33,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21866 states and 30471 transitions. [2024-11-13 15:45:33,670 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21616 [2024-11-13 15:45:33,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21866 states to 21866 states and 30471 transitions. [2024-11-13 15:45:33,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21866 [2024-11-13 15:45:33,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21866 [2024-11-13 15:45:33,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21866 states and 30471 transitions. [2024-11-13 15:45:33,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:33,907 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21866 states and 30471 transitions. [2024-11-13 15:45:33,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21866 states and 30471 transitions. [2024-11-13 15:45:34,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21866 to 21738. [2024-11-13 15:45:34,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21738 states, 21738 states have (on average 1.3958505842303799) internal successors, (30343), 21737 states have internal predecessors, (30343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:34,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21738 states to 21738 states and 30343 transitions. [2024-11-13 15:45:34,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21738 states and 30343 transitions. [2024-11-13 15:45:34,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:34,257 INFO L424 stractBuchiCegarLoop]: Abstraction has 21738 states and 30343 transitions. [2024-11-13 15:45:34,257 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 15:45:34,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21738 states and 30343 transitions. [2024-11-13 15:45:34,337 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21488 [2024-11-13 15:45:34,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:34,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:34,339 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:34,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:34,339 INFO L745 eck$LassoCheckResult]: Stem: 467629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 467630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 467776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 467777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 467411#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 467412#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467772#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 467773#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 467691#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 467469#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 467470#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 467391#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 467392#L684 assume !(0 == ~M_E~0); 467913#L684-2 assume !(0 == ~T1_E~0); 467727#L689-1 assume !(0 == ~T2_E~0); 467728#L694-1 assume !(0 == ~T3_E~0); 467725#L699-1 assume !(0 == ~T4_E~0); 467726#L704-1 assume !(0 == ~T5_E~0); 467677#L709-1 assume !(0 == ~T6_E~0); 467607#L714-1 assume !(0 == ~E_M~0); 467608#L719-1 assume !(0 == ~E_1~0); 467875#L724-1 assume !(0 == ~E_2~0); 467357#L729-1 assume !(0 == ~E_3~0); 467358#L734-1 assume !(0 == ~E_4~0); 467945#L739-1 assume !(0 == ~E_5~0); 467566#L744-1 assume !(0 == ~E_6~0); 467567#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467314#L334 assume !(1 == ~m_pc~0); 467315#L334-2 is_master_triggered_~__retres1~0#1 := 0; 467666#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467569#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 467535#L849 assume !(0 != activate_threads_~tmp~1#1); 467536#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467465#L353 assume !(1 == ~t1_pc~0); 467466#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 467780#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467329#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 467330#L857 assume !(0 != activate_threads_~tmp___0~0#1); 467413#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 467414#L372 assume !(1 == ~t2_pc~0); 467524#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467523#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467660#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 467781#L865 assume !(0 != activate_threads_~tmp___1~0#1); 467303#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 467304#L391 assume !(1 == ~t3_pc~0); 467226#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 467227#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467253#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467254#L873 assume !(0 != activate_threads_~tmp___2~0#1); 467542#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 467543#L410 assume !(1 == ~t4_pc~0); 467798#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 467799#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 467427#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 467428#L881 assume !(0 != activate_threads_~tmp___3~0#1); 467552#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467553#L429 assume !(1 == ~t5_pc~0); 467363#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 467364#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 467578#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467579#L889 assume !(0 != activate_threads_~tmp___4~0#1); 467805#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 467534#L448 assume !(1 == ~t6_pc~0); 467449#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 467450#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467764#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 467765#L897 assume !(0 != activate_threads_~tmp___5~0#1); 467976#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 468032#L762 assume !(1 == ~M_E~0); 467585#L762-2 assume !(1 == ~T1_E~0); 467586#L767-1 assume !(1 == ~T2_E~0); 467982#L772-1 assume !(1 == ~T3_E~0); 467836#L777-1 assume !(1 == ~T4_E~0); 467709#L782-1 assume !(1 == ~T5_E~0); 467395#L787-1 assume !(1 == ~T6_E~0); 467393#L792-1 assume !(1 == ~E_M~0); 467394#L797-1 assume !(1 == ~E_1~0); 467433#L802-1 assume !(1 == ~E_2~0); 467670#L807-1 assume !(1 == ~E_3~0); 467671#L812-1 assume !(1 == ~E_4~0); 467941#L817-1 assume !(1 == ~E_5~0); 467729#L822-1 assume !(1 == ~E_6~0); 467730#L827-1 assume { :end_inline_reset_delta_events } true; 467952#L1053-2 [2024-11-13 15:45:34,340 INFO L747 eck$LassoCheckResult]: Loop: 467952#L1053-2 assume !false; 471859#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 471858#L659-1 assume !false; 471857#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 471855#L518 assume !(0 == ~m_st~0); 471856#L522 assume !(0 == ~t1_st~0); 471851#L526 assume !(0 == ~t2_st~0); 471852#L530 assume !(0 == ~t3_st~0); 471854#L534 assume !(0 == ~t4_st~0); 471849#L538 assume !(0 == ~t5_st~0); 471850#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 471853#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 472084#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 472082#L570 assume !(0 != eval_~tmp~0#1); 472080#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 472078#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 472076#L684-3 assume !(0 == ~M_E~0); 472074#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 472071#L689-3 assume !(0 == ~T2_E~0); 472069#L694-3 assume !(0 == ~T3_E~0); 472067#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 472065#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 472063#L709-3 assume !(0 == ~T6_E~0); 472061#L714-3 assume !(0 == ~E_M~0); 472059#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 472057#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 472055#L729-3 assume !(0 == ~E_3~0); 472053#L734-3 assume !(0 == ~E_4~0); 472051#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 472049#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 472046#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 472044#L334-24 assume !(1 == ~m_pc~0); 472042#L334-26 is_master_triggered_~__retres1~0#1 := 0; 472039#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 472037#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 472035#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 472033#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 472031#L353-24 assume !(1 == ~t1_pc~0); 472029#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 472027#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472025#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472023#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 472021#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 472019#L372-24 assume !(1 == ~t2_pc~0); 472017#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 472014#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 472012#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 472008#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 472006#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472004#L391-24 assume !(1 == ~t3_pc~0); 472002#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 471999#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 471997#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 471995#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 471993#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 471991#L410-24 assume !(1 == ~t4_pc~0); 471989#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 471987#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 471985#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 471984#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 471983#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 471982#L429-24 assume 1 == ~t5_pc~0; 471981#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 471980#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471978#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 471974#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 471972#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 471969#L448-24 assume !(1 == ~t6_pc~0); 471967#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 471965#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 471963#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 471961#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 471959#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471957#L762-3 assume !(1 == ~M_E~0); 471953#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 471951#L767-3 assume !(1 == ~T2_E~0); 471949#L772-3 assume !(1 == ~T3_E~0); 471947#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 471945#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 471942#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 471940#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 471938#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 471936#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471934#L807-3 assume !(1 == ~E_3~0); 471932#L812-3 assume !(1 == ~E_4~0); 471930#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 471928#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 471926#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 471921#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 471914#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 471912#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 471910#L1072 assume !(0 == start_simulation_~tmp~3#1); 471907#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 471887#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 471884#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 471882#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 471880#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 471876#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 471874#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 471872#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 467952#L1053-2 [2024-11-13 15:45:34,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:34,341 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2024-11-13 15:45:34,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:34,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664465968] [2024-11-13 15:45:34,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:34,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:34,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:34,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:34,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:34,394 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:34,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:34,395 INFO L85 PathProgramCache]: Analyzing trace with hash -2077228660, now seen corresponding path program 1 times [2024-11-13 15:45:34,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:34,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690571995] [2024-11-13 15:45:34,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:34,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:34,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:34,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:34,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:34,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690571995] [2024-11-13 15:45:34,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690571995] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:34,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:34,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:34,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715361799] [2024-11-13 15:45:34,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:34,530 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:34,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:34,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:34,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:34,531 INFO L87 Difference]: Start difference. First operand 21738 states and 30343 transitions. cyclomatic complexity: 8621 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:34,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:34,868 INFO L93 Difference]: Finished difference Result 22629 states and 31234 transitions. [2024-11-13 15:45:34,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22629 states and 31234 transitions. [2024-11-13 15:45:34,982 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22376 [2024-11-13 15:45:35,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22629 states to 22629 states and 31234 transitions. [2024-11-13 15:45:35,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22629 [2024-11-13 15:45:35,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22629 [2024-11-13 15:45:35,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22629 states and 31234 transitions. [2024-11-13 15:45:35,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:35,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22629 states and 31234 transitions. [2024-11-13 15:45:35,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22629 states and 31234 transitions. [2024-11-13 15:45:35,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22629 to 22629. [2024-11-13 15:45:35,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22629 states, 22629 states have (on average 1.380264262671793) internal successors, (31234), 22628 states have internal predecessors, (31234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:35,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22629 states to 22629 states and 31234 transitions. [2024-11-13 15:45:35,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22629 states and 31234 transitions. [2024-11-13 15:45:35,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:35,674 INFO L424 stractBuchiCegarLoop]: Abstraction has 22629 states and 31234 transitions. [2024-11-13 15:45:35,674 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 15:45:35,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22629 states and 31234 transitions. [2024-11-13 15:45:35,735 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22376 [2024-11-13 15:45:35,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:35,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:35,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:35,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:35,737 INFO L745 eck$LassoCheckResult]: Stem: 512007#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 512008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 512160#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512161#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 511787#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 511788#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 512156#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 512157#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 512077#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 511843#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 511844#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 511767#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 511768#L684 assume !(0 == ~M_E~0); 512305#L684-2 assume !(0 == ~T1_E~0); 512107#L689-1 assume !(0 == ~T2_E~0); 512108#L694-1 assume !(0 == ~T3_E~0); 512105#L699-1 assume !(0 == ~T4_E~0); 512106#L704-1 assume !(0 == ~T5_E~0); 512061#L709-1 assume !(0 == ~T6_E~0); 511981#L714-1 assume !(0 == ~E_M~0); 511982#L719-1 assume !(0 == ~E_1~0); 512261#L724-1 assume !(0 == ~E_2~0); 511736#L729-1 assume !(0 == ~E_3~0); 511737#L734-1 assume !(0 == ~E_4~0); 512342#L739-1 assume !(0 == ~E_5~0); 511940#L744-1 assume !(0 == ~E_6~0); 511941#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 511689#L334 assume !(1 == ~m_pc~0); 511690#L334-2 is_master_triggered_~__retres1~0#1 := 0; 512049#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 512490#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 511910#L849 assume !(0 != activate_threads_~tmp~1#1); 511911#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 511839#L353 assume !(1 == ~t1_pc~0); 511840#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512162#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 511705#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 511706#L857 assume !(0 != activate_threads_~tmp___0~0#1); 511789#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 511790#L372 assume !(1 == ~t2_pc~0); 511899#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 511898#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512042#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 512163#L865 assume !(0 != activate_threads_~tmp___1~0#1); 511677#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511678#L391 assume !(1 == ~t3_pc~0); 511601#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 511602#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 511627#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 511628#L873 assume !(0 != activate_threads_~tmp___2~0#1); 511917#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 511918#L410 assume !(1 == ~t4_pc~0); 512178#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 512179#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 511804#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 511805#L881 assume !(0 != activate_threads_~tmp___3~0#1); 511926#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 511927#L429 assume !(1 == ~t5_pc~0); 511742#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 511743#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 511954#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 511955#L889 assume !(0 != activate_threads_~tmp___4~0#1); 512185#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 511909#L448 assume !(1 == ~t6_pc~0); 511823#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 511824#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512146#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 512147#L897 assume !(0 != activate_threads_~tmp___5~0#1); 512382#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 512453#L762 assume !(1 == ~M_E~0); 511962#L762-2 assume !(1 == ~T1_E~0); 511963#L767-1 assume !(1 == ~T2_E~0); 512391#L772-1 assume !(1 == ~T3_E~0); 512222#L777-1 assume !(1 == ~T4_E~0); 512093#L782-1 assume !(1 == ~T5_E~0); 511771#L787-1 assume !(1 == ~T6_E~0); 511769#L792-1 assume !(1 == ~E_M~0); 511770#L797-1 assume !(1 == ~E_1~0); 511810#L802-1 assume !(1 == ~E_2~0); 512053#L807-1 assume !(1 == ~E_3~0); 512054#L812-1 assume !(1 == ~E_4~0); 512338#L817-1 assume !(1 == ~E_5~0); 512111#L822-1 assume !(1 == ~E_6~0); 512112#L827-1 assume { :end_inline_reset_delta_events } true; 512352#L1053-2 [2024-11-13 15:45:35,738 INFO L747 eck$LassoCheckResult]: Loop: 512352#L1053-2 assume !false; 517989#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 517988#L659-1 assume !false; 517987#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 517610#L518 assume !(0 == ~m_st~0); 517611#L522 assume !(0 == ~t1_st~0); 517606#L526 assume !(0 == ~t2_st~0); 517607#L530 assume !(0 == ~t3_st~0); 517609#L534 assume !(0 == ~t4_st~0); 517604#L538 assume !(0 == ~t5_st~0); 517605#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 517608#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 514931#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 514932#L570 assume !(0 != eval_~tmp~0#1); 518894#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 518884#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 518875#L684-3 assume !(0 == ~M_E~0); 518869#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 518866#L689-3 assume !(0 == ~T2_E~0); 518837#L694-3 assume !(0 == ~T3_E~0); 518830#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 518824#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 518819#L709-3 assume !(0 == ~T6_E~0); 518814#L714-3 assume !(0 == ~E_M~0); 518799#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 518793#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 518787#L729-3 assume !(0 == ~E_3~0); 518782#L734-3 assume !(0 == ~E_4~0); 518778#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 518773#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 518768#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 518764#L334-24 assume 1 == ~m_pc~0; 518759#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 518754#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518749#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 518744#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 518739#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 518735#L353-24 assume !(1 == ~t1_pc~0); 518730#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 518724#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 518717#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 518710#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 518703#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 518696#L372-24 assume !(1 == ~t2_pc~0); 518690#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 518682#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 518677#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 518671#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 518666#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518658#L391-24 assume !(1 == ~t3_pc~0); 518652#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 518647#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 518639#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 518634#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 518628#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518622#L410-24 assume !(1 == ~t4_pc~0); 518616#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 518610#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 518605#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 518348#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 518347#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 518093#L429-24 assume 1 == ~t5_pc~0; 518091#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 518092#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 518098#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 518082#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 518080#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 518076#L448-24 assume !(1 == ~t6_pc~0); 518074#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 518072#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 518070#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 518067#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 518065#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 518063#L762-3 assume !(1 == ~M_E~0); 518059#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 518057#L767-3 assume !(1 == ~T2_E~0); 518055#L772-3 assume !(1 == ~T3_E~0); 518053#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 518051#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 518048#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 518046#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 518044#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 518042#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 518040#L807-3 assume !(1 == ~E_3~0); 518038#L812-3 assume !(1 == ~E_4~0); 518036#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 518034#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 518032#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 518027#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 518020#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 518018#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 518016#L1072 assume !(0 == start_simulation_~tmp~3#1); 518014#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 518006#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 518005#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 518004#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 518003#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 518001#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517998#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 517996#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 512352#L1053-2 [2024-11-13 15:45:35,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:35,738 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2024-11-13 15:45:35,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:35,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954426728] [2024-11-13 15:45:35,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:35,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:35,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:35,753 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:35,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:35,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:35,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:35,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1080109771, now seen corresponding path program 1 times [2024-11-13 15:45:35,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:35,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746026398] [2024-11-13 15:45:35,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:35,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:35,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:35,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:35,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:35,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746026398] [2024-11-13 15:45:35,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746026398] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:35,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:35,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:35,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778785066] [2024-11-13 15:45:35,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:35,882 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:35,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:35,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:35,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:35,884 INFO L87 Difference]: Start difference. First operand 22629 states and 31234 transitions. cyclomatic complexity: 8621 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:36,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:36,162 INFO L93 Difference]: Finished difference Result 23109 states and 31577 transitions. [2024-11-13 15:45:36,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23109 states and 31577 transitions. [2024-11-13 15:45:36,244 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22856 [2024-11-13 15:45:36,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23109 states to 23109 states and 31577 transitions. [2024-11-13 15:45:36,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23109 [2024-11-13 15:45:36,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23109 [2024-11-13 15:45:36,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23109 states and 31577 transitions. [2024-11-13 15:45:36,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:36,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23109 states and 31577 transitions. [2024-11-13 15:45:36,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23109 states and 31577 transitions. [2024-11-13 15:45:36,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23109 to 23109. [2024-11-13 15:45:36,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23109 states, 23109 states have (on average 1.3664373187935437) internal successors, (31577), 23108 states have internal predecessors, (31577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:36,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23109 states to 23109 states and 31577 transitions. [2024-11-13 15:45:36,832 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23109 states and 31577 transitions. [2024-11-13 15:45:36,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:36,833 INFO L424 stractBuchiCegarLoop]: Abstraction has 23109 states and 31577 transitions. [2024-11-13 15:45:36,833 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 15:45:36,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23109 states and 31577 transitions. [2024-11-13 15:45:36,892 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22856 [2024-11-13 15:45:36,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:36,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:36,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:36,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:36,894 INFO L745 eck$LassoCheckResult]: Stem: 557742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 557743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 557889#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 557890#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 557524#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 557525#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 557887#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 557888#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 557810#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557581#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 557582#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557505#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 557506#L684 assume !(0 == ~M_E~0); 558023#L684-2 assume !(0 == ~T1_E~0); 557845#L689-1 assume !(0 == ~T2_E~0); 557846#L694-1 assume !(0 == ~T3_E~0); 557843#L699-1 assume !(0 == ~T4_E~0); 557844#L704-1 assume !(0 == ~T5_E~0); 557793#L709-1 assume !(0 == ~T6_E~0); 557722#L714-1 assume !(0 == ~E_M~0); 557723#L719-1 assume !(0 == ~E_1~0); 557985#L724-1 assume !(0 == ~E_2~0); 557479#L729-1 assume !(0 == ~E_3~0); 557480#L734-1 assume !(0 == ~E_4~0); 558061#L739-1 assume !(0 == ~E_5~0); 557681#L744-1 assume !(0 == ~E_6~0); 557682#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 557435#L334 assume !(1 == ~m_pc~0); 557436#L334-2 is_master_triggered_~__retres1~0#1 := 0; 557785#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 558181#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 557651#L849 assume !(0 != activate_threads_~tmp~1#1); 557652#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 557579#L353 assume !(1 == ~t1_pc~0); 557580#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 557893#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 557450#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 557451#L857 assume !(0 != activate_threads_~tmp___0~0#1); 557529#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 557530#L372 assume !(1 == ~t2_pc~0); 557639#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 557638#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 557777#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 557894#L865 assume !(0 != activate_threads_~tmp___1~0#1); 557424#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 557425#L391 assume !(1 == ~t3_pc~0); 557347#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 557348#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557373#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 557374#L873 assume !(0 != activate_threads_~tmp___2~0#1); 557658#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557659#L410 assume !(1 == ~t4_pc~0); 557908#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 557909#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557543#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 557544#L881 assume !(0 != activate_threads_~tmp___3~0#1); 557665#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 557666#L429 assume !(1 == ~t5_pc~0); 557485#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 557486#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 557696#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 557697#L889 assume !(0 != activate_threads_~tmp___4~0#1); 557914#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 557649#L448 assume !(1 == ~t6_pc~0); 557562#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 557563#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557878#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 557879#L897 assume !(0 != activate_threads_~tmp___5~0#1); 558095#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 558154#L762 assume !(1 == ~M_E~0); 557701#L762-2 assume !(1 == ~T1_E~0); 557702#L767-1 assume !(1 == ~T2_E~0); 558101#L772-1 assume !(1 == ~T3_E~0); 557949#L777-1 assume !(1 == ~T4_E~0); 557827#L782-1 assume !(1 == ~T5_E~0); 557511#L787-1 assume !(1 == ~T6_E~0); 557509#L792-1 assume !(1 == ~E_M~0); 557510#L797-1 assume !(1 == ~E_1~0); 557548#L802-1 assume !(1 == ~E_2~0); 557789#L807-1 assume !(1 == ~E_3~0); 557790#L812-1 assume !(1 == ~E_4~0); 558056#L817-1 assume !(1 == ~E_5~0); 557847#L822-1 assume !(1 == ~E_6~0); 557848#L827-1 assume { :end_inline_reset_delta_events } true; 558067#L1053-2 [2024-11-13 15:45:36,894 INFO L747 eck$LassoCheckResult]: Loop: 558067#L1053-2 assume !false; 577364#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 576334#L659-1 assume !false; 577361#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 577359#L518 assume !(0 == ~m_st~0); 577356#L522 assume !(0 == ~t1_st~0); 577354#L526 assume !(0 == ~t2_st~0); 577352#L530 assume !(0 == ~t3_st~0); 577349#L534 assume !(0 == ~t4_st~0); 577347#L538 assume !(0 == ~t5_st~0); 577344#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 577341#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 577339#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 577337#L570 assume !(0 != eval_~tmp~0#1); 577334#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 577332#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 577330#L684-3 assume !(0 == ~M_E~0); 577328#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 577326#L689-3 assume !(0 == ~T2_E~0); 577325#L694-3 assume !(0 == ~T3_E~0); 577324#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 577311#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 576942#L709-3 assume !(0 == ~T6_E~0); 576941#L714-3 assume !(0 == ~E_M~0); 576940#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 576939#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 576938#L729-3 assume !(0 == ~E_3~0); 576937#L734-3 assume !(0 == ~E_4~0); 576936#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 576934#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 576933#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 576932#L334-24 assume !(1 == ~m_pc~0); 576930#L334-26 is_master_triggered_~__retres1~0#1 := 0; 576928#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 576926#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 576925#L849-24 assume !(0 != activate_threads_~tmp~1#1); 576923#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 576922#L353-24 assume !(1 == ~t1_pc~0); 576921#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 576920#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 576918#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 576916#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 576915#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 576914#L372-24 assume 1 == ~t2_pc~0; 576912#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 576910#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 576907#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 576905#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 576903#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 576900#L391-24 assume !(1 == ~t3_pc~0); 576898#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 576896#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 576894#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 576892#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 576890#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 576888#L410-24 assume !(1 == ~t4_pc~0); 576886#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 576884#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 576881#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 576879#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 576877#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 576875#L429-24 assume 1 == ~t5_pc~0; 576872#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 576869#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 576867#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 576863#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 576861#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 576859#L448-24 assume !(1 == ~t6_pc~0); 576857#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 576855#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 576853#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 576852#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 576850#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 576848#L762-3 assume !(1 == ~M_E~0); 576842#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 576840#L767-3 assume !(1 == ~T2_E~0); 576838#L772-3 assume !(1 == ~T3_E~0); 576836#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 576833#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 576831#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 576829#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 576826#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 576824#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 576712#L807-3 assume !(1 == ~E_3~0); 575929#L812-3 assume !(1 == ~E_4~0); 575926#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 575924#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 575922#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 557750#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 557384#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 557861#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 557862#L1072 assume !(0 == start_simulation_~tmp~3#1); 558143#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 577377#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 577376#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 577375#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 577373#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 577371#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 577370#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 577369#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 558067#L1053-2 [2024-11-13 15:45:36,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:36,895 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2024-11-13 15:45:36,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:36,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368673633] [2024-11-13 15:45:36,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:36,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:36,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:36,906 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:36,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:36,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:36,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:36,924 INFO L85 PathProgramCache]: Analyzing trace with hash 851991247, now seen corresponding path program 1 times [2024-11-13 15:45:36,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:36,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55033047] [2024-11-13 15:45:36,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:36,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:36,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:36,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:36,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:36,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55033047] [2024-11-13 15:45:36,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55033047] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:36,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:36,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:36,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900062047] [2024-11-13 15:45:36,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:36,974 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:36,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:36,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:36,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:36,975 INFO L87 Difference]: Start difference. First operand 23109 states and 31577 transitions. cyclomatic complexity: 8484 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:37,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:37,129 INFO L93 Difference]: Finished difference Result 43293 states and 58477 transitions. [2024-11-13 15:45:37,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43293 states and 58477 transitions. [2024-11-13 15:45:37,295 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42880 [2024-11-13 15:45:37,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43293 states to 43293 states and 58477 transitions. [2024-11-13 15:45:37,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43293 [2024-11-13 15:45:37,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43293 [2024-11-13 15:45:37,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43293 states and 58477 transitions. [2024-11-13 15:45:37,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:37,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43293 states and 58477 transitions. [2024-11-13 15:45:37,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43293 states and 58477 transitions. [2024-11-13 15:45:38,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43293 to 41053. [2024-11-13 15:45:38,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41053 states, 41053 states have (on average 1.354663483789248) internal successors, (55613), 41052 states have internal predecessors, (55613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:38,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41053 states to 41053 states and 55613 transitions. [2024-11-13 15:45:38,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41053 states and 55613 transitions. [2024-11-13 15:45:38,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:45:38,210 INFO L424 stractBuchiCegarLoop]: Abstraction has 41053 states and 55613 transitions. [2024-11-13 15:45:38,210 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 15:45:38,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41053 states and 55613 transitions. [2024-11-13 15:45:38,364 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40640 [2024-11-13 15:45:38,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:38,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:38,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:38,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:38,368 INFO L745 eck$LassoCheckResult]: Stem: 624160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 624161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 624309#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 624310#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 623935#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 623936#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 624305#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 624306#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 624224#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 623993#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 623994#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 623915#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 623916#L684 assume !(0 == ~M_E~0); 624445#L684-2 assume !(0 == ~T1_E~0); 624258#L689-1 assume !(0 == ~T2_E~0); 624259#L694-1 assume !(0 == ~T3_E~0); 624256#L699-1 assume !(0 == ~T4_E~0); 624257#L704-1 assume !(0 == ~T5_E~0); 624209#L709-1 assume !(0 == ~T6_E~0); 624135#L714-1 assume !(0 == ~E_M~0); 624136#L719-1 assume !(0 == ~E_1~0); 624408#L724-1 assume !(0 == ~E_2~0); 623885#L729-1 assume !(0 == ~E_3~0); 623886#L734-1 assume !(0 == ~E_4~0); 624490#L739-1 assume !(0 == ~E_5~0); 624093#L744-1 assume !(0 == ~E_6~0); 624094#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 623841#L334 assume !(1 == ~m_pc~0); 623842#L334-2 is_master_triggered_~__retres1~0#1 := 0; 624197#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 624617#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 624062#L849 assume !(0 != activate_threads_~tmp~1#1); 624063#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623989#L353 assume !(1 == ~t1_pc~0); 623990#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 624311#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 623856#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 623857#L857 assume !(0 != activate_threads_~tmp___0~0#1); 623937#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 623938#L372 assume !(1 == ~t2_pc~0); 624050#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 624049#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 624190#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 624312#L865 assume !(0 != activate_threads_~tmp___1~0#1); 623830#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 623831#L391 assume !(1 == ~t3_pc~0); 623755#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 623756#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 623780#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 623781#L873 assume !(0 != activate_threads_~tmp___2~0#1); 624069#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 624070#L410 assume !(1 == ~t4_pc~0); 624327#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 624328#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 623952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 623953#L881 assume !(0 != activate_threads_~tmp___3~0#1); 624078#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 624079#L429 assume !(1 == ~t5_pc~0); 623891#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 623892#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624108#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 624109#L889 assume !(0 != activate_threads_~tmp___4~0#1); 624333#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 624061#L448 assume !(1 == ~t6_pc~0); 623972#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 623973#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 624296#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 624297#L897 assume !(0 != activate_threads_~tmp___5~0#1); 624523#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 624582#L762 assume !(1 == ~M_E~0); 624114#L762-2 assume !(1 == ~T1_E~0); 624115#L767-1 assume !(1 == ~T2_E~0); 624529#L772-1 assume !(1 == ~T3_E~0); 624368#L777-1 assume !(1 == ~T4_E~0); 624240#L782-1 assume !(1 == ~T5_E~0); 623919#L787-1 assume !(1 == ~T6_E~0); 623917#L792-1 assume !(1 == ~E_M~0); 623918#L797-1 assume !(1 == ~E_1~0); 623959#L802-1 assume !(1 == ~E_2~0); 624201#L807-1 assume !(1 == ~E_3~0); 624202#L812-1 assume !(1 == ~E_4~0); 624487#L817-1 assume !(1 == ~E_5~0); 624262#L822-1 assume !(1 == ~E_6~0); 624263#L827-1 assume { :end_inline_reset_delta_events } true; 624496#L1053-2 [2024-11-13 15:45:38,368 INFO L747 eck$LassoCheckResult]: Loop: 624496#L1053-2 assume !false; 633598#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 633596#L659-1 assume !false; 633594#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 633592#L518 assume !(0 == ~m_st~0); 630334#L522 assume !(0 == ~t1_st~0); 630332#L526 assume !(0 == ~t2_st~0); 630330#L530 assume !(0 == ~t3_st~0); 630328#L534 assume !(0 == ~t4_st~0); 630326#L538 assume !(0 == ~t5_st~0); 630323#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 630321#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 630319#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 630315#L570 assume !(0 != eval_~tmp~0#1); 630313#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 630311#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 630308#L684-3 assume !(0 == ~M_E~0); 630306#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 630304#L689-3 assume !(0 == ~T2_E~0); 630303#L694-3 assume !(0 == ~T3_E~0); 630300#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 630298#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 630296#L709-3 assume !(0 == ~T6_E~0); 630294#L714-3 assume !(0 == ~E_M~0); 630292#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 630288#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 630286#L729-3 assume !(0 == ~E_3~0); 630284#L734-3 assume !(0 == ~E_4~0); 630282#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 630280#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 630278#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630276#L334-24 assume 1 == ~m_pc~0; 630273#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 630271#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630269#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 630266#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630264#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630263#L353-24 assume !(1 == ~t1_pc~0); 630259#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 630257#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630255#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 630253#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 630250#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630248#L372-24 assume !(1 == ~t2_pc~0); 630245#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 630242#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630240#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 630238#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 630236#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630232#L391-24 assume !(1 == ~t3_pc~0); 630230#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 630228#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630227#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630224#L873-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 630223#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 630222#L410-24 assume !(1 == ~t4_pc~0); 630219#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 630009#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630005#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630003#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 630001#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 629999#L429-24 assume 1 == ~t5_pc~0; 629997#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 629998#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633567#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 629989#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 629987#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 629984#L448-24 assume !(1 == ~t6_pc~0); 629982#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 629980#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 629978#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 629976#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 629974#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 629972#L762-3 assume !(1 == ~M_E~0); 629677#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 629970#L767-3 assume !(1 == ~T2_E~0); 629969#L772-3 assume !(1 == ~T3_E~0); 629966#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 629963#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 629958#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 629954#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 629950#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 629947#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 629942#L807-3 assume !(1 == ~E_3~0); 629938#L812-3 assume !(1 == ~E_4~0); 629933#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 629927#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 629922#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 629916#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 629912#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 629907#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 629899#L1072 assume !(0 == start_simulation_~tmp~3#1); 629900#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 633713#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 633711#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 633709#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 633707#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 633638#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 633631#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 633630#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 624496#L1053-2 [2024-11-13 15:45:38,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:38,369 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2024-11-13 15:45:38,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:38,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257569271] [2024-11-13 15:45:38,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:38,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:38,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:38,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:38,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:38,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:38,408 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:38,408 INFO L85 PathProgramCache]: Analyzing trace with hash 1640809549, now seen corresponding path program 1 times [2024-11-13 15:45:38,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:38,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166781904] [2024-11-13 15:45:38,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:38,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:38,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:38,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:38,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:38,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166781904] [2024-11-13 15:45:38,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166781904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:38,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:38,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:38,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034285255] [2024-11-13 15:45:38,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:38,504 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:38,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:38,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:38,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:38,505 INFO L87 Difference]: Start difference. First operand 41053 states and 55613 transitions. cyclomatic complexity: 14576 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:39,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:39,220 INFO L93 Difference]: Finished difference Result 41629 states and 55836 transitions. [2024-11-13 15:45:39,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41629 states and 55836 transitions. [2024-11-13 15:45:39,481 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41216 [2024-11-13 15:45:39,604 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41629 states to 41629 states and 55836 transitions. [2024-11-13 15:45:39,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41629 [2024-11-13 15:45:39,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41629 [2024-11-13 15:45:39,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41629 states and 55836 transitions. [2024-11-13 15:45:39,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:39,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41629 states and 55836 transitions. [2024-11-13 15:45:39,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41629 states and 55836 transitions. [2024-11-13 15:45:40,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41629 to 41629. [2024-11-13 15:45:40,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41629 states, 41629 states have (on average 1.3412765139686276) internal successors, (55836), 41628 states have internal predecessors, (55836), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:40,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41629 states to 41629 states and 55836 transitions. [2024-11-13 15:45:40,273 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41629 states and 55836 transitions. [2024-11-13 15:45:40,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:40,274 INFO L424 stractBuchiCegarLoop]: Abstraction has 41629 states and 55836 transitions. [2024-11-13 15:45:40,274 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 15:45:40,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41629 states and 55836 transitions. [2024-11-13 15:45:40,435 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41216 [2024-11-13 15:45:40,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:40,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:40,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:40,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:40,439 INFO L745 eck$LassoCheckResult]: Stem: 706839#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 706840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 706984#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 706985#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 706624#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 706625#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 706982#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 706983#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 706905#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 706681#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 706682#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 706605#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 706606#L684 assume !(0 == ~M_E~0); 707126#L684-2 assume !(0 == ~T1_E~0); 706939#L689-1 assume !(0 == ~T2_E~0); 706940#L694-1 assume !(0 == ~T3_E~0); 706937#L699-1 assume !(0 == ~T4_E~0); 706938#L704-1 assume !(0 == ~T5_E~0); 706889#L709-1 assume !(0 == ~T6_E~0); 706822#L714-1 assume !(0 == ~E_M~0); 706823#L719-1 assume !(0 == ~E_1~0); 707086#L724-1 assume !(0 == ~E_2~0); 706577#L729-1 assume !(0 == ~E_3~0); 706578#L734-1 assume !(0 == ~E_4~0); 707169#L739-1 assume !(0 == ~E_5~0); 706782#L744-1 assume !(0 == ~E_6~0); 706783#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 706532#L334 assume !(1 == ~m_pc~0); 706533#L334-2 is_master_triggered_~__retres1~0#1 := 0; 706880#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 707293#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 706750#L849 assume !(0 != activate_threads_~tmp~1#1); 706751#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 706679#L353 assume !(1 == ~t1_pc~0); 706680#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 706988#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 706548#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 706549#L857 assume !(0 != activate_threads_~tmp___0~0#1); 706629#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706630#L372 assume !(1 == ~t2_pc~0); 706737#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 706736#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 706874#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 706989#L865 assume !(0 != activate_threads_~tmp___1~0#1); 706521#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 706522#L391 assume !(1 == ~t3_pc~0); 706445#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 706446#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 706471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 706472#L873 assume !(0 != activate_threads_~tmp___2~0#1); 706757#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 706758#L410 assume !(1 == ~t4_pc~0); 707004#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 707005#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 706643#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 706644#L881 assume !(0 != activate_threads_~tmp___3~0#1); 706763#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 706764#L429 assume !(1 == ~t5_pc~0); 706583#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 706584#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 706796#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706797#L889 assume !(0 != activate_threads_~tmp___4~0#1); 707012#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 706747#L448 assume !(1 == ~t6_pc~0); 706662#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 706663#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 706971#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 706972#L897 assume !(0 != activate_threads_~tmp___5~0#1); 707200#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707256#L762 assume !(1 == ~M_E~0); 706801#L762-2 assume !(1 == ~T1_E~0); 706802#L767-1 assume !(1 == ~T2_E~0); 707207#L772-1 assume !(1 == ~T3_E~0); 707047#L777-1 assume !(1 == ~T4_E~0); 706921#L782-1 assume !(1 == ~T5_E~0); 706611#L787-1 assume !(1 == ~T6_E~0); 706609#L792-1 assume !(1 == ~E_M~0); 706610#L797-1 assume !(1 == ~E_1~0); 706648#L802-1 assume !(1 == ~E_2~0); 706884#L807-1 assume !(1 == ~E_3~0); 706885#L812-1 assume !(1 == ~E_4~0); 707162#L817-1 assume !(1 == ~E_5~0); 706941#L822-1 assume !(1 == ~E_6~0); 706942#L827-1 assume { :end_inline_reset_delta_events } true; 707177#L1053-2 [2024-11-13 15:45:40,439 INFO L747 eck$LassoCheckResult]: Loop: 707177#L1053-2 assume !false; 722990#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 722989#L659-1 assume !false; 722988#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 722985#L518 assume !(0 == ~m_st~0); 715272#L522 assume !(0 == ~t1_st~0); 715264#L526 assume !(0 == ~t2_st~0); 715254#L530 assume !(0 == ~t3_st~0); 715247#L534 assume !(0 == ~t4_st~0); 715241#L538 assume !(0 == ~t5_st~0); 715234#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 715228#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 715220#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 715213#L570 assume !(0 != eval_~tmp~0#1); 715206#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 715198#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 715190#L684-3 assume !(0 == ~M_E~0); 715183#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 715177#L689-3 assume !(0 == ~T2_E~0); 715171#L694-3 assume !(0 == ~T3_E~0); 715165#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 715159#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 715153#L709-3 assume !(0 == ~T6_E~0); 715147#L714-3 assume !(0 == ~E_M~0); 714797#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 714794#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 714792#L729-3 assume !(0 == ~E_3~0); 714790#L734-3 assume !(0 == ~E_4~0); 714787#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 714785#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 714783#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 714781#L334-24 assume 1 == ~m_pc~0; 714778#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 714775#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 714773#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 714771#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 714769#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 714767#L353-24 assume !(1 == ~t1_pc~0); 714765#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 714763#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714761#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 714759#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 714757#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714755#L372-24 assume 1 == ~t2_pc~0; 714752#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 714750#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714748#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 714746#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 714744#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 714738#L391-24 assume !(1 == ~t3_pc~0); 714736#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 714734#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 714730#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 714728#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 714726#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 714725#L410-24 assume !(1 == ~t4_pc~0); 714724#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 714614#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 714604#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 714426#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 714422#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 714420#L429-24 assume 1 == ~t5_pc~0; 714418#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 714419#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 714584#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 714408#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 714406#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 714369#L448-24 assume !(1 == ~t6_pc~0); 714360#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 714350#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 714344#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 714339#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 714334#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 714329#L762-3 assume !(1 == ~M_E~0); 713618#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 714298#L767-3 assume !(1 == ~T2_E~0); 714293#L772-3 assume !(1 == ~T3_E~0); 714286#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 714280#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 714275#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 714270#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 714266#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 714071#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 714067#L807-3 assume !(1 == ~E_3~0); 714065#L812-3 assume !(1 == ~E_4~0); 714062#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 714060#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 714058#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 714056#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 714054#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 714052#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 714049#L1072 assume !(0 == start_simulation_~tmp~3#1); 714050#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 722903#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 722901#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 722900#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 722898#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 722891#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 722892#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 732892#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 707177#L1053-2 [2024-11-13 15:45:40,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:40,440 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2024-11-13 15:45:40,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:40,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630063016] [2024-11-13 15:45:40,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:40,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:40,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:40,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:40,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:40,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:40,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:40,489 INFO L85 PathProgramCache]: Analyzing trace with hash 1047453838, now seen corresponding path program 1 times [2024-11-13 15:45:40,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:40,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428604431] [2024-11-13 15:45:40,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:40,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:40,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:40,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:40,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:40,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428604431] [2024-11-13 15:45:40,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428604431] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:40,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:40,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:40,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793419907] [2024-11-13 15:45:40,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:40,587 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:40,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:40,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:40,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:40,587 INFO L87 Difference]: Start difference. First operand 41629 states and 55836 transitions. cyclomatic complexity: 14223 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:41,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:41,267 INFO L93 Difference]: Finished difference Result 43264 states and 57471 transitions. [2024-11-13 15:45:41,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43264 states and 57471 transitions. [2024-11-13 15:45:41,443 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42848 [2024-11-13 15:45:41,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43264 states to 43264 states and 57471 transitions. [2024-11-13 15:45:41,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43264 [2024-11-13 15:45:41,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43264 [2024-11-13 15:45:41,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43264 states and 57471 transitions. [2024-11-13 15:45:41,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:41,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43264 states and 57471 transitions. [2024-11-13 15:45:41,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43264 states and 57471 transitions. [2024-11-13 15:45:41,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43264 to 43264. [2024-11-13 15:45:41,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43264 states, 43264 states have (on average 1.3283792529585798) internal successors, (57471), 43263 states have internal predecessors, (57471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:42,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43264 states to 43264 states and 57471 transitions. [2024-11-13 15:45:42,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43264 states and 57471 transitions. [2024-11-13 15:45:42,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:42,052 INFO L424 stractBuchiCegarLoop]: Abstraction has 43264 states and 57471 transitions. [2024-11-13 15:45:42,052 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 15:45:42,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43264 states and 57471 transitions. [2024-11-13 15:45:42,434 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42848 [2024-11-13 15:45:42,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:42,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:42,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:42,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:42,437 INFO L745 eck$LassoCheckResult]: Stem: 791745#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 791746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 791898#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 791899#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 791527#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 791528#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 791894#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 791895#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 791815#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 791586#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 791587#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 791507#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 791508#L684 assume !(0 == ~M_E~0); 792032#L684-2 assume !(0 == ~T1_E~0); 791848#L689-1 assume !(0 == ~T2_E~0); 791849#L694-1 assume !(0 == ~T3_E~0); 791846#L699-1 assume !(0 == ~T4_E~0); 791847#L704-1 assume !(0 == ~T5_E~0); 791800#L709-1 assume !(0 == ~T6_E~0); 791723#L714-1 assume !(0 == ~E_M~0); 791724#L719-1 assume !(0 == ~E_1~0); 791994#L724-1 assume !(0 == ~E_2~0); 791479#L729-1 assume !(0 == ~E_3~0); 791480#L734-1 assume !(0 == ~E_4~0); 792078#L739-1 assume !(0 == ~E_5~0); 791683#L744-1 assume !(0 == ~E_6~0); 791684#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 791435#L334 assume !(1 == ~m_pc~0); 791436#L334-2 is_master_triggered_~__retres1~0#1 := 0; 791788#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792190#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 791653#L849 assume !(0 != activate_threads_~tmp~1#1); 791654#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791582#L353 assume !(1 == ~t1_pc~0); 791583#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 791900#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 791450#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 791451#L857 assume !(0 != activate_threads_~tmp___0~0#1); 791529#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 791530#L372 assume !(1 == ~t2_pc~0); 791640#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 791665#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 791781#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 792187#L865 assume !(0 != activate_threads_~tmp___1~0#1); 791424#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 791425#L391 assume !(1 == ~t3_pc~0); 791346#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 791347#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 791373#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 791374#L873 assume !(0 != activate_threads_~tmp___2~0#1); 791660#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 791661#L410 assume !(1 == ~t4_pc~0); 791918#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 791919#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 791545#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 791546#L881 assume !(0 != activate_threads_~tmp___3~0#1); 791667#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 791668#L429 assume !(1 == ~t5_pc~0); 791485#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 791486#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 791697#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 791698#L889 assume !(0 != activate_threads_~tmp___4~0#1); 791924#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 791652#L448 assume !(1 == ~t6_pc~0); 791566#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 791567#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 791885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 791886#L897 assume !(0 != activate_threads_~tmp___5~0#1); 792107#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 792160#L762 assume !(1 == ~M_E~0); 791703#L762-2 assume !(1 == ~T1_E~0); 791704#L767-1 assume !(1 == ~T2_E~0); 792114#L772-1 assume !(1 == ~T3_E~0); 791959#L777-1 assume !(1 == ~T4_E~0); 791832#L782-1 assume !(1 == ~T5_E~0); 791511#L787-1 assume !(1 == ~T6_E~0); 791509#L792-1 assume !(1 == ~E_M~0); 791510#L797-1 assume !(1 == ~E_1~0); 791553#L802-1 assume !(1 == ~E_2~0); 791792#L807-1 assume !(1 == ~E_3~0); 791793#L812-1 assume !(1 == ~E_4~0); 792075#L817-1 assume !(1 == ~E_5~0); 791850#L822-1 assume !(1 == ~E_6~0); 791851#L827-1 assume { :end_inline_reset_delta_events } true; 792086#L1053-2 [2024-11-13 15:45:42,437 INFO L747 eck$LassoCheckResult]: Loop: 792086#L1053-2 assume !false; 799857#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 799855#L659-1 assume !false; 799854#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 799849#L518 assume !(0 == ~m_st~0); 799850#L522 assume !(0 == ~t1_st~0); 800338#L526 assume !(0 == ~t2_st~0); 800336#L530 assume !(0 == ~t3_st~0); 800334#L534 assume !(0 == ~t4_st~0); 800332#L538 assume !(0 == ~t5_st~0); 800328#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 800326#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 800324#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 800322#L570 assume !(0 != eval_~tmp~0#1); 800320#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 800318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 800316#L684-3 assume !(0 == ~M_E~0); 800313#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 800311#L689-3 assume !(0 == ~T2_E~0); 800309#L694-3 assume !(0 == ~T3_E~0); 800306#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 800304#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 800302#L709-3 assume !(0 == ~T6_E~0); 800300#L714-3 assume !(0 == ~E_M~0); 800298#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 800296#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 800294#L729-3 assume !(0 == ~E_3~0); 800292#L734-3 assume !(0 == ~E_4~0); 800289#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 800288#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 800286#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 800284#L334-24 assume 1 == ~m_pc~0; 800282#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 800280#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 800277#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 800274#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 800271#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 800269#L353-24 assume !(1 == ~t1_pc~0); 800267#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 800264#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 800262#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 800260#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 800259#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 800258#L372-24 assume 1 == ~t2_pc~0; 800255#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 800253#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 800252#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 800251#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 800248#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 800247#L391-24 assume !(1 == ~t3_pc~0); 800246#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 800245#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 800241#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 800239#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 800237#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 800235#L410-24 assume !(1 == ~t4_pc~0); 800230#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 800228#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 800226#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 800224#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 800222#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 800220#L429-24 assume !(1 == ~t5_pc~0); 800216#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 800214#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 800210#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 800208#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 800205#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 800203#L448-24 assume !(1 == ~t6_pc~0); 800200#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 800198#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 800196#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 800194#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 800192#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 800190#L762-3 assume !(1 == ~M_E~0); 798696#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 800187#L767-3 assume !(1 == ~T2_E~0); 800184#L772-3 assume !(1 == ~T3_E~0); 800182#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 800180#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 800178#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 800176#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 800174#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 800173#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 800169#L807-3 assume !(1 == ~E_3~0); 800167#L812-3 assume !(1 == ~E_4~0); 800165#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 800163#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 800160#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 800157#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 800155#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 800153#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 800151#L1072 assume !(0 == start_simulation_~tmp~3#1); 800148#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 800145#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 800143#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 800139#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 800137#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 800135#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 800134#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 800131#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 792086#L1053-2 [2024-11-13 15:45:42,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:42,438 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2024-11-13 15:45:42,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:42,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383620654] [2024-11-13 15:45:42,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:42,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:42,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:42,456 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:42,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:42,486 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:42,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:42,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1197380721, now seen corresponding path program 1 times [2024-11-13 15:45:42,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:42,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931155207] [2024-11-13 15:45:42,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:42,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:42,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:42,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:42,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:42,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931155207] [2024-11-13 15:45:42,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931155207] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:42,584 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:42,584 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:42,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387300760] [2024-11-13 15:45:42,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:42,585 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:42,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:42,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:42,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:42,586 INFO L87 Difference]: Start difference. First operand 43264 states and 57471 transitions. cyclomatic complexity: 14223 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:42,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:42,917 INFO L93 Difference]: Finished difference Result 43360 states and 57038 transitions. [2024-11-13 15:45:42,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43360 states and 57038 transitions. [2024-11-13 15:45:43,095 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42944 [2024-11-13 15:45:43,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43360 states to 43360 states and 57038 transitions. [2024-11-13 15:45:43,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43360 [2024-11-13 15:45:43,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43360 [2024-11-13 15:45:43,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43360 states and 57038 transitions. [2024-11-13 15:45:43,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:43,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43360 states and 57038 transitions. [2024-11-13 15:45:43,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43360 states and 57038 transitions. [2024-11-13 15:45:43,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43360 to 43360. [2024-11-13 15:45:43,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43360 states, 43360 states have (on average 1.3154520295202952) internal successors, (57038), 43359 states have internal predecessors, (57038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:44,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43360 states to 43360 states and 57038 transitions. [2024-11-13 15:45:44,039 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43360 states and 57038 transitions. [2024-11-13 15:45:44,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:44,044 INFO L424 stractBuchiCegarLoop]: Abstraction has 43360 states and 57038 transitions. [2024-11-13 15:45:44,044 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 15:45:44,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43360 states and 57038 transitions. [2024-11-13 15:45:44,173 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42944 [2024-11-13 15:45:44,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:44,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:44,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:44,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:44,176 INFO L745 eck$LassoCheckResult]: Stem: 878381#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 878382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 878537#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 878538#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 878160#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 878161#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 878533#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 878534#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 878448#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 878219#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 878220#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 878139#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 878140#L684 assume !(0 == ~M_E~0); 878692#L684-2 assume !(0 == ~T1_E~0); 878483#L689-1 assume !(0 == ~T2_E~0); 878484#L694-1 assume !(0 == ~T3_E~0); 878481#L699-1 assume !(0 == ~T4_E~0); 878482#L704-1 assume !(0 == ~T5_E~0); 878434#L709-1 assume !(0 == ~T6_E~0); 878358#L714-1 assume !(0 == ~E_M~0); 878359#L719-1 assume !(0 == ~E_1~0); 878647#L724-1 assume !(0 == ~E_2~0); 878110#L729-1 assume !(0 == ~E_3~0); 878111#L734-1 assume !(0 == ~E_4~0); 878734#L739-1 assume !(0 == ~E_5~0); 878316#L744-1 assume !(0 == ~E_6~0); 878317#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 878065#L334 assume !(1 == ~m_pc~0); 878066#L334-2 is_master_triggered_~__retres1~0#1 := 0; 878422#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 878871#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 878286#L849 assume !(0 != activate_threads_~tmp~1#1); 878287#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 878215#L353 assume !(1 == ~t1_pc~0); 878216#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 878540#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 878080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 878081#L857 assume !(0 != activate_threads_~tmp___0~0#1); 878162#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 878163#L372 assume !(1 == ~t2_pc~0); 878273#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 878298#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 878416#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 878868#L865 assume !(0 != activate_threads_~tmp___1~0#1); 878054#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 878055#L391 assume !(1 == ~t3_pc~0); 877978#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 877979#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 878003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 878004#L873 assume !(0 != activate_threads_~tmp___2~0#1); 878293#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 878294#L410 assume !(1 == ~t4_pc~0); 878559#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 878560#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 878178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 878179#L881 assume !(0 != activate_threads_~tmp___3~0#1); 878302#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 878303#L429 assume !(1 == ~t5_pc~0); 878116#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 878117#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 878331#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 878332#L889 assume !(0 != activate_threads_~tmp___4~0#1); 878566#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 878285#L448 assume !(1 == ~t6_pc~0); 878199#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 878200#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 878523#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 878524#L897 assume !(0 != activate_threads_~tmp___5~0#1); 878771#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 878839#L762 assume !(1 == ~M_E~0); 878337#L762-2 assume !(1 == ~T1_E~0); 878338#L767-1 assume !(1 == ~T2_E~0); 878777#L772-1 assume !(1 == ~T3_E~0); 878606#L777-1 assume !(1 == ~T4_E~0); 878467#L782-1 assume !(1 == ~T5_E~0); 878143#L787-1 assume !(1 == ~T6_E~0); 878141#L792-1 assume !(1 == ~E_M~0); 878142#L797-1 assume !(1 == ~E_1~0); 878186#L802-1 assume !(1 == ~E_2~0); 878426#L807-1 assume !(1 == ~E_3~0); 878427#L812-1 assume !(1 == ~E_4~0); 878730#L817-1 assume !(1 == ~E_5~0); 878487#L822-1 assume !(1 == ~E_6~0); 878488#L827-1 assume { :end_inline_reset_delta_events } true; 878741#L1053-2 [2024-11-13 15:45:44,176 INFO L747 eck$LassoCheckResult]: Loop: 878741#L1053-2 assume !false; 893231#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 893230#L659-1 assume !false; 893228#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 893226#L518 assume !(0 == ~m_st~0); 893227#L522 assume !(0 == ~t1_st~0); 893601#L526 assume !(0 == ~t2_st~0); 893598#L530 assume !(0 == ~t3_st~0); 893596#L534 assume !(0 == ~t4_st~0); 893594#L538 assume !(0 == ~t5_st~0); 893592#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 893591#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 893589#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 893587#L570 assume !(0 != eval_~tmp~0#1); 893586#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 893585#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 893583#L684-3 assume !(0 == ~M_E~0); 893581#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 893579#L689-3 assume !(0 == ~T2_E~0); 893577#L694-3 assume !(0 == ~T3_E~0); 893575#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 893573#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 893571#L709-3 assume !(0 == ~T6_E~0); 893569#L714-3 assume !(0 == ~E_M~0); 893567#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 893565#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 893563#L729-3 assume !(0 == ~E_3~0); 893561#L734-3 assume !(0 == ~E_4~0); 893559#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 893556#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 893554#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 893552#L334-24 assume 1 == ~m_pc~0; 893548#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 893547#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 893545#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 893541#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 893539#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 893537#L353-24 assume !(1 == ~t1_pc~0); 893532#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 893530#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 893528#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 893526#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 893524#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 893522#L372-24 assume 1 == ~t2_pc~0; 893519#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 893517#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 893513#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 893511#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 893508#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893506#L391-24 assume !(1 == ~t3_pc~0); 893503#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 893501#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 893499#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 893497#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 893495#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 893493#L410-24 assume !(1 == ~t4_pc~0); 893491#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 893489#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 893487#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 893485#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 893483#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 893481#L429-24 assume !(1 == ~t5_pc~0); 893477#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 893475#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 893471#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 893469#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 893466#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 893464#L448-24 assume !(1 == ~t6_pc~0); 893461#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 893459#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 893457#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 893455#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 893453#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 893451#L762-3 assume !(1 == ~M_E~0); 893447#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 893445#L767-3 assume !(1 == ~T2_E~0); 893442#L772-3 assume !(1 == ~T3_E~0); 893440#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 893438#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 893436#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 893434#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 893432#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 893430#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893428#L807-3 assume !(1 == ~E_3~0); 893426#L812-3 assume !(1 == ~E_4~0); 893424#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 893422#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 893420#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 893417#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 893415#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 893414#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 893411#L1072 assume !(0 == start_simulation_~tmp~3#1); 893409#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 893407#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 893406#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 893404#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 893403#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 893402#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 893400#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 893399#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 878741#L1053-2 [2024-11-13 15:45:44,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:44,177 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 10 times [2024-11-13 15:45:44,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:44,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392125435] [2024-11-13 15:45:44,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:44,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:44,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:44,191 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:44,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:44,216 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:44,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:44,216 INFO L85 PathProgramCache]: Analyzing trace with hash -773733999, now seen corresponding path program 1 times [2024-11-13 15:45:44,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:44,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008865861] [2024-11-13 15:45:44,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:44,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:44,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:44,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:44,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:44,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008865861] [2024-11-13 15:45:44,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008865861] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:44,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:44,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 15:45:44,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072097919] [2024-11-13 15:45:44,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:44,303 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:45:44,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:44,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 15:45:44,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 15:45:44,304 INFO L87 Difference]: Start difference. First operand 43360 states and 57038 transitions. cyclomatic complexity: 13694 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:44,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:44,659 INFO L93 Difference]: Finished difference Result 44272 states and 57693 transitions. [2024-11-13 15:45:44,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44272 states and 57693 transitions. [2024-11-13 15:45:44,819 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43856 [2024-11-13 15:45:44,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44272 states to 44272 states and 57693 transitions. [2024-11-13 15:45:44,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44272 [2024-11-13 15:45:44,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44272 [2024-11-13 15:45:44,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44272 states and 57693 transitions. [2024-11-13 15:45:44,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 15:45:44,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44272 states and 57693 transitions. [2024-11-13 15:45:44,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44272 states and 57693 transitions. [2024-11-13 15:45:45,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44272 to 44272. [2024-11-13 15:45:45,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44272 states, 44272 states have (on average 1.3031487170220455) internal successors, (57693), 44271 states have internal predecessors, (57693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:45,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44272 states to 44272 states and 57693 transitions. [2024-11-13 15:45:45,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44272 states and 57693 transitions. [2024-11-13 15:45:45,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 15:45:45,782 INFO L424 stractBuchiCegarLoop]: Abstraction has 44272 states and 57693 transitions. [2024-11-13 15:45:45,782 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 15:45:45,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44272 states and 57693 transitions. [2024-11-13 15:45:45,932 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43856 [2024-11-13 15:45:45,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:45:45,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:45:45,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:45,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:45:45,934 INFO L745 eck$LassoCheckResult]: Stem: 966021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 966022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 966171#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 966172#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 965796#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 965797#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 966169#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 966170#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 966092#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 965856#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 965857#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 965777#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 965778#L684 assume !(0 == ~M_E~0); 966306#L684-2 assume !(0 == ~T1_E~0); 966128#L689-1 assume !(0 == ~T2_E~0); 966129#L694-1 assume !(0 == ~T3_E~0); 966126#L699-1 assume !(0 == ~T4_E~0); 966127#L704-1 assume !(0 == ~T5_E~0); 966075#L709-1 assume !(0 == ~T6_E~0); 965999#L714-1 assume !(0 == ~E_M~0); 966000#L719-1 assume !(0 == ~E_1~0); 966270#L724-1 assume !(0 == ~E_2~0); 965751#L729-1 assume !(0 == ~E_3~0); 965752#L734-1 assume !(0 == ~E_4~0); 966349#L739-1 assume !(0 == ~E_5~0); 965961#L744-1 assume !(0 == ~E_6~0); 965962#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 965706#L334 assume !(1 == ~m_pc~0); 965707#L334-2 is_master_triggered_~__retres1~0#1 := 0; 966066#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 966462#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 965930#L849 assume !(0 != activate_threads_~tmp~1#1); 965931#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 965854#L353 assume !(1 == ~t1_pc~0); 965855#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 966175#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 965721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 965722#L857 assume !(0 != activate_threads_~tmp___0~0#1); 965801#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 965802#L372 assume !(1 == ~t2_pc~0); 965918#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 965941#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 966059#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 966459#L865 assume !(0 != activate_threads_~tmp___1~0#1); 965695#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 965696#L391 assume !(1 == ~t3_pc~0); 965618#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 965619#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 965644#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 965645#L873 assume !(0 != activate_threads_~tmp___2~0#1); 965937#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 965938#L410 assume !(1 == ~t4_pc~0); 966190#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 966191#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 965815#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 965816#L881 assume !(0 != activate_threads_~tmp___3~0#1); 965943#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 965944#L429 assume !(1 == ~t5_pc~0); 965757#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 965758#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965974#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 965975#L889 assume !(0 != activate_threads_~tmp___4~0#1); 966197#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965928#L448 assume !(1 == ~t6_pc~0); 965836#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 965837#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 966159#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 966160#L897 assume !(0 != activate_threads_~tmp___5~0#1); 966375#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 966435#L762 assume !(1 == ~M_E~0); 965979#L762-2 assume !(1 == ~T1_E~0); 965980#L767-1 assume !(1 == ~T2_E~0); 966382#L772-1 assume !(1 == ~T3_E~0); 966230#L777-1 assume !(1 == ~T4_E~0); 966110#L782-1 assume !(1 == ~T5_E~0); 965783#L787-1 assume !(1 == ~T6_E~0); 965781#L792-1 assume !(1 == ~E_M~0); 965782#L797-1 assume !(1 == ~E_1~0); 965821#L802-1 assume !(1 == ~E_2~0); 966070#L807-1 assume !(1 == ~E_3~0); 966071#L812-1 assume !(1 == ~E_4~0); 966342#L817-1 assume !(1 == ~E_5~0); 966130#L822-1 assume !(1 == ~E_6~0); 966131#L827-1 assume { :end_inline_reset_delta_events } true; 966354#L1053-2 [2024-11-13 15:45:45,935 INFO L747 eck$LassoCheckResult]: Loop: 966354#L1053-2 assume !false; 979001#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 978999#L659-1 assume !false; 978996#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 978993#L518 assume !(0 == ~m_st~0); 978994#L522 assume !(0 == ~t1_st~0); 979299#L526 assume !(0 == ~t2_st~0); 979297#L530 assume !(0 == ~t3_st~0); 979295#L534 assume !(0 == ~t4_st~0); 979292#L538 assume !(0 == ~t5_st~0); 979289#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 979287#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 979285#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 979282#L570 assume !(0 != eval_~tmp~0#1); 979280#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 979278#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 979276#L684-3 assume !(0 == ~M_E~0); 979274#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 979272#L689-3 assume !(0 == ~T2_E~0); 979270#L694-3 assume !(0 == ~T3_E~0); 979268#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 979266#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 979264#L709-3 assume !(0 == ~T6_E~0); 979260#L714-3 assume !(0 == ~E_M~0); 979258#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 979256#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 979254#L729-3 assume !(0 == ~E_3~0); 979251#L734-3 assume !(0 == ~E_4~0); 979249#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 979247#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 979245#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 979243#L334-24 assume 1 == ~m_pc~0; 979240#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 979238#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 979236#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 979234#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 979233#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 979231#L353-24 assume !(1 == ~t1_pc~0); 979230#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 979229#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 979227#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 979226#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 979225#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 979224#L372-24 assume 1 == ~t2_pc~0; 979222#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 979223#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 979215#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 979211#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 979208#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 979206#L391-24 assume !(1 == ~t3_pc~0); 979204#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 979201#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 979199#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 979197#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 979195#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 979193#L410-24 assume !(1 == ~t4_pc~0); 979191#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 979189#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 979187#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 979185#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 979183#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 979181#L429-24 assume 1 == ~t5_pc~0; 979179#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 979180#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 979228#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 979168#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 979166#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 979164#L448-24 assume !(1 == ~t6_pc~0); 979162#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 979159#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 979157#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 979155#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 979153#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 979151#L762-3 assume !(1 == ~M_E~0); 979147#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 979145#L767-3 assume !(1 == ~T2_E~0); 979143#L772-3 assume !(1 == ~T3_E~0); 979140#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 979138#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 979136#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 979134#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 979132#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 979130#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 979128#L807-3 assume !(1 == ~E_3~0); 979126#L812-3 assume !(1 == ~E_4~0); 979124#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 979122#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 979120#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 979117#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 979115#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 979113#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 979111#L1072 assume !(0 == start_simulation_~tmp~3#1); 979109#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 979104#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 979102#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 979100#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 979098#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 979093#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 979091#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 979089#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 966354#L1053-2 [2024-11-13 15:45:45,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:45,936 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 11 times [2024-11-13 15:45:45,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:45,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539685857] [2024-11-13 15:45:45,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:45,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:45,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:45,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:45,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:45,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:45,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:45,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1881564016, now seen corresponding path program 1 times [2024-11-13 15:45:45,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:45,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852836723] [2024-11-13 15:45:45,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:45,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:45,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:45,994 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:45:46,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:45:46,016 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:45:46,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:46,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1709791576, now seen corresponding path program 1 times [2024-11-13 15:45:46,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:45:46,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286253843] [2024-11-13 15:45:46,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:45:46,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:45:46,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:46,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:46,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:45:46,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286253843] [2024-11-13 15:45:46,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286253843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:45:46,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:45:46,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:45:46,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024972491] [2024-11-13 15:45:46,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:45:48,339 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:45:48,340 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:45:48,340 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:45:48,341 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:45:48,341 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 15:45:48,341 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:48,341 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:45:48,342 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:45:48,342 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration30_Loop [2024-11-13 15:45:48,342 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:45:48,342 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:45:48,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,409 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,476 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,490 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,540 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,543 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,553 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,587 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:48,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:49,449 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:45:49,450 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 15:45:49,453 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,454 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,456 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 15:45:49,460 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,460 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:49,480 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:49,480 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:49,500 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-13 15:45:49,500 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,501 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,503 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,803 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 15:45:49,805 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,805 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:49,823 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:49,823 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:49,841 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:49,842 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,842 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,845 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 15:45:49,849 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,849 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:49,873 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:49,873 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:49,888 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:49,888 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,888 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,890 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,892 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 15:45:49,893 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,893 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:49,909 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:49,909 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:49,929 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 15:45:49,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,933 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,937 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 15:45:49,938 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,938 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:49,958 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:49,959 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:49,980 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:49,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:49,981 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:49,983 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:49,986 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 15:45:49,989 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:49,989 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,022 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,022 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,044 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 15:45:50,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,047 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,050 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,050 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 15:45:50,072 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,072 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,093 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 15:45:50,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,094 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,096 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,098 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 15:45:50,099 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,099 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,120 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,120 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,141 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,142 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,145 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 15:45:50,150 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,150 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,174 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,175 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,197 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,197 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,197 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,200 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,202 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 15:45:50,203 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,203 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,235 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,235 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-8} Honda state: {~E_4~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,257 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,258 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,260 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 15:45:50,264 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,265 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,285 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,286 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,308 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-13 15:45:50,308 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,311 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,314 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 15:45:50,315 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,315 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,335 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,335 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,357 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,358 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,358 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,360 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,363 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 15:45:50,364 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,364 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,394 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,395 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,415 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,416 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,419 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,421 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 15:45:50,422 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,422 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,452 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,452 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,473 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:50,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,474 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,476 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,479 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 15:45:50,480 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,480 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,499 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,499 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,520 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 15:45:50,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,524 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 15:45:50,527 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,528 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,547 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,547 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,568 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 15:45:50,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,571 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 15:45:50,575 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,575 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,594 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,594 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet6#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,608 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-13 15:45:50,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,610 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 15:45:50,612 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,612 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,627 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,628 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,641 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 15:45:50,641 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,641 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,643 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,646 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,646 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,648 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 15:45:50,661 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,661 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,676 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 15:45:50,676 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,678 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 15:45:50,681 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,681 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,703 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,703 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,717 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 15:45:50,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,719 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,720 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 15:45:50,721 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,721 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,736 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,736 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,751 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 15:45:50,751 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,753 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,754 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 15:45:50,755 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,755 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,770 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,770 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,784 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-13 15:45:50,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,787 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 15:45:50,790 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,790 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,805 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,805 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,818 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-13 15:45:50,818 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,820 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 15:45:50,822 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,822 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,837 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,837 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,852 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 15:45:50,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,855 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 15:45:50,856 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,856 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,871 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,872 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,885 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-13 15:45:50,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,887 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 15:45:50,890 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,890 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,905 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,906 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,918 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 15:45:50,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,920 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,921 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-13 15:45:50,922 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,922 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,935 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,935 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,948 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-13 15:45:50,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,948 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,950 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-13 15:45:50,951 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,951 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:50,970 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 15:45:50,970 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 15:45:50,990 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-13 15:45:50,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:50,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:50,992 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:50,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-13 15:45:50,996 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 15:45:50,996 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:51,023 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-13 15:45:51,023 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:51,024 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:51,025 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:51,026 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-13 15:45:51,027 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 15:45:51,027 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 15:45:51,052 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 15:45:51,064 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2024-11-13 15:45:51,064 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 15:45:51,064 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 15:45:51,064 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 15:45:51,064 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 15:45:51,064 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 15:45:51,064 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:51,064 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 15:45:51,064 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 15:45:51,064 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration30_Loop [2024-11-13 15:45:51,064 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 15:45:51,064 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 15:45:51,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,080 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,088 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,093 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,106 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,111 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,114 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,116 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,137 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,140 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,148 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,151 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,154 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,165 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,203 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,207 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,225 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,235 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,282 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,285 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,319 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,357 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:51,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 15:45:52,082 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 15:45:52,086 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 15:45:52,087 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,087 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,090 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-13 15:45:52,096 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,112 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,112 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,113 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,113 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,114 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,121 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,121 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,125 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,143 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-13 15:45:52,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,143 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,145 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-13 15:45:52,149 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,163 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,163 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,163 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,163 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,163 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,164 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,164 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,165 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,183 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-13 15:45:52,183 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,185 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,189 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-13 15:45:52,204 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,204 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,204 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,204 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,204 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,205 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,205 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,209 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,227 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,228 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,228 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,230 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-13 15:45:52,232 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,246 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,246 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,247 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,247 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,247 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,247 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,247 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,252 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,269 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,272 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,274 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-13 15:45:52,275 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,289 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,289 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,290 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,290 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:45:52,290 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,292 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:45:52,293 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,296 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,314 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,316 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,317 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-13 15:45:52,318 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,328 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,329 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,329 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,329 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,329 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,329 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,329 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,330 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,342 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2024-11-13 15:45:52,342 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,344 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-13 15:45:52,346 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,357 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,357 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,357 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,357 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,357 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,357 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,357 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,359 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,370 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-11-13 15:45:52,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,373 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-13 15:45:52,374 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,385 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,385 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,385 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,385 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,385 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,386 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,386 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,387 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,398 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2024-11-13 15:45:52,399 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,399 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,400 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,401 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-13 15:45:52,402 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,413 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,413 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,413 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,413 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,413 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,414 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,414 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,415 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,435 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,438 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-13 15:45:52,440 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,454 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,455 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,455 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,455 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:45:52,455 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,456 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:45:52,456 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,458 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,472 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,472 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,474 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,475 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-13 15:45:52,476 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,487 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,487 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,487 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,487 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,487 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,489 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,489 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,494 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,512 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2024-11-13 15:45:52,512 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,512 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,514 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,515 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-13 15:45:52,515 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,526 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,526 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,526 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,526 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,526 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,527 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,527 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,528 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,539 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2024-11-13 15:45:52,539 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,541 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-13 15:45:52,543 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,554 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,554 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,554 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,554 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,554 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,555 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,555 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,556 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,571 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-13 15:45:52,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,573 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,574 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-13 15:45:52,575 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,585 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,585 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,586 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,586 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,586 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,586 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,586 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,588 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,599 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2024-11-13 15:45:52,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,601 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-13 15:45:52,602 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,613 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,613 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,613 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,613 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:45:52,613 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,614 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:45:52,614 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,617 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,631 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-11-13 15:45:52,631 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,633 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,634 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-13 15:45:52,634 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,645 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,645 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,645 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,645 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,645 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,646 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,646 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,647 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,659 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-11-13 15:45:52,660 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,661 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-13 15:45:52,663 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,673 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,673 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,674 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,674 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 15:45:52,674 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,674 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 15:45:52,675 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,678 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,691 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2024-11-13 15:45:52,692 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,692 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,693 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,694 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-11-13 15:45:52,695 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,706 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,706 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,706 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,706 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,706 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,707 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,707 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,711 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,726 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Ended with exit code 0 [2024-11-13 15:45:52,726 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,726 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,728 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,729 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-11-13 15:45:52,730 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,741 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,741 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,741 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,741 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,741 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,742 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,742 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,745 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,758 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2024-11-13 15:45:52,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,759 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,761 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-11-13 15:45:52,762 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,773 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,773 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,773 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,773 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,773 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,775 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,775 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,779 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,799 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Ended with exit code 0 [2024-11-13 15:45:52,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,803 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,805 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-11-13 15:45:52,806 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,822 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,822 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,822 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,822 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,822 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,823 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,823 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,825 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,838 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Forceful destruction successful, exit code 0 [2024-11-13 15:45:52,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,838 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,840 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,841 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-11-13 15:45:52,842 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,854 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,854 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,854 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,855 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,855 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,855 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,855 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,856 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,869 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2024-11-13 15:45:52,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,871 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,872 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-11-13 15:45:52,873 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,887 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,887 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,887 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,887 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,888 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,888 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,891 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,904 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-11-13 15:45:52,904 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,906 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-11-13 15:45:52,907 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,920 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,920 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,921 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,921 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,921 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,921 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,921 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,923 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,936 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Ended with exit code 0 [2024-11-13 15:45:52,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,937 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,938 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-11-13 15:45:52,940 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,953 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,953 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,953 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,953 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,953 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,954 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,954 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,956 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:52,979 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2024-11-13 15:45:52,979 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:52,979 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:52,981 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:52,982 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-11-13 15:45:52,983 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:52,996 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:52,996 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:52,996 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:52,996 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:52,996 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:52,997 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:52,997 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:52,999 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:53,016 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2024-11-13 15:45:53,016 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:53,016 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:53,018 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:53,019 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-11-13 15:45:53,020 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:53,033 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:53,033 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:53,033 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:53,033 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:53,033 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:53,034 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:53,034 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:53,035 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:53,048 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Ended with exit code 0 [2024-11-13 15:45:53,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:53,049 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:53,050 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:53,184 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:53,187 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-11-13 15:45:53,199 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:53,199 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:53,199 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:53,199 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:53,199 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:53,200 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:53,200 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:53,202 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:53,215 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-11-13 15:45:53,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:53,215 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:53,217 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:53,218 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-11-13 15:45:53,219 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:53,231 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:53,231 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:53,232 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:53,232 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:53,232 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:53,232 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:53,232 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:53,234 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 15:45:53,247 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2024-11-13 15:45:53,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:53,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:53,249 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:53,250 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2024-11-13 15:45:53,251 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 15:45:53,264 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 15:45:53,264 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 15:45:53,264 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 15:45:53,264 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 15:45:53,264 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 15:45:53,265 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 15:45:53,265 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 15:45:53,267 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 15:45:53,271 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 15:45:53,274 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 15:45:53,275 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 15:45:53,276 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 15:45:53,279 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 15:45:53,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Waiting until timeout for monitored process [2024-11-13 15:45:53,281 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 15:45:53,281 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 15:45:53,281 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 15:45:53,281 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2024-11-13 15:45:53,295 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Ended with exit code 0 [2024-11-13 15:45:53,298 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 15:45:53,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:45:53,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:53,399 INFO L255 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 15:45:53,402 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:45:53,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:45:53,629 INFO L255 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 15:45:53,632 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 15:45:54,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:45:54,013 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 15:45:54,014 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 44272 states and 57693 transitions. cyclomatic complexity: 13437 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:54,739 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 44272 states and 57693 transitions. cyclomatic complexity: 13437. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 88930 states and 116416 transitions. Complement of second has 4 states. [2024-11-13 15:45:54,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 15:45:54,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:54,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 977 transitions. [2024-11-13 15:45:54,751 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 977 transitions. Stem has 84 letters. Loop has 100 letters. [2024-11-13 15:45:54,756 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:45:54,758 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 977 transitions. Stem has 184 letters. Loop has 100 letters. [2024-11-13 15:45:54,760 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:45:54,760 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 977 transitions. Stem has 84 letters. Loop has 200 letters. [2024-11-13 15:45:54,762 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 15:45:54,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88930 states and 116416 transitions. [2024-11-13 15:45:55,236 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43856 [2024-11-13 15:45:55,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88930 states to 88930 states and 116416 transitions. [2024-11-13 15:45:55,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44273 [2024-11-13 15:45:55,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44514 [2024-11-13 15:45:55,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88930 states and 116416 transitions. [2024-11-13 15:45:55,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:45:55,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88930 states and 116416 transitions. [2024-11-13 15:45:55,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88930 states and 116416 transitions. [2024-11-13 15:45:56,259 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_966d5d1e-20bb-495c-92be-d7d84db563c2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Ended with exit code 0 [2024-11-13 15:45:56,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88930 to 88689. [2024-11-13 15:45:56,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88689 states, 88689 states have (on average 1.3077495518046207) internal successors, (115983), 88688 states have internal predecessors, (115983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:56,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88689 states to 88689 states and 115983 transitions. [2024-11-13 15:45:56,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88689 states and 115983 transitions. [2024-11-13 15:45:56,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:45:56,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:45:56,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:45:56,938 INFO L87 Difference]: Start difference. First operand 88689 states and 115983 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:45:57,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:45:57,413 INFO L93 Difference]: Finished difference Result 93697 states and 121711 transitions. [2024-11-13 15:45:57,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93697 states and 121711 transitions. [2024-11-13 15:45:58,382 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46360 [2024-11-13 15:45:58,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93697 states to 93697 states and 121711 transitions. [2024-11-13 15:45:58,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46777 [2024-11-13 15:45:58,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46777 [2024-11-13 15:45:58,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93697 states and 121711 transitions. [2024-11-13 15:45:58,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:45:58,726 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93697 states and 121711 transitions. [2024-11-13 15:45:58,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93697 states and 121711 transitions. [2024-11-13 15:45:59,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93697 to 88689. [2024-11-13 15:45:59,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88689 states, 88689 states have (on average 1.3041414380588348) internal successors, (115663), 88688 states have internal predecessors, (115663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:00,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88689 states to 88689 states and 115663 transitions. [2024-11-13 15:46:00,147 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88689 states and 115663 transitions. [2024-11-13 15:46:00,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:46:00,148 INFO L424 stractBuchiCegarLoop]: Abstraction has 88689 states and 115663 transitions. [2024-11-13 15:46:00,148 INFO L331 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-13 15:46:00,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88689 states and 115663 transitions. [2024-11-13 15:46:00,387 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43856 [2024-11-13 15:46:00,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:46:00,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:46:00,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:00,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:00,390 INFO L745 eck$LassoCheckResult]: Stem: 1282535#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1282536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1282821#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1282822#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1282121#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1282122#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1282819#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1282820#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1282666#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1282238#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1282239#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1282087#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1282088#L684 assume !(0 == ~M_E~0); 1283084#L684-2 assume !(0 == ~T1_E~0); 1282730#L689-1 assume !(0 == ~T2_E~0); 1282731#L694-1 assume !(0 == ~T3_E~0); 1282728#L699-1 assume !(0 == ~T4_E~0); 1282729#L704-1 assume !(0 == ~T5_E~0); 1282633#L709-1 assume !(0 == ~T6_E~0); 1282501#L714-1 assume !(0 == ~E_M~0); 1282502#L719-1 assume !(0 == ~E_1~0); 1283012#L724-1 assume !(0 == ~E_2~0); 1282037#L729-1 assume !(0 == ~E_3~0); 1282038#L734-1 assume !(0 == ~E_4~0); 1283165#L739-1 assume !(0 == ~E_5~0); 1282427#L744-1 assume !(0 == ~E_6~0); 1282428#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1281952#L334 assume !(1 == ~m_pc~0); 1281953#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1282618#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1283398#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1282372#L849 assume !(0 != activate_threads_~tmp~1#1); 1282373#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1282236#L353 assume !(1 == ~t1_pc~0); 1282237#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1282827#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1281979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1281980#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1282131#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1282132#L372 assume !(1 == ~t2_pc~0); 1282348#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1282392#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1282605#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1283397#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1281932#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1281933#L391 assume !(1 == ~t3_pc~0); 1281783#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1281784#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1281833#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1281834#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1282384#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1282385#L410 assume !(1 == ~t4_pc~0); 1282853#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1282854#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1282160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1282161#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1282395#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1282396#L429 assume !(1 == ~t5_pc~0); 1282047#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1282048#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1283399#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1282864#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1282865#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1282369#L448 assume !(1 == ~t6_pc~0); 1282204#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1282205#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1282795#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1282796#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1283228#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1283342#L762 assume !(1 == ~M_E~0); 1282461#L762-2 assume !(1 == ~T1_E~0); 1282462#L767-1 assume !(1 == ~T2_E~0); 1283243#L772-1 assume !(1 == ~T3_E~0); 1282935#L777-1 assume !(1 == ~T4_E~0); 1282699#L782-1 assume !(1 == ~T5_E~0); 1282095#L787-1 assume !(1 == ~T6_E~0); 1282093#L792-1 assume !(1 == ~E_M~0); 1282094#L797-1 assume !(1 == ~E_1~0); 1282170#L802-1 assume !(1 == ~E_2~0); 1282625#L807-1 assume !(1 == ~E_3~0); 1282626#L812-1 assume !(1 == ~E_4~0); 1283154#L817-1 assume !(1 == ~E_5~0); 1282732#L822-1 assume !(1 == ~E_6~0); 1282733#L827-1 assume { :end_inline_reset_delta_events } true; 1283180#L1053-2 assume !false; 1344450#L1054 [2024-11-13 15:46:00,391 INFO L747 eck$LassoCheckResult]: Loop: 1344450#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1345447#L659-1 assume !false; 1345445#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1345443#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1345442#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1345439#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1345438#L570 assume 0 != eval_~tmp~0#1; 1345436#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1345434#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 1345435#L74 assume 0 == ~m_pc~0; 1370455#L99-1 assume !false; 1370454#L86 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1283384#L334-3 assume 1 == ~m_pc~0; 1283155#L335-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1282144#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1281969#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1281970#L849-3 assume !(0 != activate_threads_~tmp~1#1); 1283223#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1283229#L353-3 assume !(1 == ~t1_pc~0); 1282441#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1281995#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1281996#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1283089#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 1283267#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1281963#L372-3 assume 1 == ~t2_pc~0; 1281965#L373-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1282479#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1282872#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1282919#L865-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1282920#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1282839#L391-3 assume !(1 == ~t3_pc~0); 1281973#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1281974#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1282425#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1281944#L873-3 assume !(0 != activate_threads_~tmp___2~0#1); 1281945#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1283216#L410-3 assume !(1 == ~t4_pc~0); 1283217#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1283347#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1283082#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1282738#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 1282739#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1283181#L429-3 assume !(1 == ~t5_pc~0); 1282991#L429-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1282517#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1282518#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1283107#L889-3 assume !(0 != activate_threads_~tmp___4~0#1); 1283108#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1281795#L448-3 assume !(1 == ~t6_pc~0); 1281796#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1283170#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1282862#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1282523#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 1282524#L897-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true; 1283183#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1335930#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 1335928#L578-2 havoc eval_~tmp_ndt_1~0#1; 1335924#L575-1 assume !(0 == ~t1_st~0); 1335921#L589-1 assume !(0 == ~t2_st~0); 1335918#L603-1 assume !(0 == ~t3_st~0); 1335915#L617-1 assume !(0 == ~t4_st~0); 1335911#L631-1 assume !(0 == ~t5_st~0); 1335908#L645-1 assume !(0 == ~t6_st~0); 1335905#L659-1 assume !false; 1335904#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1335902#L518 assume !(0 == ~m_st~0); 1335901#L522 assume !(0 == ~t1_st~0); 1335900#L526 assume !(0 == ~t2_st~0); 1335899#L530 assume !(0 == ~t3_st~0); 1335897#L534 assume !(0 == ~t4_st~0); 1335896#L538 assume !(0 == ~t5_st~0); 1335894#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1335893#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1335891#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1335888#L570 assume !(0 != eval_~tmp~0#1); 1335887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1335886#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1335884#L684-3 assume !(0 == ~M_E~0); 1335883#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1335882#L689-3 assume !(0 == ~T2_E~0); 1335880#L694-3 assume !(0 == ~T3_E~0); 1335879#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1335878#L704-3 assume !(0 == ~T5_E~0); 1335646#L709-3 assume !(0 == ~T6_E~0); 1335644#L714-3 assume !(0 == ~E_M~0); 1335642#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1335641#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1335640#L729-3 assume !(0 == ~E_3~0); 1335638#L734-3 assume !(0 == ~E_4~0); 1335636#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1335635#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1335634#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1335632#L334-24 assume 1 == ~m_pc~0; 1335629#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1335628#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1335627#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1335624#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1335623#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1335622#L353-24 assume !(1 == ~t1_pc~0); 1335621#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1335619#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1335617#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1335616#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1335614#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1335612#L372-24 assume 1 == ~t2_pc~0; 1335609#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1335607#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1335605#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1335603#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1335600#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1335598#L391-24 assume !(1 == ~t3_pc~0); 1335596#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1335594#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1335591#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1335589#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1335587#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1335584#L410-24 assume !(1 == ~t4_pc~0); 1335582#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1335580#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1335578#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1335576#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 1335574#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1335572#L429-24 assume !(1 == ~t5_pc~0); 1335568#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1335566#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1335563#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1335561#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 1335558#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1335555#L448-24 assume !(1 == ~t6_pc~0); 1335553#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1335551#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1335549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1335547#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 1335545#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1335543#L762-3 assume !(1 == ~M_E~0); 1334860#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1335540#L767-3 assume !(1 == ~T2_E~0); 1335538#L772-3 assume !(1 == ~T3_E~0); 1335536#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1335534#L782-3 assume !(1 == ~T5_E~0); 1335498#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1335496#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1335494#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1335491#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1335490#L807-3 assume !(1 == ~E_3~0); 1335488#L812-3 assume !(1 == ~E_4~0); 1335485#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1335483#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1335481#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1335476#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1335474#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1335472#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1335469#L1072 assume !(0 == start_simulation_~tmp~3#1); 1335470#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1345478#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1345476#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1345474#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1345472#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1345468#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1345466#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1345464#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1345463#L1053-2 assume !false; 1344450#L1054 [2024-11-13 15:46:00,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:00,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793377, now seen corresponding path program 1 times [2024-11-13 15:46:00,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:00,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376994457] [2024-11-13 15:46:00,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:00,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:00,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:00,412 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:00,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:00,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:00,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:00,441 INFO L85 PathProgramCache]: Analyzing trace with hash -749308551, now seen corresponding path program 1 times [2024-11-13 15:46:00,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:00,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712900175] [2024-11-13 15:46:00,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:00,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:00,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:46:00,505 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:46:00,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:46:00,506 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [712900175] [2024-11-13 15:46:00,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [712900175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:46:00,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:46:00,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:46:00,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268818227] [2024-11-13 15:46:00,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:46:00,507 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 15:46:00,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:46:00,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:46:00,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:46:00,508 INFO L87 Difference]: Start difference. First operand 88689 states and 115663 transitions. cyclomatic complexity: 27006 Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:00,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:46:00,911 INFO L93 Difference]: Finished difference Result 107815 states and 139090 transitions. [2024-11-13 15:46:00,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107815 states and 139090 transitions. [2024-11-13 15:46:01,728 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 53292 [2024-11-13 15:46:02,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107815 states to 107815 states and 139090 transitions. [2024-11-13 15:46:02,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53834 [2024-11-13 15:46:02,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53834 [2024-11-13 15:46:02,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107815 states and 139090 transitions. [2024-11-13 15:46:02,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:46:02,280 INFO L218 hiAutomatonCegarLoop]: Abstraction has 107815 states and 139090 transitions. [2024-11-13 15:46:02,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107815 states and 139090 transitions. [2024-11-13 15:46:03,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107815 to 102423. [2024-11-13 15:46:03,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102423 states, 102423 states have (on average 1.2951973677787216) internal successors, (132658), 102422 states have internal predecessors, (132658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:03,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102423 states to 102423 states and 132658 transitions. [2024-11-13 15:46:03,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102423 states and 132658 transitions. [2024-11-13 15:46:03,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:46:03,888 INFO L424 stractBuchiCegarLoop]: Abstraction has 102423 states and 132658 transitions. [2024-11-13 15:46:03,888 INFO L331 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-13 15:46:03,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102423 states and 132658 transitions. [2024-11-13 15:46:04,075 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 50596 [2024-11-13 15:46:04,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:46:04,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:46:04,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:04,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:04,076 INFO L745 eck$LassoCheckResult]: Stem: 1479043#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1479044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1479341#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1479342#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1478630#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1478631#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1479339#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1479340#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1479181#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1478741#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1478742#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1478596#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1478597#L684 assume !(0 == ~M_E~0); 1479626#L684-2 assume !(0 == ~T1_E~0); 1479250#L689-1 assume !(0 == ~T2_E~0); 1479251#L694-1 assume !(0 == ~T3_E~0); 1479248#L699-1 assume !(0 == ~T4_E~0); 1479249#L704-1 assume !(0 == ~T5_E~0); 1479146#L709-1 assume !(0 == ~T6_E~0); 1479009#L714-1 assume !(0 == ~E_M~0); 1479010#L719-1 assume !(0 == ~E_1~0); 1479545#L724-1 assume !(0 == ~E_2~0); 1478544#L729-1 assume !(0 == ~E_3~0); 1478545#L734-1 assume !(0 == ~E_4~0); 1479718#L739-1 assume !(0 == ~E_5~0); 1478938#L744-1 assume !(0 == ~E_6~0); 1478939#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1478460#L334 assume !(1 == ~m_pc~0); 1478461#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1479131#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1478941#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1478879#L849 assume !(0 != activate_threads_~tmp~1#1); 1478880#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478739#L353 assume !(1 == ~t1_pc~0); 1478740#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1479349#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1478486#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1478487#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1478638#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1478639#L372 assume !(1 == ~t2_pc~0); 1478856#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1478900#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1479116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1479982#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1478440#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1478441#L391 assume !(1 == ~t3_pc~0); 1478293#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1478294#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1478341#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1478342#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1478891#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1478892#L410 assume !(1 == ~t4_pc~0); 1479380#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1479381#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1478667#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1478668#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1478903#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478904#L429 assume !(1 == ~t5_pc~0); 1478554#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1478555#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1479940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1479393#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1479394#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1478876#L448 assume !(1 == ~t6_pc~0); 1478707#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1478708#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1479317#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1479318#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1479778#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1479905#L762 assume !(1 == ~M_E~0); 1478970#L762-2 assume !(1 == ~T1_E~0); 1478971#L767-1 assume !(1 == ~T2_E~0); 1479790#L772-1 assume !(1 == ~T3_E~0); 1479461#L777-1 assume !(1 == ~T4_E~0); 1479215#L782-1 assume !(1 == ~T5_E~0); 1478604#L787-1 assume !(1 == ~T6_E~0); 1478602#L792-1 assume !(1 == ~E_M~0); 1478603#L797-1 assume !(1 == ~E_1~0); 1478677#L802-1 assume !(1 == ~E_2~0); 1479138#L807-1 assume !(1 == ~E_3~0); 1479139#L812-1 assume !(1 == ~E_4~0); 1479705#L817-1 assume !(1 == ~E_5~0); 1479252#L822-1 assume !(1 == ~E_6~0); 1479253#L827-1 assume { :end_inline_reset_delta_events } true; 1479735#L1053-2 assume !false; 1533964#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1533962#L659-1 [2024-11-13 15:46:04,076 INFO L747 eck$LassoCheckResult]: Loop: 1533962#L659-1 assume !false; 1533960#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1533958#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1533956#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1533954#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1533953#L570 assume 0 != eval_~tmp~0#1; 1533949#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1533946#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1533944#L578-2 havoc eval_~tmp_ndt_1~0#1; 1533942#L575-1 assume !(0 == ~t1_st~0); 1533943#L589-1 assume !(0 == ~t2_st~0); 1533979#L603-1 assume !(0 == ~t3_st~0); 1533974#L617-1 assume !(0 == ~t4_st~0); 1533970#L631-1 assume !(0 == ~t5_st~0); 1533966#L645-1 assume !(0 == ~t6_st~0); 1533962#L659-1 [2024-11-13 15:46:04,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:04,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052149, now seen corresponding path program 1 times [2024-11-13 15:46:04,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:04,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457750959] [2024-11-13 15:46:04,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:04,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:04,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:04,089 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:04,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:04,109 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:04,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:04,110 INFO L85 PathProgramCache]: Analyzing trace with hash -303819582, now seen corresponding path program 1 times [2024-11-13 15:46:04,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:04,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35174068] [2024-11-13 15:46:04,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:04,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:04,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:04,114 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:04,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:04,119 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:04,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:04,120 INFO L85 PathProgramCache]: Analyzing trace with hash -1141675016, now seen corresponding path program 1 times [2024-11-13 15:46:04,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:04,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648432742] [2024-11-13 15:46:04,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:04,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:04,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:46:04,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:46:04,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:46:04,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648432742] [2024-11-13 15:46:04,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648432742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:46:04,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:46:04,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:46:04,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142016679] [2024-11-13 15:46:04,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:46:04,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:46:04,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:46:04,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:46:04,243 INFO L87 Difference]: Start difference. First operand 102423 states and 132658 transitions. cyclomatic complexity: 30299 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:04,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:46:04,763 INFO L93 Difference]: Finished difference Result 190232 states and 244205 transitions. [2024-11-13 15:46:04,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190232 states and 244205 transitions. [2024-11-13 15:46:05,807 INFO L131 ngComponentsAnalysis]: Automaton has 56 accepting balls. 91964 [2024-11-13 15:46:06,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190232 states to 190232 states and 244205 transitions. [2024-11-13 15:46:06,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95014 [2024-11-13 15:46:06,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95014 [2024-11-13 15:46:06,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190232 states and 244205 transitions. [2024-11-13 15:46:06,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:46:06,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190232 states and 244205 transitions. [2024-11-13 15:46:06,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190232 states and 244205 transitions. [2024-11-13 15:46:08,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190232 to 184692. [2024-11-13 15:46:08,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184692 states, 184692 states have (on average 1.2861683234790895) internal successors, (237545), 184691 states have internal predecessors, (237545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:08,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184692 states to 184692 states and 237545 transitions. [2024-11-13 15:46:08,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 184692 states and 237545 transitions. [2024-11-13 15:46:08,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:46:08,892 INFO L424 stractBuchiCegarLoop]: Abstraction has 184692 states and 237545 transitions. [2024-11-13 15:46:08,892 INFO L331 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-13 15:46:08,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184692 states and 237545 transitions. [2024-11-13 15:46:09,375 INFO L131 ngComponentsAnalysis]: Automaton has 56 accepting balls. 89194 [2024-11-13 15:46:09,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:46:09,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:46:09,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:09,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:09,376 INFO L745 eck$LassoCheckResult]: Stem: 1771721#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1771722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1772037#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1772038#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1771297#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1771298#L475-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1772559#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1813944#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1813943#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1813942#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1813941#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1813940#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813939#L684 assume !(0 == ~M_E~0); 1813938#L684-2 assume !(0 == ~T1_E~0); 1813937#L689-1 assume !(0 == ~T2_E~0); 1813936#L694-1 assume !(0 == ~T3_E~0); 1813935#L699-1 assume !(0 == ~T4_E~0); 1813934#L704-1 assume !(0 == ~T5_E~0); 1813933#L709-1 assume !(0 == ~T6_E~0); 1813932#L714-1 assume !(0 == ~E_M~0); 1813931#L719-1 assume !(0 == ~E_1~0); 1813930#L724-1 assume !(0 == ~E_2~0); 1813929#L729-1 assume !(0 == ~E_3~0); 1813928#L734-1 assume !(0 == ~E_4~0); 1813927#L739-1 assume !(0 == ~E_5~0); 1813926#L744-1 assume !(0 == ~E_6~0); 1813925#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1813924#L334 assume !(1 == ~m_pc~0); 1813923#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1813922#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1813921#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1813920#L849 assume !(0 != activate_threads_~tmp~1#1); 1813919#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1813918#L353 assume !(1 == ~t1_pc~0); 1813917#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1813916#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1813915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1813914#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1813913#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1813912#L372 assume !(1 == ~t2_pc~0); 1813911#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1813946#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1813945#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1813906#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1813905#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1813904#L391 assume !(1 == ~t3_pc~0); 1813903#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1813902#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1813901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1813900#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1813899#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1813898#L410 assume !(1 == ~t4_pc~0); 1813897#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1813896#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1813895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1813894#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1813893#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1813892#L429 assume !(1 == ~t5_pc~0); 1813891#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1813948#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1813947#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1813884#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1813882#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1813880#L448 assume !(1 == ~t6_pc~0); 1813878#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1813876#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1813874#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1813872#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1813870#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1813868#L762 assume !(1 == ~M_E~0); 1813866#L762-2 assume !(1 == ~T1_E~0); 1813864#L767-1 assume !(1 == ~T2_E~0); 1813860#L772-1 assume !(1 == ~T3_E~0); 1813858#L777-1 assume !(1 == ~T4_E~0); 1813856#L782-1 assume !(1 == ~T5_E~0); 1813854#L787-1 assume !(1 == ~T6_E~0); 1813851#L792-1 assume !(1 == ~E_M~0); 1813849#L797-1 assume !(1 == ~E_1~0); 1813847#L802-1 assume !(1 == ~E_2~0); 1813845#L807-1 assume !(1 == ~E_3~0); 1813843#L812-1 assume !(1 == ~E_4~0); 1813841#L817-1 assume !(1 == ~E_5~0); 1813839#L822-1 assume !(1 == ~E_6~0); 1813837#L827-1 assume { :end_inline_reset_delta_events } true; 1813834#L1053-2 assume !false; 1813835#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1905578#L659-1 [2024-11-13 15:46:09,376 INFO L747 eck$LassoCheckResult]: Loop: 1905578#L659-1 assume !false; 1905577#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1905574#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1905570#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1905566#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1905562#L570 assume 0 != eval_~tmp~0#1; 1905558#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1905552#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1905553#L578-2 havoc eval_~tmp_ndt_1~0#1; 1905599#L575-1 assume !(0 == ~t1_st~0); 1905596#L589-1 assume !(0 == ~t2_st~0); 1905593#L603-1 assume !(0 == ~t3_st~0); 1905588#L617-1 assume !(0 == ~t4_st~0); 1905585#L631-1 assume !(0 == ~t5_st~0); 1905580#L645-1 assume !(0 == ~t6_st~0); 1905578#L659-1 [2024-11-13 15:46:09,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:09,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1466077069, now seen corresponding path program 1 times [2024-11-13 15:46:09,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:09,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50942541] [2024-11-13 15:46:09,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:09,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:09,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:46:09,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:46:09,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:46:09,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50942541] [2024-11-13 15:46:09,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50942541] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:46:09,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:46:09,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:46:09,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375277995] [2024-11-13 15:46:09,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:46:09,414 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 15:46:09,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:09,415 INFO L85 PathProgramCache]: Analyzing trace with hash -303819582, now seen corresponding path program 2 times [2024-11-13 15:46:09,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:09,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061997898] [2024-11-13 15:46:09,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:09,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:09,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:09,419 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:09,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:09,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:09,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:46:09,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:46:09,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:46:09,507 INFO L87 Difference]: Start difference. First operand 184692 states and 237545 transitions. cyclomatic complexity: 52965 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:10,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:46:10,768 INFO L93 Difference]: Finished difference Result 121029 states and 155759 transitions. [2024-11-13 15:46:10,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121029 states and 155759 transitions. [2024-11-13 15:46:11,081 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59851 [2024-11-13 15:46:11,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121029 states to 121029 states and 155759 transitions. [2024-11-13 15:46:11,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60453 [2024-11-13 15:46:11,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60453 [2024-11-13 15:46:11,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121029 states and 155759 transitions. [2024-11-13 15:46:11,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 15:46:11,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121029 states and 155759 transitions. [2024-11-13 15:46:11,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121029 states and 155759 transitions. [2024-11-13 15:46:12,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121029 to 121029. [2024-11-13 15:46:12,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121029 states, 121029 states have (on average 1.2869560188054103) internal successors, (155759), 121028 states have internal predecessors, (155759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:12,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121029 states to 121029 states and 155759 transitions. [2024-11-13 15:46:12,790 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121029 states and 155759 transitions. [2024-11-13 15:46:12,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 15:46:12,791 INFO L424 stractBuchiCegarLoop]: Abstraction has 121029 states and 155759 transitions. [2024-11-13 15:46:12,791 INFO L331 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2024-11-13 15:46:12,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121029 states and 155759 transitions. [2024-11-13 15:46:13,016 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59851 [2024-11-13 15:46:13,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 15:46:13,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 15:46:13,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:13,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 15:46:13,017 INFO L745 eck$LassoCheckResult]: Stem: 2077428#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2077429#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2077717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2077718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2077020#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2077021#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2077715#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2077716#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2077565#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2077128#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2077129#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2076986#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2076987#L684 assume !(0 == ~M_E~0); 2077994#L684-2 assume !(0 == ~T1_E~0); 2077628#L689-1 assume !(0 == ~T2_E~0); 2077629#L694-1 assume !(0 == ~T3_E~0); 2077626#L699-1 assume !(0 == ~T4_E~0); 2077627#L704-1 assume !(0 == ~T5_E~0); 2077530#L709-1 assume !(0 == ~T6_E~0); 2077394#L714-1 assume !(0 == ~E_M~0); 2077395#L719-1 assume !(0 == ~E_1~0); 2077912#L724-1 assume !(0 == ~E_2~0); 2076935#L729-1 assume !(0 == ~E_3~0); 2076936#L734-1 assume !(0 == ~E_4~0); 2078085#L739-1 assume !(0 == ~E_5~0); 2077324#L744-1 assume !(0 == ~E_6~0); 2077325#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2076851#L334 assume !(1 == ~m_pc~0); 2076852#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2077513#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2077327#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2077268#L849 assume !(0 != activate_threads_~tmp~1#1); 2077269#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2077126#L353 assume !(1 == ~t1_pc~0); 2077127#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2077723#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2076877#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2076878#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2077029#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2077030#L372 assume !(1 == ~t2_pc~0); 2077242#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2077289#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2077500#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2078350#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2076831#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2076832#L391 assume !(1 == ~t3_pc~0); 2076683#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2076684#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2076734#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2076735#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2077280#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2077281#L410 assume !(1 == ~t4_pc~0); 2077752#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2077753#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2077056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2077057#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2077292#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2077293#L429 assume !(1 == ~t5_pc~0); 2076945#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2076946#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2078310#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2077763#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2077764#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2077263#L448 assume !(1 == ~t6_pc~0); 2077095#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2077096#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2077695#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2077696#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2078156#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2078279#L762 assume !(1 == ~M_E~0); 2077355#L762-2 assume !(1 == ~T1_E~0); 2077356#L767-1 assume !(1 == ~T2_E~0); 2078170#L772-1 assume !(1 == ~T3_E~0); 2077835#L777-1 assume !(1 == ~T4_E~0); 2077596#L782-1 assume !(1 == ~T5_E~0); 2076994#L787-1 assume !(1 == ~T6_E~0); 2076992#L792-1 assume !(1 == ~E_M~0); 2076993#L797-1 assume !(1 == ~E_1~0); 2077064#L802-1 assume !(1 == ~E_2~0); 2077522#L807-1 assume !(1 == ~E_3~0); 2077523#L812-1 assume !(1 == ~E_4~0); 2078072#L817-1 assume !(1 == ~E_5~0); 2077630#L822-1 assume !(1 == ~E_6~0); 2077631#L827-1 assume { :end_inline_reset_delta_events } true; 2078103#L1053-2 assume !false; 2108902#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2154143#L659-1 [2024-11-13 15:46:13,017 INFO L747 eck$LassoCheckResult]: Loop: 2154143#L659-1 assume !false; 2154188#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2154185#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2154183#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2154180#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2154178#L570 assume 0 != eval_~tmp~0#1; 2154176#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2154173#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2154170#L578-2 havoc eval_~tmp_ndt_1~0#1; 2154168#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2154165#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2154163#L592-2 havoc eval_~tmp_ndt_2~0#1; 2154160#L589-1 assume !(0 == ~t2_st~0); 2154156#L603-1 assume !(0 == ~t3_st~0); 2154152#L617-1 assume !(0 == ~t4_st~0); 2154148#L631-1 assume !(0 == ~t5_st~0); 2154142#L645-1 assume !(0 == ~t6_st~0); 2154143#L659-1 [2024-11-13 15:46:13,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:13,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052149, now seen corresponding path program 2 times [2024-11-13 15:46:13,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:13,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638673495] [2024-11-13 15:46:13,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:13,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:13,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:13,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:13,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:13,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:13,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:13,050 INFO L85 PathProgramCache]: Analyzing trace with hash 257930536, now seen corresponding path program 1 times [2024-11-13 15:46:13,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:13,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046284821] [2024-11-13 15:46:13,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:13,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:13,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:13,054 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 15:46:13,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 15:46:13,057 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 15:46:13,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 15:46:13,058 INFO L85 PathProgramCache]: Analyzing trace with hash -1762257186, now seen corresponding path program 1 times [2024-11-13 15:46:13,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 15:46:13,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663071032] [2024-11-13 15:46:13,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 15:46:13,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 15:46:13,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 15:46:13,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 15:46:13,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 15:46:13,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663071032] [2024-11-13 15:46:13,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663071032] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 15:46:13,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 15:46:13,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 15:46:13,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744307992] [2024-11-13 15:46:13,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 15:46:13,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 15:46:13,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 15:46:13,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 15:46:13,181 INFO L87 Difference]: Start difference. First operand 121029 states and 155759 transitions. cyclomatic complexity: 34794 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 15:46:14,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 15:46:14,440 INFO L93 Difference]: Finished difference Result 229907 states and 294437 transitions. [2024-11-13 15:46:14,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 229907 states and 294437 transitions. [2024-11-13 15:46:15,073 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 113686