./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 12:48:42,367 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 12:48:42,492 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 12:48:42,502 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 12:48:42,502 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 12:48:42,550 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 12:48:42,551 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 12:48:42,552 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 12:48:42,552 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 12:48:42,553 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 12:48:42,555 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 12:48:42,555 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 12:48:42,555 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 12:48:42,556 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 12:48:42,556 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 12:48:42,557 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 12:48:42,557 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 12:48:42,558 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 12:48:42,558 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 12:48:42,558 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 12:48:42,558 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 12:48:42,558 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 12:48:42,558 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 12:48:42,559 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 12:48:42,560 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 12:48:42,560 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 12:48:42,560 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 12:48:42,560 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 12:48:42,560 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 12:48:42,560 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 12:48:42,561 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 12:48:42,562 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 12:48:42,562 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 12:48:42,562 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2024-11-13 12:48:42,967 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 12:48:42,978 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 12:48:42,980 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 12:48:42,982 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 12:48:42,983 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 12:48:42,984 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.07.cil-2.c Unable to find full path for "g++" [2024-11-13 12:48:45,346 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 12:48:45,732 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 12:48:45,733 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-11-13 12:48:45,750 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/data/e5b321174/1d64392b8dc54bdfb61a6acaca3a23af/FLAG0be4e8834 [2024-11-13 12:48:45,910 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/data/e5b321174/1d64392b8dc54bdfb61a6acaca3a23af [2024-11-13 12:48:45,912 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 12:48:45,914 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 12:48:45,916 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 12:48:45,916 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 12:48:45,922 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 12:48:45,923 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 12:48:45" (1/1) ... [2024-11-13 12:48:45,925 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1804a836 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:45, skipping insertion in model container [2024-11-13 12:48:45,927 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 12:48:45" (1/1) ... [2024-11-13 12:48:45,967 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 12:48:46,310 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 12:48:46,328 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 12:48:46,410 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 12:48:46,440 INFO L204 MainTranslator]: Completed translation [2024-11-13 12:48:46,441 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46 WrapperNode [2024-11-13 12:48:46,441 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 12:48:46,442 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 12:48:46,443 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 12:48:46,443 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 12:48:46,451 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,462 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,579 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2010 [2024-11-13 12:48:46,582 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 12:48:46,583 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 12:48:46,583 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 12:48:46,583 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 12:48:46,597 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,597 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,614 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,673 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 12:48:46,674 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,674 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,717 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,742 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,747 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,752 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,762 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 12:48:46,763 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 12:48:46,763 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 12:48:46,763 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 12:48:46,764 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (1/1) ... [2024-11-13 12:48:46,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:48:46,787 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:48:46,816 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:48:46,832 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 12:48:46,869 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 12:48:46,869 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 12:48:46,870 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 12:48:46,870 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 12:48:47,012 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 12:48:47,014 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 12:48:49,537 INFO L? ?]: Removed 396 outVars from TransFormulas that were not future-live. [2024-11-13 12:48:49,537 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 12:48:49,576 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 12:48:49,577 INFO L316 CfgBuilder]: Removed 10 assume(true) statements. [2024-11-13 12:48:49,577 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 12:48:49 BoogieIcfgContainer [2024-11-13 12:48:49,577 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 12:48:49,578 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 12:48:49,579 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 12:48:49,585 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 12:48:49,586 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:48:49,586 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 12:48:45" (1/3) ... [2024-11-13 12:48:49,588 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77b071a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 12:48:49, skipping insertion in model container [2024-11-13 12:48:49,588 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:48:49,589 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 12:48:46" (2/3) ... [2024-11-13 12:48:49,589 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77b071a4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 12:48:49, skipping insertion in model container [2024-11-13 12:48:49,589 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 12:48:49,590 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 12:48:49" (3/3) ... [2024-11-13 12:48:49,591 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2024-11-13 12:48:49,727 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 12:48:49,728 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 12:48:49,729 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 12:48:49,729 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 12:48:49,729 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 12:48:49,729 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 12:48:49,731 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 12:48:49,731 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 12:48:49,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:49,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-11-13 12:48:49,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:49,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:49,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:49,847 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:49,847 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 12:48:49,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:49,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2024-11-13 12:48:49,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:49,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:49,900 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:49,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:49,915 INFO L745 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 784#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 622#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 807#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 213#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 401#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 295#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 760#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 153#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 41#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 791#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 130#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 505#L781true assume !(0 == ~M_E~0); 822#L781-2true assume !(0 == ~T1_E~0); 846#L786-1true assume !(0 == ~T2_E~0); 21#L791-1true assume !(0 == ~T3_E~0); 385#L796-1true assume !(0 == ~T4_E~0); 355#L801-1true assume !(0 == ~T5_E~0); 387#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 766#L811-1true assume !(0 == ~T7_E~0); 134#L816-1true assume !(0 == ~E_M~0); 626#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 353#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 507#L841-1true assume !(0 == ~E_5~0); 107#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 799#L851-1true assume !(0 == ~E_7~0); 119#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651#L388true assume !(1 == ~m_pc~0); 116#L388-2true is_master_triggered_~__retres1~0#1 := 0; 478#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44#L967true assume !(0 != activate_threads_~tmp~1#1); 767#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11#L407true assume 1 == ~t1_pc~0; 414#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 618#L975true assume !(0 != activate_threads_~tmp___0~0#1); 644#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184#L426true assume !(1 == ~t2_pc~0); 662#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 753#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745#L983true assume !(0 != activate_threads_~tmp___1~0#1); 847#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 241#L445true assume 1 == ~t3_pc~0; 838#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 517#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 441#L991true assume !(0 != activate_threads_~tmp___2~0#1); 512#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415#L464true assume !(1 == ~t4_pc~0); 121#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 52#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 845#L999true assume !(0 != activate_threads_~tmp___3~0#1); 227#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L483true assume 1 == ~t5_pc~0; 737#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 593#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 701#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 175#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461#L502true assume 1 == ~t6_pc~0; 383#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 560#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 711#L521true assume !(1 == ~t7_pc~0); 666#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 42#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 800#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569#L1023-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469#L869true assume !(1 == ~M_E~0); 223#L869-2true assume !(1 == ~T1_E~0); 738#L874-1true assume !(1 == ~T2_E~0); 686#L879-1true assume !(1 == ~T3_E~0); 272#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 5#L889-1true assume !(1 == ~T5_E~0); 139#L894-1true assume !(1 == ~T6_E~0); 836#L899-1true assume !(1 == ~T7_E~0); 431#L904-1true assume !(1 == ~E_M~0); 239#L909-1true assume !(1 == ~E_1~0); 371#L914-1true assume !(1 == ~E_2~0); 394#L919-1true assume !(1 == ~E_3~0); 183#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 705#L934-1true assume !(1 == ~E_6~0); 225#L939-1true assume !(1 == ~E_7~0); 559#L944-1true assume { :end_inline_reset_delta_events } true; 555#L1190-2true [2024-11-13 12:48:49,922 INFO L747 eck$LassoCheckResult]: Loop: 555#L1190-2true assume !false; 135#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136#L756-1true assume !true; 491#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 302#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 59#L781-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 253#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 34#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 632#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L806-3true assume !(0 == ~T6_E~0); 303#L811-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 497#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 663#L821-3true assume 0 == ~E_1~0;~E_1~0 := 1; 777#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 437#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 679#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 112#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L846-3true assume !(0 == ~E_6~0); 321#L851-3true assume 0 == ~E_7~0;~E_7~0 := 1; 55#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 759#L388-27true assume 1 == ~m_pc~0; 608#L389-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 773#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 709#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459#L407-27true assume 1 == ~t1_pc~0; 442#L408-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482#L975-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 337#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108#L426-27true assume !(1 == ~t2_pc~0); 851#L426-29true is_transmit2_triggered_~__retres1~2#1 := 0; 113#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 438#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 707#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 602#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298#L445-27true assume 1 == ~t3_pc~0; 278#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171#L464-27true assume 1 == ~t4_pc~0; 483#L465-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796#L483-27true assume !(1 == ~t5_pc~0); 587#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 56#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1007-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717#L502-27true assume !(1 == ~t6_pc~0); 317#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 706#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume !(0 != activate_threads_~tmp___6~0#1); 328#L1023-29true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 678#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 462#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 252#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 291#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 320#L884-3true assume !(1 == ~T4_E~0); 284#L889-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 85#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 425#L899-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 97#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 269#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 74#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 94#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 619#L924-3true assume !(1 == ~E_4~0); 448#L929-3true assume 1 == ~E_5~0;~E_5~0 := 2; 374#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 565#L939-3true assume 1 == ~E_7~0;~E_7~0 := 2; 100#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 601#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 790#L1209true assume !(0 == start_simulation_~tmp~3#1); 314#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 301#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 544#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 315#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 128#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 555#L1190-2true [2024-11-13 12:48:49,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:49,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2024-11-13 12:48:49,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:49,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549196850] [2024-11-13 12:48:49,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:49,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:50,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:50,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:50,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:50,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549196850] [2024-11-13 12:48:50,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549196850] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:50,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:50,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:50,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988647292] [2024-11-13 12:48:50,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:50,375 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:50,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:50,376 INFO L85 PathProgramCache]: Analyzing trace with hash 485750512, now seen corresponding path program 1 times [2024-11-13 12:48:50,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:50,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259629130] [2024-11-13 12:48:50,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:50,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:50,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:50,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:50,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:50,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259629130] [2024-11-13 12:48:50,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259629130] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:50,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:50,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:48:50,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992365524] [2024-11-13 12:48:50,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:50,473 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:50,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:50,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:50,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:50,513 INFO L87 Difference]: Start difference. First operand has 853 states, 852 states have (on average 1.5140845070422535) internal successors, (1290), 852 states have internal predecessors, (1290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:50,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:50,645 INFO L93 Difference]: Finished difference Result 849 states and 1263 transitions. [2024-11-13 12:48:50,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 849 states and 1263 transitions. [2024-11-13 12:48:50,663 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:50,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 849 states to 843 states and 1257 transitions. [2024-11-13 12:48:50,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:50,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:50,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1257 transitions. [2024-11-13 12:48:50,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:50,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-13 12:48:50,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1257 transitions. [2024-11-13 12:48:50,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:50,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.491103202846975) internal successors, (1257), 842 states have internal predecessors, (1257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:50,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1257 transitions. [2024-11-13 12:48:50,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-13 12:48:50,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:50,807 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1257 transitions. [2024-11-13 12:48:50,807 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 12:48:50,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1257 transitions. [2024-11-13 12:48:50,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:50,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:50,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:50,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:50,828 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:50,829 INFO L745 eck$LassoCheckResult]: Stem: 1961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2549#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2104#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2105#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2227#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2228#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2005#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1796#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1797#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1966#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967#L781 assume !(0 == ~M_E~0); 2444#L781-2 assume !(0 == ~T1_E~0); 2552#L786-1 assume !(0 == ~T2_E~0); 1756#L791-1 assume !(0 == ~T3_E~0); 1757#L796-1 assume !(0 == ~T4_E~0); 2296#L801-1 assume !(0 == ~T5_E~0); 2297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2327#L811-1 assume !(0 == ~T7_E~0); 1973#L816-1 assume !(0 == ~E_M~0); 1974#L821-1 assume !(0 == ~E_1~0); 1787#L826-1 assume !(0 == ~E_2~0); 1788#L831-1 assume !(0 == ~E_3~0); 2099#L836-1 assume !(0 == ~E_4~0); 2100#L841-1 assume !(0 == ~E_5~0); 1924#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1925#L851-1 assume !(0 == ~E_7~0); 1948#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1949#L388 assume !(1 == ~m_pc~0); 1942#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1943#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2422#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1802#L967 assume !(0 != activate_threads_~tmp~1#1); 1803#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732#L407 assume 1 == ~t1_pc~0; 1733#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1737#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1773#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2507#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2059#L426 assume !(1 == ~t2_pc~0); 2060#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2524#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2082#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2545#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2145#L445 assume 1 == ~t3_pc~0; 2146#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2450#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2386#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2354#L464 assume !(1 == ~t4_pc~0); 1952#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1834#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2125#L483 assume 1 == ~t5_pc~0; 2350#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2490#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2463#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2464#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2042#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2043#L502 assume 1 == ~t6_pc~0; 2324#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1862#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1863#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2067#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2264#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2473#L521 assume !(1 == ~t7_pc~0); 2504#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1798#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1799#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2477#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2413#L869 assume !(1 == ~M_E~0); 2118#L869-2 assume !(1 == ~T1_E~0); 2119#L874-1 assume !(1 == ~T2_E~0); 2532#L879-1 assume !(1 == ~T3_E~0); 2193#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1718#L889-1 assume !(1 == ~T5_E~0); 1719#L894-1 assume !(1 == ~T6_E~0); 1981#L899-1 assume !(1 == ~T7_E~0); 2375#L904-1 assume !(1 == ~E_M~0); 2142#L909-1 assume !(1 == ~E_1~0); 2143#L914-1 assume !(1 == ~E_2~0); 2312#L919-1 assume !(1 == ~E_3~0); 2058#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1895#L929-1 assume !(1 == ~E_5~0); 1896#L934-1 assume !(1 == ~E_6~0); 2120#L939-1 assume !(1 == ~E_7~0); 2121#L944-1 assume { :end_inline_reset_delta_events } true; 1964#L1190-2 [2024-11-13 12:48:50,830 INFO L747 eck$LassoCheckResult]: Loop: 1964#L1190-2 assume !false; 1975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1976#L756-1 assume !false; 1977#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2550#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1815#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2106#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2107#L653 assume !(0 != eval_~tmp~0#1); 2158#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1835#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1836#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2164#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1782#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2044#L806-3 assume !(0 == ~T6_E~0); 2045#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2239#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2436#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2525#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2379#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2380#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1935#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1936#L846-3 assume !(0 == ~E_6~0); 2263#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1829#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1830#L388-27 assume 1 == ~m_pc~0; 2499#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2500#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2403#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2404#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2008#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2009#L407-27 assume 1 == ~t1_pc~0; 2387#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2388#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2307#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2280#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1926#L426-27 assume !(1 == ~t2_pc~0); 1927#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1940#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1941#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2381#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2496#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2231#L445-27 assume 1 == ~t3_pc~0; 2205#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1778#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1779#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2232#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2034#L464-27 assume !(1 == ~t4_pc~0); 1776#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1848#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2161#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920#L483-27 assume 1 == ~t5_pc~0; 2455#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1831#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1832#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2468#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2469#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2536#L502-27 assume !(1 == ~t6_pc~0); 2257#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2533#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720#L521-27 assume !(1 == ~t7_pc~0); 1721#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2072#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1774#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1775#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2270#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2162#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2163#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L884-3 assume !(1 == ~T4_E~0); 2216#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1885#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1886#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1906#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1907#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1865#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L924-3 assume !(1 == ~E_4~0); 2393#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2314#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2315#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1911#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1912#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1740#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2031#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2032#L1209 assume !(0 == start_simulation_~tmp~3#1); 2253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1879#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1770#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1765#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1963#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1964#L1190-2 [2024-11-13 12:48:50,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:50,831 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2024-11-13 12:48:50,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:50,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225134093] [2024-11-13 12:48:50,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:50,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:50,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:50,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:50,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:50,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225134093] [2024-11-13 12:48:50,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225134093] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:50,988 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:50,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:50,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573318216] [2024-11-13 12:48:50,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:50,989 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:50,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:50,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1121757826, now seen corresponding path program 1 times [2024-11-13 12:48:50,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:50,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966651312] [2024-11-13 12:48:50,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:50,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:51,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:51,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:51,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:51,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966651312] [2024-11-13 12:48:51,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966651312] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:51,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:51,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:51,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762672892] [2024-11-13 12:48:51,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:51,146 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:51,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:51,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:51,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:51,148 INFO L87 Difference]: Start difference. First operand 843 states and 1257 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:51,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:51,208 INFO L93 Difference]: Finished difference Result 843 states and 1256 transitions. [2024-11-13 12:48:51,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1256 transitions. [2024-11-13 12:48:51,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:51,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1256 transitions. [2024-11-13 12:48:51,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:51,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:51,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1256 transitions. [2024-11-13 12:48:51,233 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:51,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-13 12:48:51,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1256 transitions. [2024-11-13 12:48:51,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:51,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4899169632265719) internal successors, (1256), 842 states have internal predecessors, (1256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:51,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1256 transitions. [2024-11-13 12:48:51,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-13 12:48:51,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:51,287 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1256 transitions. [2024-11-13 12:48:51,287 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 12:48:51,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1256 transitions. [2024-11-13 12:48:51,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:51,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:51,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:51,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:51,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:51,301 INFO L745 eck$LassoCheckResult]: Stem: 3654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4242#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3797#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3798#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3920#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3921#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3698#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3489#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3490#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3660#L781 assume !(0 == ~M_E~0); 4137#L781-2 assume !(0 == ~T1_E~0); 4245#L786-1 assume !(0 == ~T2_E~0); 3449#L791-1 assume !(0 == ~T3_E~0); 3450#L796-1 assume !(0 == ~T4_E~0); 3989#L801-1 assume !(0 == ~T5_E~0); 3990#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4020#L811-1 assume !(0 == ~T7_E~0); 3666#L816-1 assume !(0 == ~E_M~0); 3667#L821-1 assume !(0 == ~E_1~0); 3480#L826-1 assume !(0 == ~E_2~0); 3481#L831-1 assume !(0 == ~E_3~0); 3792#L836-1 assume !(0 == ~E_4~0); 3793#L841-1 assume !(0 == ~E_5~0); 3617#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3618#L851-1 assume !(0 == ~E_7~0); 3641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3642#L388 assume !(1 == ~m_pc~0); 3635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4115#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3495#L967 assume !(0 != activate_threads_~tmp~1#1); 3496#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3425#L407 assume 1 == ~t1_pc~0; 3426#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3466#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4200#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3752#L426 assume !(1 == ~t2_pc~0); 3753#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4217#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3774#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3775#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4238#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3838#L445 assume 1 == ~t3_pc~0; 3839#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4143#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4079#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4047#L464 assume !(1 == ~t4_pc~0); 3645#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3516#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3817#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3818#L483 assume 1 == ~t5_pc~0; 4043#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4183#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4157#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3735#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3736#L502 assume 1 == ~t6_pc~0; 4017#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3555#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3760#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3957#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4166#L521 assume !(1 == ~t7_pc~0); 4197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3491#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3492#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4191#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4170#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4106#L869 assume !(1 == ~M_E~0); 3811#L869-2 assume !(1 == ~T1_E~0); 3812#L874-1 assume !(1 == ~T2_E~0); 4225#L879-1 assume !(1 == ~T3_E~0); 3886#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411#L889-1 assume !(1 == ~T5_E~0); 3412#L894-1 assume !(1 == ~T6_E~0); 3674#L899-1 assume !(1 == ~T7_E~0); 4068#L904-1 assume !(1 == ~E_M~0); 3835#L909-1 assume !(1 == ~E_1~0); 3836#L914-1 assume !(1 == ~E_2~0); 4005#L919-1 assume !(1 == ~E_3~0); 3751#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L929-1 assume !(1 == ~E_5~0); 3589#L934-1 assume !(1 == ~E_6~0); 3813#L939-1 assume !(1 == ~E_7~0); 3814#L944-1 assume { :end_inline_reset_delta_events } true; 3657#L1190-2 [2024-11-13 12:48:51,303 INFO L747 eck$LassoCheckResult]: Loop: 3657#L1190-2 assume !false; 3668#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3669#L756-1 assume !false; 3670#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4243#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3508#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3799#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3800#L653 assume !(0 != eval_~tmp~0#1); 3851#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3931#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3528#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3857#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3474#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3737#L806-3 assume !(0 == ~T6_E~0); 3738#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3932#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4129#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4218#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4072#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4073#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629#L846-3 assume !(0 == ~E_6~0); 3956#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523#L388-27 assume 1 == ~m_pc~0; 4192#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4193#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4096#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4097#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3701#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3702#L407-27 assume 1 == ~t1_pc~0; 4080#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3999#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4000#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3973#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3619#L426-27 assume !(1 == ~t2_pc~0); 3620#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 3633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4074#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4189#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3924#L445-27 assume 1 == ~t3_pc~0; 3898#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3471#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3472#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3925#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4010#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3727#L464-27 assume 1 == ~t4_pc~0; 3728#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3470#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3541#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3854#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3612#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3613#L483-27 assume 1 == ~t5_pc~0; 4148#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3525#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4161#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4162#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4229#L502-27 assume 1 == ~t6_pc~0; 4230#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3951#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4226#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4102#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4103#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3413#L521-27 assume !(1 == ~t7_pc~0); 3414#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3765#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3713#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3467#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 3468#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3963#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4099#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3856#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3916#L884-3 assume !(1 == ~T4_E~0); 3909#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3578#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3579#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3599#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3600#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3558#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L924-3 assume !(1 == ~E_4~0); 4086#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4007#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4008#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3604#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3605#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3433#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3724#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3725#L1209 assume !(0 == start_simulation_~tmp~3#1); 3946#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3929#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3572#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3462#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3463#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3458#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3459#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3657#L1190-2 [2024-11-13 12:48:51,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:51,303 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2024-11-13 12:48:51,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:51,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474938091] [2024-11-13 12:48:51,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:51,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:51,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:51,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:51,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:51,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474938091] [2024-11-13 12:48:51,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474938091] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:51,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:51,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:51,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482382344] [2024-11-13 12:48:51,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:51,425 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:51,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:51,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1880711040, now seen corresponding path program 1 times [2024-11-13 12:48:51,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:51,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094654081] [2024-11-13 12:48:51,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:51,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:51,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:51,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:51,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:51,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094654081] [2024-11-13 12:48:51,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094654081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:51,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:51,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:51,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780602061] [2024-11-13 12:48:51,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:51,618 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:51,618 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:51,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:51,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:51,619 INFO L87 Difference]: Start difference. First operand 843 states and 1256 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:51,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:51,665 INFO L93 Difference]: Finished difference Result 843 states and 1255 transitions. [2024-11-13 12:48:51,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1255 transitions. [2024-11-13 12:48:51,675 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:51,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1255 transitions. [2024-11-13 12:48:51,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:51,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:51,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1255 transitions. [2024-11-13 12:48:51,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:51,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-13 12:48:51,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1255 transitions. [2024-11-13 12:48:51,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:51,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4887307236061684) internal successors, (1255), 842 states have internal predecessors, (1255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:51,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1255 transitions. [2024-11-13 12:48:51,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-13 12:48:51,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:51,723 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1255 transitions. [2024-11-13 12:48:51,724 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 12:48:51,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1255 transitions. [2024-11-13 12:48:51,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:51,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:51,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:51,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:51,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:51,740 INFO L745 eck$LassoCheckResult]: Stem: 5347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5896#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5490#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5491#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5613#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5614#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5391#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5182#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5183#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5352#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5353#L781 assume !(0 == ~M_E~0); 5830#L781-2 assume !(0 == ~T1_E~0); 5938#L786-1 assume !(0 == ~T2_E~0); 5142#L791-1 assume !(0 == ~T3_E~0); 5143#L796-1 assume !(0 == ~T4_E~0); 5682#L801-1 assume !(0 == ~T5_E~0); 5683#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5713#L811-1 assume !(0 == ~T7_E~0); 5359#L816-1 assume !(0 == ~E_M~0); 5360#L821-1 assume !(0 == ~E_1~0); 5173#L826-1 assume !(0 == ~E_2~0); 5174#L831-1 assume !(0 == ~E_3~0); 5485#L836-1 assume !(0 == ~E_4~0); 5486#L841-1 assume !(0 == ~E_5~0); 5310#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5311#L851-1 assume !(0 == ~E_7~0); 5334#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335#L388 assume !(1 == ~m_pc~0); 5328#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5329#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5808#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5188#L967 assume !(0 != activate_threads_~tmp~1#1); 5189#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5118#L407 assume 1 == ~t1_pc~0; 5119#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5123#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5159#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5893#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5445#L426 assume !(1 == ~t2_pc~0); 5446#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5910#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5468#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5531#L445 assume 1 == ~t3_pc~0; 5532#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5836#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5117#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5772#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L464 assume !(1 == ~t4_pc~0); 5338#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5208#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5220#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5510#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5511#L483 assume 1 == ~t5_pc~0; 5736#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5876#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5850#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5428#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5429#L502 assume 1 == ~t6_pc~0; 5710#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5248#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5453#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5650#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5859#L521 assume !(1 == ~t7_pc~0); 5890#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5184#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5185#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5884#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5863#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5799#L869 assume !(1 == ~M_E~0); 5504#L869-2 assume !(1 == ~T1_E~0); 5505#L874-1 assume !(1 == ~T2_E~0); 5918#L879-1 assume !(1 == ~T3_E~0); 5579#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5104#L889-1 assume !(1 == ~T5_E~0); 5105#L894-1 assume !(1 == ~T6_E~0); 5367#L899-1 assume !(1 == ~T7_E~0); 5761#L904-1 assume !(1 == ~E_M~0); 5528#L909-1 assume !(1 == ~E_1~0); 5529#L914-1 assume !(1 == ~E_2~0); 5698#L919-1 assume !(1 == ~E_3~0); 5444#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5281#L929-1 assume !(1 == ~E_5~0); 5282#L934-1 assume !(1 == ~E_6~0); 5506#L939-1 assume !(1 == ~E_7~0); 5507#L944-1 assume { :end_inline_reset_delta_events } true; 5350#L1190-2 [2024-11-13 12:48:51,740 INFO L747 eck$LassoCheckResult]: Loop: 5350#L1190-2 assume !false; 5361#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5362#L756-1 assume !false; 5363#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5936#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5201#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5493#L653 assume !(0 != eval_~tmp~0#1); 5544#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5624#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5221#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5222#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5550#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5168#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5430#L806-3 assume !(0 == ~T6_E~0); 5431#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5822#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5911#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5765#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5766#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5321#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5322#L846-3 assume !(0 == ~E_6~0); 5649#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5215#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5216#L388-27 assume 1 == ~m_pc~0; 5885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5789#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5790#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5394#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5395#L407-27 assume 1 == ~t1_pc~0; 5773#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5774#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5693#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5666#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5312#L426-27 assume !(1 == ~t2_pc~0); 5313#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 5326#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5327#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5767#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5882#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5617#L445-27 assume 1 == ~t3_pc~0; 5591#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5164#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5618#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5703#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5420#L464-27 assume !(1 == ~t4_pc~0); 5162#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5163#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5234#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5547#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5306#L483-27 assume 1 == ~t5_pc~0; 5841#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5218#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5854#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5855#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5922#L502-27 assume 1 == ~t6_pc~0; 5923#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5644#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5919#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5795#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5796#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5106#L521-27 assume !(1 == ~t7_pc~0); 5107#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5458#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5406#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5160#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 5161#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5656#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5792#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5548#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5549#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L884-3 assume !(1 == ~T4_E~0); 5602#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5271#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5272#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5293#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5250#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5251#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5287#L924-3 assume !(1 == ~E_4~0); 5779#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5700#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5701#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5297#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5298#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5126#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5418#L1209 assume !(0 == start_simulation_~tmp~3#1); 5639#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5622#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5265#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5155#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5156#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5151#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5349#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5350#L1190-2 [2024-11-13 12:48:51,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:51,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2024-11-13 12:48:51,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:51,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742537036] [2024-11-13 12:48:51,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:51,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:51,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:51,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:51,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:51,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742537036] [2024-11-13 12:48:51,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742537036] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:51,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:51,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:51,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651039161] [2024-11-13 12:48:51,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:51,851 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:51,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:51,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1606932545, now seen corresponding path program 1 times [2024-11-13 12:48:51,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:51,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958496845] [2024-11-13 12:48:51,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:51,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:51,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:51,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:51,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:51,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958496845] [2024-11-13 12:48:51,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958496845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:51,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:51,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:51,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538894021] [2024-11-13 12:48:51,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:51,985 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:51,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:51,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:51,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:51,986 INFO L87 Difference]: Start difference. First operand 843 states and 1255 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:52,028 INFO L93 Difference]: Finished difference Result 843 states and 1254 transitions. [2024-11-13 12:48:52,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1254 transitions. [2024-11-13 12:48:52,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1254 transitions. [2024-11-13 12:48:52,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:52,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:52,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1254 transitions. [2024-11-13 12:48:52,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:52,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-13 12:48:52,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1254 transitions. [2024-11-13 12:48:52,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:52,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4875444839857652) internal successors, (1254), 842 states have internal predecessors, (1254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1254 transitions. [2024-11-13 12:48:52,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-13 12:48:52,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:52,083 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1254 transitions. [2024-11-13 12:48:52,083 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 12:48:52,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1254 transitions. [2024-11-13 12:48:52,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:52,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:52,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,099 INFO L745 eck$LassoCheckResult]: Stem: 7040#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7628#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7183#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7184#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7306#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7307#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7084#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6875#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6876#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7048#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7049#L781 assume !(0 == ~M_E~0); 7523#L781-2 assume !(0 == ~T1_E~0); 7631#L786-1 assume !(0 == ~T2_E~0); 6838#L791-1 assume !(0 == ~T3_E~0); 6839#L796-1 assume !(0 == ~T4_E~0); 7375#L801-1 assume !(0 == ~T5_E~0); 7376#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7406#L811-1 assume !(0 == ~T7_E~0); 7052#L816-1 assume !(0 == ~E_M~0); 7053#L821-1 assume !(0 == ~E_1~0); 6866#L826-1 assume !(0 == ~E_2~0); 6867#L831-1 assume !(0 == ~E_3~0); 7178#L836-1 assume !(0 == ~E_4~0); 7179#L841-1 assume !(0 == ~E_5~0); 7003#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7004#L851-1 assume !(0 == ~E_7~0); 7027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7028#L388 assume !(1 == ~m_pc~0); 7021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 7022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7501#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6881#L967 assume !(0 != activate_threads_~tmp~1#1); 6882#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6811#L407 assume 1 == ~t1_pc~0; 6812#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6819#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6854#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7586#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L426 assume !(1 == ~t2_pc~0); 7139#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7603#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7161#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7624#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7224#L445 assume 1 == ~t3_pc~0; 7225#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7529#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6810#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7465#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7433#L464 assume !(1 == ~t4_pc~0); 7031#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6913#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7203#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7204#L483 assume 1 == ~t5_pc~0; 7429#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7569#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7543#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7123#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7124#L502 assume 1 == ~t6_pc~0; 7404#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6941#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7148#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7343#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7552#L521 assume !(1 == ~t7_pc~0); 7583#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6877#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6878#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7577#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7556#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7494#L869 assume !(1 == ~M_E~0); 7197#L869-2 assume !(1 == ~T1_E~0); 7198#L874-1 assume !(1 == ~T2_E~0); 7611#L879-1 assume !(1 == ~T3_E~0); 7272#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6797#L889-1 assume !(1 == ~T5_E~0); 6798#L894-1 assume !(1 == ~T6_E~0); 7063#L899-1 assume !(1 == ~T7_E~0); 7455#L904-1 assume !(1 == ~E_M~0); 7221#L909-1 assume !(1 == ~E_1~0); 7222#L914-1 assume !(1 == ~E_2~0); 7392#L919-1 assume !(1 == ~E_3~0); 7137#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6974#L929-1 assume !(1 == ~E_5~0); 6975#L934-1 assume !(1 == ~E_6~0); 7201#L939-1 assume !(1 == ~E_7~0); 7202#L944-1 assume { :end_inline_reset_delta_events } true; 7043#L1190-2 [2024-11-13 12:48:52,100 INFO L747 eck$LassoCheckResult]: Loop: 7043#L1190-2 assume !false; 7054#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7055#L756-1 assume !false; 7056#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7629#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6896#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7186#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7187#L653 assume !(0 != eval_~tmp~0#1); 7240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7318#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6914#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6915#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7243#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6860#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6861#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7121#L806-3 assume !(0 == ~T6_E~0); 7122#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7515#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7458#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7459#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7015#L846-3 assume !(0 == ~E_6~0); 7342#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6909#L388-27 assume 1 == ~m_pc~0; 7578#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7579#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7482#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7483#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7087#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7088#L407-27 assume 1 == ~t1_pc~0; 7466#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7467#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7386#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7359#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7005#L426-27 assume !(1 == ~t2_pc~0); 7006#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 7019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7020#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7460#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7575#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7310#L445-27 assume 1 == ~t3_pc~0; 7282#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6857#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6858#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7395#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7113#L464-27 assume !(1 == ~t4_pc~0); 6855#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6856#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6927#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7238#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6998#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6999#L483-27 assume 1 == ~t5_pc~0; 7534#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7547#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7548#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7615#L502-27 assume 1 == ~t6_pc~0; 7616#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7337#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7612#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7488#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7489#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6799#L521-27 assume !(1 == ~t7_pc~0); 6800#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 7151#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6852#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 6853#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7349#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7485#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7241#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7242#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7302#L884-3 assume !(1 == ~T4_E~0); 7295#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6964#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6965#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6985#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6986#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6943#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6944#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6980#L924-3 assume !(1 == ~E_4~0); 7472#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7393#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7394#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6990#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6991#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6817#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7110#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7111#L1209 assume !(0 == start_simulation_~tmp~3#1); 7332#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7315#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6958#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6849#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6845#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7042#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1190-2 [2024-11-13 12:48:52,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2024-11-13 12:48:52,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081554118] [2024-11-13 12:48:52,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081554118] [2024-11-13 12:48:52,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081554118] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863557213] [2024-11-13 12:48:52,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,196 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:52,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1606932545, now seen corresponding path program 2 times [2024-11-13 12:48:52,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263314724] [2024-11-13 12:48:52,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263314724] [2024-11-13 12:48:52,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263314724] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424850472] [2024-11-13 12:48:52,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,312 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:52,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:52,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:52,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:52,314 INFO L87 Difference]: Start difference. First operand 843 states and 1254 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:52,346 INFO L93 Difference]: Finished difference Result 843 states and 1253 transitions. [2024-11-13 12:48:52,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1253 transitions. [2024-11-13 12:48:52,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1253 transitions. [2024-11-13 12:48:52,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:52,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:52,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1253 transitions. [2024-11-13 12:48:52,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:52,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-13 12:48:52,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1253 transitions. [2024-11-13 12:48:52,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:52,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4863582443653618) internal successors, (1253), 842 states have internal predecessors, (1253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1253 transitions. [2024-11-13 12:48:52,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-13 12:48:52,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:52,423 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1253 transitions. [2024-11-13 12:48:52,424 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 12:48:52,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1253 transitions. [2024-11-13 12:48:52,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:52,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:52,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,434 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,434 INFO L745 eck$LassoCheckResult]: Stem: 8733#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9321#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8876#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8877#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8999#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9000#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8777#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8568#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8569#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8741#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8742#L781 assume !(0 == ~M_E~0); 9216#L781-2 assume !(0 == ~T1_E~0); 9324#L786-1 assume !(0 == ~T2_E~0); 8528#L791-1 assume !(0 == ~T3_E~0); 8529#L796-1 assume !(0 == ~T4_E~0); 9068#L801-1 assume !(0 == ~T5_E~0); 9069#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9099#L811-1 assume !(0 == ~T7_E~0); 8745#L816-1 assume !(0 == ~E_M~0); 8746#L821-1 assume !(0 == ~E_1~0); 8559#L826-1 assume !(0 == ~E_2~0); 8560#L831-1 assume !(0 == ~E_3~0); 8871#L836-1 assume !(0 == ~E_4~0); 8872#L841-1 assume !(0 == ~E_5~0); 8696#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8697#L851-1 assume !(0 == ~E_7~0); 8720#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8721#L388 assume !(1 == ~m_pc~0); 8714#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9194#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8574#L967 assume !(0 != activate_threads_~tmp~1#1); 8575#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8504#L407 assume 1 == ~t1_pc~0; 8505#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8512#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8547#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9279#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8831#L426 assume !(1 == ~t2_pc~0); 8832#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9296#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8854#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9317#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8917#L445 assume 1 == ~t3_pc~0; 8918#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9222#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8503#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9158#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9126#L464 assume !(1 == ~t4_pc~0); 8724#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8594#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8595#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8606#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8896#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8897#L483 assume 1 == ~t5_pc~0; 9122#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9262#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9235#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9236#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8814#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L502 assume 1 == ~t6_pc~0; 9097#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8634#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8839#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 9036#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9245#L521 assume !(1 == ~t7_pc~0); 9276#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8570#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8571#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9270#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9249#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9185#L869 assume !(1 == ~M_E~0); 8890#L869-2 assume !(1 == ~T1_E~0); 8891#L874-1 assume !(1 == ~T2_E~0); 9304#L879-1 assume !(1 == ~T3_E~0); 8965#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8490#L889-1 assume !(1 == ~T5_E~0); 8491#L894-1 assume !(1 == ~T6_E~0); 8753#L899-1 assume !(1 == ~T7_E~0); 9148#L904-1 assume !(1 == ~E_M~0); 8914#L909-1 assume !(1 == ~E_1~0); 8915#L914-1 assume !(1 == ~E_2~0); 9084#L919-1 assume !(1 == ~E_3~0); 8830#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8667#L929-1 assume !(1 == ~E_5~0); 8668#L934-1 assume !(1 == ~E_6~0); 8892#L939-1 assume !(1 == ~E_7~0); 8893#L944-1 assume { :end_inline_reset_delta_events } true; 8736#L1190-2 [2024-11-13 12:48:52,435 INFO L747 eck$LassoCheckResult]: Loop: 8736#L1190-2 assume !false; 8747#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8748#L756-1 assume !false; 8749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9322#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8589#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8879#L653 assume !(0 != eval_~tmp~0#1); 8931#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9009#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9010#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8607#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8608#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8936#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8553#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8554#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8816#L806-3 assume !(0 == ~T6_E~0); 8817#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9011#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9208#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9297#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9152#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8707#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8708#L846-3 assume !(0 == ~E_6~0); 9035#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8601#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L388-27 assume 1 == ~m_pc~0; 9271#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9272#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9175#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9176#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8780#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8781#L407-27 assume 1 == ~t1_pc~0; 9159#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9160#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9078#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9079#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9052#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8698#L426-27 assume !(1 == ~t2_pc~0); 8699#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8712#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8713#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9153#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9268#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9003#L445-27 assume 1 == ~t3_pc~0; 8977#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8550#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9004#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9088#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8806#L464-27 assume !(1 == ~t4_pc~0); 8548#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8691#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8692#L483-27 assume 1 == ~t5_pc~0; 9227#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8604#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9240#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9241#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9308#L502-27 assume !(1 == ~t6_pc~0); 9029#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9030#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9305#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9181#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8492#L521-27 assume !(1 == ~t7_pc~0); 8493#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8844#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8792#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8545#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 8546#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9040#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9178#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8934#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8935#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8995#L884-3 assume !(1 == ~T4_E~0); 8988#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8657#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8658#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8678#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8679#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8636#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8637#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8673#L924-3 assume !(1 == ~E_4~0); 9165#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9086#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9087#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8683#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8684#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8804#L1209 assume !(0 == start_simulation_~tmp~3#1); 9025#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9008#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8651#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8542#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8537#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8538#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8735#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8736#L1190-2 [2024-11-13 12:48:52,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,436 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2024-11-13 12:48:52,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569345377] [2024-11-13 12:48:52,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569345377] [2024-11-13 12:48:52,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569345377] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,510 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639811962] [2024-11-13 12:48:52,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,511 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:52,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1121757826, now seen corresponding path program 2 times [2024-11-13 12:48:52,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784706102] [2024-11-13 12:48:52,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784706102] [2024-11-13 12:48:52,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784706102] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929719954] [2024-11-13 12:48:52,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,603 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:52,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:52,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:52,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:52,604 INFO L87 Difference]: Start difference. First operand 843 states and 1253 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:52,634 INFO L93 Difference]: Finished difference Result 843 states and 1252 transitions. [2024-11-13 12:48:52,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1252 transitions. [2024-11-13 12:48:52,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1252 transitions. [2024-11-13 12:48:52,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:52,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:52,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1252 transitions. [2024-11-13 12:48:52,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:52,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-13 12:48:52,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1252 transitions. [2024-11-13 12:48:52,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:52,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4851720047449586) internal successors, (1252), 842 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1252 transitions. [2024-11-13 12:48:52,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-13 12:48:52,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:52,677 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1252 transitions. [2024-11-13 12:48:52,679 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 12:48:52,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1252 transitions. [2024-11-13 12:48:52,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:52,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:52,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,688 INFO L745 eck$LassoCheckResult]: Stem: 10426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11014#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10569#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10570#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10692#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10693#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10470#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10261#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10262#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10431#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10432#L781 assume !(0 == ~M_E~0); 10909#L781-2 assume !(0 == ~T1_E~0); 11017#L786-1 assume !(0 == ~T2_E~0); 10221#L791-1 assume !(0 == ~T3_E~0); 10222#L796-1 assume !(0 == ~T4_E~0); 10761#L801-1 assume !(0 == ~T5_E~0); 10762#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10792#L811-1 assume !(0 == ~T7_E~0); 10438#L816-1 assume !(0 == ~E_M~0); 10439#L821-1 assume !(0 == ~E_1~0); 10252#L826-1 assume !(0 == ~E_2~0); 10253#L831-1 assume !(0 == ~E_3~0); 10564#L836-1 assume !(0 == ~E_4~0); 10565#L841-1 assume !(0 == ~E_5~0); 10389#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L851-1 assume !(0 == ~E_7~0); 10413#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10414#L388 assume !(1 == ~m_pc~0); 10407#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10408#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10887#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10267#L967 assume !(0 != activate_threads_~tmp~1#1); 10268#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10197#L407 assume 1 == ~t1_pc~0; 10198#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10202#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10238#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10972#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10524#L426 assume !(1 == ~t2_pc~0); 10525#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10989#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10546#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 11010#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10610#L445 assume 1 == ~t3_pc~0; 10611#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10915#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10195#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10196#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10851#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10819#L464 assume !(1 == ~t4_pc~0); 10417#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10287#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10299#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10589#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10590#L483 assume 1 == ~t5_pc~0; 10815#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10955#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10929#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10507#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10508#L502 assume 1 == ~t6_pc~0; 10789#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10327#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10328#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10532#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10729#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L521 assume !(1 == ~t7_pc~0); 10969#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10263#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10963#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10942#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10878#L869 assume !(1 == ~M_E~0); 10583#L869-2 assume !(1 == ~T1_E~0); 10584#L874-1 assume !(1 == ~T2_E~0); 10997#L879-1 assume !(1 == ~T3_E~0); 10658#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10183#L889-1 assume !(1 == ~T5_E~0); 10184#L894-1 assume !(1 == ~T6_E~0); 10446#L899-1 assume !(1 == ~T7_E~0); 10840#L904-1 assume !(1 == ~E_M~0); 10607#L909-1 assume !(1 == ~E_1~0); 10608#L914-1 assume !(1 == ~E_2~0); 10777#L919-1 assume !(1 == ~E_3~0); 10523#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10360#L929-1 assume !(1 == ~E_5~0); 10361#L934-1 assume !(1 == ~E_6~0); 10585#L939-1 assume !(1 == ~E_7~0); 10586#L944-1 assume { :end_inline_reset_delta_events } true; 10429#L1190-2 [2024-11-13 12:48:52,688 INFO L747 eck$LassoCheckResult]: Loop: 10429#L1190-2 assume !false; 10440#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10441#L756-1 assume !false; 10442#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11015#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10280#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10572#L653 assume !(0 != eval_~tmp~0#1); 10623#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10703#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10300#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10301#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10629#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10246#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10509#L806-3 assume !(0 == ~T6_E~0); 10510#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10704#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10901#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10990#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10844#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10845#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10400#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L846-3 assume !(0 == ~E_6~0); 10728#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10294#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10295#L388-27 assume 1 == ~m_pc~0; 10964#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10965#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10868#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10869#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10473#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10474#L407-27 assume 1 == ~t1_pc~0; 10852#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10853#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10745#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10391#L426-27 assume !(1 == ~t2_pc~0); 10392#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10405#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10406#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10961#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10696#L445-27 assume 1 == ~t3_pc~0; 10670#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10243#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10244#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10697#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10782#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10499#L464-27 assume !(1 == ~t4_pc~0); 10241#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 10242#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10313#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10626#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10384#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10385#L483-27 assume 1 == ~t5_pc~0; 10920#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10933#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10934#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11001#L502-27 assume !(1 == ~t6_pc~0); 10722#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10723#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10998#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10875#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10185#L521-27 assume !(1 == ~t7_pc~0); 10186#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10537#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10485#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10239#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 10240#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10735#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10871#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10627#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10628#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10688#L884-3 assume !(1 == ~T4_E~0); 10681#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10350#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10351#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10371#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10372#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10329#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10366#L924-3 assume !(1 == ~E_4~0); 10858#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10779#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10780#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10376#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10377#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10205#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10497#L1209 assume !(0 == start_simulation_~tmp~3#1); 10718#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10701#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10344#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10234#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10235#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10230#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10428#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10429#L1190-2 [2024-11-13 12:48:52,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2024-11-13 12:48:52,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375509314] [2024-11-13 12:48:52,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375509314] [2024-11-13 12:48:52,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375509314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,745 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234985595] [2024-11-13 12:48:52,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,746 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:52,746 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1121757826, now seen corresponding path program 3 times [2024-11-13 12:48:52,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222661465] [2024-11-13 12:48:52,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:52,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:52,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:52,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222661465] [2024-11-13 12:48:52,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222661465] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:52,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:52,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:52,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011296637] [2024-11-13 12:48:52,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:52,817 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:52,817 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:52,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:52,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:52,818 INFO L87 Difference]: Start difference. First operand 843 states and 1252 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:52,848 INFO L93 Difference]: Finished difference Result 843 states and 1251 transitions. [2024-11-13 12:48:52,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 1251 transitions. [2024-11-13 12:48:52,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 843 states and 1251 transitions. [2024-11-13 12:48:52,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 843 [2024-11-13 12:48:52,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 843 [2024-11-13 12:48:52,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 843 states and 1251 transitions. [2024-11-13 12:48:52,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:52,865 INFO L218 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-13 12:48:52,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 843 states and 1251 transitions. [2024-11-13 12:48:52,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 843 to 843. [2024-11-13 12:48:52,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 843 states, 843 states have (on average 1.4839857651245552) internal successors, (1251), 842 states have internal predecessors, (1251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:52,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 843 states and 1251 transitions. [2024-11-13 12:48:52,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-13 12:48:52,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:52,890 INFO L424 stractBuchiCegarLoop]: Abstraction has 843 states and 1251 transitions. [2024-11-13 12:48:52,890 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 12:48:52,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 843 states and 1251 transitions. [2024-11-13 12:48:52,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 740 [2024-11-13 12:48:52,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:52,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:52,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:52,898 INFO L745 eck$LassoCheckResult]: Stem: 12119#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12120#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12667#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12668#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12707#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12262#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12263#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12385#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12386#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12163#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11954#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11955#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12124#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L781 assume !(0 == ~M_E~0); 12602#L781-2 assume !(0 == ~T1_E~0); 12710#L786-1 assume !(0 == ~T2_E~0); 11914#L791-1 assume !(0 == ~T3_E~0); 11915#L796-1 assume !(0 == ~T4_E~0); 12454#L801-1 assume !(0 == ~T5_E~0); 12455#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12485#L811-1 assume !(0 == ~T7_E~0); 12131#L816-1 assume !(0 == ~E_M~0); 12132#L821-1 assume !(0 == ~E_1~0); 11945#L826-1 assume !(0 == ~E_2~0); 11946#L831-1 assume !(0 == ~E_3~0); 12257#L836-1 assume !(0 == ~E_4~0); 12258#L841-1 assume !(0 == ~E_5~0); 12082#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12083#L851-1 assume !(0 == ~E_7~0); 12106#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12107#L388 assume !(1 == ~m_pc~0); 12100#L388-2 is_master_triggered_~__retres1~0#1 := 0; 12101#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12580#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11960#L967 assume !(0 != activate_threads_~tmp~1#1); 11961#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11890#L407 assume 1 == ~t1_pc~0; 11891#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11895#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11896#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11931#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12665#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12217#L426 assume !(1 == ~t2_pc~0); 12218#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12682#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12240#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12703#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12303#L445 assume 1 == ~t3_pc~0; 12304#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11888#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11889#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12544#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12512#L464 assume !(1 == ~t4_pc~0); 12110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11980#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11992#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12282#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12283#L483 assume 1 == ~t5_pc~0; 12508#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12648#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12621#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12622#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12200#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12201#L502 assume 1 == ~t6_pc~0; 12482#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12020#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12021#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12422#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12631#L521 assume !(1 == ~t7_pc~0); 12662#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11956#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11957#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12656#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12635#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12571#L869 assume !(1 == ~M_E~0); 12276#L869-2 assume !(1 == ~T1_E~0); 12277#L874-1 assume !(1 == ~T2_E~0); 12690#L879-1 assume !(1 == ~T3_E~0); 12351#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L889-1 assume !(1 == ~T5_E~0); 11877#L894-1 assume !(1 == ~T6_E~0); 12139#L899-1 assume !(1 == ~T7_E~0); 12533#L904-1 assume !(1 == ~E_M~0); 12300#L909-1 assume !(1 == ~E_1~0); 12301#L914-1 assume !(1 == ~E_2~0); 12470#L919-1 assume !(1 == ~E_3~0); 12216#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12053#L929-1 assume !(1 == ~E_5~0); 12054#L934-1 assume !(1 == ~E_6~0); 12278#L939-1 assume !(1 == ~E_7~0); 12279#L944-1 assume { :end_inline_reset_delta_events } true; 12122#L1190-2 [2024-11-13 12:48:52,899 INFO L747 eck$LassoCheckResult]: Loop: 12122#L1190-2 assume !false; 12133#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12134#L756-1 assume !false; 12135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12708#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11973#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12264#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12265#L653 assume !(0 != eval_~tmp~0#1); 12316#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12396#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11993#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11994#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12322#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11939#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11940#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12202#L806-3 assume !(0 == ~T6_E~0); 12203#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12397#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12594#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12683#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12537#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12538#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12094#L846-3 assume !(0 == ~E_6~0); 12421#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11987#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11988#L388-27 assume 1 == ~m_pc~0; 12657#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12658#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12561#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12166#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12167#L407-27 assume 1 == ~t1_pc~0; 12545#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12464#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12465#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12438#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426-27 assume !(1 == ~t2_pc~0); 12085#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 12098#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12099#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12539#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12654#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12389#L445-27 assume 1 == ~t3_pc~0; 12363#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11936#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11937#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12390#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12475#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12192#L464-27 assume 1 == ~t4_pc~0; 12193#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11935#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12006#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12319#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12077#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12078#L483-27 assume 1 == ~t5_pc~0; 12613#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11990#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12626#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12627#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12694#L502-27 assume 1 == ~t6_pc~0; 12695#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12416#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12691#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12567#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12568#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11878#L521-27 assume !(1 == ~t7_pc~0); 11879#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12230#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12178#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11932#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 11933#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12428#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12564#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12320#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12321#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12381#L884-3 assume !(1 == ~T4_E~0); 12374#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12043#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12044#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12064#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12065#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12022#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12023#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12059#L924-3 assume !(1 == ~E_4~0); 12551#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12472#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12473#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12069#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12070#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11898#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12189#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12190#L1209 assume !(0 == start_simulation_~tmp~3#1); 12411#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12394#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12037#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11928#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11923#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11924#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12121#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12122#L1190-2 [2024-11-13 12:48:52,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:52,900 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2024-11-13 12:48:52,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:52,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546921233] [2024-11-13 12:48:52,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:52,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:52,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:53,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:53,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:53,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546921233] [2024-11-13 12:48:53,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546921233] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:53,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:53,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:53,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948140069] [2024-11-13 12:48:53,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:53,016 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:53,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:53,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1880711040, now seen corresponding path program 2 times [2024-11-13 12:48:53,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:53,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414763588] [2024-11-13 12:48:53,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:53,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:53,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:53,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:53,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:53,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414763588] [2024-11-13 12:48:53,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414763588] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:53,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:53,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:53,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814725072] [2024-11-13 12:48:53,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:53,092 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:53,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:53,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:48:53,093 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:48:53,093 INFO L87 Difference]: Start difference. First operand 843 states and 1251 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:53,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:53,300 INFO L93 Difference]: Finished difference Result 1525 states and 2254 transitions. [2024-11-13 12:48:53,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1525 states and 2254 transitions. [2024-11-13 12:48:53,318 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-11-13 12:48:53,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-11-13 12:48:53,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1525 [2024-11-13 12:48:53,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1525 [2024-11-13 12:48:53,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1525 states and 2254 transitions. [2024-11-13 12:48:53,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:53,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-13 12:48:53,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1525 states and 2254 transitions. [2024-11-13 12:48:53,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1525 to 1525. [2024-11-13 12:48:53,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.4780327868852459) internal successors, (2254), 1524 states have internal predecessors, (2254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:53,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2254 transitions. [2024-11-13 12:48:53,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-13 12:48:53,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:48:53,387 INFO L424 stractBuchiCegarLoop]: Abstraction has 1525 states and 2254 transitions. [2024-11-13 12:48:53,388 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 12:48:53,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2254 transitions. [2024-11-13 12:48:53,398 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1406 [2024-11-13 12:48:53,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:53,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:53,401 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:53,401 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:53,402 INFO L745 eck$LassoCheckResult]: Stem: 14500#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15091#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15092#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15148#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14646#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14647#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14778#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14779#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14545#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14332#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14333#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14505#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14506#L781 assume !(0 == ~M_E~0); 15018#L781-2 assume !(0 == ~T1_E~0); 15154#L786-1 assume !(0 == ~T2_E~0); 14292#L791-1 assume !(0 == ~T3_E~0); 14293#L796-1 assume !(0 == ~T4_E~0); 14857#L801-1 assume !(0 == ~T5_E~0); 14858#L806-1 assume !(0 == ~T6_E~0); 14890#L811-1 assume !(0 == ~T7_E~0); 14512#L816-1 assume !(0 == ~E_M~0); 14513#L821-1 assume !(0 == ~E_1~0); 14323#L826-1 assume !(0 == ~E_2~0); 14324#L831-1 assume !(0 == ~E_3~0); 14641#L836-1 assume !(0 == ~E_4~0); 14642#L841-1 assume !(0 == ~E_5~0); 14462#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14463#L851-1 assume !(0 == ~E_7~0); 14486#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14487#L388 assume !(1 == ~m_pc~0); 14480#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14481#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14994#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14338#L967 assume !(0 != activate_threads_~tmp~1#1); 14339#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14268#L407 assume 1 == ~t1_pc~0; 14269#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14273#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14274#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14309#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15087#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14600#L426 assume !(1 == ~t2_pc~0); 14601#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15109#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14623#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14624#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15141#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14689#L445 assume 1 == ~t3_pc~0; 14690#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15024#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14267#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14955#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14922#L464 assume !(1 == ~t4_pc~0); 14490#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14358#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14370#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14666#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14667#L483 assume 1 == ~t5_pc~0; 14917#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15069#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15038#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15039#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14583#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14584#L502 assume 1 == ~t6_pc~0; 14887#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14398#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14609#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14820#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15051#L521 assume !(1 == ~t7_pc~0); 15083#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14334#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14335#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15077#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15055#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14983#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14660#L869-2 assume !(1 == ~T1_E~0); 14661#L874-1 assume !(1 == ~T2_E~0); 15121#L879-1 assume !(1 == ~T3_E~0); 14740#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14741#L889-1 assume !(1 == ~T5_E~0); 15342#L894-1 assume !(1 == ~T6_E~0); 14520#L899-1 assume !(1 == ~T7_E~0); 15338#L904-1 assume !(1 == ~E_M~0); 15336#L909-1 assume !(1 == ~E_1~0); 15334#L914-1 assume !(1 == ~E_2~0); 15332#L919-1 assume !(1 == ~E_3~0); 15330#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15327#L929-1 assume !(1 == ~E_5~0); 15325#L934-1 assume !(1 == ~E_6~0); 14662#L939-1 assume !(1 == ~E_7~0); 14663#L944-1 assume { :end_inline_reset_delta_events } true; 15047#L1190-2 [2024-11-13 12:48:53,402 INFO L747 eck$LassoCheckResult]: Loop: 15047#L1190-2 assume !false; 15048#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15168#L756-1 assume !false; 15167#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15166#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14912#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14913#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14701#L653 assume !(0 != eval_~tmp~0#1); 14703#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14790#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15158#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15771#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15770#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15769#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15768#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15767#L806-3 assume !(0 == ~T6_E~0); 15766#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15765#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15764#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15763#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15762#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15761#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15760#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15759#L846-3 assume !(0 == ~E_6~0); 15758#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15757#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15756#L388-27 assume 1 == ~m_pc~0; 15754#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15753#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15752#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15751#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15750#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15749#L407-27 assume 1 == ~t1_pc~0; 15747#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15746#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15745#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15744#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15743#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15742#L426-27 assume !(1 == ~t2_pc~0); 15740#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15739#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15738#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15737#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15736#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15735#L445-27 assume 1 == ~t3_pc~0; 15733#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15732#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15731#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15730#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15729#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15728#L464-27 assume !(1 == ~t4_pc~0); 15726#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15725#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15724#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15723#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15722#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15721#L483-27 assume 1 == ~t5_pc~0; 15719#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15718#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15717#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15716#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15715#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15714#L502-27 assume !(1 == ~t6_pc~0); 15712#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15711#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15122#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15123#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15142#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15143#L521-27 assume 1 == ~t7_pc~0; 15709#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15708#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14560#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14561#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 14828#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14829#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14975#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14976#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14772#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14773#L884-3 assume !(1 == ~T4_E~0); 14764#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14765#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14422#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14937#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14733#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14734#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14438#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14439#L924-3 assume !(1 == ~E_4~0); 14962#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14877#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14878#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14449#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14450#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14276#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14573#L1209 assume !(0 == start_simulation_~tmp~3#1); 14822#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14788#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14415#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14305#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 14306#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14301#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14302#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14807#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 15047#L1190-2 [2024-11-13 12:48:53,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:53,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2024-11-13 12:48:53,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:53,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181674611] [2024-11-13 12:48:53,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:53,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:53,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:53,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:53,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:53,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181674611] [2024-11-13 12:48:53,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181674611] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:53,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:53,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:53,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59874469] [2024-11-13 12:48:53,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:53,516 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:53,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:53,517 INFO L85 PathProgramCache]: Analyzing trace with hash 70308737, now seen corresponding path program 1 times [2024-11-13 12:48:53,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:53,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200583065] [2024-11-13 12:48:53,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:53,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:53,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:53,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:53,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:53,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200583065] [2024-11-13 12:48:53,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200583065] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:53,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:53,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:53,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398392024] [2024-11-13 12:48:53,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:53,592 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:53,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:53,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:48:53,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:48:53,593 INFO L87 Difference]: Start difference. First operand 1525 states and 2254 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:53,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:53,862 INFO L93 Difference]: Finished difference Result 2755 states and 4059 transitions. [2024-11-13 12:48:53,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2755 states and 4059 transitions. [2024-11-13 12:48:53,890 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-11-13 12:48:53,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2755 states to 2755 states and 4059 transitions. [2024-11-13 12:48:53,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2755 [2024-11-13 12:48:53,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2755 [2024-11-13 12:48:53,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2755 states and 4059 transitions. [2024-11-13 12:48:53,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:53,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2755 states and 4059 transitions. [2024-11-13 12:48:53,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2755 states and 4059 transitions. [2024-11-13 12:48:53,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2755 to 2753. [2024-11-13 12:48:53,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2753 states, 2753 states have (on average 1.473665092626226) internal successors, (4057), 2752 states have internal predecessors, (4057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:54,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2753 states to 2753 states and 4057 transitions. [2024-11-13 12:48:54,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-11-13 12:48:54,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:48:54,008 INFO L424 stractBuchiCegarLoop]: Abstraction has 2753 states and 4057 transitions. [2024-11-13 12:48:54,008 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 12:48:54,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2753 states and 4057 transitions. [2024-11-13 12:48:54,027 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2622 [2024-11-13 12:48:54,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:54,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:54,030 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:54,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:54,030 INFO L745 eck$LassoCheckResult]: Stem: 18791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19418#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19419#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19496#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18940#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18941#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19073#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19074#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18838#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18622#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18623#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18800#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18801#L781 assume !(0 == ~M_E~0); 19330#L781-2 assume !(0 == ~T1_E~0); 19505#L786-1 assume !(0 == ~T2_E~0); 18585#L791-1 assume !(0 == ~T3_E~0); 18586#L796-1 assume !(0 == ~T4_E~0); 19153#L801-1 assume !(0 == ~T5_E~0); 19154#L806-1 assume !(0 == ~T6_E~0); 19190#L811-1 assume !(0 == ~T7_E~0); 18805#L816-1 assume !(0 == ~E_M~0); 18806#L821-1 assume !(0 == ~E_1~0); 18613#L826-1 assume !(0 == ~E_2~0); 18614#L831-1 assume !(0 == ~E_3~0); 18935#L836-1 assume !(0 == ~E_4~0); 18936#L841-1 assume !(0 == ~E_5~0); 18753#L846-1 assume !(0 == ~E_6~0); 18754#L851-1 assume !(0 == ~E_7~0); 18777#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18778#L388 assume !(1 == ~m_pc~0); 18771#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18772#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19297#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18628#L967 assume !(0 != activate_threads_~tmp~1#1); 18629#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18558#L407 assume 1 == ~t1_pc~0; 18559#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18566#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18567#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18601#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19416#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18893#L426 assume !(1 == ~t2_pc~0); 18894#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19440#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18916#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18917#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19482#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18985#L445 assume 1 == ~t3_pc~0; 18986#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19339#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18557#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19259#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19223#L464 assume !(1 == ~t4_pc~0); 18781#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18648#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18660#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18962#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18963#L483 assume 1 == ~t5_pc~0; 19219#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19393#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19355#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19356#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18875#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18876#L502 assume 1 == ~t6_pc~0; 19188#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18689#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18690#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18903#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 19117#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19365#L521 assume !(1 == ~t7_pc~0); 19412#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18624#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19406#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19373#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19289#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19290#L869-2 assume !(1 == ~T1_E~0); 19478#L874-1 assume !(1 == ~T2_E~0); 19479#L879-1 assume !(1 == ~T3_E~0); 19036#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18544#L889-1 assume !(1 == ~T5_E~0); 18545#L894-1 assume !(1 == ~T6_E~0); 18817#L899-1 assume !(1 == ~T7_E~0); 19507#L904-1 assume !(1 == ~E_M~0); 19890#L909-1 assume !(1 == ~E_1~0); 19888#L914-1 assume !(1 == ~E_2~0); 19200#L919-1 assume !(1 == ~E_3~0); 18892#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18724#L929-1 assume !(1 == ~E_5~0); 18725#L934-1 assume !(1 == ~E_6~0); 19868#L939-1 assume !(1 == ~E_7~0); 19859#L944-1 assume { :end_inline_reset_delta_events } true; 19537#L1190-2 [2024-11-13 12:48:54,030 INFO L747 eck$LassoCheckResult]: Loop: 19537#L1190-2 assume !false; 19531#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19527#L756-1 assume !false; 19526#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19525#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19517#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19516#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19514#L653 assume !(0 != eval_~tmp~0#1); 19513#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19510#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19511#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20462#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20458#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20455#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20451#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20447#L806-3 assume !(0 == ~T6_E~0); 20443#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20439#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20433#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20430#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20427#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20425#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20422#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20403#L846-3 assume !(0 == ~E_6~0); 20401#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20399#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20397#L388-27 assume 1 == ~m_pc~0; 20393#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20257#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20251#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20249#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20247#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20236#L407-27 assume 1 == ~t1_pc~0; 20230#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20227#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20224#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19301#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19302#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18755#L426-27 assume !(1 == ~t2_pc~0); 18756#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 18769#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18770#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19254#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19464#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19079#L445-27 assume 1 == ~t3_pc~0; 19046#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19047#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20177#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19508#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19509#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18867#L464-27 assume 1 == ~t4_pc~0; 18868#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18603#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20155#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20153#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20148#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20146#L483-27 assume 1 == ~t5_pc~0; 20141#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20137#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20134#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20131#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20128#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20125#L502-27 assume !(1 == ~t6_pc~0); 20120#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 20116#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20113#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20110#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20107#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20104#L521-27 assume 1 == ~t7_pc~0; 20099#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20095#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20092#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20089#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 20086#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20083#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19446#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20078#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20075#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20072#L884-3 assume !(1 == ~T4_E~0); 19060#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19061#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18714#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20063#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20061#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20059#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20057#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20055#L924-3 assume !(1 == ~E_4~0); 20053#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20050#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20048#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20047#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20045#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20036#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20030#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20029#L1209 assume !(0 == start_simulation_~tmp~3#1); 19118#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19919#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19912#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19910#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19892#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19871#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19860#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19537#L1190-2 [2024-11-13 12:48:54,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:54,031 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2024-11-13 12:48:54,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:54,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684978647] [2024-11-13 12:48:54,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:54,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:54,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:54,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:54,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:54,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684978647] [2024-11-13 12:48:54,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684978647] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:54,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:54,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:48:54,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336134238] [2024-11-13 12:48:54,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:54,145 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:54,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:54,145 INFO L85 PathProgramCache]: Analyzing trace with hash 344087232, now seen corresponding path program 1 times [2024-11-13 12:48:54,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:54,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263141979] [2024-11-13 12:48:54,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:54,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:54,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:54,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:54,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:54,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263141979] [2024-11-13 12:48:54,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263141979] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:54,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:54,214 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:54,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648048315] [2024-11-13 12:48:54,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:54,215 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:54,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:54,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:54,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:54,216 INFO L87 Difference]: Start difference. First operand 2753 states and 4057 transitions. cyclomatic complexity: 1308 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:54,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:54,377 INFO L93 Difference]: Finished difference Result 5107 states and 7472 transitions. [2024-11-13 12:48:54,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5107 states and 7472 transitions. [2024-11-13 12:48:54,414 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4969 [2024-11-13 12:48:54,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5107 states to 5107 states and 7472 transitions. [2024-11-13 12:48:54,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5107 [2024-11-13 12:48:54,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5107 [2024-11-13 12:48:54,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5107 states and 7472 transitions. [2024-11-13 12:48:54,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:54,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5107 states and 7472 transitions. [2024-11-13 12:48:54,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5107 states and 7472 transitions. [2024-11-13 12:48:54,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5107 to 5099. [2024-11-13 12:48:54,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4638164345950186) internal successors, (7464), 5098 states have internal predecessors, (7464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:54,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7464 transitions. [2024-11-13 12:48:54,613 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-11-13 12:48:54,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:54,614 INFO L424 stractBuchiCegarLoop]: Abstraction has 5099 states and 7464 transitions. [2024-11-13 12:48:54,615 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 12:48:54,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7464 transitions. [2024-11-13 12:48:54,643 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4961 [2024-11-13 12:48:54,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:54,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:54,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:54,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:54,645 INFO L745 eck$LassoCheckResult]: Stem: 26661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27323#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27324#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27412#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26812#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26813#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26948#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26949#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26707#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26488#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26489#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26669#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26670#L781 assume !(0 == ~M_E~0); 27219#L781-2 assume !(0 == ~T1_E~0); 27429#L786-1 assume !(0 == ~T2_E~0); 26448#L791-1 assume !(0 == ~T3_E~0); 26449#L796-1 assume !(0 == ~T4_E~0); 27027#L801-1 assume !(0 == ~T5_E~0); 27028#L806-1 assume !(0 == ~T6_E~0); 27067#L811-1 assume !(0 == ~T7_E~0); 26674#L816-1 assume !(0 == ~E_M~0); 26675#L821-1 assume !(0 == ~E_1~0); 26479#L826-1 assume !(0 == ~E_2~0); 26480#L831-1 assume !(0 == ~E_3~0); 26807#L836-1 assume !(0 == ~E_4~0); 26808#L841-1 assume !(0 == ~E_5~0); 26622#L846-1 assume !(0 == ~E_6~0); 26623#L851-1 assume !(0 == ~E_7~0); 26646#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26647#L388 assume !(1 == ~m_pc~0); 26640#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26641#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27184#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26494#L967 assume !(0 != activate_threads_~tmp~1#1); 26495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26425#L407 assume !(1 == ~t1_pc~0); 26426#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26432#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26467#L975 assume !(0 != activate_threads_~tmp___0~0#1); 27321#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26763#L426 assume !(1 == ~t2_pc~0); 26764#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27349#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26787#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26788#L983 assume !(0 != activate_threads_~tmp___1~0#1); 27397#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26857#L445 assume 1 == ~t3_pc~0; 26858#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27229#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26424#L991 assume !(0 != activate_threads_~tmp___2~0#1); 27135#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27100#L464 assume !(1 == ~t4_pc~0); 26650#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26514#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26526#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26835#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26836#L483 assume 1 == ~t5_pc~0; 27096#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27296#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27253#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26746#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26747#L502 assume 1 == ~t6_pc~0; 27065#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26554#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26555#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26772#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26988#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27266#L521 assume !(1 == ~t7_pc~0); 27317#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26490#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26491#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27309#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27275#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27170#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 26829#L869-2 assume !(1 == ~T1_E~0); 26830#L874-1 assume !(1 == ~T2_E~0); 27365#L879-1 assume !(1 == ~T3_E~0); 26908#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26411#L889-1 assume !(1 == ~T5_E~0); 26412#L894-1 assume !(1 == ~T6_E~0); 26685#L899-1 assume !(1 == ~T7_E~0); 27125#L904-1 assume !(1 == ~E_M~0); 26854#L909-1 assume !(1 == ~E_1~0); 26855#L914-1 assume !(1 == ~E_2~0); 29519#L919-1 assume !(1 == ~E_3~0); 29517#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 29514#L929-1 assume !(1 == ~E_5~0); 29512#L934-1 assume !(1 == ~E_6~0); 29508#L939-1 assume !(1 == ~E_7~0); 29503#L944-1 assume { :end_inline_reset_delta_events } true; 29500#L1190-2 [2024-11-13 12:48:54,646 INFO L747 eck$LassoCheckResult]: Loop: 29500#L1190-2 assume !false; 29498#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29493#L756-1 assume !false; 28360#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27930#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27921#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27919#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27914#L653 assume !(0 != eval_~tmp~0#1); 27912#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27913#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27908#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27909#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30343#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30341#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30340#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30331#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30329#L806-3 assume !(0 == ~T6_E~0); 30327#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30325#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30323#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30310#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30301#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30294#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30289#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30285#L846-3 assume !(0 == ~E_6~0); 30282#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30279#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30278#L388-27 assume 1 == ~m_pc~0; 30276#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30275#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30274#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30273#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30272#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30271#L407-27 assume !(1 == ~t1_pc~0); 30269#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 30266#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30264#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30262#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30260#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30259#L426-27 assume !(1 == ~t2_pc~0); 30257#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 30256#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30255#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30254#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30253#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30252#L445-27 assume 1 == ~t3_pc~0; 30250#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30249#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30248#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30247#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30246#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30237#L464-27 assume !(1 == ~t4_pc~0); 30233#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 30230#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30228#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30226#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30224#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30222#L483-27 assume 1 == ~t5_pc~0; 30219#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30217#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30215#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30213#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30211#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30209#L502-27 assume !(1 == ~t6_pc~0); 30206#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 30204#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30202#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30200#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30198#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30196#L521-27 assume 1 == ~t7_pc~0; 30086#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30084#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30082#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30080#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 30078#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30076#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27358#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30064#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30058#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30052#L884-3 assume !(1 == ~T4_E~0); 30046#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30041#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30033#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30027#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30021#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30016#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30011#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30006#L924-3 assume !(1 == ~E_4~0); 29994#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29992#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29986#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29955#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 29881#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 29874#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 29873#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 29872#L1209 assume !(0 == start_simulation_~tmp~3#1); 26990#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 29870#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 29863#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 29862#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 29861#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29860#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29856#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 29504#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 29500#L1190-2 [2024-11-13 12:48:54,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:54,647 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2024-11-13 12:48:54,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:54,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194591938] [2024-11-13 12:48:54,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:54,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:54,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:54,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:54,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:54,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194591938] [2024-11-13 12:48:54,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194591938] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:54,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:54,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:48:54,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62958675] [2024-11-13 12:48:54,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:54,732 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:54,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:54,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1885012478, now seen corresponding path program 1 times [2024-11-13 12:48:54,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:54,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644081873] [2024-11-13 12:48:54,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:54,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:54,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:54,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:54,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:54,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644081873] [2024-11-13 12:48:54,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644081873] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:54,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:54,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:54,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416995722] [2024-11-13 12:48:54,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:54,805 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:54,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:54,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:54,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:54,806 INFO L87 Difference]: Start difference. First operand 5099 states and 7464 transitions. cyclomatic complexity: 2373 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:54,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:54,979 INFO L93 Difference]: Finished difference Result 9533 states and 13868 transitions. [2024-11-13 12:48:54,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9533 states and 13868 transitions. [2024-11-13 12:48:55,050 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9380 [2024-11-13 12:48:55,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9533 states to 9533 states and 13868 transitions. [2024-11-13 12:48:55,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9533 [2024-11-13 12:48:55,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9533 [2024-11-13 12:48:55,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9533 states and 13868 transitions. [2024-11-13 12:48:55,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:55,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9533 states and 13868 transitions. [2024-11-13 12:48:55,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9533 states and 13868 transitions. [2024-11-13 12:48:55,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9533 to 9517. [2024-11-13 12:48:55,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9517 states, 9517 states have (on average 1.4555006829883366) internal successors, (13852), 9516 states have internal predecessors, (13852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:55,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9517 states to 9517 states and 13852 transitions. [2024-11-13 12:48:55,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-11-13 12:48:55,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:55,403 INFO L424 stractBuchiCegarLoop]: Abstraction has 9517 states and 13852 transitions. [2024-11-13 12:48:55,403 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 12:48:55,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9517 states and 13852 transitions. [2024-11-13 12:48:55,455 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9364 [2024-11-13 12:48:55,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:55,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:55,457 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:55,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:55,458 INFO L745 eck$LassoCheckResult]: Stem: 41294#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 41295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41992#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 41443#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41444#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41573#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41574#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41341#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41125#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41126#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41303#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41304#L781 assume !(0 == ~M_E~0); 41827#L781-2 assume !(0 == ~T1_E~0); 42005#L786-1 assume !(0 == ~T2_E~0); 41089#L791-1 assume !(0 == ~T3_E~0); 41090#L796-1 assume !(0 == ~T4_E~0); 41649#L801-1 assume !(0 == ~T5_E~0); 41650#L806-1 assume !(0 == ~T6_E~0); 41685#L811-1 assume !(0 == ~T7_E~0); 41307#L816-1 assume !(0 == ~E_M~0); 41308#L821-1 assume !(0 == ~E_1~0); 41117#L826-1 assume !(0 == ~E_2~0); 41118#L831-1 assume !(0 == ~E_3~0); 41438#L836-1 assume !(0 == ~E_4~0); 41439#L841-1 assume !(0 == ~E_5~0); 41257#L846-1 assume !(0 == ~E_6~0); 41258#L851-1 assume !(0 == ~E_7~0); 41281#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41282#L388 assume !(1 == ~m_pc~0); 41275#L388-2 is_master_triggered_~__retres1~0#1 := 0; 41276#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41799#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41131#L967 assume !(0 != activate_threads_~tmp~1#1); 41132#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41064#L407 assume !(1 == ~t1_pc~0); 41065#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41105#L975 assume !(0 != activate_threads_~tmp___0~0#1); 41903#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41397#L426 assume !(1 == ~t2_pc~0); 41398#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41932#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41420#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41421#L983 assume !(0 != activate_threads_~tmp___1~0#1); 41976#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41486#L445 assume !(1 == ~t3_pc~0); 41487#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41835#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41062#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41063#L991 assume !(0 != activate_threads_~tmp___2~0#1); 41755#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41720#L464 assume !(1 == ~t4_pc~0); 41285#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41151#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41152#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41165#L999 assume !(0 != activate_threads_~tmp___3~0#1); 41464#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41465#L483 assume 1 == ~t5_pc~0; 41715#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41885#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41851#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 41381#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41382#L502 assume 1 == ~t6_pc~0; 41683#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41192#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41193#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41407#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 41614#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41866#L521 assume !(1 == ~t7_pc~0); 41900#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41127#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41128#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41894#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41870#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41790#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 41791#L869-2 assume !(1 == ~T1_E~0); 41973#L874-1 assume !(1 == ~T2_E~0); 41946#L879-1 assume !(1 == ~T3_E~0); 41536#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41050#L889-1 assume !(1 == ~T5_E~0); 41051#L894-1 assume !(1 == ~T6_E~0); 43107#L899-1 assume !(1 == ~T7_E~0); 43105#L904-1 assume !(1 == ~E_M~0); 43104#L909-1 assume !(1 == ~E_1~0); 43102#L914-1 assume !(1 == ~E_2~0); 41694#L919-1 assume !(1 == ~E_3~0); 41396#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 41227#L929-1 assume !(1 == ~E_5~0); 41228#L934-1 assume !(1 == ~E_6~0); 43062#L939-1 assume !(1 == ~E_7~0); 43053#L944-1 assume { :end_inline_reset_delta_events } true; 43046#L1190-2 [2024-11-13 12:48:55,458 INFO L747 eck$LassoCheckResult]: Loop: 43046#L1190-2 assume !false; 43040#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43036#L756-1 assume !false; 43035#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43034#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43026#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43025#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43023#L653 assume !(0 != eval_~tmp~0#1); 43022#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43018#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43019#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44253#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44252#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44251#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44250#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44249#L806-3 assume !(0 == ~T6_E~0); 44248#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44247#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44246#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44245#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44244#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44243#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44242#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44241#L846-3 assume !(0 == ~E_6~0); 44240#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44239#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44238#L388-27 assume 1 == ~m_pc~0; 44236#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44235#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44234#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44233#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44232#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44231#L407-27 assume !(1 == ~t1_pc~0); 44230#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 44229#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44228#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44227#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44226#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44225#L426-27 assume 1 == ~t2_pc~0; 44224#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44222#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42575#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42573#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42570#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42568#L445-27 assume !(1 == ~t3_pc~0); 42564#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 42565#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44125#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44122#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44121#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42539#L464-27 assume !(1 == ~t4_pc~0); 42537#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 42536#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42383#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42382#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42381#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42380#L483-27 assume 1 == ~t5_pc~0; 42378#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42376#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42377#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44076#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44074#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42356#L502-27 assume !(1 == ~t6_pc~0); 42352#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 42353#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42346#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42336#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42328#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42320#L521-27 assume 1 == ~t7_pc~0; 42257#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42255#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42253#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42250#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 42248#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42246#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42230#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42224#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42215#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42206#L884-3 assume !(1 == ~T4_E~0); 42207#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43893#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42184#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43886#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 43883#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43880#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43877#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43874#L924-3 assume !(1 == ~E_4~0); 43870#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43199#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43191#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43187#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43160#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43152#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43150#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 43147#L1209 assume !(0 == start_simulation_~tmp~3#1); 43144#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43135#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43085#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43082#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 43080#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43076#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43063#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 43054#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 43046#L1190-2 [2024-11-13 12:48:55,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:55,459 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2024-11-13 12:48:55,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:55,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029978095] [2024-11-13 12:48:55,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:55,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:55,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:55,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:55,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:55,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029978095] [2024-11-13 12:48:55,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029978095] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:55,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:55,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:48:55,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425164820] [2024-11-13 12:48:55,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:55,611 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:55,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:55,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1000981186, now seen corresponding path program 1 times [2024-11-13 12:48:55,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:55,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634114407] [2024-11-13 12:48:55,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:55,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:55,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:55,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:55,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:55,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634114407] [2024-11-13 12:48:55,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634114407] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:55,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:55,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:55,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86749926] [2024-11-13 12:48:55,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:55,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:55,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:55,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:55,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:55,689 INFO L87 Difference]: Start difference. First operand 9517 states and 13852 transitions. cyclomatic complexity: 4351 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:55,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:55,929 INFO L93 Difference]: Finished difference Result 18316 states and 26485 transitions. [2024-11-13 12:48:55,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18316 states and 26485 transitions. [2024-11-13 12:48:56,050 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18108 [2024-11-13 12:48:56,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18316 states to 18316 states and 26485 transitions. [2024-11-13 12:48:56,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18316 [2024-11-13 12:48:56,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18316 [2024-11-13 12:48:56,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18316 states and 26485 transitions. [2024-11-13 12:48:56,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:56,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18316 states and 26485 transitions. [2024-11-13 12:48:56,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18316 states and 26485 transitions. [2024-11-13 12:48:56,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18316 to 18284. [2024-11-13 12:48:56,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18284 states, 18284 states have (on average 1.4467840735068913) internal successors, (26453), 18283 states have internal predecessors, (26453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:56,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18284 states to 18284 states and 26453 transitions. [2024-11-13 12:48:56,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-11-13 12:48:56,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:56,828 INFO L424 stractBuchiCegarLoop]: Abstraction has 18284 states and 26453 transitions. [2024-11-13 12:48:56,828 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 12:48:56,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18284 states and 26453 transitions. [2024-11-13 12:48:56,910 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18076 [2024-11-13 12:48:56,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:56,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:56,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:56,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:56,912 INFO L745 eck$LassoCheckResult]: Stem: 69132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 69133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 69759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69760#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69844#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 69281#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69282#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69418#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69419#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69178#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68965#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68966#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69140#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69141#L781 assume !(0 == ~M_E~0); 69669#L781-2 assume !(0 == ~T1_E~0); 69858#L786-1 assume !(0 == ~T2_E~0); 68926#L791-1 assume !(0 == ~T3_E~0); 68927#L796-1 assume !(0 == ~T4_E~0); 69496#L801-1 assume !(0 == ~T5_E~0); 69497#L806-1 assume !(0 == ~T6_E~0); 69536#L811-1 assume !(0 == ~T7_E~0); 69145#L816-1 assume !(0 == ~E_M~0); 69146#L821-1 assume !(0 == ~E_1~0); 68957#L826-1 assume !(0 == ~E_2~0); 68958#L831-1 assume !(0 == ~E_3~0); 69276#L836-1 assume !(0 == ~E_4~0); 69277#L841-1 assume !(0 == ~E_5~0); 69095#L846-1 assume !(0 == ~E_6~0); 69096#L851-1 assume !(0 == ~E_7~0); 69119#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69120#L388 assume !(1 == ~m_pc~0); 69113#L388-2 is_master_triggered_~__retres1~0#1 := 0; 69114#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69644#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68971#L967 assume !(0 != activate_threads_~tmp~1#1); 68972#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68904#L407 assume !(1 == ~t1_pc~0); 68905#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68911#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68912#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68945#L975 assume !(0 != activate_threads_~tmp___0~0#1); 69757#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69232#L426 assume !(1 == ~t2_pc~0); 69233#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69788#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69255#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69256#L983 assume !(0 != activate_threads_~tmp___1~0#1); 69832#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69327#L445 assume !(1 == ~t3_pc~0); 69328#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69678#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68903#L991 assume !(0 != activate_threads_~tmp___2~0#1); 69603#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69567#L464 assume !(1 == ~t4_pc~0); 69123#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68991#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68992#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69003#L999 assume !(0 != activate_threads_~tmp___3~0#1); 69305#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69306#L483 assume !(1 == ~t5_pc~0); 69563#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69736#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69696#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69697#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 69215#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69216#L502 assume 1 == ~t6_pc~0; 69534#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69031#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69032#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69241#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 69458#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69711#L521 assume !(1 == ~t7_pc~0); 69753#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68967#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69747#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69718#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69634#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 69298#L869-2 assume !(1 == ~T1_E~0); 69299#L874-1 assume !(1 == ~T2_E~0); 69798#L879-1 assume !(1 == ~T3_E~0); 69380#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68890#L889-1 assume !(1 == ~T5_E~0); 68891#L894-1 assume !(1 == ~T6_E~0); 69153#L899-1 assume !(1 == ~T7_E~0); 70825#L904-1 assume !(1 == ~E_M~0); 70804#L909-1 assume !(1 == ~E_1~0); 69517#L914-1 assume !(1 == ~E_2~0); 69518#L919-1 assume !(1 == ~E_3~0); 69231#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69066#L929-1 assume !(1 == ~E_5~0); 69067#L934-1 assume !(1 == ~E_6~0); 70663#L939-1 assume !(1 == ~E_7~0); 70655#L944-1 assume { :end_inline_reset_delta_events } true; 70648#L1190-2 [2024-11-13 12:48:56,913 INFO L747 eck$LassoCheckResult]: Loop: 70648#L1190-2 assume !false; 70642#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70638#L756-1 assume !false; 70637#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70636#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 70628#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 70627#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70625#L653 assume !(0 != eval_~tmp~0#1); 70624#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70620#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70617#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70615#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70612#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70613#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70607#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70604#L806-3 assume !(0 == ~T6_E~0); 70605#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71273#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71271#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71269#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71267#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71265#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71263#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71260#L846-3 assume !(0 == ~E_6~0); 71258#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71257#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71246#L388-27 assume !(1 == ~m_pc~0); 71241#L388-29 is_master_triggered_~__retres1~0#1 := 0; 71238#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71235#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71232#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 71229#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71225#L407-27 assume !(1 == ~t1_pc~0); 71222#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 71218#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71215#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71212#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71209#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71205#L426-27 assume 1 == ~t2_pc~0; 71200#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71195#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71193#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71191#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71190#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71189#L445-27 assume !(1 == ~t3_pc~0); 71188#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 71187#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71185#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71184#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71182#L464-27 assume !(1 == ~t4_pc~0); 71179#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 71177#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71174#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70502#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70500#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70498#L483-27 assume !(1 == ~t5_pc~0); 70499#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 71105#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71103#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71100#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 71098#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71096#L502-27 assume !(1 == ~t6_pc~0); 71089#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 71083#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71077#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71074#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 71040#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71023#L521-27 assume 1 == ~t7_pc~0; 71001#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 70993#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70986#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70980#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 70974#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70968#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 70458#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70953#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70946#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70447#L884-3 assume !(1 == ~T4_E~0); 70444#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70445#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70924#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70922#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70920#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70917#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70913#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70910#L924-3 assume !(1 == ~E_4~0); 70907#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70900#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70898#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70896#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70887#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 70880#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 70879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 70835#L1209 assume !(0 == start_simulation_~tmp~3#1); 70824#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 70800#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 70792#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 70790#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 70679#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70675#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70664#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 70656#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 70648#L1190-2 [2024-11-13 12:48:56,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:56,914 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2024-11-13 12:48:56,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:56,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759389219] [2024-11-13 12:48:56,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:56,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:56,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:57,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:57,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:57,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [759389219] [2024-11-13 12:48:57,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [759389219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:57,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:57,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:48:57,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427274289] [2024-11-13 12:48:57,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:57,123 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:57,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:57,124 INFO L85 PathProgramCache]: Analyzing trace with hash 1560192516, now seen corresponding path program 1 times [2024-11-13 12:48:57,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:57,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134545276] [2024-11-13 12:48:57,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:57,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:57,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:57,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:57,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:57,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134545276] [2024-11-13 12:48:57,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134545276] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:57,204 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:57,204 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:57,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652908550] [2024-11-13 12:48:57,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:57,205 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:57,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:57,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:48:57,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:48:57,208 INFO L87 Difference]: Start difference. First operand 18284 states and 26453 transitions. cyclomatic complexity: 8201 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:57,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:48:57,579 INFO L93 Difference]: Finished difference Result 34391 states and 49534 transitions. [2024-11-13 12:48:57,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34391 states and 49534 transitions. [2024-11-13 12:48:57,802 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34040 [2024-11-13 12:48:58,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34391 states to 34391 states and 49534 transitions. [2024-11-13 12:48:58,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34391 [2024-11-13 12:48:58,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34391 [2024-11-13 12:48:58,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34391 states and 49534 transitions. [2024-11-13 12:48:58,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:48:58,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34391 states and 49534 transitions. [2024-11-13 12:48:58,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34391 states and 49534 transitions. [2024-11-13 12:48:58,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34391 to 34327. [2024-11-13 12:48:58,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34327 states, 34327 states have (on average 1.4411396276983133) internal successors, (49470), 34326 states have internal predecessors, (49470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:48:59,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34327 states to 34327 states and 49470 transitions. [2024-11-13 12:48:59,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-11-13 12:48:59,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:48:59,256 INFO L424 stractBuchiCegarLoop]: Abstraction has 34327 states and 49470 transitions. [2024-11-13 12:48:59,256 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 12:48:59,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34327 states and 49470 transitions. [2024-11-13 12:48:59,357 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 33976 [2024-11-13 12:48:59,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:48:59,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:48:59,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:59,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:48:59,360 INFO L745 eck$LassoCheckResult]: Stem: 121814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 121815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122449#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122450#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122532#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 121966#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121967#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122097#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122098#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121859#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121648#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121649#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121819#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121820#L781 assume !(0 == ~M_E~0); 122346#L781-2 assume !(0 == ~T1_E~0); 122539#L786-1 assume !(0 == ~T2_E~0); 121608#L791-1 assume !(0 == ~T3_E~0); 121609#L796-1 assume !(0 == ~T4_E~0); 122175#L801-1 assume !(0 == ~T5_E~0); 122176#L806-1 assume !(0 == ~T6_E~0); 122211#L811-1 assume !(0 == ~T7_E~0); 121826#L816-1 assume !(0 == ~E_M~0); 121827#L821-1 assume !(0 == ~E_1~0); 121639#L826-1 assume !(0 == ~E_2~0); 121640#L831-1 assume !(0 == ~E_3~0); 121961#L836-1 assume !(0 == ~E_4~0); 121962#L841-1 assume !(0 == ~E_5~0); 121778#L846-1 assume !(0 == ~E_6~0); 121779#L851-1 assume !(0 == ~E_7~0); 121801#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121802#L388 assume !(1 == ~m_pc~0); 121795#L388-2 is_master_triggered_~__retres1~0#1 := 0; 121796#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122318#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121654#L967 assume !(0 != activate_threads_~tmp~1#1); 121655#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121586#L407 assume !(1 == ~t1_pc~0); 121587#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121590#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121591#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121625#L975 assume !(0 != activate_threads_~tmp___0~0#1); 122447#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121918#L426 assume !(1 == ~t2_pc~0); 121919#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122477#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121944#L983 assume !(0 != activate_threads_~tmp___1~0#1); 122523#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122010#L445 assume !(1 == ~t3_pc~0); 122011#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122355#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121585#L991 assume !(0 != activate_threads_~tmp___2~0#1); 122277#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122239#L464 assume !(1 == ~t4_pc~0); 121805#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121674#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121675#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121686#L999 assume !(0 != activate_threads_~tmp___3~0#1); 121988#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121989#L483 assume !(1 == ~t5_pc~0); 122236#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122423#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122378#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122379#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 121901#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121902#L502 assume !(1 == ~t6_pc~0); 121756#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121714#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121715#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121929#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 122140#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122396#L521 assume !(1 == ~t7_pc~0); 122442#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121650#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121651#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122435#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 122403#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122307#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 121982#L869-2 assume !(1 == ~T1_E~0); 121983#L874-1 assume !(1 == ~T2_E~0); 122491#L879-1 assume !(1 == ~T3_E~0); 122061#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121572#L889-1 assume !(1 == ~T5_E~0); 121573#L894-1 assume !(1 == ~T6_E~0); 121835#L899-1 assume !(1 == ~T7_E~0); 136692#L904-1 assume !(1 == ~E_M~0); 136690#L909-1 assume !(1 == ~E_1~0); 136688#L914-1 assume !(1 == ~E_2~0); 136686#L919-1 assume !(1 == ~E_3~0); 136685#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 136684#L929-1 assume !(1 == ~E_5~0); 136680#L934-1 assume !(1 == ~E_6~0); 122498#L939-1 assume !(1 == ~E_7~0); 122394#L944-1 assume { :end_inline_reset_delta_events } true; 122395#L1190-2 [2024-11-13 12:48:59,361 INFO L747 eck$LassoCheckResult]: Loop: 122395#L1190-2 assume !false; 145710#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145699#L756-1 assume !false; 145692#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 145683#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 145674#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 145666#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 145657#L653 assume !(0 != eval_~tmp~0#1); 145658#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 155096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 155095#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 155094#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155092#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 155089#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121633#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121634#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121903#L806-3 assume !(0 == ~T6_E~0); 121904#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 122111#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 122338#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122478#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 122270#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 122271#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 121789#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121790#L846-3 assume !(0 == ~E_6~0); 122139#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 121681#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121682#L388-27 assume 1 == ~m_pc~0; 122436#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 122437#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122295#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122296#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 121862#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121863#L407-27 assume !(1 == ~t1_pc~0); 122297#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 122371#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122186#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122187#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 122157#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121780#L426-27 assume !(1 == ~t2_pc~0); 121781#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 121791#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121792#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 122272#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 122430#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122102#L445-27 assume !(1 == ~t3_pc~0); 122103#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 122528#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122104#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 122105#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122199#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122200#L464-27 assume 1 == ~t4_pc~0; 122322#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 121629#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121700#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 122112#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 122113#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154312#L483-27 assume !(1 == ~t5_pc~0); 154311#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 154310#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154309#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154308#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 154307#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122501#L502-27 assume !(1 == ~t6_pc~0); 122502#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 154624#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154623#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154622#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154621#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154620#L521-27 assume 1 == ~t7_pc~0; 154618#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154617#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154615#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154612#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 154610#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154608#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 133798#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 154606#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 154605#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122138#L884-3 assume !(1 == ~T4_E~0); 122084#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121739#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 121740#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 121760#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 121761#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121716#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121717#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121755#L924-3 assume !(1 == ~E_4~0); 122284#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122195#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 122196#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 121765#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 121766#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 123189#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 123187#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 123021#L1209 assume !(0 == start_simulation_~tmp~3#1); 123022#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 145785#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 145772#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 145764#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 145756#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145746#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145739#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 145732#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 122395#L1190-2 [2024-11-13 12:48:59,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:59,362 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2024-11-13 12:48:59,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:59,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765450298] [2024-11-13 12:48:59,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:59,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:59,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:59,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:59,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:59,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765450298] [2024-11-13 12:48:59,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765450298] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:59,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:59,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:48:59,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463303300] [2024-11-13 12:48:59,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:59,463 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:48:59,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:48:59,464 INFO L85 PathProgramCache]: Analyzing trace with hash -241039677, now seen corresponding path program 1 times [2024-11-13 12:48:59,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:48:59,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023962094] [2024-11-13 12:48:59,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:48:59,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:48:59,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:48:59,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:48:59,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:48:59,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023962094] [2024-11-13 12:48:59,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023962094] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:48:59,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:48:59,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:48:59,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128961398] [2024-11-13 12:48:59,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:48:59,524 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:48:59,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:48:59,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:48:59,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:48:59,524 INFO L87 Difference]: Start difference. First operand 34327 states and 49470 transitions. cyclomatic complexity: 15207 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:00,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:00,113 INFO L93 Difference]: Finished difference Result 35674 states and 50817 transitions. [2024-11-13 12:49:00,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35674 states and 50817 transitions. [2024-11-13 12:49:00,268 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-11-13 12:49:00,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-11-13 12:49:00,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35674 [2024-11-13 12:49:00,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35674 [2024-11-13 12:49:00,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35674 states and 50817 transitions. [2024-11-13 12:49:00,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:00,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-13 12:49:00,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35674 states and 50817 transitions. [2024-11-13 12:49:01,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35674 to 35674. [2024-11-13 12:49:01,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35674 states, 35674 states have (on average 1.4244828166171442) internal successors, (50817), 35673 states have internal predecessors, (50817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:01,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35674 states to 35674 states and 50817 transitions. [2024-11-13 12:49:01,394 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-13 12:49:01,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:01,395 INFO L424 stractBuchiCegarLoop]: Abstraction has 35674 states and 50817 transitions. [2024-11-13 12:49:01,395 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 12:49:01,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35674 states and 50817 transitions. [2024-11-13 12:49:01,514 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 35320 [2024-11-13 12:49:01,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:01,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:01,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:01,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:01,517 INFO L745 eck$LassoCheckResult]: Stem: 191831#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 191832#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 192481#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 192482#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192580#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 191981#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191982#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192119#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192120#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191878#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 191658#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 191659#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 191837#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191838#L781 assume !(0 == ~M_E~0); 192384#L781-2 assume !(0 == ~T1_E~0); 192603#L786-1 assume !(0 == ~T2_E~0); 191618#L791-1 assume !(0 == ~T3_E~0); 191619#L796-1 assume !(0 == ~T4_E~0); 192198#L801-1 assume !(0 == ~T5_E~0); 192199#L806-1 assume !(0 == ~T6_E~0); 192240#L811-1 assume !(0 == ~T7_E~0); 191844#L816-1 assume !(0 == ~E_M~0); 191845#L821-1 assume !(0 == ~E_1~0); 191649#L826-1 assume !(0 == ~E_2~0); 191650#L831-1 assume !(0 == ~E_3~0); 191976#L836-1 assume !(0 == ~E_4~0); 191977#L841-1 assume !(0 == ~E_5~0); 191792#L846-1 assume !(0 == ~E_6~0); 191793#L851-1 assume !(0 == ~E_7~0); 191816#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191817#L388 assume !(1 == ~m_pc~0); 191810#L388-2 is_master_triggered_~__retres1~0#1 := 0; 191811#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192354#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 191664#L967 assume !(0 != activate_threads_~tmp~1#1); 191665#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191596#L407 assume !(1 == ~t1_pc~0); 191597#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191600#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191601#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191635#L975 assume !(0 != activate_threads_~tmp___0~0#1); 192478#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191933#L426 assume !(1 == ~t2_pc~0); 191934#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192512#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191958#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 191959#L983 assume !(0 != activate_threads_~tmp___1~0#1); 192563#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192025#L445 assume !(1 == ~t3_pc~0); 192026#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 192394#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191594#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191595#L991 assume !(0 != activate_threads_~tmp___2~0#1); 192310#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192270#L464 assume !(1 == ~t4_pc~0); 191820#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 191684#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191685#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 191696#L999 assume !(0 != activate_threads_~tmp___3~0#1); 192002#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192003#L483 assume !(1 == ~t5_pc~0); 192267#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 192453#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192412#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192413#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 191916#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191917#L502 assume !(1 == ~t6_pc~0); 191770#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 191725#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191726#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 191944#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 192159#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 192428#L521 assume !(1 == ~t7_pc~0); 192475#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 191660#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192467#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 192434#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192343#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 191996#L869-2 assume !(1 == ~T1_E~0); 191997#L874-1 assume !(1 == ~T2_E~0); 192529#L879-1 assume !(1 == ~T3_E~0); 192079#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 191582#L889-1 assume !(1 == ~T5_E~0); 191583#L894-1 assume !(1 == ~T6_E~0); 191852#L899-1 assume !(1 == ~T7_E~0); 192295#L904-1 assume !(1 == ~E_M~0); 192022#L909-1 assume !(1 == ~E_1~0); 192023#L914-1 assume !(1 == ~E_2~0); 192222#L919-1 assume !(1 == ~E_3~0); 191932#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 191761#L929-1 assume !(1 == ~E_5~0); 191762#L934-1 assume !(1 == ~E_6~0); 192538#L939-1 assume !(1 == ~E_7~0); 202518#L944-1 assume { :end_inline_reset_delta_events } true; 202516#L1190-2 [2024-11-13 12:49:01,518 INFO L747 eck$LassoCheckResult]: Loop: 202516#L1190-2 assume !false; 202514#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 202510#L756-1 assume !false; 202509#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 197773#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 197764#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 197763#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 197759#L653 assume !(0 != eval_~tmp~0#1); 197760#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 208987#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 208986#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 208985#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 208984#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 208983#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 208981#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 208978#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 208976#L806-3 assume !(0 == ~T6_E~0); 208974#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 208972#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 208970#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 208968#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 208966#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 208964#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 208962#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 208960#L846-3 assume !(0 == ~E_6~0); 208958#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 208956#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 208953#L388-27 assume !(1 == ~m_pc~0); 208951#L388-29 is_master_triggered_~__retres1~0#1 := 0; 208949#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 208948#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 208946#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 208944#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 208942#L407-27 assume !(1 == ~t1_pc~0); 208940#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 208938#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 208936#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 208935#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 208934#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208933#L426-27 assume 1 == ~t2_pc~0; 208929#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 208926#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208924#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 208922#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 208920#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 208918#L445-27 assume !(1 == ~t3_pc~0); 208916#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 208914#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 208912#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 208910#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 208908#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 208906#L464-27 assume !(1 == ~t4_pc~0); 208903#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 208900#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 208898#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 208896#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 208894#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 208892#L483-27 assume !(1 == ~t5_pc~0); 208890#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 208889#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 208888#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 208887#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 208885#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208882#L502-27 assume !(1 == ~t6_pc~0); 208880#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 208878#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 208876#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 208874#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 208861#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 208856#L521-27 assume !(1 == ~t7_pc~0); 208850#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 208846#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 208841#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 207767#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 207764#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 207762#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 202094#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 207758#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 207754#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 207751#L884-3 assume !(1 == ~T4_E~0); 207748#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 207744#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 204860#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 207737#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 207733#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 207729#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 207725#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 207721#L924-3 assume !(1 == ~E_4~0); 207717#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 207713#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 202863#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 207703#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 207666#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 207656#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 207652#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 207648#L1209 assume !(0 == start_simulation_~tmp~3#1); 205911#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 202537#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 202529#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 202527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 202525#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 202523#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 202521#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 202519#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 202516#L1190-2 [2024-11-13 12:49:01,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:01,519 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2024-11-13 12:49:01,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:01,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338974699] [2024-11-13 12:49:01,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:01,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:01,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:01,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:01,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:01,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338974699] [2024-11-13 12:49:01,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338974699] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:01,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:01,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 12:49:01,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305037631] [2024-11-13 12:49:01,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:01,633 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:49:01,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:01,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1683325691, now seen corresponding path program 1 times [2024-11-13 12:49:01,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:01,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088117745] [2024-11-13 12:49:01,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:01,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:01,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:01,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:01,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:01,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088117745] [2024-11-13 12:49:01,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088117745] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:01,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:01,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:01,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446855705] [2024-11-13 12:49:01,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:01,875 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:01,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:01,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:01,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:01,876 INFO L87 Difference]: Start difference. First operand 35674 states and 50817 transitions. cyclomatic complexity: 15207 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:02,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:02,069 INFO L93 Difference]: Finished difference Result 44740 states and 63748 transitions. [2024-11-13 12:49:02,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44740 states and 63748 transitions. [2024-11-13 12:49:02,454 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 44344 [2024-11-13 12:49:02,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44740 states to 44740 states and 63748 transitions. [2024-11-13 12:49:02,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44740 [2024-11-13 12:49:02,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44740 [2024-11-13 12:49:02,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44740 states and 63748 transitions. [2024-11-13 12:49:02,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:02,685 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44740 states and 63748 transitions. [2024-11-13 12:49:02,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44740 states and 63748 transitions. [2024-11-13 12:49:03,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44740 to 19206. [2024-11-13 12:49:03,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.4305425387899615) internal successors, (27475), 19205 states have internal predecessors, (27475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:03,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27475 transitions. [2024-11-13 12:49:03,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-11-13 12:49:03,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:49:03,230 INFO L424 stractBuchiCegarLoop]: Abstraction has 19206 states and 27475 transitions. [2024-11-13 12:49:03,230 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 12:49:03,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27475 transitions. [2024-11-13 12:49:03,310 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-13 12:49:03,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:03,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:03,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:03,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:03,314 INFO L745 eck$LassoCheckResult]: Stem: 272243#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 272244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 272867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 272868#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 272951#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 272391#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 272392#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 272525#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 272526#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 272290#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272078#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 272079#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 272251#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272252#L781 assume !(0 == ~M_E~0); 272773#L781-2 assume !(0 == ~T1_E~0); 272972#L786-1 assume !(0 == ~T2_E~0); 272042#L791-1 assume !(0 == ~T3_E~0); 272043#L796-1 assume !(0 == ~T4_E~0); 272603#L801-1 assume !(0 == ~T5_E~0); 272604#L806-1 assume !(0 == ~T6_E~0); 272637#L811-1 assume !(0 == ~T7_E~0); 272255#L816-1 assume !(0 == ~E_M~0); 272256#L821-1 assume !(0 == ~E_1~0); 272070#L826-1 assume !(0 == ~E_2~0); 272071#L831-1 assume !(0 == ~E_3~0); 272386#L836-1 assume !(0 == ~E_4~0); 272387#L841-1 assume !(0 == ~E_5~0); 272207#L846-1 assume !(0 == ~E_6~0); 272208#L851-1 assume !(0 == ~E_7~0); 272230#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272231#L388 assume !(1 == ~m_pc~0); 272224#L388-2 is_master_triggered_~__retres1~0#1 := 0; 272225#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272745#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272084#L967 assume !(0 != activate_threads_~tmp~1#1); 272085#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272017#L407 assume !(1 == ~t1_pc~0); 272018#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 272024#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272025#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272058#L975 assume !(0 != activate_threads_~tmp___0~0#1); 272863#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272345#L426 assume !(1 == ~t2_pc~0); 272346#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 272893#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272367#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272368#L983 assume !(0 != activate_threads_~tmp___1~0#1); 272937#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272435#L445 assume !(1 == ~t3_pc~0); 272436#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 272780#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272016#L991 assume !(0 != activate_threads_~tmp___2~0#1); 272702#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272665#L464 assume !(1 == ~t4_pc~0); 272236#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 272104#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272105#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272118#L999 assume !(0 != activate_threads_~tmp___3~0#1); 272412#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272413#L483 assume !(1 == ~t5_pc~0); 272662#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 272837#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272798#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 272799#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 272330#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272331#L502 assume !(1 == ~t6_pc~0); 272185#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 272144#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 272355#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 272565#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272810#L521 assume !(1 == ~t7_pc~0); 272858#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 272895#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 272978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272852#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 272817#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 272737#L869 assume !(1 == ~M_E~0); 272406#L869-2 assume !(1 == ~T1_E~0); 272407#L874-1 assume !(1 == ~T2_E~0); 272906#L879-1 assume !(1 == ~T3_E~0); 272488#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 272003#L889-1 assume !(1 == ~T5_E~0); 272004#L894-1 assume !(1 == ~T6_E~0); 272266#L899-1 assume !(1 == ~T7_E~0); 272690#L904-1 assume !(1 == ~E_M~0); 272432#L909-1 assume !(1 == ~E_1~0); 272433#L914-1 assume !(1 == ~E_2~0); 272623#L919-1 assume !(1 == ~E_3~0); 272344#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 272178#L929-1 assume !(1 == ~E_5~0); 272179#L934-1 assume !(1 == ~E_6~0); 272410#L939-1 assume !(1 == ~E_7~0); 272411#L944-1 assume { :end_inline_reset_delta_events } true; 272809#L1190-2 [2024-11-13 12:49:03,314 INFO L747 eck$LassoCheckResult]: Loop: 272809#L1190-2 assume !false; 278266#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278261#L756-1 assume !false; 278259#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278256#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278247#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278245#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 278242#L653 assume !(0 != eval_~tmp~0#1); 278240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 278238#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278236#L781-3 assume !(0 == ~M_E~0); 278234#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 278232#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 278230#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 278228#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 278226#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 278224#L806-3 assume !(0 == ~T6_E~0); 278222#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 278220#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 278218#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278216#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278214#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 278212#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 278210#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 278208#L846-3 assume !(0 == ~E_6~0); 278205#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 278203#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278201#L388-27 assume 1 == ~m_pc~0; 278194#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 278192#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278190#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 278188#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278186#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278184#L407-27 assume !(1 == ~t1_pc~0); 278181#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 278179#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278177#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 278175#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 278173#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278171#L426-27 assume !(1 == ~t2_pc~0); 278168#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 278166#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278164#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 278162#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278160#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278158#L445-27 assume !(1 == ~t3_pc~0); 278155#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 278153#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278151#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 278149#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 278147#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278145#L464-27 assume !(1 == ~t4_pc~0); 278141#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 278139#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278137#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 278135#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 278133#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278131#L483-27 assume !(1 == ~t5_pc~0); 278129#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 278127#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278125#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278123#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 278121#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278119#L502-27 assume !(1 == ~t6_pc~0); 278116#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 278114#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 278112#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278109#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 278107#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278105#L521-27 assume 1 == ~t7_pc~0; 278103#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278101#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278099#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278097#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 278094#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 278012#L869-3 assume !(1 == ~M_E~0); 277455#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 278000#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 277997#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 277994#L884-3 assume !(1 == ~T4_E~0); 277991#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 277988#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 277985#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 277982#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 277978#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 277971#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 277959#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 277958#L924-3 assume !(1 == ~E_4~0); 277957#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 277956#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 277955#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 277954#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 277952#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 277945#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 277944#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 272956#L1209 assume !(0 == start_simulation_~tmp~3#1); 272957#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 278853#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 278845#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 278843#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 278840#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 278838#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 278836#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 278833#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 272809#L1190-2 [2024-11-13 12:49:03,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:03,315 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2024-11-13 12:49:03,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:03,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19431209] [2024-11-13 12:49:03,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:03,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:03,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:03,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:03,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:03,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19431209] [2024-11-13 12:49:03,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19431209] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:03,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:03,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:03,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285267193] [2024-11-13 12:49:03,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:03,442 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:49:03,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:03,442 INFO L85 PathProgramCache]: Analyzing trace with hash -747589692, now seen corresponding path program 1 times [2024-11-13 12:49:03,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:03,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792754791] [2024-11-13 12:49:03,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:03,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:03,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:03,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:03,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:03,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792754791] [2024-11-13 12:49:03,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792754791] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:03,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:03,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:03,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361391304] [2024-11-13 12:49:03,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:03,525 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:03,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:03,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:49:03,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:49:03,526 INFO L87 Difference]: Start difference. First operand 19206 states and 27475 transitions. cyclomatic complexity: 8285 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:03,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:03,790 INFO L93 Difference]: Finished difference Result 30482 states and 43470 transitions. [2024-11-13 12:49:03,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30482 states and 43470 transitions. [2024-11-13 12:49:03,957 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30128 [2024-11-13 12:49:04,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30482 states to 30482 states and 43470 transitions. [2024-11-13 12:49:04,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30482 [2024-11-13 12:49:04,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30482 [2024-11-13 12:49:04,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30482 states and 43470 transitions. [2024-11-13 12:49:04,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:04,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30482 states and 43470 transitions. [2024-11-13 12:49:04,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30482 states and 43470 transitions. [2024-11-13 12:49:04,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30482 to 21646. [2024-11-13 12:49:04,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4298715698050448) internal successors, (30951), 21645 states have internal predecessors, (30951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:04,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30951 transitions. [2024-11-13 12:49:04,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-11-13 12:49:04,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:49:04,579 INFO L424 stractBuchiCegarLoop]: Abstraction has 21646 states and 30951 transitions. [2024-11-13 12:49:04,579 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 12:49:04,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30951 transitions. [2024-11-13 12:49:04,645 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-13 12:49:04,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:04,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:04,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:04,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:04,649 INFO L745 eck$LassoCheckResult]: Stem: 321945#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 321946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 322579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 322580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 322686#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 322090#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 322091#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 322220#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 322221#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 321990#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 321777#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 321778#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 321950#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321951#L781 assume !(0 == ~M_E~0); 322483#L781-2 assume !(0 == ~T1_E~0); 322702#L786-1 assume !(0 == ~T2_E~0); 321737#L791-1 assume !(0 == ~T3_E~0); 321738#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 322303#L801-1 assume !(0 == ~T5_E~0); 322304#L806-1 assume !(0 == ~T6_E~0); 322673#L811-1 assume !(0 == ~T7_E~0); 322674#L816-1 assume !(0 == ~E_M~0); 322582#L821-1 assume !(0 == ~E_1~0); 322583#L826-1 assume !(0 == ~E_2~0); 322300#L831-1 assume !(0 == ~E_3~0); 322301#L836-1 assume !(0 == ~E_4~0); 322735#L841-1 assume !(0 == ~E_5~0); 321907#L846-1 assume !(0 == ~E_6~0); 321908#L851-1 assume !(0 == ~E_7~0); 322734#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 322606#L388 assume !(1 == ~m_pc~0); 322607#L388-2 is_master_triggered_~__retres1~0#1 := 0; 322733#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 322512#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 322513#L967 assume !(0 != activate_threads_~tmp~1#1); 322675#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 322676#L407 assume !(1 == ~t1_pc~0); 322685#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321720#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 321754#L975 assume !(0 != activate_threads_~tmp___0~0#1); 322600#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322601#L426 assume !(1 == ~t2_pc~0); 322615#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 322616#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 322067#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 322068#L983 assume !(0 != activate_threads_~tmp___1~0#1); 322730#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322729#L445 assume !(1 == ~t3_pc~0); 322703#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 322493#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 322494#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 322727#L991 assume !(0 != activate_threads_~tmp___2~0#1); 322726#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 322373#L464 assume !(1 == ~t4_pc~0); 321934#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321935#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 322723#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 322722#L999 assume !(0 != activate_threads_~tmp___3~0#1); 322721#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 322369#L483 assume !(1 == ~t5_pc~0); 322370#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 322554#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 322555#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 322638#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 322639#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 322720#L502 assume !(1 == ~t6_pc~0); 321884#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 321885#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 322052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322053#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 322532#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 322533#L521 assume !(1 == ~t7_pc~0); 322573#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 321779#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 321780#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 322712#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 322537#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322446#L869 assume !(1 == ~M_E~0); 322105#L869-2 assume !(1 == ~T1_E~0); 322106#L874-1 assume !(1 == ~T2_E~0); 322630#L879-1 assume !(1 == ~T3_E~0); 322631#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 321701#L889-1 assume !(1 == ~T5_E~0); 321702#L894-1 assume !(1 == ~T6_E~0); 321965#L899-1 assume !(1 == ~T7_E~0); 322399#L904-1 assume !(1 == ~E_M~0); 322128#L909-1 assume !(1 == ~E_1~0); 322129#L914-1 assume !(1 == ~E_2~0); 322323#L919-1 assume !(1 == ~E_3~0); 322042#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 321877#L929-1 assume !(1 == ~E_5~0); 321878#L934-1 assume !(1 == ~E_6~0); 322107#L939-1 assume !(1 == ~E_7~0); 322108#L944-1 assume { :end_inline_reset_delta_events } true; 322531#L1190-2 [2024-11-13 12:49:04,649 INFO L747 eck$LassoCheckResult]: Loop: 322531#L1190-2 assume !false; 340400#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 340395#L756-1 assume !false; 340393#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 340391#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 340381#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 340379#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 340374#L653 assume !(0 != eval_~tmp~0#1); 340375#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343084#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343081#L781-3 assume !(0 == ~M_E~0); 343079#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 343077#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 322241#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 321762#L796-3 assume !(0 == ~T4_E~0); 321764#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 322030#L806-3 assume !(0 == ~T6_E~0); 322031#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 322233#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 322475#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 322617#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 322404#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 322405#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 321918#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 321919#L846-3 assume !(0 == ~E_6~0); 322259#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 321810#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 321811#L388-27 assume 1 == ~m_pc~0; 322567#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 322568#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 322432#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 322433#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 321993#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 321994#L407-27 assume !(1 == ~t1_pc~0); 322434#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 322510#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 322314#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 322315#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 322281#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 321909#L426-27 assume !(1 == ~t2_pc~0); 321910#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 321920#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 321921#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 322406#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 322562#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322225#L445-27 assume !(1 == ~t3_pc~0); 322226#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 321759#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 321760#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 322227#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 322330#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 322020#L464-27 assume 1 == ~t4_pc~0; 322021#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 321758#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321829#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 322148#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 321902#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 321903#L483-27 assume !(1 == ~t5_pc~0); 322549#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 321812#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 321813#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 322523#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 322524#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 322647#L502-27 assume !(1 == ~t6_pc~0); 322253#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 322254#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 322632#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 322441#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 322442#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 321703#L521-27 assume !(1 == ~t7_pc~0); 321704#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 322706#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 343272#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 343271#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 322270#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322271#L869-3 assume !(1 == ~M_E~0); 322438#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 322149#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 322150#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 322216#L884-3 assume !(1 == ~T4_E~0); 322208#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 321866#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 321867#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 321889#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 321890#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 321845#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 321846#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 321883#L924-3 assume !(1 == ~E_4~0); 322421#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 322327#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 322328#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 321894#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 321895#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 321722#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 341387#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 326659#L1209 assume !(0 == start_simulation_~tmp~3#1); 326660#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 340433#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 340425#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 340423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 340419#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 340416#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 340411#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 340408#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 322531#L1190-2 [2024-11-13 12:49:04,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:04,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2024-11-13 12:49:04,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:04,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66722345] [2024-11-13 12:49:04,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:04,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:04,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:04,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:04,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:04,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66722345] [2024-11-13 12:49:04,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66722345] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:04,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:04,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:04,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551030319] [2024-11-13 12:49:04,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:04,759 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:49:04,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:04,759 INFO L85 PathProgramCache]: Analyzing trace with hash -1840266174, now seen corresponding path program 1 times [2024-11-13 12:49:04,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:04,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580041126] [2024-11-13 12:49:04,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:04,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:04,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:04,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:04,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:04,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580041126] [2024-11-13 12:49:04,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580041126] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:04,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:04,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:04,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984965235] [2024-11-13 12:49:04,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:04,819 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:04,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:04,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:49:04,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:49:04,820 INFO L87 Difference]: Start difference. First operand 21646 states and 30951 transitions. cyclomatic complexity: 9321 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:05,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:05,168 INFO L93 Difference]: Finished difference Result 28030 states and 39857 transitions. [2024-11-13 12:49:05,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28030 states and 39857 transitions. [2024-11-13 12:49:05,282 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27760 [2024-11-13 12:49:05,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28030 states to 28030 states and 39857 transitions. [2024-11-13 12:49:05,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28030 [2024-11-13 12:49:05,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28030 [2024-11-13 12:49:05,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28030 states and 39857 transitions. [2024-11-13 12:49:05,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:05,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28030 states and 39857 transitions. [2024-11-13 12:49:05,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28030 states and 39857 transitions. [2024-11-13 12:49:05,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28030 to 19206. [2024-11-13 12:49:05,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.42543996667708) internal successors, (27377), 19205 states have internal predecessors, (27377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:05,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27377 transitions. [2024-11-13 12:49:05,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-11-13 12:49:05,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:49:05,679 INFO L424 stractBuchiCegarLoop]: Abstraction has 19206 states and 27377 transitions. [2024-11-13 12:49:05,679 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 12:49:05,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27377 transitions. [2024-11-13 12:49:05,737 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-13 12:49:05,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:05,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:05,739 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:05,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:05,739 INFO L745 eck$LassoCheckResult]: Stem: 371631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 371632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 372232#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372233#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372299#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 371779#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 371780#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 371906#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371907#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371678#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371463#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 371464#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 371636#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 371637#L781 assume !(0 == ~M_E~0); 372152#L781-2 assume !(0 == ~T1_E~0); 372316#L786-1 assume !(0 == ~T2_E~0); 371423#L791-1 assume !(0 == ~T3_E~0); 371424#L796-1 assume !(0 == ~T4_E~0); 371987#L801-1 assume !(0 == ~T5_E~0); 371988#L806-1 assume !(0 == ~T6_E~0); 372020#L811-1 assume !(0 == ~T7_E~0); 371643#L816-1 assume !(0 == ~E_M~0); 371644#L821-1 assume !(0 == ~E_1~0); 371454#L826-1 assume !(0 == ~E_2~0); 371455#L831-1 assume !(0 == ~E_3~0); 371774#L836-1 assume !(0 == ~E_4~0); 371775#L841-1 assume !(0 == ~E_5~0); 371594#L846-1 assume !(0 == ~E_6~0); 371595#L851-1 assume !(0 == ~E_7~0); 371618#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 371619#L388 assume !(1 == ~m_pc~0); 371612#L388-2 is_master_triggered_~__retres1~0#1 := 0; 371613#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372125#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371469#L967 assume !(0 != activate_threads_~tmp~1#1); 371470#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 371401#L407 assume !(1 == ~t1_pc~0); 371402#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 371405#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371406#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371440#L975 assume !(0 != activate_threads_~tmp___0~0#1); 372229#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 371732#L426 assume !(1 == ~t2_pc~0); 371733#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372257#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371756#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 371757#L983 assume !(0 != activate_threads_~tmp___1~0#1); 372290#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371820#L445 assume !(1 == ~t3_pc~0); 371821#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372158#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 371400#L991 assume !(0 != activate_threads_~tmp___2~0#1); 372083#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372047#L464 assume !(1 == ~t4_pc~0); 371622#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371489#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371490#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 371501#L999 assume !(0 != activate_threads_~tmp___3~0#1); 371800#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371801#L483 assume !(1 == ~t5_pc~0); 372044#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372209#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372177#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 371716#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 371717#L502 assume !(1 == ~t6_pc~0); 371572#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 371530#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 371531#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 371742#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 371949#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 372188#L521 assume !(1 == ~t7_pc~0); 372225#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 371465#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 371466#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 372218#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 372192#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 372116#L869 assume !(1 == ~M_E~0); 371794#L869-2 assume !(1 == ~T1_E~0); 371795#L874-1 assume !(1 == ~T2_E~0); 372269#L879-1 assume !(1 == ~T3_E~0); 371867#L884-1 assume !(1 == ~T4_E~0); 371387#L889-1 assume !(1 == ~T5_E~0); 371388#L894-1 assume !(1 == ~T6_E~0); 371652#L899-1 assume !(1 == ~T7_E~0); 372072#L904-1 assume !(1 == ~E_M~0); 371817#L909-1 assume !(1 == ~E_1~0); 371818#L914-1 assume !(1 == ~E_2~0); 372005#L919-1 assume !(1 == ~E_3~0); 371731#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 371564#L929-1 assume !(1 == ~E_5~0); 371565#L934-1 assume !(1 == ~E_6~0); 371796#L939-1 assume !(1 == ~E_7~0); 371797#L944-1 assume { :end_inline_reset_delta_events } true; 372187#L1190-2 [2024-11-13 12:49:05,740 INFO L747 eck$LassoCheckResult]: Loop: 372187#L1190-2 assume !false; 384809#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 384803#L756-1 assume !false; 384801#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384799#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384791#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384788#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 384786#L653 assume !(0 != eval_~tmp~0#1); 384787#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 390333#L781-3 assume !(0 == ~M_E~0); 390331#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 390329#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 390327#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 390325#L796-3 assume !(0 == ~T4_E~0); 390323#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 390320#L806-3 assume !(0 == ~T6_E~0); 390318#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 390316#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 390314#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 390312#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 390310#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 390309#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 390308#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390306#L846-3 assume !(0 == ~E_6~0); 390304#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 390302#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390300#L388-27 assume !(1 == ~m_pc~0); 390297#L388-29 is_master_triggered_~__retres1~0#1 := 0; 390294#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390292#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390290#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 390288#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390286#L407-27 assume !(1 == ~t1_pc~0); 390284#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 390279#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390277#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390275#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 390273#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390271#L426-27 assume 1 == ~t2_pc~0; 390268#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 390265#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390263#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390261#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 390260#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390259#L445-27 assume !(1 == ~t3_pc~0); 390258#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 390256#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390251#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390216#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 390215#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390214#L464-27 assume 1 == ~t4_pc~0; 390213#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 390211#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390210#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 371921#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 371589#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371590#L483-27 assume !(1 == ~t5_pc~0); 372308#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 390140#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 385778#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 385769#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 385767#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 385765#L502-27 assume !(1 == ~t6_pc~0); 385762#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 385760#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 385758#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 385756#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 385754#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 385752#L521-27 assume 1 == ~t7_pc~0; 385749#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 385747#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 385745#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 385743#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 385740#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 385738#L869-3 assume !(1 == ~M_E~0); 377279#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 385735#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 385733#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 385731#L884-3 assume !(1 == ~T4_E~0); 385729#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 385727#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 385725#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 385723#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 385721#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 385718#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 385716#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 385714#L924-3 assume !(1 == ~E_4~0); 385712#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 385710#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 385708#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 385705#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 385699#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 385691#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 385690#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 377453#L1209 assume !(0 == start_simulation_~tmp~3#1); 377454#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384831#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384823#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 384819#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 384818#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 384814#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 384812#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 372187#L1190-2 [2024-11-13 12:49:05,741 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:05,742 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2024-11-13 12:49:05,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:05,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787918710] [2024-11-13 12:49:05,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:05,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:05,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:06,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:06,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:06,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787918710] [2024-11-13 12:49:06,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787918710] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:06,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:06,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:06,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358390328] [2024-11-13 12:49:06,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:06,029 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:49:06,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:06,029 INFO L85 PathProgramCache]: Analyzing trace with hash -816704575, now seen corresponding path program 1 times [2024-11-13 12:49:06,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:06,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380701192] [2024-11-13 12:49:06,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:06,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:06,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:06,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:06,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:06,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380701192] [2024-11-13 12:49:06,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380701192] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:06,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:06,100 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:06,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503801870] [2024-11-13 12:49:06,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:06,101 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:06,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:06,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:49:06,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:49:06,101 INFO L87 Difference]: Start difference. First operand 19206 states and 27377 transitions. cyclomatic complexity: 8187 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:06,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:06,385 INFO L93 Difference]: Finished difference Result 30510 states and 43007 transitions. [2024-11-13 12:49:06,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30510 states and 43007 transitions. [2024-11-13 12:49:06,517 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30116 [2024-11-13 12:49:06,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30510 states to 30510 states and 43007 transitions. [2024-11-13 12:49:06,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30510 [2024-11-13 12:49:06,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30510 [2024-11-13 12:49:06,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30510 states and 43007 transitions. [2024-11-13 12:49:06,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:06,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30510 states and 43007 transitions. [2024-11-13 12:49:06,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30510 states and 43007 transitions. [2024-11-13 12:49:07,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30510 to 21646. [2024-11-13 12:49:07,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21646 states, 21646 states have (on average 1.4149496442760787) internal successors, (30628), 21645 states have internal predecessors, (30628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:07,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21646 states to 21646 states and 30628 transitions. [2024-11-13 12:49:07,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-11-13 12:49:07,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:49:07,195 INFO L424 stractBuchiCegarLoop]: Abstraction has 21646 states and 30628 transitions. [2024-11-13 12:49:07,195 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 12:49:07,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21646 states and 30628 transitions. [2024-11-13 12:49:07,282 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21360 [2024-11-13 12:49:07,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:07,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:07,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:07,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:07,285 INFO L745 eck$LassoCheckResult]: Stem: 421352#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 421353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 421971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 421972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422074#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 421499#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 421500#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 421631#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 421632#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 421398#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 421188#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 421189#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 421359#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421360#L781 assume !(0 == ~M_E~0); 421877#L781-2 assume !(0 == ~T1_E~0); 422091#L786-1 assume !(0 == ~T2_E~0); 421152#L791-1 assume !(0 == ~T3_E~0); 421153#L796-1 assume !(0 == ~T4_E~0); 421707#L801-1 assume !(0 == ~T5_E~0); 421708#L806-1 assume !(0 == ~T6_E~0); 421738#L811-1 assume !(0 == ~T7_E~0); 421363#L816-1 assume !(0 == ~E_M~0); 421364#L821-1 assume !(0 == ~E_1~0); 421180#L826-1 assume !(0 == ~E_2~0); 421181#L831-1 assume !(0 == ~E_3~0); 421493#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 421494#L841-1 assume !(0 == ~E_5~0); 421316#L846-1 assume !(0 == ~E_6~0); 421317#L851-1 assume !(0 == ~E_7~0); 422150#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421996#L388 assume !(1 == ~m_pc~0); 421997#L388-2 is_master_triggered_~__retres1~0#1 := 0; 422149#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 421903#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421904#L967 assume !(0 != activate_threads_~tmp~1#1); 422064#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422065#L407 assume !(1 == ~t1_pc~0); 422072#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421134#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421168#L975 assume !(0 != activate_threads_~tmp___0~0#1); 421991#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421992#L426 assume !(1 == ~t2_pc~0); 422006#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422007#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 421473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 421474#L983 assume !(0 != activate_threads_~tmp___1~0#1); 422145#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422144#L445 assume !(1 == ~t3_pc~0); 422143#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422142#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421126#L991 assume !(0 != activate_threads_~tmp___2~0#1); 421805#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 421884#L464 assume !(1 == ~t4_pc~0); 422138#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 422137#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 422136#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422135#L999 assume !(0 != activate_threads_~tmp___3~0#1); 422134#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422133#L483 assume !(1 == ~t5_pc~0); 422132#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422131#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422130#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422129#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 422128#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422127#L502 assume !(1 == ~t6_pc~0); 422126#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 422125#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422124#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 422123#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 422122#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 422121#L521 assume !(1 == ~t7_pc~0); 422119#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 422117#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 422115#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 422113#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 422112#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422111#L869 assume !(1 == ~M_E~0); 422110#L869-2 assume !(1 == ~T1_E~0); 422109#L874-1 assume !(1 == ~T2_E~0); 422108#L879-1 assume !(1 == ~T3_E~0); 422107#L884-1 assume !(1 == ~T4_E~0); 422106#L889-1 assume !(1 == ~T5_E~0); 422105#L894-1 assume !(1 == ~T6_E~0); 422104#L899-1 assume !(1 == ~T7_E~0); 422103#L904-1 assume !(1 == ~E_M~0); 422102#L909-1 assume !(1 == ~E_1~0); 422101#L914-1 assume !(1 == ~E_2~0); 422100#L919-1 assume !(1 == ~E_3~0); 422099#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 421286#L929-1 assume !(1 == ~E_5~0); 421287#L934-1 assume !(1 == ~E_6~0); 421521#L939-1 assume !(1 == ~E_7~0); 421522#L944-1 assume { :end_inline_reset_delta_events } true; 421921#L1190-2 [2024-11-13 12:49:07,286 INFO L747 eck$LassoCheckResult]: Loop: 421921#L1190-2 assume !false; 432709#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 432704#L756-1 assume !false; 432702#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 430848#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 430840#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 430839#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 430835#L653 assume !(0 != eval_~tmp~0#1); 430836#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 433134#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 433132#L781-3 assume !(0 == ~M_E~0); 433130#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 433127#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 433125#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 433121#L796-3 assume !(0 == ~T4_E~0); 433102#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 433097#L806-3 assume !(0 == ~T6_E~0); 433048#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 428637#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 428619#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 428616#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 428613#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 428608#L836-3 assume !(0 == ~E_4~0); 428609#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 433547#L846-3 assume !(0 == ~E_6~0); 433545#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 433543#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 433516#L388-27 assume 1 == ~m_pc~0; 433484#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 433481#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 433478#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 433184#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 433183#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433182#L407-27 assume !(1 == ~t1_pc~0); 433181#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 433180#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 433178#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 433175#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 433173#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 433171#L426-27 assume !(1 == ~t2_pc~0); 433168#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 433166#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433164#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 433162#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 433160#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 433158#L445-27 assume !(1 == ~t3_pc~0); 433156#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 433154#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433152#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 433149#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 433147#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 433143#L464-27 assume !(1 == ~t4_pc~0); 428576#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 433140#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 433138#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 433131#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 433123#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 433104#L483-27 assume !(1 == ~t5_pc~0); 433099#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 433094#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 433089#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 433088#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 433087#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 433086#L502-27 assume !(1 == ~t6_pc~0); 433085#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 433084#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 433075#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 433073#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 433071#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 433069#L521-27 assume 1 == ~t7_pc~0; 433066#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 433064#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 433062#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 433061#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 433059#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433058#L869-3 assume !(1 == ~M_E~0); 425221#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 433056#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 433054#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 433052#L884-3 assume !(1 == ~T4_E~0); 433049#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 428638#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 428620#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 428617#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 428614#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 428611#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 428550#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 428526#L924-3 assume !(1 == ~E_4~0); 428524#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 428523#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 428522#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 428521#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 428519#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 428512#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 428511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 425514#L1209 assume !(0 == start_simulation_~tmp~3#1); 425515#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 433082#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 433074#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 433072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 433070#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 433068#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 433065#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 433063#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 421921#L1190-2 [2024-11-13 12:49:07,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:07,287 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2024-11-13 12:49:07,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:07,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327351920] [2024-11-13 12:49:07,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:07,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:07,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:07,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:07,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:07,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327351920] [2024-11-13 12:49:07,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327351920] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:07,391 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:07,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:07,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998410747] [2024-11-13 12:49:07,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:07,393 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 12:49:07,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:07,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1598735808, now seen corresponding path program 1 times [2024-11-13 12:49:07,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:07,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463000157] [2024-11-13 12:49:07,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:07,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:07,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:07,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:07,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:07,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463000157] [2024-11-13 12:49:07,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463000157] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:07,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:07,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:07,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917676694] [2024-11-13 12:49:07,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:07,561 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:07,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:07,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 12:49:07,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 12:49:07,561 INFO L87 Difference]: Start difference. First operand 21646 states and 30628 transitions. cyclomatic complexity: 8998 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:07,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:07,817 INFO L93 Difference]: Finished difference Result 27562 states and 38762 transitions. [2024-11-13 12:49:07,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27562 states and 38762 transitions. [2024-11-13 12:49:07,975 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27284 [2024-11-13 12:49:08,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27562 states to 27562 states and 38762 transitions. [2024-11-13 12:49:08,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27562 [2024-11-13 12:49:08,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27562 [2024-11-13 12:49:08,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27562 states and 38762 transitions. [2024-11-13 12:49:08,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:08,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27562 states and 38762 transitions. [2024-11-13 12:49:08,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27562 states and 38762 transitions. [2024-11-13 12:49:08,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27562 to 19206. [2024-11-13 12:49:08,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19206 states, 19206 states have (on average 1.408622305529522) internal successors, (27054), 19205 states have internal predecessors, (27054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:08,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19206 states to 19206 states and 27054 transitions. [2024-11-13 12:49:08,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-11-13 12:49:08,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 12:49:08,757 INFO L424 stractBuchiCegarLoop]: Abstraction has 19206 states and 27054 transitions. [2024-11-13 12:49:08,757 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 12:49:08,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19206 states and 27054 transitions. [2024-11-13 12:49:08,806 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18992 [2024-11-13 12:49:08,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:08,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:08,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:08,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:08,809 INFO L745 eck$LassoCheckResult]: Stem: 470575#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 470576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 471180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 471181#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 471259#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 470722#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 470723#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 470851#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 470852#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 470623#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 470409#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 470410#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 470581#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 470582#L781 assume !(0 == ~M_E~0); 471096#L781-2 assume !(0 == ~T1_E~0); 471275#L786-1 assume !(0 == ~T2_E~0); 470372#L791-1 assume !(0 == ~T3_E~0); 470373#L796-1 assume !(0 == ~T4_E~0); 470925#L801-1 assume !(0 == ~T5_E~0); 470926#L806-1 assume !(0 == ~T6_E~0); 470958#L811-1 assume !(0 == ~T7_E~0); 470588#L816-1 assume !(0 == ~E_M~0); 470589#L821-1 assume !(0 == ~E_1~0); 470400#L826-1 assume !(0 == ~E_2~0); 470401#L831-1 assume !(0 == ~E_3~0); 470717#L836-1 assume !(0 == ~E_4~0); 470718#L841-1 assume !(0 == ~E_5~0); 470537#L846-1 assume !(0 == ~E_6~0); 470538#L851-1 assume !(0 == ~E_7~0); 470561#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470562#L388 assume !(1 == ~m_pc~0); 470555#L388-2 is_master_triggered_~__retres1~0#1 := 0; 470556#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471072#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 470415#L967 assume !(0 != activate_threads_~tmp~1#1); 470416#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470347#L407 assume !(1 == ~t1_pc~0); 470348#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 470354#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470355#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470388#L975 assume !(0 != activate_threads_~tmp___0~0#1); 471178#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470677#L426 assume !(1 == ~t2_pc~0); 470678#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 471206#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470698#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470699#L983 assume !(0 != activate_threads_~tmp___1~0#1); 471245#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470764#L445 assume !(1 == ~t3_pc~0); 470765#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 471107#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470345#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470346#L991 assume !(0 != activate_threads_~tmp___2~0#1); 471027#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 470986#L464 assume !(1 == ~t4_pc~0); 470568#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 470435#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 470436#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470449#L999 assume !(0 != activate_threads_~tmp___3~0#1); 470744#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 470745#L483 assume !(1 == ~t5_pc~0); 470983#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 471156#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471123#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 471124#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 470663#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470664#L502 assume !(1 == ~t6_pc~0); 470514#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 470474#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 470475#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 470687#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 470889#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471136#L521 assume !(1 == ~t7_pc~0); 471174#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 470411#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 470412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471167#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 471140#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471063#L869 assume !(1 == ~M_E~0); 470738#L869-2 assume !(1 == ~T1_E~0); 470739#L874-1 assume !(1 == ~T2_E~0); 471218#L879-1 assume !(1 == ~T3_E~0); 470814#L884-1 assume !(1 == ~T4_E~0); 470333#L889-1 assume !(1 == ~T5_E~0); 470334#L894-1 assume !(1 == ~T6_E~0); 470599#L899-1 assume !(1 == ~T7_E~0); 471013#L904-1 assume !(1 == ~E_M~0); 470761#L909-1 assume !(1 == ~E_1~0); 470762#L914-1 assume !(1 == ~E_2~0); 470944#L919-1 assume !(1 == ~E_3~0); 470676#L924-1 assume !(1 == ~E_4~0); 470507#L929-1 assume !(1 == ~E_5~0); 470508#L934-1 assume !(1 == ~E_6~0); 470742#L939-1 assume !(1 == ~E_7~0); 470743#L944-1 assume { :end_inline_reset_delta_events } true; 471135#L1190-2 [2024-11-13 12:49:08,809 INFO L747 eck$LassoCheckResult]: Loop: 471135#L1190-2 assume !false; 478882#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 478877#L756-1 assume !false; 478875#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 473663#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 473654#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 473652#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 473648#L653 assume !(0 != eval_~tmp~0#1); 473649#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 479382#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 479381#L781-3 assume !(0 == ~M_E~0); 479380#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 479379#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 479378#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 479377#L796-3 assume !(0 == ~T4_E~0); 479375#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 479373#L806-3 assume !(0 == ~T6_E~0); 479371#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 479369#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 479367#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 479365#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 479363#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 479361#L836-3 assume !(0 == ~E_4~0); 479359#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 479357#L846-3 assume !(0 == ~E_6~0); 479355#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 479353#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 479351#L388-27 assume !(1 == ~m_pc~0); 479349#L388-29 is_master_triggered_~__retres1~0#1 := 0; 479346#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 479344#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 479342#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 479340#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 479338#L407-27 assume !(1 == ~t1_pc~0); 479337#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 479334#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 479332#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 479330#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 479328#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 479326#L426-27 assume 1 == ~t2_pc~0; 479324#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 479321#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 479319#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 479317#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 479315#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 479313#L445-27 assume !(1 == ~t3_pc~0); 479311#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 479308#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 479306#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 479304#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 479302#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 479298#L464-27 assume !(1 == ~t4_pc~0); 479296#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 479294#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 479292#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 479290#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 479288#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 479287#L483-27 assume !(1 == ~t5_pc~0); 479284#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 479282#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 479280#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 479278#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 479276#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 479274#L502-27 assume !(1 == ~t6_pc~0); 479272#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 479269#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 479267#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 479265#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 479263#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 479261#L521-27 assume !(1 == ~t7_pc~0); 479259#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 479384#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 479383#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 479251#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 479249#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 479247#L869-3 assume !(1 == ~M_E~0); 476041#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 479243#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 479241#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 479239#L884-3 assume !(1 == ~T4_E~0); 479236#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 479234#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 479232#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 479231#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 479229#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 479129#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 479124#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 479120#L924-3 assume !(1 == ~E_4~0); 479114#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 479110#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 479106#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 479103#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478942#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478934#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 475966#L1209 assume !(0 == start_simulation_~tmp~3#1); 475967#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 478904#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 478896#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 478894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 478892#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 478890#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 478888#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 478885#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 471135#L1190-2 [2024-11-13 12:49:08,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:08,810 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2024-11-13 12:49:08,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:08,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394710336] [2024-11-13 12:49:08,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:08,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:08,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:08,834 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:08,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:08,941 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:08,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:08,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1527723969, now seen corresponding path program 1 times [2024-11-13 12:49:08,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:08,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040207879] [2024-11-13 12:49:08,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:08,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:08,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:09,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:09,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:09,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040207879] [2024-11-13 12:49:09,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040207879] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:09,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:09,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:09,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716225131] [2024-11-13 12:49:09,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:09,033 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:09,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:09,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:09,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:09,033 INFO L87 Difference]: Start difference. First operand 19206 states and 27054 transitions. cyclomatic complexity: 7864 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:09,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:09,246 INFO L93 Difference]: Finished difference Result 19430 states and 27278 transitions. [2024-11-13 12:49:09,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19430 states and 27278 transitions. [2024-11-13 12:49:09,354 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19216 [2024-11-13 12:49:09,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19430 states to 19430 states and 27278 transitions. [2024-11-13 12:49:09,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19430 [2024-11-13 12:49:09,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19430 [2024-11-13 12:49:09,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19430 states and 27278 transitions. [2024-11-13 12:49:09,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:09,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19430 states and 27278 transitions. [2024-11-13 12:49:09,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19430 states and 27278 transitions. [2024-11-13 12:49:09,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19430 to 19302. [2024-11-13 12:49:09,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19302 states, 19302 states have (on average 1.4065899906745416) internal successors, (27150), 19301 states have internal predecessors, (27150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:09,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19302 states to 19302 states and 27150 transitions. [2024-11-13 12:49:09,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19302 states and 27150 transitions. [2024-11-13 12:49:09,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:09,661 INFO L424 stractBuchiCegarLoop]: Abstraction has 19302 states and 27150 transitions. [2024-11-13 12:49:09,661 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 12:49:09,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19302 states and 27150 transitions. [2024-11-13 12:49:09,721 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19088 [2024-11-13 12:49:09,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:09,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:09,725 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:09,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:09,725 INFO L745 eck$LassoCheckResult]: Stem: 509222#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 509223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 509860#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509861#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509959#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 509369#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 509370#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509499#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509500#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509269#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509052#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509053#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509229#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509230#L781 assume !(0 == ~M_E~0); 509760#L781-2 assume !(0 == ~T1_E~0); 509980#L786-1 assume !(0 == ~T2_E~0); 509016#L791-1 assume !(0 == ~T3_E~0); 509017#L796-1 assume !(0 == ~T4_E~0); 509583#L801-1 assume !(0 == ~T5_E~0); 509584#L806-1 assume !(0 == ~T6_E~0); 509617#L811-1 assume !(0 == ~T7_E~0); 509233#L816-1 assume !(0 == ~E_M~0); 509234#L821-1 assume !(0 == ~E_1~0); 509044#L826-1 assume !(0 == ~E_2~0); 509045#L831-1 assume !(0 == ~E_3~0); 509364#L836-1 assume !(0 == ~E_4~0); 509365#L841-1 assume !(0 == ~E_5~0); 509186#L846-1 assume !(0 == ~E_6~0); 509187#L851-1 assume !(0 == ~E_7~0); 509209#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509210#L388 assume !(1 == ~m_pc~0); 509203#L388-2 is_master_triggered_~__retres1~0#1 := 0; 509204#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 509733#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 509058#L967 assume !(0 != activate_threads_~tmp~1#1); 509059#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 508991#L407 assume !(1 == ~t1_pc~0); 508992#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 508998#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 508999#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 509032#L975 assume !(0 != activate_threads_~tmp___0~0#1); 509856#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509324#L426 assume !(1 == ~t2_pc~0); 509325#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509884#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 509348#L983 assume !(0 != activate_threads_~tmp___1~0#1); 509939#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509411#L445 assume !(1 == ~t3_pc~0); 509412#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 509768#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 508990#L991 assume !(0 != activate_threads_~tmp___2~0#1); 509683#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 509645#L464 assume !(1 == ~t4_pc~0); 509215#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 509078#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 509079#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509094#L999 assume !(0 != activate_threads_~tmp___3~0#1); 509390#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509391#L483 assume !(1 == ~t5_pc~0); 509642#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 509830#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509791#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 509792#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 509310#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 509311#L502 assume !(1 == ~t6_pc~0); 509161#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 509119#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509336#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 509540#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 509807#L521 assume !(1 == ~t7_pc~0); 509852#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 509054#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 509055#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509844#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 509811#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 509723#L869 assume !(1 == ~M_E~0); 509384#L869-2 assume !(1 == ~T1_E~0); 509385#L874-1 assume !(1 == ~T2_E~0); 509899#L879-1 assume !(1 == ~T3_E~0); 509461#L884-1 assume !(1 == ~T4_E~0); 508977#L889-1 assume !(1 == ~T5_E~0); 508978#L894-1 assume !(1 == ~T6_E~0); 509246#L899-1 assume !(1 == ~T7_E~0); 509673#L904-1 assume !(1 == ~E_M~0); 509408#L909-1 assume !(1 == ~E_1~0); 509409#L914-1 assume !(1 == ~E_2~0); 509603#L919-1 assume !(1 == ~E_3~0); 509323#L924-1 assume !(1 == ~E_4~0); 509153#L929-1 assume !(1 == ~E_5~0); 509154#L934-1 assume !(1 == ~E_6~0); 509388#L939-1 assume !(1 == ~E_7~0); 509389#L944-1 assume { :end_inline_reset_delta_events } true; 509806#L1190-2 [2024-11-13 12:49:09,726 INFO L747 eck$LassoCheckResult]: Loop: 509806#L1190-2 assume !false; 525137#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 525132#L756-1 assume !false; 525130#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 525128#L596 assume !(0 == ~m_st~0); 525122#L600 assume !(0 == ~t1_st~0); 525123#L604 assume !(0 == ~t2_st~0); 525127#L608 assume !(0 == ~t3_st~0); 525120#L612 assume !(0 == ~t4_st~0); 525121#L616 assume !(0 == ~t5_st~0); 525126#L620 assume !(0 == ~t6_st~0); 525124#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 525125#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 525362#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 525360#L653 assume !(0 != eval_~tmp~0#1); 525358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 525356#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525354#L781-3 assume !(0 == ~M_E~0); 525352#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 525350#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 525349#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 525346#L796-3 assume !(0 == ~T4_E~0); 525344#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 525342#L806-3 assume !(0 == ~T6_E~0); 525340#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 525338#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 525336#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 525334#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 525332#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 525330#L836-3 assume !(0 == ~E_4~0); 525328#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 525326#L846-3 assume !(0 == ~E_6~0); 525324#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 525322#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525320#L388-27 assume 1 == ~m_pc~0; 525317#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 525315#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 525313#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 525311#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 525309#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 525306#L407-27 assume !(1 == ~t1_pc~0); 525304#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 525302#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 525299#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 525297#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 525296#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 525295#L426-27 assume !(1 == ~t2_pc~0); 525293#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 525291#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 525289#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 525288#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 525287#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 525286#L445-27 assume !(1 == ~t3_pc~0); 525285#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 525284#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 525283#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 525281#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 525279#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 525275#L464-27 assume !(1 == ~t4_pc~0); 525273#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 525271#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525269#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525267#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 525265#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 525263#L483-27 assume !(1 == ~t5_pc~0); 525261#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 525259#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 525257#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 525255#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 525253#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 525251#L502-27 assume !(1 == ~t6_pc~0); 525249#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 525247#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 525245#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 525243#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 525241#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525239#L521-27 assume 1 == ~t7_pc~0; 525235#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 525233#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 525231#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525229#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 525226#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525224#L869-3 assume !(1 == ~M_E~0); 525219#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 525217#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 525215#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 525213#L884-3 assume !(1 == ~T4_E~0); 525211#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 525209#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 525206#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 525204#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 525202#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 525200#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 525198#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 525196#L924-3 assume !(1 == ~E_4~0); 525193#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 525191#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 525189#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 525187#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 525180#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 525172#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 525170#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 525168#L1209 assume !(0 == start_simulation_~tmp~3#1); 525165#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 525158#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 525150#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 525148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 525146#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 525144#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 525142#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 525140#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 509806#L1190-2 [2024-11-13 12:49:09,726 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:09,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2024-11-13 12:49:09,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:09,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984258170] [2024-11-13 12:49:09,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:09,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:09,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:09,743 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:09,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:09,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:09,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:09,817 INFO L85 PathProgramCache]: Analyzing trace with hash 589067854, now seen corresponding path program 1 times [2024-11-13 12:49:09,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:09,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036375243] [2024-11-13 12:49:09,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:09,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:09,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:09,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:09,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:09,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036375243] [2024-11-13 12:49:09,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036375243] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:09,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:09,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:09,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92011799] [2024-11-13 12:49:09,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:09,917 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:09,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:09,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:09,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:09,919 INFO L87 Difference]: Start difference. First operand 19302 states and 27150 transitions. cyclomatic complexity: 7864 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:10,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:10,304 INFO L93 Difference]: Finished difference Result 19302 states and 26909 transitions. [2024-11-13 12:49:10,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19302 states and 26909 transitions. [2024-11-13 12:49:10,543 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19088 [2024-11-13 12:49:10,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19302 states to 19302 states and 26909 transitions. [2024-11-13 12:49:10,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19302 [2024-11-13 12:49:10,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19302 [2024-11-13 12:49:10,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19302 states and 26909 transitions. [2024-11-13 12:49:10,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:10,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19302 states and 26909 transitions. [2024-11-13 12:49:10,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19302 states and 26909 transitions. [2024-11-13 12:49:10,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19302 to 19302. [2024-11-13 12:49:10,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19302 states, 19302 states have (on average 1.394104237902808) internal successors, (26909), 19301 states have internal predecessors, (26909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:10,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19302 states to 19302 states and 26909 transitions. [2024-11-13 12:49:10,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19302 states and 26909 transitions. [2024-11-13 12:49:10,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:10,823 INFO L424 stractBuchiCegarLoop]: Abstraction has 19302 states and 26909 transitions. [2024-11-13 12:49:10,823 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 12:49:10,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19302 states and 26909 transitions. [2024-11-13 12:49:10,880 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19088 [2024-11-13 12:49:10,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:10,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:10,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:10,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:10,883 INFO L745 eck$LassoCheckResult]: Stem: 547828#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 547829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 548432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 548433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 548513#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 547975#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 547976#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 548107#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 548108#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 547874#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 547664#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 547665#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 547834#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 547835#L781 assume !(0 == ~M_E~0); 548345#L781-2 assume !(0 == ~T1_E~0); 548535#L786-1 assume !(0 == ~T2_E~0); 547625#L791-1 assume !(0 == ~T3_E~0); 547626#L796-1 assume !(0 == ~T4_E~0); 548180#L801-1 assume !(0 == ~T5_E~0); 548181#L806-1 assume !(0 == ~T6_E~0); 548211#L811-1 assume !(0 == ~T7_E~0); 547840#L816-1 assume !(0 == ~E_M~0); 547841#L821-1 assume !(0 == ~E_1~0); 547656#L826-1 assume !(0 == ~E_2~0); 547657#L831-1 assume !(0 == ~E_3~0); 547970#L836-1 assume !(0 == ~E_4~0); 547971#L841-1 assume !(0 == ~E_5~0); 547791#L846-1 assume !(0 == ~E_6~0); 547792#L851-1 assume !(0 == ~E_7~0); 547814#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 547815#L388 assume !(1 == ~m_pc~0); 547808#L388-2 is_master_triggered_~__retres1~0#1 := 0; 547809#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 548321#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 547670#L967 assume !(0 != activate_threads_~tmp~1#1); 547671#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 547603#L407 assume !(1 == ~t1_pc~0); 547604#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 547607#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 547608#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 547642#L975 assume !(0 != activate_threads_~tmp___0~0#1); 548429#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 547929#L426 assume !(1 == ~t2_pc~0); 547930#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 548459#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547952#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 547953#L983 assume !(0 != activate_threads_~tmp___1~0#1); 548501#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 548019#L445 assume !(1 == ~t3_pc~0); 548020#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 548353#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 547601#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 547602#L991 assume !(0 != activate_threads_~tmp___2~0#1); 548280#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 548241#L464 assume !(1 == ~t4_pc~0); 547818#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 547690#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547691#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 547702#L999 assume !(0 != activate_threads_~tmp___3~0#1); 547998#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 547999#L483 assume !(1 == ~t5_pc~0); 548237#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 548410#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 548373#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 547913#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 547914#L502 assume !(1 == ~t6_pc~0); 547769#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 547729#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 547730#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 547939#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 548145#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548386#L521 assume !(1 == ~t7_pc~0); 548426#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 548461#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 548521#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 548522#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 548390#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548311#L869 assume !(1 == ~M_E~0); 547992#L869-2 assume !(1 == ~T1_E~0); 547993#L874-1 assume !(1 == ~T2_E~0); 548472#L879-1 assume !(1 == ~T3_E~0); 548070#L884-1 assume !(1 == ~T4_E~0); 547589#L889-1 assume !(1 == ~T5_E~0); 547590#L894-1 assume !(1 == ~T6_E~0); 547848#L899-1 assume !(1 == ~T7_E~0); 548267#L904-1 assume !(1 == ~E_M~0); 548016#L909-1 assume !(1 == ~E_1~0); 548017#L914-1 assume !(1 == ~E_2~0); 548197#L919-1 assume !(1 == ~E_3~0); 547928#L924-1 assume !(1 == ~E_4~0); 547762#L929-1 assume !(1 == ~E_5~0); 547763#L934-1 assume !(1 == ~E_6~0); 547994#L939-1 assume !(1 == ~E_7~0); 547995#L944-1 assume { :end_inline_reset_delta_events } true; 548385#L1190-2 [2024-11-13 12:49:10,884 INFO L747 eck$LassoCheckResult]: Loop: 548385#L1190-2 assume !false; 555209#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 555205#L756-1 assume !false; 555204#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 555203#L596 assume !(0 == ~m_st~0); 555199#L600 assume !(0 == ~t1_st~0); 555200#L604 assume !(0 == ~t2_st~0); 555202#L608 assume !(0 == ~t3_st~0); 555195#L612 assume !(0 == ~t4_st~0); 555196#L616 assume !(0 == ~t5_st~0); 555201#L620 assume !(0 == ~t6_st~0); 555197#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 555198#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 554699#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 554700#L653 assume !(0 != eval_~tmp~0#1); 555569#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555567#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 555565#L781-3 assume !(0 == ~M_E~0); 555563#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 555560#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 555557#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 555554#L796-3 assume !(0 == ~T4_E~0); 555551#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 555548#L806-3 assume !(0 == ~T6_E~0); 555545#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 555542#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 555539#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 555536#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 555533#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 555530#L836-3 assume !(0 == ~E_4~0); 555527#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 555524#L846-3 assume !(0 == ~E_6~0); 555521#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 555518#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 555507#L388-27 assume 1 == ~m_pc~0; 555503#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 555499#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 555495#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 555493#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 555490#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555486#L407-27 assume !(1 == ~t1_pc~0); 555483#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 555480#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 555477#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 555474#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 555471#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 555468#L426-27 assume !(1 == ~t2_pc~0); 555464#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 555460#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 555457#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 555454#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 555451#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 555447#L445-27 assume !(1 == ~t3_pc~0); 555444#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 555441#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 555438#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555435#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 555432#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 555428#L464-27 assume !(1 == ~t4_pc~0); 555424#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 555421#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 555418#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 555415#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 555411#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 555407#L483-27 assume !(1 == ~t5_pc~0); 555402#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 555398#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 555394#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 555390#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 555386#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555382#L502-27 assume !(1 == ~t6_pc~0); 555378#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 555374#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 555370#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 555366#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 555362#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 555358#L521-27 assume !(1 == ~t7_pc~0); 555352#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 555346#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 555340#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 555334#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 555329#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 555324#L869-3 assume !(1 == ~M_E~0); 555318#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 555314#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 555310#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 555307#L884-3 assume !(1 == ~T4_E~0); 555303#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 555299#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 555296#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 555293#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 555290#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 555287#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 555284#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 555281#L924-3 assume !(1 == ~E_4~0); 555278#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 555275#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 555272#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 555269#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 555264#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 555255#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 555252#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 555248#L1209 assume !(0 == start_simulation_~tmp~3#1); 555245#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 555239#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 555230#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 555227#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 555224#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 555222#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 555218#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 555216#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 548385#L1190-2 [2024-11-13 12:49:10,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:10,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2024-11-13 12:49:10,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:10,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982367426] [2024-11-13 12:49:10,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:10,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:10,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:10,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:10,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:10,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:10,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:10,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1640516943, now seen corresponding path program 1 times [2024-11-13 12:49:10,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:10,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089371112] [2024-11-13 12:49:10,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:10,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:10,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:11,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:11,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:11,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089371112] [2024-11-13 12:49:11,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089371112] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:11,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:11,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:11,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269770075] [2024-11-13 12:49:11,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:11,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:11,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:11,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:11,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:11,065 INFO L87 Difference]: Start difference. First operand 19302 states and 26909 transitions. cyclomatic complexity: 7623 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:11,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:11,419 INFO L93 Difference]: Finished difference Result 19686 states and 27180 transitions. [2024-11-13 12:49:11,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19686 states and 27180 transitions. [2024-11-13 12:49:11,497 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19472 [2024-11-13 12:49:11,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19686 states to 19686 states and 27180 transitions. [2024-11-13 12:49:11,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19686 [2024-11-13 12:49:11,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19686 [2024-11-13 12:49:11,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19686 states and 27180 transitions. [2024-11-13 12:49:11,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:11,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19686 states and 27180 transitions. [2024-11-13 12:49:11,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19686 states and 27180 transitions. [2024-11-13 12:49:11,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19686 to 19686. [2024-11-13 12:49:11,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19686 states, 19686 states have (on average 1.3806766229807985) internal successors, (27180), 19685 states have internal predecessors, (27180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:12,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19686 states to 19686 states and 27180 transitions. [2024-11-13 12:49:12,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19686 states and 27180 transitions. [2024-11-13 12:49:12,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:12,027 INFO L424 stractBuchiCegarLoop]: Abstraction has 19686 states and 27180 transitions. [2024-11-13 12:49:12,027 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 12:49:12,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19686 states and 27180 transitions. [2024-11-13 12:49:12,087 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19472 [2024-11-13 12:49:12,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:12,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:12,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:12,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:12,090 INFO L745 eck$LassoCheckResult]: Stem: 586825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 586826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 587428#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 587429#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 587507#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 586970#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 586971#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 587101#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 587102#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 586870#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 586661#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 586662#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 586830#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 586831#L781 assume !(0 == ~M_E~0); 587344#L781-2 assume !(0 == ~T1_E~0); 587521#L786-1 assume !(0 == ~T2_E~0); 586622#L791-1 assume !(0 == ~T3_E~0); 586623#L796-1 assume !(0 == ~T4_E~0); 587179#L801-1 assume !(0 == ~T5_E~0); 587180#L806-1 assume !(0 == ~T6_E~0); 587214#L811-1 assume !(0 == ~T7_E~0); 586836#L816-1 assume !(0 == ~E_M~0); 586837#L821-1 assume !(0 == ~E_1~0); 586653#L826-1 assume !(0 == ~E_2~0); 586654#L831-1 assume !(0 == ~E_3~0); 586965#L836-1 assume !(0 == ~E_4~0); 586966#L841-1 assume !(0 == ~E_5~0); 586789#L846-1 assume !(0 == ~E_6~0); 586790#L851-1 assume !(0 == ~E_7~0); 586812#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 586813#L388 assume !(1 == ~m_pc~0); 586806#L388-2 is_master_triggered_~__retres1~0#1 := 0; 586807#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 587320#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 586667#L967 assume !(0 != activate_threads_~tmp~1#1); 586668#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 586599#L407 assume !(1 == ~t1_pc~0); 586600#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 586603#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 586604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 586639#L975 assume !(0 != activate_threads_~tmp___0~0#1); 587426#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 586924#L426 assume !(1 == ~t2_pc~0); 586925#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 587451#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 586948#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 586949#L983 assume !(0 != activate_threads_~tmp___1~0#1); 587496#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 587015#L445 assume !(1 == ~t3_pc~0); 587016#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 587353#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 586597#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 586598#L991 assume !(0 != activate_threads_~tmp___2~0#1); 587277#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 587242#L464 assume !(1 == ~t4_pc~0); 586816#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 586687#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 586688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 586699#L999 assume !(0 != activate_threads_~tmp___3~0#1); 586994#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 586995#L483 assume !(1 == ~t5_pc~0); 587239#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 587407#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 587371#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 587372#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 586908#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 586909#L502 assume !(1 == ~t6_pc~0); 586767#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 586726#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 586727#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 586935#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 587141#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 587386#L521 assume !(1 == ~t7_pc~0); 587423#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 587453#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 587514#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 587515#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 587390#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 587309#L869 assume !(1 == ~M_E~0); 586988#L869-2 assume !(1 == ~T1_E~0); 586989#L874-1 assume !(1 == ~T2_E~0); 587469#L879-1 assume !(1 == ~T3_E~0); 587063#L884-1 assume !(1 == ~T4_E~0); 586585#L889-1 assume !(1 == ~T5_E~0); 586586#L894-1 assume !(1 == ~T6_E~0); 586844#L899-1 assume !(1 == ~T7_E~0); 587264#L904-1 assume !(1 == ~E_M~0); 587012#L909-1 assume !(1 == ~E_1~0); 587013#L914-1 assume !(1 == ~E_2~0); 587200#L919-1 assume !(1 == ~E_3~0); 586923#L924-1 assume !(1 == ~E_4~0); 586760#L929-1 assume !(1 == ~E_5~0); 586761#L934-1 assume !(1 == ~E_6~0); 586990#L939-1 assume !(1 == ~E_7~0); 586991#L944-1 assume { :end_inline_reset_delta_events } true; 587385#L1190-2 [2024-11-13 12:49:12,090 INFO L747 eck$LassoCheckResult]: Loop: 587385#L1190-2 assume !false; 606012#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 606009#L756-1 assume !false; 606007#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 605007#L596 assume !(0 == ~m_st~0); 605003#L600 assume !(0 == ~t1_st~0); 605004#L604 assume !(0 == ~t2_st~0); 605006#L608 assume !(0 == ~t3_st~0); 604999#L612 assume !(0 == ~t4_st~0); 605000#L616 assume !(0 == ~t5_st~0); 605005#L620 assume !(0 == ~t6_st~0); 605001#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 605002#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 605917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 605916#L653 assume !(0 != eval_~tmp~0#1); 605915#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 605914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 605913#L781-3 assume !(0 == ~M_E~0); 605912#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 605911#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 605909#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 605907#L796-3 assume !(0 == ~T4_E~0); 605906#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 605905#L806-3 assume !(0 == ~T6_E~0); 605903#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 605901#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 605900#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 605899#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 605897#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 605895#L836-3 assume !(0 == ~E_4~0); 605894#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 605893#L846-3 assume !(0 == ~E_6~0); 605892#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 605890#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 605888#L388-27 assume 1 == ~m_pc~0; 605885#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 605883#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 605881#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 605880#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 605879#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 605878#L407-27 assume !(1 == ~t1_pc~0); 605877#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 605876#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605875#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 605866#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 605864#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 605862#L426-27 assume 1 == ~t2_pc~0; 605859#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 605856#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 605855#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 605854#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 605853#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 605844#L445-27 assume !(1 == ~t3_pc~0); 605842#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 605840#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 605838#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 605836#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 605834#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 605830#L464-27 assume !(1 == ~t4_pc~0); 605826#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 605824#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 605822#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 605812#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 605811#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 605810#L483-27 assume !(1 == ~t5_pc~0); 605809#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 605808#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 605807#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 605805#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 605803#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 605801#L502-27 assume !(1 == ~t6_pc~0); 605799#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 605797#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 605795#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 605793#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 605791#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 605790#L521-27 assume !(1 == ~t7_pc~0); 605789#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 605787#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 605785#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 605782#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 605781#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 604990#L869-3 assume !(1 == ~M_E~0); 604986#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 604987#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 605910#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 605908#L884-3 assume !(1 == ~T4_E~0); 604976#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 604974#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 604971#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 604972#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 605898#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 605896#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 603817#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 603816#L924-3 assume !(1 == ~E_4~0); 603815#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 603814#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 603813#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 603812#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 603807#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 603799#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 603794#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 603545#L1209 assume !(0 == start_simulation_~tmp~3#1); 603546#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 606032#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 606025#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 606024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 606020#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 606018#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 606016#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 606015#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 587385#L1190-2 [2024-11-13 12:49:12,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:12,091 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2024-11-13 12:49:12,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:12,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161662190] [2024-11-13 12:49:12,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:12,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:12,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:12,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:12,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:12,155 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:12,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:12,155 INFO L85 PathProgramCache]: Analyzing trace with hash 46720400, now seen corresponding path program 1 times [2024-11-13 12:49:12,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:12,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097004684] [2024-11-13 12:49:12,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:12,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:12,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:12,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:12,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:12,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097004684] [2024-11-13 12:49:12,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097004684] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:12,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:12,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:12,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448399312] [2024-11-13 12:49:12,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:12,276 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:12,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:12,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:12,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:12,277 INFO L87 Difference]: Start difference. First operand 19686 states and 27180 transitions. cyclomatic complexity: 7510 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:12,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:12,622 INFO L93 Difference]: Finished difference Result 20070 states and 27451 transitions. [2024-11-13 12:49:12,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20070 states and 27451 transitions. [2024-11-13 12:49:12,704 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19856 [2024-11-13 12:49:12,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20070 states to 20070 states and 27451 transitions. [2024-11-13 12:49:12,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20070 [2024-11-13 12:49:12,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20070 [2024-11-13 12:49:12,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20070 states and 27451 transitions. [2024-11-13 12:49:12,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:12,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20070 states and 27451 transitions. [2024-11-13 12:49:12,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20070 states and 27451 transitions. [2024-11-13 12:49:12,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20070 to 20070. [2024-11-13 12:49:12,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20070 states, 20070 states have (on average 1.3677628300946687) internal successors, (27451), 20069 states have internal predecessors, (27451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:13,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20070 states to 20070 states and 27451 transitions. [2024-11-13 12:49:13,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20070 states and 27451 transitions. [2024-11-13 12:49:13,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:13,011 INFO L424 stractBuchiCegarLoop]: Abstraction has 20070 states and 27451 transitions. [2024-11-13 12:49:13,012 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 12:49:13,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20070 states and 27451 transitions. [2024-11-13 12:49:13,073 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19856 [2024-11-13 12:49:13,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:13,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:13,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:13,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:13,076 INFO L745 eck$LassoCheckResult]: Stem: 626590#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 626591#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 627210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 627211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 627298#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 626737#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 626738#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 626869#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 626870#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 626638#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 626426#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 626427#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 626595#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 626596#L781 assume !(0 == ~M_E~0); 627119#L781-2 assume !(0 == ~T1_E~0); 627317#L786-1 assume !(0 == ~T2_E~0); 626385#L791-1 assume !(0 == ~T3_E~0); 626386#L796-1 assume !(0 == ~T4_E~0); 626945#L801-1 assume !(0 == ~T5_E~0); 626946#L806-1 assume !(0 == ~T6_E~0); 626980#L811-1 assume !(0 == ~T7_E~0); 626601#L816-1 assume !(0 == ~E_M~0); 626602#L821-1 assume !(0 == ~E_1~0); 626417#L826-1 assume !(0 == ~E_2~0); 626418#L831-1 assume !(0 == ~E_3~0); 626732#L836-1 assume !(0 == ~E_4~0); 626733#L841-1 assume !(0 == ~E_5~0); 626554#L846-1 assume !(0 == ~E_6~0); 626555#L851-1 assume !(0 == ~E_7~0); 626577#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 626578#L388 assume !(1 == ~m_pc~0); 626571#L388-2 is_master_triggered_~__retres1~0#1 := 0; 626572#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 627093#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626432#L967 assume !(0 != activate_threads_~tmp~1#1); 626433#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 626363#L407 assume !(1 == ~t1_pc~0); 626364#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 626370#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 626371#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 626404#L975 assume !(0 != activate_threads_~tmp___0~0#1); 627206#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 626692#L426 assume !(1 == ~t2_pc~0); 626693#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 627234#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 626713#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 626714#L983 assume !(0 != activate_threads_~tmp___1~0#1); 627282#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 626781#L445 assume !(1 == ~t3_pc~0); 626782#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 627128#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 626361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 626362#L991 assume !(0 != activate_threads_~tmp___2~0#1); 627048#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 627010#L464 assume !(1 == ~t4_pc~0); 626581#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 626452#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 626453#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 626464#L999 assume !(0 != activate_threads_~tmp___3~0#1); 626760#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 626761#L483 assume !(1 == ~t5_pc~0); 627007#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 627187#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 627147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 627148#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 626676#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 626677#L502 assume !(1 == ~t6_pc~0); 626532#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 626491#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 626492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 626700#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 626908#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 627162#L521 assume !(1 == ~t7_pc~0); 627202#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 627236#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 627306#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 627307#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 627168#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 627084#L869 assume !(1 == ~M_E~0); 626754#L869-2 assume !(1 == ~T1_E~0); 626755#L874-1 assume !(1 == ~T2_E~0); 627249#L879-1 assume !(1 == ~T3_E~0); 626831#L884-1 assume !(1 == ~T4_E~0); 626349#L889-1 assume !(1 == ~T5_E~0); 626350#L894-1 assume !(1 == ~T6_E~0); 626614#L899-1 assume !(1 == ~T7_E~0); 627037#L904-1 assume !(1 == ~E_M~0); 626778#L909-1 assume !(1 == ~E_1~0); 626779#L914-1 assume !(1 == ~E_2~0); 626967#L919-1 assume !(1 == ~E_3~0); 626691#L924-1 assume !(1 == ~E_4~0); 626525#L929-1 assume !(1 == ~E_5~0); 626526#L934-1 assume !(1 == ~E_6~0); 626758#L939-1 assume !(1 == ~E_7~0); 626759#L944-1 assume { :end_inline_reset_delta_events } true; 627161#L1190-2 [2024-11-13 12:49:13,076 INFO L747 eck$LassoCheckResult]: Loop: 627161#L1190-2 assume !false; 644188#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 644181#L756-1 assume !false; 642203#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 640472#L596 assume !(0 == ~m_st~0); 640466#L600 assume !(0 == ~t1_st~0); 640467#L604 assume !(0 == ~t2_st~0); 640471#L608 assume !(0 == ~t3_st~0); 640464#L612 assume !(0 == ~t4_st~0); 640465#L616 assume !(0 == ~t5_st~0); 640470#L620 assume !(0 == ~t6_st~0); 640468#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 640469#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 643423#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 643422#L653 assume !(0 != eval_~tmp~0#1); 643421#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 643420#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 643419#L781-3 assume !(0 == ~M_E~0); 643418#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 643417#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 643415#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 643414#L796-3 assume !(0 == ~T4_E~0); 643413#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 643412#L806-3 assume !(0 == ~T6_E~0); 643410#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 643409#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 643408#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 643407#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 643406#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 643405#L836-3 assume !(0 == ~E_4~0); 643404#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 643403#L846-3 assume !(0 == ~E_6~0); 643402#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 643401#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643400#L388-27 assume 1 == ~m_pc~0; 643397#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 643395#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 643393#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 643391#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 643389#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643387#L407-27 assume !(1 == ~t1_pc~0); 643385#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 643383#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 643381#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 643378#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 643376#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 643374#L426-27 assume !(1 == ~t2_pc~0); 643301#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 643299#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 643297#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 643295#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 643293#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 643291#L445-27 assume !(1 == ~t3_pc~0); 643289#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 643286#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 643284#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 643282#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 643280#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 643276#L464-27 assume !(1 == ~t4_pc~0); 643274#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 643272#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 643270#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 643268#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 643266#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 643262#L483-27 assume !(1 == ~t5_pc~0); 643260#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 643258#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 643256#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 643253#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 643251#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 643250#L502-27 assume !(1 == ~t6_pc~0); 643246#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 643244#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 643242#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 643241#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 643238#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 643237#L521-27 assume 1 == ~t7_pc~0; 643235#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643233#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 643231#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 643230#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 643228#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643225#L869-3 assume !(1 == ~M_E~0); 643060#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 643220#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 643219#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 643218#L884-3 assume !(1 == ~T4_E~0); 643217#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 643216#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 643215#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 643213#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 643211#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 643209#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 643207#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 643205#L924-3 assume !(1 == ~E_4~0); 643203#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 643201#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 643199#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 643197#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 643191#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 643183#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 643181#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 643178#L1209 assume !(0 == start_simulation_~tmp~3#1); 643179#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 644297#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 644286#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 644281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 644280#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 644279#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 644274#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 644269#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 627161#L1190-2 [2024-11-13 12:49:13,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:13,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2024-11-13 12:49:13,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:13,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505506125] [2024-11-13 12:49:13,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:13,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:13,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:13,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:13,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:13,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:13,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:13,130 INFO L85 PathProgramCache]: Analyzing trace with hash 58099664, now seen corresponding path program 1 times [2024-11-13 12:49:13,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:13,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539958803] [2024-11-13 12:49:13,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:13,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:13,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:13,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:13,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:13,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539958803] [2024-11-13 12:49:13,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539958803] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:13,395 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:13,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:13,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795773686] [2024-11-13 12:49:13,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:13,396 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:13,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:13,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:13,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:13,396 INFO L87 Difference]: Start difference. First operand 20070 states and 27451 transitions. cyclomatic complexity: 7397 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:13,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:13,777 INFO L93 Difference]: Finished difference Result 20793 states and 28174 transitions. [2024-11-13 12:49:13,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20793 states and 28174 transitions. [2024-11-13 12:49:13,885 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20576 [2024-11-13 12:49:13,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20793 states to 20793 states and 28174 transitions. [2024-11-13 12:49:13,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20793 [2024-11-13 12:49:13,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20793 [2024-11-13 12:49:13,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20793 states and 28174 transitions. [2024-11-13 12:49:13,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:13,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20793 states and 28174 transitions. [2024-11-13 12:49:14,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20793 states and 28174 transitions. [2024-11-13 12:49:14,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20793 to 20793. [2024-11-13 12:49:14,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20793 states, 20793 states have (on average 1.3549752320492474) internal successors, (28174), 20792 states have internal predecessors, (28174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:14,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20793 states to 20793 states and 28174 transitions. [2024-11-13 12:49:14,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20793 states and 28174 transitions. [2024-11-13 12:49:14,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:14,314 INFO L424 stractBuchiCegarLoop]: Abstraction has 20793 states and 28174 transitions. [2024-11-13 12:49:14,314 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 12:49:14,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20793 states and 28174 transitions. [2024-11-13 12:49:14,393 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20576 [2024-11-13 12:49:14,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:14,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:14,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:14,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:14,396 INFO L745 eck$LassoCheckResult]: Stem: 667461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 667462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 668078#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 668079#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 668160#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 667605#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 667606#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 667736#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 667737#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 667506#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 667296#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 667297#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 667468#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 667469#L781 assume !(0 == ~M_E~0); 667995#L781-2 assume !(0 == ~T1_E~0); 668176#L786-1 assume !(0 == ~T2_E~0); 667260#L791-1 assume !(0 == ~T3_E~0); 667261#L796-1 assume !(0 == ~T4_E~0); 667815#L801-1 assume !(0 == ~T5_E~0); 667816#L806-1 assume !(0 == ~T6_E~0); 667848#L811-1 assume !(0 == ~T7_E~0); 667472#L816-1 assume !(0 == ~E_M~0); 667473#L821-1 assume !(0 == ~E_1~0); 667288#L826-1 assume !(0 == ~E_2~0); 667289#L831-1 assume !(0 == ~E_3~0); 667600#L836-1 assume !(0 == ~E_4~0); 667601#L841-1 assume !(0 == ~E_5~0); 667424#L846-1 assume !(0 == ~E_6~0); 667425#L851-1 assume !(0 == ~E_7~0); 667448#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 667449#L388 assume !(1 == ~m_pc~0); 667442#L388-2 is_master_triggered_~__retres1~0#1 := 0; 667443#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 667967#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 667302#L967 assume !(0 != activate_threads_~tmp~1#1); 667303#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 667234#L407 assume !(1 == ~t1_pc~0); 667235#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 667241#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 667242#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 667276#L975 assume !(0 != activate_threads_~tmp___0~0#1); 668076#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667559#L426 assume !(1 == ~t2_pc~0); 667560#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 668105#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 668188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 668145#L983 assume !(0 != activate_threads_~tmp___1~0#1); 668146#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 667648#L445 assume !(1 == ~t3_pc~0); 667649#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 668001#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 667232#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 667233#L991 assume !(0 != activate_threads_~tmp___2~0#1); 667918#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 667879#L464 assume !(1 == ~t4_pc~0); 667454#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 667322#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 667323#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667336#L999 assume !(0 != activate_threads_~tmp___3~0#1); 667626#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 667627#L483 assume !(1 == ~t5_pc~0); 667876#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 668057#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 668021#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 668022#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 667546#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 667547#L502 assume !(1 == ~t6_pc~0); 667402#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 667361#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 667362#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 667572#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 667774#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 668036#L521 assume !(1 == ~t7_pc~0); 668073#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 668108#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 668166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 668167#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 668041#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 667956#L869 assume !(1 == ~M_E~0); 667620#L869-2 assume !(1 == ~T1_E~0); 667621#L874-1 assume !(1 == ~T2_E~0); 668120#L879-1 assume !(1 == ~T3_E~0); 667698#L884-1 assume !(1 == ~T4_E~0); 667220#L889-1 assume !(1 == ~T5_E~0); 667221#L894-1 assume !(1 == ~T6_E~0); 667483#L899-1 assume !(1 == ~T7_E~0); 667908#L904-1 assume !(1 == ~E_M~0); 667644#L909-1 assume !(1 == ~E_1~0); 667645#L914-1 assume !(1 == ~E_2~0); 667835#L919-1 assume !(1 == ~E_3~0); 667558#L924-1 assume !(1 == ~E_4~0); 667395#L929-1 assume !(1 == ~E_5~0); 667396#L934-1 assume !(1 == ~E_6~0); 667624#L939-1 assume !(1 == ~E_7~0); 667625#L944-1 assume { :end_inline_reset_delta_events } true; 668035#L1190-2 [2024-11-13 12:49:14,397 INFO L747 eck$LassoCheckResult]: Loop: 668035#L1190-2 assume !false; 674359#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674355#L756-1 assume !false; 674354#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 674353#L596 assume !(0 == ~m_st~0); 674349#L600 assume !(0 == ~t1_st~0); 674350#L604 assume !(0 == ~t2_st~0); 674352#L608 assume !(0 == ~t3_st~0); 674345#L612 assume !(0 == ~t4_st~0); 674346#L616 assume !(0 == ~t5_st~0); 674351#L620 assume !(0 == ~t6_st~0); 674347#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 674348#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 677720#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 677718#L653 assume !(0 != eval_~tmp~0#1); 677716#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 677714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 677712#L781-3 assume !(0 == ~M_E~0); 677710#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 677708#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 677706#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 677704#L796-3 assume !(0 == ~T4_E~0); 677702#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 677700#L806-3 assume !(0 == ~T6_E~0); 677698#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 677696#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 677694#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 677692#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 677690#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 677688#L836-3 assume !(0 == ~E_4~0); 677686#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 677684#L846-3 assume !(0 == ~E_6~0); 677682#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 677680#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 677678#L388-27 assume 1 == ~m_pc~0; 677675#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 677672#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 677670#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 677668#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 677666#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 677664#L407-27 assume !(1 == ~t1_pc~0); 677662#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 677660#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 677658#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 677656#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 677654#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 677652#L426-27 assume !(1 == ~t2_pc~0); 677646#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 677644#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 677642#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 677640#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 677636#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 677634#L445-27 assume !(1 == ~t3_pc~0); 677632#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 677630#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 677628#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 677626#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 677624#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 677619#L464-27 assume !(1 == ~t4_pc~0); 677617#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 677615#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 677613#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 677611#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 677609#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 677607#L483-27 assume !(1 == ~t5_pc~0); 677605#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 677603#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 677601#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 677599#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 677597#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 677595#L502-27 assume !(1 == ~t6_pc~0); 677593#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 677591#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 677589#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 677587#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 677585#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 677583#L521-27 assume 1 == ~t7_pc~0; 677579#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 677577#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 677575#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 677572#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 677569#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 677568#L869-3 assume !(1 == ~M_E~0); 677565#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 677562#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 677558#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 677554#L884-3 assume !(1 == ~T4_E~0); 677552#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 677550#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 677549#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 677546#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 677543#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 677529#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 676352#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 676348#L924-3 assume !(1 == ~E_4~0); 676333#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 676332#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 676322#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 676316#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 675016#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674398#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 674388#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 674385#L1209 assume !(0 == start_simulation_~tmp~3#1); 674382#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 674379#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 674372#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 674371#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 674367#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 674365#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 674363#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 674362#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 668035#L1190-2 [2024-11-13 12:49:14,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:14,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2024-11-13 12:49:14,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:14,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20427218] [2024-11-13 12:49:14,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:14,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:14,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:14,420 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:14,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:14,454 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:14,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:14,455 INFO L85 PathProgramCache]: Analyzing trace with hash 2019674322, now seen corresponding path program 1 times [2024-11-13 12:49:14,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:14,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969359179] [2024-11-13 12:49:14,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:14,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:14,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:14,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:14,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:14,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969359179] [2024-11-13 12:49:14,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969359179] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:14,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:14,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:14,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092612237] [2024-11-13 12:49:14,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:14,589 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:14,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:14,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:14,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:14,590 INFO L87 Difference]: Start difference. First operand 20793 states and 28174 transitions. cyclomatic complexity: 7397 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:14,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:14,922 INFO L93 Difference]: Finished difference Result 20841 states and 27997 transitions. [2024-11-13 12:49:14,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20841 states and 27997 transitions. [2024-11-13 12:49:15,034 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20624 [2024-11-13 12:49:15,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20841 states to 20841 states and 27997 transitions. [2024-11-13 12:49:15,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20841 [2024-11-13 12:49:15,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20841 [2024-11-13 12:49:15,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20841 states and 27997 transitions. [2024-11-13 12:49:15,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:15,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20841 states and 27997 transitions. [2024-11-13 12:49:15,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20841 states and 27997 transitions. [2024-11-13 12:49:15,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20841 to 20841. [2024-11-13 12:49:15,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20841 states, 20841 states have (on average 1.3433616429154072) internal successors, (27997), 20840 states have internal predecessors, (27997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:15,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20841 states to 20841 states and 27997 transitions. [2024-11-13 12:49:15,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20841 states and 27997 transitions. [2024-11-13 12:49:15,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:15,599 INFO L424 stractBuchiCegarLoop]: Abstraction has 20841 states and 27997 transitions. [2024-11-13 12:49:15,599 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 12:49:15,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20841 states and 27997 transitions. [2024-11-13 12:49:15,641 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20624 [2024-11-13 12:49:15,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:15,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:15,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:15,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:15,642 INFO L745 eck$LassoCheckResult]: Stem: 709104#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 709105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 709739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 709740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 709834#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 709253#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 709254#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 709383#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 709384#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 709150#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 708938#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 708939#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 709111#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 709112#L781 assume !(0 == ~M_E~0); 709647#L781-2 assume !(0 == ~T1_E~0); 709847#L786-1 assume !(0 == ~T2_E~0); 708901#L791-1 assume !(0 == ~T3_E~0); 708902#L796-1 assume !(0 == ~T4_E~0); 709465#L801-1 assume !(0 == ~T5_E~0); 709466#L806-1 assume !(0 == ~T6_E~0); 709496#L811-1 assume !(0 == ~T7_E~0); 709115#L816-1 assume !(0 == ~E_M~0); 709116#L821-1 assume !(0 == ~E_1~0); 708929#L826-1 assume !(0 == ~E_2~0); 708930#L831-1 assume !(0 == ~E_3~0); 709248#L836-1 assume !(0 == ~E_4~0); 709249#L841-1 assume !(0 == ~E_5~0); 709067#L846-1 assume !(0 == ~E_6~0); 709068#L851-1 assume !(0 == ~E_7~0); 709090#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 709091#L388 assume !(1 == ~m_pc~0); 709084#L388-2 is_master_triggered_~__retres1~0#1 := 0; 709085#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 709615#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 708944#L967 assume !(0 != activate_threads_~tmp~1#1); 708945#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 708876#L407 assume !(1 == ~t1_pc~0); 708877#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 708883#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 708884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 708917#L975 assume !(0 != activate_threads_~tmp___0~0#1); 709736#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 709203#L426 assume !(1 == ~t2_pc~0); 709204#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 709771#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 709862#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 709819#L983 assume !(0 != activate_threads_~tmp___1~0#1); 709820#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 709295#L445 assume !(1 == ~t3_pc~0); 709296#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 709655#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 708874#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 708875#L991 assume !(0 != activate_threads_~tmp___2~0#1); 709568#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 709528#L464 assume !(1 == ~t4_pc~0); 709096#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 708964#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 708965#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 708978#L999 assume !(0 != activate_threads_~tmp___3~0#1); 709274#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 709275#L483 assume !(1 == ~t5_pc~0); 709525#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 709713#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 709675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 709676#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 709189#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 709190#L502 assume !(1 == ~t6_pc~0); 709045#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 709003#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 709004#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 709217#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 709423#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 709689#L521 assume !(1 == ~t7_pc~0); 709732#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 709773#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 709840#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 709841#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 709696#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 709606#L869 assume !(1 == ~M_E~0); 709268#L869-2 assume !(1 == ~T1_E~0); 709269#L874-1 assume !(1 == ~T2_E~0); 709784#L879-1 assume !(1 == ~T3_E~0); 709345#L884-1 assume !(1 == ~T4_E~0); 708862#L889-1 assume !(1 == ~T5_E~0); 708863#L894-1 assume !(1 == ~T6_E~0); 709127#L899-1 assume !(1 == ~T7_E~0); 709557#L904-1 assume !(1 == ~E_M~0); 709292#L909-1 assume !(1 == ~E_1~0); 709293#L914-1 assume !(1 == ~E_2~0); 709482#L919-1 assume !(1 == ~E_3~0); 709202#L924-1 assume !(1 == ~E_4~0); 709037#L929-1 assume !(1 == ~E_5~0); 709038#L934-1 assume !(1 == ~E_6~0); 709272#L939-1 assume !(1 == ~E_7~0); 709273#L944-1 assume { :end_inline_reset_delta_events } true; 709688#L1190-2 [2024-11-13 12:49:15,642 INFO L747 eck$LassoCheckResult]: Loop: 709688#L1190-2 assume !false; 727182#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 727178#L756-1 assume !false; 727176#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 727166#L596 assume !(0 == ~m_st~0); 727162#L600 assume !(0 == ~t1_st~0); 727163#L604 assume !(0 == ~t2_st~0); 727165#L608 assume !(0 == ~t3_st~0); 727158#L612 assume !(0 == ~t4_st~0); 727159#L616 assume !(0 == ~t5_st~0); 727164#L620 assume !(0 == ~t6_st~0); 727160#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 727161#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 729125#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 729122#L653 assume !(0 != eval_~tmp~0#1); 729120#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 729118#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 729115#L781-3 assume !(0 == ~M_E~0); 729113#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 729112#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 729111#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 729108#L796-3 assume !(0 == ~T4_E~0); 729106#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 729104#L806-3 assume !(0 == ~T6_E~0); 729103#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 729100#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 729099#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 729098#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 729097#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 729095#L836-3 assume !(0 == ~E_4~0); 729093#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 729091#L846-3 assume !(0 == ~E_6~0); 729089#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 729087#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729085#L388-27 assume !(1 == ~m_pc~0); 729083#L388-29 is_master_triggered_~__retres1~0#1 := 0; 729080#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 729078#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 729076#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 729074#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 729072#L407-27 assume !(1 == ~t1_pc~0); 729070#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 729068#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 729067#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 729066#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 729065#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 729064#L426-27 assume 1 == ~t2_pc~0; 729063#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 729061#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 729059#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 729056#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 729055#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 729054#L445-27 assume !(1 == ~t3_pc~0); 729053#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 729052#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 729051#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 729050#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 729048#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 729044#L464-27 assume !(1 == ~t4_pc~0); 729042#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 729040#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 729038#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 729036#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 729034#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 729032#L483-27 assume !(1 == ~t5_pc~0); 729030#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 729028#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 729026#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 729024#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 729022#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 729020#L502-27 assume !(1 == ~t6_pc~0); 729019#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 729018#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 729017#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 729016#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 729015#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 729014#L521-27 assume 1 == ~t7_pc~0; 729011#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 729009#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 729008#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 729007#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 729004#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 729002#L869-3 assume !(1 == ~M_E~0); 728006#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 728999#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 728997#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 728995#L884-3 assume !(1 == ~T4_E~0); 728993#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 728991#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 728989#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 728987#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 728985#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 728983#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 728981#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 728979#L924-3 assume !(1 == ~E_4~0); 728978#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 728977#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 728976#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 728975#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 728973#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 728965#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 728963#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 728961#L1209 assume !(0 == start_simulation_~tmp~3#1); 728958#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 728956#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 728949#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 728948#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 728939#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 727190#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 727187#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 727185#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 709688#L1190-2 [2024-11-13 12:49:15,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:15,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2024-11-13 12:49:15,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:15,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557679233] [2024-11-13 12:49:15,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:15,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:15,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:15,659 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:15,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:15,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:15,685 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:15,685 INFO L85 PathProgramCache]: Analyzing trace with hash 2117591634, now seen corresponding path program 1 times [2024-11-13 12:49:15,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:15,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559688296] [2024-11-13 12:49:15,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:15,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:15,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:15,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:15,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:15,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559688296] [2024-11-13 12:49:15,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559688296] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:15,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:15,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:15,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403763805] [2024-11-13 12:49:15,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:15,780 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:15,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:15,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:15,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:15,781 INFO L87 Difference]: Start difference. First operand 20841 states and 27997 transitions. cyclomatic complexity: 7172 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:16,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:16,110 INFO L93 Difference]: Finished difference Result 21564 states and 28720 transitions. [2024-11-13 12:49:16,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21564 states and 28720 transitions. [2024-11-13 12:49:16,191 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21344 [2024-11-13 12:49:16,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21564 states to 21564 states and 28720 transitions. [2024-11-13 12:49:16,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21564 [2024-11-13 12:49:16,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21564 [2024-11-13 12:49:16,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21564 states and 28720 transitions. [2024-11-13 12:49:16,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:16,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21564 states and 28720 transitions. [2024-11-13 12:49:16,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21564 states and 28720 transitions. [2024-11-13 12:49:16,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21564 to 21564. [2024-11-13 12:49:16,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21564 states, 21564 states have (on average 1.331849378593953) internal successors, (28720), 21563 states have internal predecessors, (28720), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:16,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21564 states to 21564 states and 28720 transitions. [2024-11-13 12:49:16,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21564 states and 28720 transitions. [2024-11-13 12:49:16,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:16,493 INFO L424 stractBuchiCegarLoop]: Abstraction has 21564 states and 28720 transitions. [2024-11-13 12:49:16,493 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 12:49:16,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21564 states and 28720 transitions. [2024-11-13 12:49:16,554 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21344 [2024-11-13 12:49:16,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:16,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:16,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:16,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:16,556 INFO L745 eck$LassoCheckResult]: Stem: 751515#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 751516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 752154#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 752155#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 752247#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 751664#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 751665#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 751795#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 751796#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 751561#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 751350#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 751351#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 751520#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 751521#L781 assume !(0 == ~M_E~0); 752051#L781-2 assume !(0 == ~T1_E~0); 752260#L786-1 assume !(0 == ~T2_E~0); 751311#L791-1 assume !(0 == ~T3_E~0); 751312#L796-1 assume !(0 == ~T4_E~0); 751875#L801-1 assume !(0 == ~T5_E~0); 751876#L806-1 assume !(0 == ~T6_E~0); 751910#L811-1 assume !(0 == ~T7_E~0); 751526#L816-1 assume !(0 == ~E_M~0); 751527#L821-1 assume !(0 == ~E_1~0); 751342#L826-1 assume !(0 == ~E_2~0); 751343#L831-1 assume !(0 == ~E_3~0); 751659#L836-1 assume !(0 == ~E_4~0); 751660#L841-1 assume !(0 == ~E_5~0); 751479#L846-1 assume !(0 == ~E_6~0); 751480#L851-1 assume !(0 == ~E_7~0); 751502#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 751503#L388 assume !(1 == ~m_pc~0); 751496#L388-2 is_master_triggered_~__retres1~0#1 := 0; 751497#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 752083#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 751356#L967 assume !(0 != activate_threads_~tmp~1#1); 751357#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 751289#L407 assume !(1 == ~t1_pc~0); 751290#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 751293#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 751294#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 751328#L975 assume !(0 != activate_threads_~tmp___0~0#1); 752150#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 751615#L426 assume !(1 == ~t2_pc~0); 751616#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752182#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 752231#L983 assume !(0 != activate_threads_~tmp___1~0#1); 752232#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 751707#L445 assume !(1 == ~t3_pc~0); 751708#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 752060#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 751287#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 751288#L991 assume !(0 != activate_threads_~tmp___2~0#1); 751978#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 751942#L464 assume !(1 == ~t4_pc~0); 751506#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 751376#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 751377#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 751388#L999 assume !(0 != activate_threads_~tmp___3~0#1); 751687#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 751688#L483 assume !(1 == ~t5_pc~0); 751939#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 752129#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 752087#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 752088#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 751598#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 751599#L502 assume !(1 == ~t6_pc~0); 751457#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 751415#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 751416#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 751626#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 751834#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 752102#L521 assume !(1 == ~t7_pc~0); 752147#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 752186#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 752250#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 752251#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 752109#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 752009#L869 assume !(1 == ~M_E~0); 751681#L869-2 assume !(1 == ~T1_E~0); 751682#L874-1 assume !(1 == ~T2_E~0); 752199#L879-1 assume !(1 == ~T3_E~0); 751758#L884-1 assume !(1 == ~T4_E~0); 751275#L889-1 assume !(1 == ~T5_E~0); 751276#L894-1 assume !(1 == ~T6_E~0); 751534#L899-1 assume !(1 == ~T7_E~0); 751965#L904-1 assume !(1 == ~E_M~0); 751704#L909-1 assume !(1 == ~E_1~0); 751705#L914-1 assume !(1 == ~E_2~0); 751895#L919-1 assume !(1 == ~E_3~0); 751614#L924-1 assume !(1 == ~E_4~0); 751449#L929-1 assume !(1 == ~E_5~0); 751450#L934-1 assume !(1 == ~E_6~0); 751683#L939-1 assume !(1 == ~E_7~0); 751684#L944-1 assume { :end_inline_reset_delta_events } true; 751518#L1190-2 [2024-11-13 12:49:16,557 INFO L747 eck$LassoCheckResult]: Loop: 751518#L1190-2 assume !false; 751528#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 751529#L756-1 assume !false; 751530#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 752253#L596 assume !(0 == ~m_st~0); 772514#L600 assume !(0 == ~t1_st~0); 772515#L604 assume !(0 == ~t2_st~0); 772519#L608 assume !(0 == ~t3_st~0); 772512#L612 assume !(0 == ~t4_st~0); 772513#L616 assume !(0 == ~t5_st~0); 772518#L620 assume !(0 == ~t6_st~0); 772516#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 772517#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 772827#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 772826#L653 assume !(0 != eval_~tmp~0#1); 772825#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 772824#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 772823#L781-3 assume !(0 == ~M_E~0); 751389#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 751390#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 772822#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 772821#L796-3 assume !(0 == ~T4_E~0); 772820#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 772819#L806-3 assume !(0 == ~T6_E~0); 751808#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 751809#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 752183#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 752184#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 751971#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 751972#L836-3 assume !(0 == ~E_4~0); 772770#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 772768#L846-3 assume !(0 == ~E_6~0); 751833#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 751383#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 751384#L388-27 assume 1 == ~m_pc~0; 752142#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 752143#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 772779#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 772777#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 751564#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 751565#L407-27 assume !(1 == ~t1_pc~0); 751999#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 752081#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 751886#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 751887#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 751854#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 751481#L426-27 assume 1 == ~t2_pc~0; 751483#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 752204#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 772816#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 772772#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 752137#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 751800#L445-27 assume !(1 == ~t3_pc~0); 751801#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 751333#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 751334#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 751802#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 751900#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 751590#L464-27 assume !(1 == ~t4_pc~0); 751331#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 751332#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 751402#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 751722#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 751476#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 751477#L483-27 assume !(1 == ~t5_pc~0); 752123#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 751385#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 751386#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 752092#L1007-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 752093#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 752214#L502-27 assume !(1 == ~t6_pc~0); 751827#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 751828#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752205#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 752005#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 752006#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 751277#L521-27 assume 1 == ~t7_pc~0; 751279#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 751631#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 751576#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 751329#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 751330#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 751842#L869-3 assume !(1 == ~M_E~0); 752002#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 751723#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 751724#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 751791#L884-3 assume !(1 == ~T4_E~0); 751782#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 751438#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 751439#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 751461#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 751462#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 751417#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 751418#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 751456#L924-3 assume !(1 == ~E_4~0); 751986#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 751897#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 751898#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 751466#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 751467#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 751296#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 751587#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 751588#L1209 assume !(0 == start_simulation_~tmp~3#1); 751823#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 751805#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 751432#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 751324#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 751325#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 751320#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 751321#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 751517#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 751518#L1190-2 [2024-11-13 12:49:16,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:16,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2024-11-13 12:49:16,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:16,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576232691] [2024-11-13 12:49:16,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:16,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:16,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:16,571 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:16,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:16,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:16,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:16,596 INFO L85 PathProgramCache]: Analyzing trace with hash -335061871, now seen corresponding path program 1 times [2024-11-13 12:49:16,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:16,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267253898] [2024-11-13 12:49:16,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:16,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:16,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:16,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:16,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:16,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267253898] [2024-11-13 12:49:16,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267253898] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:16,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:16,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:16,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471540170] [2024-11-13 12:49:16,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:16,687 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:16,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:16,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:16,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:16,688 INFO L87 Difference]: Start difference. First operand 21564 states and 28720 transitions. cyclomatic complexity: 7172 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:17,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:17,014 INFO L93 Difference]: Finished difference Result 21948 states and 28991 transitions. [2024-11-13 12:49:17,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21948 states and 28991 transitions. [2024-11-13 12:49:17,291 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21728 [2024-11-13 12:49:17,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21948 states to 21948 states and 28991 transitions. [2024-11-13 12:49:17,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21948 [2024-11-13 12:49:17,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21948 [2024-11-13 12:49:17,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21948 states and 28991 transitions. [2024-11-13 12:49:17,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:17,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21948 states and 28991 transitions. [2024-11-13 12:49:17,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21948 states and 28991 transitions. [2024-11-13 12:49:17,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21948 to 21948. [2024-11-13 12:49:17,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21948 states, 21948 states have (on average 1.3208948423546565) internal successors, (28991), 21947 states have internal predecessors, (28991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:17,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21948 states to 21948 states and 28991 transitions. [2024-11-13 12:49:17,588 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21948 states and 28991 transitions. [2024-11-13 12:49:17,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:17,589 INFO L424 stractBuchiCegarLoop]: Abstraction has 21948 states and 28991 transitions. [2024-11-13 12:49:17,589 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 12:49:17,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21948 states and 28991 transitions. [2024-11-13 12:49:17,652 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21728 [2024-11-13 12:49:17,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:17,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:17,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:17,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:17,655 INFO L745 eck$LassoCheckResult]: Stem: 795035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 795036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 795681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 795682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 795774#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 795180#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 795181#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 795310#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 795311#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 795081#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 794870#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 794871#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 795041#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 795042#L781 assume !(0 == ~M_E~0); 795578#L781-2 assume !(0 == ~T1_E~0); 795794#L786-1 assume !(0 == ~T2_E~0); 794834#L791-1 assume !(0 == ~T3_E~0); 794835#L796-1 assume !(0 == ~T4_E~0); 795395#L801-1 assume !(0 == ~T5_E~0); 795396#L806-1 assume !(0 == ~T6_E~0); 795430#L811-1 assume !(0 == ~T7_E~0); 795047#L816-1 assume !(0 == ~E_M~0); 795048#L821-1 assume !(0 == ~E_1~0); 794862#L826-1 assume !(0 == ~E_2~0); 794863#L831-1 assume !(0 == ~E_3~0); 795175#L836-1 assume !(0 == ~E_4~0); 795176#L841-1 assume !(0 == ~E_5~0); 794998#L846-1 assume !(0 == ~E_6~0); 794999#L851-1 assume !(0 == ~E_7~0); 795022#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 795023#L388 assume !(1 == ~m_pc~0); 795016#L388-2 is_master_triggered_~__retres1~0#1 := 0; 795017#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 795606#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 794876#L967 assume !(0 != activate_threads_~tmp~1#1); 794877#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 794809#L407 assume !(1 == ~t1_pc~0); 794810#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 794816#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 794817#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 794850#L975 assume !(0 != activate_threads_~tmp___0~0#1); 795677#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 795134#L426 assume !(1 == ~t2_pc~0); 795135#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 795705#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 795806#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 795757#L983 assume !(0 != activate_threads_~tmp___1~0#1); 795758#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 795223#L445 assume !(1 == ~t3_pc~0); 795224#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 795588#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 794807#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 794808#L991 assume !(0 != activate_threads_~tmp___2~0#1); 795499#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 795462#L464 assume !(1 == ~t4_pc~0); 795028#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 794896#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 794897#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 794910#L999 assume !(0 != activate_threads_~tmp___3~0#1); 795202#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 795203#L483 assume !(1 == ~t5_pc~0); 795459#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 795657#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 795611#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 795612#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 795121#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 795122#L502 assume !(1 == ~t6_pc~0); 794976#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 794935#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 794936#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 795145#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 795351#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 795628#L521 assume !(1 == ~t7_pc~0); 795672#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 795707#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 795782#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 795783#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 795636#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 795536#L869 assume !(1 == ~M_E~0); 795196#L869-2 assume !(1 == ~T1_E~0); 795197#L874-1 assume !(1 == ~T2_E~0); 795723#L879-1 assume !(1 == ~T3_E~0); 795273#L884-1 assume !(1 == ~T4_E~0); 794795#L889-1 assume !(1 == ~T5_E~0); 794796#L894-1 assume !(1 == ~T6_E~0); 795058#L899-1 assume !(1 == ~T7_E~0); 795488#L904-1 assume !(1 == ~E_M~0); 795220#L909-1 assume !(1 == ~E_1~0); 795221#L914-1 assume !(1 == ~E_2~0); 795416#L919-1 assume !(1 == ~E_3~0); 795133#L924-1 assume !(1 == ~E_4~0); 794968#L929-1 assume !(1 == ~E_5~0); 794969#L934-1 assume !(1 == ~E_6~0); 795200#L939-1 assume !(1 == ~E_7~0); 795201#L944-1 assume { :end_inline_reset_delta_events } true; 795627#L1190-2 [2024-11-13 12:49:17,655 INFO L747 eck$LassoCheckResult]: Loop: 795627#L1190-2 assume !false; 815139#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 815136#L756-1 assume !false; 815135#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 815134#L596 assume !(0 == ~m_st~0); 815129#L600 assume !(0 == ~t1_st~0); 815130#L604 assume !(0 == ~t2_st~0); 815132#L608 assume !(0 == ~t3_st~0); 815127#L612 assume !(0 == ~t4_st~0); 815128#L616 assume !(0 == ~t5_st~0); 815131#L620 assume !(0 == ~t6_st~0); 815133#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 815126#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 815124#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 804062#L653 assume !(0 != eval_~tmp~0#1); 804059#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 804053#L781-3 assume !(0 == ~M_E~0); 804050#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 804047#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 804044#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 804041#L796-3 assume !(0 == ~T4_E~0); 804038#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 804033#L806-3 assume !(0 == ~T6_E~0); 804030#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 803934#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 803928#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 803926#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 803924#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 803920#L836-3 assume !(0 == ~E_4~0); 803918#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 803916#L846-3 assume !(0 == ~E_6~0); 803914#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 803911#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 803909#L388-27 assume 1 == ~m_pc~0; 803906#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 803905#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 803893#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 803838#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 803835#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 803833#L407-27 assume !(1 == ~t1_pc~0); 803832#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 803831#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 803830#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 803829#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 803828#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 803827#L426-27 assume !(1 == ~t2_pc~0); 803825#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 803823#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 803821#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 803820#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 803818#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 803816#L445-27 assume !(1 == ~t3_pc~0); 803815#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 803814#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 803812#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 803810#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 803809#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 803807#L464-27 assume !(1 == ~t4_pc~0); 803805#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 803804#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 803803#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 803802#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 803800#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 803799#L483-27 assume !(1 == ~t5_pc~0); 803798#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 803797#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 803795#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 803794#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 803793#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 803791#L502-27 assume !(1 == ~t6_pc~0); 803790#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 803789#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 803788#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 803787#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 803786#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 803785#L521-27 assume !(1 == ~t7_pc~0); 803784#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 803782#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 803780#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 803777#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 803776#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 803775#L869-3 assume !(1 == ~M_E~0); 803619#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 803773#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 803771#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 803769#L884-3 assume !(1 == ~T4_E~0); 803767#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 803765#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 803763#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 803761#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 803759#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 803757#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 803755#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 803753#L924-3 assume !(1 == ~E_4~0); 803751#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 803749#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 803747#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 803745#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 803733#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 803725#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 803723#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 803720#L1209 assume !(0 == start_simulation_~tmp~3#1); 803721#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 815159#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 815152#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 815151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 815147#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 815145#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 815143#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 815142#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 795627#L1190-2 [2024-11-13 12:49:17,656 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:17,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2024-11-13 12:49:17,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:17,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678601834] [2024-11-13 12:49:17,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:17,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:17,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:17,674 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:17,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:17,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:17,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:17,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1435156007, now seen corresponding path program 1 times [2024-11-13 12:49:17,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:17,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702902725] [2024-11-13 12:49:17,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:17,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:17,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:17,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:17,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:17,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702902725] [2024-11-13 12:49:17,799 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702902725] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:17,799 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:17,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 12:49:17,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374187032] [2024-11-13 12:49:17,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:17,800 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:17,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:17,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 12:49:17,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 12:49:17,801 INFO L87 Difference]: Start difference. First operand 21948 states and 28991 transitions. cyclomatic complexity: 7059 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:18,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:18,135 INFO L93 Difference]: Finished difference Result 22332 states and 29262 transitions. [2024-11-13 12:49:18,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22332 states and 29262 transitions. [2024-11-13 12:49:18,221 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22112 [2024-11-13 12:49:18,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22332 states to 22332 states and 29262 transitions. [2024-11-13 12:49:18,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22332 [2024-11-13 12:49:18,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22332 [2024-11-13 12:49:18,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22332 states and 29262 transitions. [2024-11-13 12:49:18,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:18,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22332 states and 29262 transitions. [2024-11-13 12:49:18,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22332 states and 29262 transitions. [2024-11-13 12:49:18,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22332 to 22332. [2024-11-13 12:49:18,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22332 states, 22332 states have (on average 1.3103170338527674) internal successors, (29262), 22331 states have internal predecessors, (29262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:18,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22332 states to 22332 states and 29262 transitions. [2024-11-13 12:49:18,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22332 states and 29262 transitions. [2024-11-13 12:49:18,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 12:49:18,684 INFO L424 stractBuchiCegarLoop]: Abstraction has 22332 states and 29262 transitions. [2024-11-13 12:49:18,684 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 12:49:18,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22332 states and 29262 transitions. [2024-11-13 12:49:18,736 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22112 [2024-11-13 12:49:18,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:18,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:18,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:18,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:18,738 INFO L745 eck$LassoCheckResult]: Stem: 839329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 839330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 839977#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 839978#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 840077#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 839477#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 839478#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 839614#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 839615#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 839377#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 839159#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 839160#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 839336#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839337#L781 assume !(0 == ~M_E~0); 839867#L781-2 assume !(0 == ~T1_E~0); 840097#L786-1 assume !(0 == ~T2_E~0); 839122#L791-1 assume !(0 == ~T3_E~0); 839123#L796-1 assume !(0 == ~T4_E~0); 839693#L801-1 assume !(0 == ~T5_E~0); 839694#L806-1 assume !(0 == ~T6_E~0); 839728#L811-1 assume !(0 == ~T7_E~0); 839341#L816-1 assume !(0 == ~E_M~0); 839342#L821-1 assume !(0 == ~E_1~0); 839150#L826-1 assume !(0 == ~E_2~0); 839151#L831-1 assume !(0 == ~E_3~0); 839472#L836-1 assume !(0 == ~E_4~0); 839473#L841-1 assume !(0 == ~E_5~0); 839292#L846-1 assume !(0 == ~E_6~0); 839293#L851-1 assume !(0 == ~E_7~0); 839315#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839316#L388 assume !(1 == ~m_pc~0); 839309#L388-2 is_master_triggered_~__retres1~0#1 := 0; 839310#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839901#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839165#L967 assume !(0 != activate_threads_~tmp~1#1); 839166#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 839097#L407 assume !(1 == ~t1_pc~0); 839098#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 839104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839105#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 839138#L975 assume !(0 != activate_threads_~tmp___0~0#1); 839974#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 839430#L426 assume !(1 == ~t2_pc~0); 839431#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 840003#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 840112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 840057#L983 assume !(0 != activate_threads_~tmp___1~0#1); 840058#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 839524#L445 assume !(1 == ~t3_pc~0); 839525#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 839877#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 839095#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 839096#L991 assume !(0 != activate_threads_~tmp___2~0#1); 839798#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 839760#L464 assume !(1 == ~t4_pc~0); 839321#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 839185#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 839186#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 839201#L999 assume !(0 != activate_threads_~tmp___3~0#1); 839501#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839502#L483 assume !(1 == ~t5_pc~0); 839757#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 839950#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 839906#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 839907#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 839417#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 839418#L502 assume !(1 == ~t6_pc~0); 839269#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 839226#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 839227#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 839441#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 839654#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 839922#L521 assume !(1 == ~t7_pc~0); 839970#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 840005#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 840088#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 840089#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 839928#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 839830#L869 assume !(1 == ~M_E~0); 839494#L869-2 assume !(1 == ~T1_E~0); 839495#L874-1 assume !(1 == ~T2_E~0); 840019#L879-1 assume !(1 == ~T3_E~0); 839576#L884-1 assume !(1 == ~T4_E~0); 839083#L889-1 assume !(1 == ~T5_E~0); 839084#L894-1 assume !(1 == ~T6_E~0); 839352#L899-1 assume !(1 == ~T7_E~0); 839787#L904-1 assume !(1 == ~E_M~0); 839521#L909-1 assume !(1 == ~E_1~0); 839522#L914-1 assume !(1 == ~E_2~0); 839714#L919-1 assume !(1 == ~E_3~0); 839429#L924-1 assume !(1 == ~E_4~0); 839260#L929-1 assume !(1 == ~E_5~0); 839261#L934-1 assume !(1 == ~E_6~0); 839499#L939-1 assume !(1 == ~E_7~0); 839500#L944-1 assume { :end_inline_reset_delta_events } true; 839921#L1190-2 [2024-11-13 12:49:18,738 INFO L747 eck$LassoCheckResult]: Loop: 839921#L1190-2 assume !false; 851201#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 851196#L756-1 assume !false; 851194#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 851189#L596 assume !(0 == ~m_st~0); 851185#L600 assume !(0 == ~t1_st~0); 851186#L604 assume !(0 == ~t2_st~0); 851188#L608 assume !(0 == ~t3_st~0); 851181#L612 assume !(0 == ~t4_st~0); 851182#L616 assume !(0 == ~t5_st~0); 851187#L620 assume !(0 == ~t6_st~0); 851183#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 851184#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 851438#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 851436#L653 assume !(0 != eval_~tmp~0#1); 851434#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 851432#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 851430#L781-3 assume !(0 == ~M_E~0); 851428#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 851426#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 851424#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 851422#L796-3 assume !(0 == ~T4_E~0); 851420#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 851418#L806-3 assume !(0 == ~T6_E~0); 851416#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 851414#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 851412#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 851410#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 851408#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 851406#L836-3 assume !(0 == ~E_4~0); 851404#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 851401#L846-3 assume !(0 == ~E_6~0); 851399#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 851397#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 851396#L388-27 assume !(1 == ~m_pc~0); 851394#L388-29 is_master_triggered_~__retres1~0#1 := 0; 851392#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851390#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 851389#L967-27 assume !(0 != activate_threads_~tmp~1#1); 851385#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 851383#L407-27 assume !(1 == ~t1_pc~0); 851381#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 851379#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 851377#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 851375#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 851373#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 851371#L426-27 assume 1 == ~t2_pc~0; 851369#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 851370#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 851441#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 851358#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 851355#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 851353#L445-27 assume !(1 == ~t3_pc~0); 851351#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 851349#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 851347#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 851345#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 851343#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 851338#L464-27 assume !(1 == ~t4_pc~0); 851336#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 851334#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 851332#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 851330#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 851328#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 851326#L483-27 assume !(1 == ~t5_pc~0); 851324#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 851322#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 851320#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 851318#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 851316#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 851314#L502-27 assume !(1 == ~t6_pc~0); 851312#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 851310#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 851308#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 851306#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 851304#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 851302#L521-27 assume 1 == ~t7_pc~0; 851298#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 851296#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 851294#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 851291#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 851288#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 851287#L869-3 assume !(1 == ~M_E~0); 851281#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 851279#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 851277#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 851275#L884-3 assume !(1 == ~T4_E~0); 851272#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 851270#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 851267#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 851265#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 851263#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 851261#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 851259#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 851257#L924-3 assume !(1 == ~E_4~0); 851255#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 851253#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 851251#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 851249#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 851243#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 851235#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 851233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 851231#L1209 assume !(0 == start_simulation_~tmp~3#1); 851229#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 851227#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 851220#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 851219#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 851210#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 851208#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 851206#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 851204#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 839921#L1190-2 [2024-11-13 12:49:18,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:18,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2024-11-13 12:49:18,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:18,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028766537] [2024-11-13 12:49:18,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:18,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:18,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:18,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:18,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:18,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:18,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:18,788 INFO L85 PathProgramCache]: Analyzing trace with hash -31312680, now seen corresponding path program 1 times [2024-11-13 12:49:18,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:18,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240393867] [2024-11-13 12:49:18,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:18,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:18,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:18,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:18,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:18,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240393867] [2024-11-13 12:49:18,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240393867] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:18,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:18,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:18,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937525092] [2024-11-13 12:49:18,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:18,837 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:18,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:18,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:18,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:18,837 INFO L87 Difference]: Start difference. First operand 22332 states and 29262 transitions. cyclomatic complexity: 6946 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:19,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:19,009 INFO L93 Difference]: Finished difference Result 42220 states and 54430 transitions. [2024-11-13 12:49:19,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42220 states and 54430 transitions. [2024-11-13 12:49:19,181 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 41888 [2024-11-13 12:49:19,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42220 states to 42220 states and 54430 transitions. [2024-11-13 12:49:19,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42220 [2024-11-13 12:49:19,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42220 [2024-11-13 12:49:19,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42220 states and 54430 transitions. [2024-11-13 12:49:19,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 12:49:19,304 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42220 states and 54430 transitions. [2024-11-13 12:49:19,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42220 states and 54430 transitions. [2024-11-13 12:49:19,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42220 to 40268. [2024-11-13 12:49:19,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40268 states, 40268 states have (on average 1.2936823283997219) internal successors, (52094), 40267 states have internal predecessors, (52094), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:20,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40268 states to 40268 states and 52094 transitions. [2024-11-13 12:49:20,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40268 states and 52094 transitions. [2024-11-13 12:49:20,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:49:20,014 INFO L424 stractBuchiCegarLoop]: Abstraction has 40268 states and 52094 transitions. [2024-11-13 12:49:20,014 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 12:49:20,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40268 states and 52094 transitions. [2024-11-13 12:49:20,093 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39936 [2024-11-13 12:49:20,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:20,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:20,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:20,095 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:20,095 INFO L745 eck$LassoCheckResult]: Stem: 903887#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 903888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 904553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 904554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 904662#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 904036#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 904037#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 904172#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 904173#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 903934#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 903718#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 903719#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 903892#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 903893#L781 assume !(0 == ~M_E~0); 904441#L781-2 assume !(0 == ~T1_E~0); 904688#L786-1 assume !(0 == ~T2_E~0); 903678#L791-1 assume !(0 == ~T3_E~0); 903679#L796-1 assume !(0 == ~T4_E~0); 904254#L801-1 assume !(0 == ~T5_E~0); 904255#L806-1 assume !(0 == ~T6_E~0); 904296#L811-1 assume !(0 == ~T7_E~0); 903898#L816-1 assume !(0 == ~E_M~0); 903899#L821-1 assume !(0 == ~E_1~0); 903710#L826-1 assume !(0 == ~E_2~0); 903711#L831-1 assume !(0 == ~E_3~0); 904031#L836-1 assume !(0 == ~E_4~0); 904032#L841-1 assume !(0 == ~E_5~0); 903849#L846-1 assume !(0 == ~E_6~0); 903850#L851-1 assume !(0 == ~E_7~0); 903873#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 903874#L388 assume !(1 == ~m_pc~0); 903867#L388-2 is_master_triggered_~__retres1~0#1 := 0; 903868#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 904473#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 903724#L967 assume !(0 != activate_threads_~tmp~1#1); 903725#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 903655#L407 assume !(1 == ~t1_pc~0); 903656#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 903659#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 903660#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 903695#L975 assume !(0 != activate_threads_~tmp___0~0#1); 904549#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 903988#L426 assume !(1 == ~t2_pc~0); 903989#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 904583#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904701#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 904640#L983 assume !(0 != activate_threads_~tmp___1~0#1); 904641#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904084#L445 assume !(1 == ~t3_pc~0); 904085#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 904449#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903653#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 903654#L991 assume !(0 != activate_threads_~tmp___2~0#1); 904363#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 904327#L464 assume !(1 == ~t4_pc~0); 903877#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 903744#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 903745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 903756#L999 assume !(0 != activate_threads_~tmp___3~0#1); 904062#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 904063#L483 assume !(1 == ~t5_pc~0); 904324#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 904529#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 904478#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 904479#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 903972#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 903973#L502 assume !(1 == ~t6_pc~0); 903826#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 903783#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 903784#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 903998#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 904213#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 904494#L521 assume !(1 == ~t7_pc~0); 904546#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 904585#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 904674#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 904675#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 904503#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 904398#L869 assume !(1 == ~M_E~0); 904056#L869-2 assume !(1 == ~T1_E~0); 904057#L874-1 assume !(1 == ~T2_E~0); 904600#L879-1 assume !(1 == ~T3_E~0); 904135#L884-1 assume !(1 == ~T4_E~0); 903641#L889-1 assume !(1 == ~T5_E~0); 903642#L894-1 assume !(1 == ~T6_E~0); 903907#L899-1 assume !(1 == ~T7_E~0); 904352#L904-1 assume !(1 == ~E_M~0); 904081#L909-1 assume !(1 == ~E_1~0); 904082#L914-1 assume !(1 == ~E_2~0); 904280#L919-1 assume !(1 == ~E_3~0); 903987#L924-1 assume !(1 == ~E_4~0); 903817#L929-1 assume !(1 == ~E_5~0); 903818#L934-1 assume !(1 == ~E_6~0); 904058#L939-1 assume !(1 == ~E_7~0); 904059#L944-1 assume { :end_inline_reset_delta_events } true; 904493#L1190-2 [2024-11-13 12:49:20,096 INFO L747 eck$LassoCheckResult]: Loop: 904493#L1190-2 assume !false; 912516#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 912512#L756-1 assume !false; 912511#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 912509#L596 assume !(0 == ~m_st~0); 912510#L600 assume !(0 == ~t1_st~0); 912769#L604 assume !(0 == ~t2_st~0); 912766#L608 assume !(0 == ~t3_st~0); 912764#L612 assume !(0 == ~t4_st~0); 912762#L616 assume !(0 == ~t5_st~0); 912760#L620 assume !(0 == ~t6_st~0); 912757#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 912755#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 912753#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 912751#L653 assume !(0 != eval_~tmp~0#1); 912748#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 912746#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 912744#L781-3 assume !(0 == ~M_E~0); 912742#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 912740#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 912738#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 912736#L796-3 assume !(0 == ~T4_E~0); 912734#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 912732#L806-3 assume !(0 == ~T6_E~0); 912730#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 912728#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 912726#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 912724#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 912722#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 912720#L836-3 assume !(0 == ~E_4~0); 912718#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 912716#L846-3 assume !(0 == ~E_6~0); 912714#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 912710#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 912708#L388-27 assume 1 == ~m_pc~0; 912705#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 912703#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 912700#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 912697#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 912696#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 912692#L407-27 assume !(1 == ~t1_pc~0); 912690#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 912688#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 912687#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 912684#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 912683#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912682#L426-27 assume 1 == ~t2_pc~0; 912680#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 912681#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 913028#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 912667#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 912664#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 912661#L445-27 assume !(1 == ~t3_pc~0); 912659#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 912656#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 912654#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 912652#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 912649#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 912634#L464-27 assume !(1 == ~t4_pc~0); 912632#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 912630#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 912628#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 912626#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 912624#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 912622#L483-27 assume !(1 == ~t5_pc~0); 912620#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 912616#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 912614#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 912612#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 912610#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 912607#L502-27 assume !(1 == ~t6_pc~0); 912605#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 912603#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 912601#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 912599#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 912597#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 912595#L521-27 assume !(1 == ~t7_pc~0); 912593#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 913039#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 913037#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 912585#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 912583#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 912581#L869-3 assume !(1 == ~M_E~0); 912577#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 912575#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 912573#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 912571#L884-3 assume !(1 == ~T4_E~0); 912569#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 912567#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 912565#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 912563#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 912561#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 912559#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 912557#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 912555#L924-3 assume !(1 == ~E_4~0); 912553#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 912551#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 912549#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 912546#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 912543#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 912541#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 912538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 912535#L1209 assume !(0 == start_simulation_~tmp~3#1); 912533#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 912531#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 912527#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 912525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 912523#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 912522#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 912519#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 912518#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 904493#L1190-2 [2024-11-13 12:49:20,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:20,096 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 11 times [2024-11-13 12:49:20,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:20,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106033127] [2024-11-13 12:49:20,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:20,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:20,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:20,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:20,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:20,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:20,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:20,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1180125336, now seen corresponding path program 1 times [2024-11-13 12:49:20,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:20,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419354803] [2024-11-13 12:49:20,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:20,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:20,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:20,171 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:20,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:20,201 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:20,202 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:20,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1160570028, now seen corresponding path program 1 times [2024-11-13 12:49:20,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:20,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771711804] [2024-11-13 12:49:20,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:20,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:20,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:20,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:20,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:20,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771711804] [2024-11-13 12:49:20,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771711804] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:20,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:20,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:20,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755581145] [2024-11-13 12:49:20,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:23,067 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 12:49:23,068 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 12:49:23,068 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 12:49:23,068 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 12:49:23,069 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-13 12:49:23,069 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:23,069 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 12:49:23,069 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 12:49:23,069 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-2.c_Iteration30_Loop [2024-11-13 12:49:23,070 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 12:49:23,070 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 12:49:23,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,145 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,149 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,167 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,178 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,188 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,225 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,419 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,426 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,459 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,473 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,476 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:23,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:24,271 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 12:49:24,277 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-13 12:49:24,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,282 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,285 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-13 12:49:24,286 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,286 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,312 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,313 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,335 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:24,336 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,340 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,343 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-13 12:49:24,346 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,346 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,367 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,367 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,388 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-13 12:49:24,389 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,389 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,394 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-13 12:49:24,613 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,614 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,638 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,638 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,654 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-13 12:49:24,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,656 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-13 12:49:24,662 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,662 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,692 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,693 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,713 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-13 12:49:24,713 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,713 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,715 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,718 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-13 12:49:24,719 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,719 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,743 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,743 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,770 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-13 12:49:24,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,773 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,777 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-13 12:49:24,778 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,778 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,793 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,793 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,807 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-13 12:49:24,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,808 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,809 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-13 12:49:24,811 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,811 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,827 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,827 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,842 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-13 12:49:24,842 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,842 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,844 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-13 12:49:24,847 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,847 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,866 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,866 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,887 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-13 12:49:24,887 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,888 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,890 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,892 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-13 12:49:24,893 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,893 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,913 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,914 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,933 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:24,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,936 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-13 12:49:24,940 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,940 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:24,962 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:24,963 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:24,983 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-13 12:49:24,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:24,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:24,986 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:24,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-13 12:49:24,989 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:24,989 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,006 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:25,006 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:25,021 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:25,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:25,023 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:25,025 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-13 12:49:25,025 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:25,025 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,049 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:25,049 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=4} Honda state: {~t7_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:25,064 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-13 12:49:25,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:25,066 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:25,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-13 12:49:25,068 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:25,068 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,083 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:25,083 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret23#1=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret23#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:25,097 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-13 12:49:25,097 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,098 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:25,100 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:25,102 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-13 12:49:25,103 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:25,103 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,127 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-13 12:49:25,128 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-13 12:49:25,141 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-13 12:49:25,142 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:25,144 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:25,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-13 12:49:25,146 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-13 12:49:25,146 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,173 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-11-13 12:49:25,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:25,175 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:25,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-13 12:49:25,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-13 12:49:25,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-13 12:49:25,195 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-13 12:49:25,210 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-13 12:49:25,210 INFO L204 LassoAnalysis]: Preferences: [2024-11-13 12:49:25,211 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-13 12:49:25,211 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-13 12:49:25,211 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-13 12:49:25,211 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-13 12:49:25,211 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:25,211 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-13 12:49:25,211 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-13 12:49:25,211 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.07.cil-2.c_Iteration30_Loop [2024-11-13 12:49:25,211 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-13 12:49:25,211 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-13 12:49:25,217 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,230 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,287 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,330 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,333 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,378 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,391 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,397 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,419 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,425 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,467 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,476 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,481 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,484 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,486 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,531 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,534 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,540 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:25,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-13 12:49:26,299 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-13 12:49:26,304 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-13 12:49:26,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,305 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,308 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-13 12:49:26,313 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,334 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,334 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,335 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,335 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,335 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,343 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,343 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,349 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,369 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:26,370 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,372 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-13 12:49:26,377 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,393 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,393 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,394 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,394 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,394 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,395 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,395 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,399 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,420 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-13 12:49:26,420 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,423 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-13 12:49:26,426 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,443 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,443 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,444 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,444 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,444 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,445 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,445 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,447 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,468 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-13 12:49:26,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,471 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-13 12:49:26,475 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,492 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,493 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,493 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 12:49:26,493 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,494 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 12:49:26,494 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,497 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,518 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-13 12:49:26,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,521 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,523 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-13 12:49:26,524 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,541 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,542 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,542 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,542 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,542 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,543 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,543 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,545 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,566 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2024-11-13 12:49:26,566 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,567 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,569 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-13 12:49:26,572 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,589 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,590 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,590 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,590 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,590 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,591 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,591 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,593 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,614 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:26,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,614 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,616 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,617 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-13 12:49:26,618 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,632 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,632 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,632 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,632 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,632 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,633 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,633 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,635 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,653 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-13 12:49:26,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,656 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,658 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-13 12:49:26,659 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,675 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,675 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,675 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,675 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,675 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,676 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,676 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,679 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,700 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-13 12:49:26,700 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,703 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-13 12:49:26,706 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,723 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,723 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,723 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,724 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,724 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,725 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,725 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,727 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,748 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:26,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,751 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-13 12:49:26,754 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,771 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,771 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,771 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,771 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,771 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,772 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,772 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,777 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,798 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-13 12:49:26,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,801 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,803 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-13 12:49:26,804 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,821 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,821 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,821 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,821 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,821 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,822 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,822 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,827 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,848 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:26,848 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,851 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,853 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-13 12:49:26,854 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,871 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,872 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,872 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,872 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,872 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,873 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,877 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,898 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-13 12:49:26,898 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,898 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,900 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-13 12:49:26,905 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,922 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,922 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,922 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,922 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 12:49:26,922 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,923 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 12:49:26,923 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,927 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,947 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-13 12:49:26,947 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,948 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,950 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:26,952 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-13 12:49:26,953 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:26,970 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:26,970 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:26,970 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:26,970 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:26,971 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:26,971 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:26,971 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:26,974 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:26,995 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-11-13 12:49:26,995 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:26,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:26,998 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:27,000 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-13 12:49:27,001 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:27,018 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:27,019 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:27,019 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:27,019 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-13 12:49:27,019 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:27,020 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-13 12:49:27,020 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:27,022 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-13 12:49:27,043 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-13 12:49:27,043 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:27,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:27,045 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:27,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-13 12:49:27,047 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-13 12:49:27,060 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-13 12:49:27,061 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-13 12:49:27,061 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-13 12:49:27,061 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-13 12:49:27,061 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-13 12:49:27,062 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-13 12:49:27,062 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-13 12:49:27,065 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-13 12:49:27,069 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-13 12:49:27,072 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-13 12:49:27,074 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 12:49:27,074 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 12:49:27,077 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 12:49:27,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-13 12:49:27,080 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-13 12:49:27,080 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-13 12:49:27,080 INFO L474 LassoAnalysis]: Proved termination. [2024-11-13 12:49:27,081 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_5~0) = -1*~E_5~0 + 1 Supporting invariants [] [2024-11-13 12:49:27,103 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-13 12:49:27,105 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-13 12:49:27,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:27,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:27,216 INFO L255 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-13 12:49:27,219 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 12:49:27,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:27,470 INFO L255 TraceCheckSpWp]: Trace formula consists of 248 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-13 12:49:27,473 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 12:49:27,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:27,822 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-13 12:49:27,824 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 40268 states and 52094 transitions. cyclomatic complexity: 11842 Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:28,995 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe848dc5-0157-448a-8861-ee44b4ebee8a/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2024-11-13 12:49:29,089 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 40268 states and 52094 transitions. cyclomatic complexity: 11842. Second operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 111950 states and 145793 transitions. Complement of second has 5 states. [2024-11-13 12:49:29,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-13 12:49:29,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 41.2) internal successors, (206), 5 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:29,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1125 transitions. [2024-11-13 12:49:29,098 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1125 transitions. Stem has 95 letters. Loop has 111 letters. [2024-11-13 12:49:29,103 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 12:49:29,107 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1125 transitions. Stem has 206 letters. Loop has 111 letters. [2024-11-13 12:49:29,108 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 12:49:29,110 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1125 transitions. Stem has 95 letters. Loop has 222 letters. [2024-11-13 12:49:29,113 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-13 12:49:29,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111950 states and 145793 transitions. [2024-11-13 12:49:29,652 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75328 [2024-11-13 12:49:30,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111950 states to 111886 states and 145729 transitions. [2024-11-13 12:49:30,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75949 [2024-11-13 12:49:30,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76110 [2024-11-13 12:49:30,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111886 states and 145729 transitions. [2024-11-13 12:49:30,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 12:49:30,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111886 states and 145729 transitions. [2024-11-13 12:49:30,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111886 states and 145729 transitions. [2024-11-13 12:49:31,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111886 to 111661. [2024-11-13 12:49:31,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111661 states, 111661 states have (on average 1.301654113790849) internal successors, (145344), 111660 states have internal predecessors, (145344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:31,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111661 states to 111661 states and 145344 transitions. [2024-11-13 12:49:31,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 111661 states and 145344 transitions. [2024-11-13 12:49:31,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:31,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:31,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:31,997 INFO L87 Difference]: Start difference. First operand 111661 states and 145344 transitions. Second operand has 3 states, 3 states have (on average 68.66666666666667) internal successors, (206), 3 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:33,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:33,036 INFO L93 Difference]: Finished difference Result 117517 states and 151968 transitions. [2024-11-13 12:49:33,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117517 states and 151968 transitions. [2024-11-13 12:49:33,539 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79232 [2024-11-13 12:49:34,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117517 states to 117517 states and 151968 transitions. [2024-11-13 12:49:34,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79789 [2024-11-13 12:49:34,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79789 [2024-11-13 12:49:34,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117517 states and 151968 transitions. [2024-11-13 12:49:34,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 12:49:34,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117517 states and 151968 transitions. [2024-11-13 12:49:34,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117517 states and 151968 transitions. [2024-11-13 12:49:36,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117517 to 111661. [2024-11-13 12:49:36,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111661 states, 111661 states have (on average 1.2982151333052723) internal successors, (144960), 111660 states have internal predecessors, (144960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:36,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111661 states to 111661 states and 144960 transitions. [2024-11-13 12:49:36,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 111661 states and 144960 transitions. [2024-11-13 12:49:36,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:49:36,426 INFO L424 stractBuchiCegarLoop]: Abstraction has 111661 states and 144960 transitions. [2024-11-13 12:49:36,426 INFO L331 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-13 12:49:36,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 111661 states and 144960 transitions. [2024-11-13 12:49:36,725 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75328 [2024-11-13 12:49:36,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:36,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:36,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:36,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:36,729 INFO L745 eck$LassoCheckResult]: Stem: 1286130#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1286131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1287392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1287393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1287620#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1286412#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1286413#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1286655#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1286656#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1286217#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1285816#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1285817#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1286140#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1286141#L781 assume !(0 == ~M_E~0); 1287175#L781-2 assume !(0 == ~T1_E~0); 1287653#L786-1 assume !(0 == ~T2_E~0); 1285744#L791-1 assume !(0 == ~T3_E~0); 1285745#L796-1 assume !(0 == ~T4_E~0); 1286814#L801-1 assume !(0 == ~T5_E~0); 1286815#L806-1 assume !(0 == ~T6_E~0); 1286892#L811-1 assume !(0 == ~T7_E~0); 1286151#L816-1 assume !(0 == ~E_M~0); 1286152#L821-1 assume !(0 == ~E_1~0); 1285800#L826-1 assume !(0 == ~E_2~0); 1285801#L831-1 assume !(0 == ~E_3~0); 1286404#L836-1 assume !(0 == ~E_4~0); 1286405#L841-1 assume !(0 == ~E_5~0); 1286061#L846-1 assume !(0 == ~E_6~0); 1286062#L851-1 assume !(0 == ~E_7~0); 1286104#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1286105#L388 assume !(1 == ~m_pc~0); 1286094#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1286095#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1287680#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1285824#L967 assume !(0 != activate_threads_~tmp~1#1); 1285825#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1285703#L407 assume !(1 == ~t1_pc~0); 1285704#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1285709#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1285710#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1285774#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1287386#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1286324#L426 assume !(1 == ~t2_pc~0); 1286325#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1287448#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1287590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1287580#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1287581#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1286488#L445 assume !(1 == ~t3_pc~0); 1286489#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1287195#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1285701#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1285702#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1287022#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1286951#L464 assume !(1 == ~t4_pc~0); 1286110#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1285862#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1285863#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1285886#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1286452#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1286453#L483 assume !(1 == ~t5_pc~0); 1286944#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1287342#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1287251#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1287252#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1286295#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1286296#L502 assume !(1 == ~t6_pc~0); 1286014#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1285938#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1285939#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1286340#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1286735#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1287280#L521 assume !(1 == ~t7_pc~0); 1287378#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1287454#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1287636#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1287637#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1287299#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1287096#L869 assume !(1 == ~M_E~0); 1286442#L869-2 assume !(1 == ~T1_E~0); 1286443#L874-1 assume !(1 == ~T2_E~0); 1287496#L879-1 assume !(1 == ~T3_E~0); 1286581#L884-1 assume !(1 == ~T4_E~0); 1285684#L889-1 assume !(1 == ~T5_E~0); 1285685#L894-1 assume !(1 == ~T6_E~0); 1286165#L899-1 assume !(1 == ~T7_E~0); 1286999#L904-1 assume !(1 == ~E_M~0); 1286484#L909-1 assume !(1 == ~E_1~0); 1286485#L914-1 assume !(1 == ~E_2~0); 1286861#L919-1 assume !(1 == ~E_3~0); 1286323#L924-1 assume !(1 == ~E_4~0); 1285999#L929-1 assume !(1 == ~E_5~0); 1286000#L934-1 assume !(1 == ~E_6~0); 1286446#L939-1 assume !(1 == ~E_7~0); 1286447#L944-1 assume { :end_inline_reset_delta_events } true; 1287279#L1190-2 assume !false; 1296353#L1191 [2024-11-13 12:49:36,730 INFO L747 eck$LassoCheckResult]: Loop: 1296353#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1336204#L756-1 assume !false; 1336203#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1336202#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1336200#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1336197#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1336195#L653 assume 0 != eval_~tmp~0#1; 1336193#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1336187#L661 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1336188#L80 assume 0 == ~m_pc~0; 1354451#L116 assume !false; 1354449#L92 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1354446#L388-3 assume !(1 == ~m_pc~0); 1354444#L388-5 is_master_triggered_~__retres1~0#1 := 0; 1354442#L399-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1354439#is_master_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1354381#L967-3 assume !(0 != activate_threads_~tmp~1#1); 1354378#L967-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1354376#L407-3 assume !(1 == ~t1_pc~0); 1354374#L407-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1354372#L418-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1354370#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1354368#L975-3 assume !(0 != activate_threads_~tmp___0~0#1); 1354366#L975-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1354364#L426-3 assume !(1 == ~t2_pc~0); 1354360#L426-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1354358#L437-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1354356#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1354354#L983-3 assume !(0 != activate_threads_~tmp___1~0#1); 1354351#L983-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1354349#L445-3 assume !(1 == ~t3_pc~0); 1354345#L445-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1354343#L456-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1354341#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1354339#L991-3 assume !(0 != activate_threads_~tmp___2~0#1); 1354336#L991-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1354334#L464-3 assume !(1 == ~t4_pc~0); 1354332#L464-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1354331#L475-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1354330#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1354328#L999-3 assume !(0 != activate_threads_~tmp___3~0#1); 1354327#L999-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1354326#L483-3 assume !(1 == ~t5_pc~0); 1354325#L483-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1354323#L494-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1354322#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1354321#L1007-3 assume !(0 != activate_threads_~tmp___4~0#1); 1354319#L1007-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1354318#L502-3 assume !(1 == ~t6_pc~0); 1354317#L502-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1354313#L513-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1354311#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1354309#L1015-3 assume !(0 != activate_threads_~tmp___5~0#1); 1354307#L1015-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1354301#L521-3 assume 1 == ~t7_pc~0; 1354302#L522-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1354303#L532-1 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1354324#is_transmit7_triggered_returnLabel#2 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1354291#L1023-3 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1354210#L1023-5 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true; 1337718#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1337716#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 1337712#L661-2 havoc eval_~tmp_ndt_1~0#1; 1337710#L658-1 assume !(0 == ~t1_st~0); 1333335#L672-1 assume !(0 == ~t2_st~0); 1333332#L686-1 assume !(0 == ~t3_st~0); 1333333#L700-1 assume !(0 == ~t4_st~0); 1340475#L714-1 assume !(0 == ~t5_st~0); 1340476#L728-1 assume !(0 == ~t6_st~0); 1341324#L742-1 assume !(0 == ~t7_st~0); 1326461#L756-1 assume !false; 1326455#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1326454#L596 assume !(0 == ~m_st~0); 1326445#L600 assume !(0 == ~t1_st~0); 1326446#L604 assume !(0 == ~t2_st~0); 1326450#L608 assume !(0 == ~t3_st~0); 1326443#L612 assume !(0 == ~t4_st~0); 1326444#L616 assume !(0 == ~t5_st~0); 1326449#L620 assume !(0 == ~t6_st~0); 1326447#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1326448#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1350028#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1350026#L653 assume !(0 != eval_~tmp~0#1); 1350024#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1350022#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1350021#L781-3 assume !(0 == ~M_E~0); 1350018#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1350016#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1350014#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1350012#L796-3 assume !(0 == ~T4_E~0); 1350010#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1350008#L806-3 assume !(0 == ~T6_E~0); 1350006#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1350004#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1350002#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1350000#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1349998#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1349996#L836-3 assume !(0 == ~E_4~0); 1349994#L841-3 assume !(0 == ~E_5~0); 1349992#L846-3 assume !(0 == ~E_6~0); 1349990#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1349988#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1349986#L388-27 assume 1 == ~m_pc~0; 1349983#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1349981#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1349978#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1349976#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1349974#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1349971#L407-27 assume !(1 == ~t1_pc~0); 1349969#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1349968#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1349967#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1349965#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1349964#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1349963#L426-27 assume !(1 == ~t2_pc~0); 1349961#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1349959#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1349957#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1349956#L983-27 assume !(0 != activate_threads_~tmp___1~0#1); 1349953#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1349951#L445-27 assume !(1 == ~t3_pc~0); 1349949#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1349947#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1349945#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1349943#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1349941#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1349929#L464-27 assume !(1 == ~t4_pc~0); 1349927#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1349925#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1349923#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1349921#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1349919#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1349917#L483-27 assume !(1 == ~t5_pc~0); 1349915#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1349914#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1349911#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1349909#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1349907#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1349905#L502-27 assume !(1 == ~t6_pc~0); 1349903#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1349901#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1349899#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1349897#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 1349895#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1349893#L521-27 assume !(1 == ~t7_pc~0); 1349889#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1349887#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1349885#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1349316#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1349314#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1349311#L869-3 assume !(1 == ~M_E~0); 1349307#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1349304#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1349302#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1349300#L884-3 assume !(1 == ~T4_E~0); 1349298#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1349296#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1349294#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1349292#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1349290#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1349288#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1349286#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1349284#L924-3 assume !(1 == ~E_4~0); 1349282#L929-3 assume !(1 == ~E_5~0); 1349280#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1326560#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1349278#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1349277#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1349275#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1349273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1349271#L1209 assume !(0 == start_simulation_~tmp~3#1); 1349269#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1349268#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1349266#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1346948#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1346947#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1341335#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1341334#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1341333#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1336210#L1190-2 assume !false; 1296353#L1191 [2024-11-13 12:49:36,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:36,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1048388200, now seen corresponding path program 1 times [2024-11-13 12:49:36,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:36,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419734354] [2024-11-13 12:49:36,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:36,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:36,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:36,754 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:36,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:36,788 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:36,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:36,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1275109359, now seen corresponding path program 1 times [2024-11-13 12:49:36,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:36,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561388336] [2024-11-13 12:49:36,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:36,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:36,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:36,871 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:36,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:36,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561388336] [2024-11-13 12:49:36,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561388336] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:36,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:36,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:36,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379093127] [2024-11-13 12:49:36,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:36,873 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:36,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:36,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:36,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:36,874 INFO L87 Difference]: Start difference. First operand 111661 states and 144960 transitions. cyclomatic complexity: 33347 Second operand has 3 states, 3 states have (on average 60.0) internal successors, (180), 3 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:37,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:37,728 INFO L93 Difference]: Finished difference Result 194861 states and 253696 transitions. [2024-11-13 12:49:37,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194861 states and 253696 transitions. [2024-11-13 12:49:38,860 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 131776 [2024-11-13 12:49:39,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194861 states to 194861 states and 253696 transitions. [2024-11-13 12:49:39,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132781 [2024-11-13 12:49:39,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132781 [2024-11-13 12:49:39,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 194861 states and 253696 transitions. [2024-11-13 12:49:39,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 12:49:39,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 194861 states and 253696 transitions. [2024-11-13 12:49:39,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194861 states and 253696 transitions. [2024-11-13 12:49:41,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194861 to 191597. [2024-11-13 12:49:41,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191597 states, 191597 states have (on average 1.307076833144569) internal successors, (250432), 191596 states have internal predecessors, (250432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:42,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191597 states to 191597 states and 250432 transitions. [2024-11-13 12:49:42,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191597 states and 250432 transitions. [2024-11-13 12:49:42,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:49:42,073 INFO L424 stractBuchiCegarLoop]: Abstraction has 191597 states and 250432 transitions. [2024-11-13 12:49:42,073 INFO L331 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-13 12:49:42,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191597 states and 250432 transitions. [2024-11-13 12:49:42,485 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 129536 [2024-11-13 12:49:42,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:42,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:42,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:42,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:42,487 INFO L745 eck$LassoCheckResult]: Stem: 1592654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1592655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1593956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1593957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1594180#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1592938#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1592939#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1593183#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1593184#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1592743#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1592343#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1592344#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1592664#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1592665#L781 assume !(0 == ~M_E~0); 1593732#L781-2 assume !(0 == ~T1_E~0); 1594237#L786-1 assume !(0 == ~T2_E~0); 1592278#L791-1 assume !(0 == ~T3_E~0); 1592279#L796-1 assume !(0 == ~T4_E~0); 1593354#L801-1 assume !(0 == ~T5_E~0); 1593355#L806-1 assume !(0 == ~T6_E~0); 1593431#L811-1 assume !(0 == ~T7_E~0); 1592675#L816-1 assume !(0 == ~E_M~0); 1592676#L821-1 assume !(0 == ~E_1~0); 1592328#L826-1 assume !(0 == ~E_2~0); 1592329#L831-1 assume !(0 == ~E_3~0); 1592930#L836-1 assume !(0 == ~E_4~0); 1592931#L841-1 assume !(0 == ~E_5~0); 1592587#L846-1 assume !(0 == ~E_6~0); 1592588#L851-1 assume !(0 == ~E_7~0); 1592630#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1592631#L388 assume !(1 == ~m_pc~0); 1592620#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1592621#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1594265#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1592351#L967 assume !(0 != activate_threads_~tmp~1#1); 1592352#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1592231#L407 assume !(1 == ~t1_pc~0); 1592232#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1592243#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1592244#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1592306#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1593950#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1592846#L426 assume !(1 == ~t2_pc~0); 1592847#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1594023#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1594149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1594142#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1594143#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1593016#L445 assume !(1 == ~t3_pc~0); 1593017#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1593754#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1592229#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1592230#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1593570#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1593493#L464 assume !(1 == ~t4_pc~0); 1592636#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1592389#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1592390#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1592411#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1592977#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1592978#L483 assume !(1 == ~t5_pc~0); 1593486#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1593903#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1593823#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1593824#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1592821#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1592822#L502 assume !(1 == ~t6_pc~0); 1592543#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1592462#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1592463#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1592868#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1593270#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1593852#L521 assume !(1 == ~t7_pc~0); 1593940#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1594027#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1594208#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1594209#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1593866#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1593647#L869 assume !(1 == ~M_E~0); 1592967#L869-2 assume !(1 == ~T1_E~0); 1592968#L874-1 assume !(1 == ~T2_E~0); 1594062#L879-1 assume !(1 == ~T3_E~0); 1593108#L884-1 assume !(1 == ~T4_E~0); 1592212#L889-1 assume !(1 == ~T5_E~0); 1592213#L894-1 assume !(1 == ~T6_E~0); 1592696#L899-1 assume !(1 == ~T7_E~0); 1593546#L904-1 assume !(1 == ~E_M~0); 1593011#L909-1 assume !(1 == ~E_1~0); 1593012#L914-1 assume !(1 == ~E_2~0); 1593399#L919-1 assume !(1 == ~E_3~0); 1592845#L924-1 assume !(1 == ~E_4~0); 1592524#L929-1 assume !(1 == ~E_5~0); 1592525#L934-1 assume !(1 == ~E_6~0); 1592975#L939-1 assume !(1 == ~E_7~0); 1592976#L944-1 assume { :end_inline_reset_delta_events } true; 1593851#L1190-2 assume !false; 1624965#L1191 [2024-11-13 12:49:42,488 INFO L747 eck$LassoCheckResult]: Loop: 1624965#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1741962#L756-1 assume !false; 1741960#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1741958#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1741955#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1741953#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1741951#L653 assume 0 != eval_~tmp~0#1; 1741950#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1741947#L661 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 1741830#L80 assume 0 == ~m_pc~0; 1741827#L116 assume !false; 1741824#L92 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1741821#L388-3 assume 1 == ~m_pc~0; 1741819#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1741820#L399-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1742033#is_master_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1741810#L967-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1741807#L967-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1741805#L407-3 assume !(1 == ~t1_pc~0); 1741803#L407-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1741802#L418-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1741801#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1741799#L975-3 assume !(0 != activate_threads_~tmp___0~0#1); 1741798#L975-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1741797#L426-3 assume !(1 == ~t2_pc~0); 1741795#L426-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1741793#L437-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1741791#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1741790#L983-3 assume !(0 != activate_threads_~tmp___1~0#1); 1741788#L983-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741784#L445-3 assume !(1 == ~t3_pc~0); 1741782#L445-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1741780#L456-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1741778#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1741773#L991-3 assume !(0 != activate_threads_~tmp___2~0#1); 1741771#L991-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1741769#L464-3 assume !(1 == ~t4_pc~0); 1741766#L464-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1741764#L475-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1741762#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1741760#L999-3 assume !(0 != activate_threads_~tmp___3~0#1); 1741758#L999-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1741754#L483-3 assume !(1 == ~t5_pc~0); 1741752#L483-5 is_transmit5_triggered_~__retres1~5#1 := 0; 1741750#L494-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1741748#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1741745#L1007-3 assume !(0 != activate_threads_~tmp___4~0#1); 1741743#L1007-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1741741#L502-3 assume !(1 == ~t6_pc~0); 1741739#L502-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1741737#L513-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1741735#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1741733#L1015-3 assume !(0 != activate_threads_~tmp___5~0#1); 1741731#L1015-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1741726#L521-3 assume 1 == ~t7_pc~0; 1741727#L522-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1695958#L532-1 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1745486#is_transmit7_triggered_returnLabel#2 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1741717#L1023-3 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1741713#L1023-5 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true; 1741711#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 1741689#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 1741613#L661-2 havoc eval_~tmp_ndt_1~0#1; 1741593#L658-1 assume !(0 == ~t1_st~0); 1741582#L672-1 assume !(0 == ~t2_st~0); 1741573#L686-1 assume !(0 == ~t3_st~0); 1741561#L700-1 assume !(0 == ~t4_st~0); 1741552#L714-1 assume !(0 == ~t5_st~0); 1741553#L728-1 assume !(0 == ~t6_st~0); 1742017#L742-1 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0#1;havoc eval_#t~nondet14#1;eval_~tmp_ndt_8~0#1 := eval_#t~nondet14#1;havoc eval_#t~nondet14#1; 1692213#L759 assume 0 != eval_~tmp_ndt_8~0#1;~t7_st~0 := 1;assume { :begin_inline_transmit7 } true; 1742015#L352 assume 0 == ~t7_pc~0; 1771138#L363-1 assume !false; 1692219#L364 ~t7_pc~0 := 1;~t7_st~0 := 2; 1692217#transmit7_returnLabel#1 assume { :end_inline_transmit7 } true; 1692214#L759-2 havoc eval_~tmp_ndt_8~0#1; 1692211#L756-1 assume !false; 1692210#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1692208#L596 assume !(0 == ~m_st~0); 1692206#L600 assume !(0 == ~t1_st~0); 1692204#L604 assume !(0 == ~t2_st~0); 1692202#L608 assume !(0 == ~t3_st~0); 1692200#L612 assume !(0 == ~t4_st~0); 1692198#L616 assume !(0 == ~t5_st~0); 1692195#L620 assume !(0 == ~t6_st~0); 1692192#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1692190#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1692188#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1692185#L653 assume !(0 != eval_~tmp~0#1); 1692183#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1692181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1692179#L781-3 assume !(0 == ~M_E~0); 1692177#L781-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1692175#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1692174#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1692172#L796-3 assume !(0 == ~T4_E~0); 1692170#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1692167#L806-3 assume !(0 == ~T6_E~0); 1692165#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1692163#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1692161#L821-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1692159#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1692157#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1692155#L836-3 assume !(0 == ~E_4~0); 1692153#L841-3 assume !(0 == ~E_5~0); 1692151#L846-3 assume !(0 == ~E_6~0); 1654375#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1692148#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1692144#L388-27 assume 1 == ~m_pc~0; 1692141#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1692139#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1692137#is_master_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1692133#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1692131#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1692129#L407-27 assume !(1 == ~t1_pc~0); 1692127#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1692125#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1692123#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1692121#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1692119#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1692118#L426-27 assume 1 == ~t2_pc~0; 1692117#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1692115#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1692113#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1692110#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1692107#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1692105#L445-27 assume !(1 == ~t3_pc~0); 1692103#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1692101#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1692099#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1692097#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1692095#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1692091#L464-27 assume !(1 == ~t4_pc~0); 1692089#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1692087#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1692085#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1692083#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1692081#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1692079#L483-27 assume !(1 == ~t5_pc~0); 1692077#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1692075#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1692073#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1692069#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1692067#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1692065#L502-27 assume !(1 == ~t6_pc~0); 1692063#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1692061#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1692059#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1692058#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 1692057#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1692056#L521-27 assume 1 == ~t7_pc~0; 1692054#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1692055#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1713776#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1713772#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1713770#L1023-29 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1713768#L869-3 assume !(1 == ~M_E~0); 1713579#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1713765#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1713764#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1713762#L884-3 assume !(1 == ~T4_E~0); 1713760#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1713758#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1713756#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1713754#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1713752#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1713748#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1713746#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1713744#L924-3 assume !(1 == ~E_4~0); 1713742#L929-3 assume !(1 == ~E_5~0); 1713737#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1713735#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1713733#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1713731#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1713729#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1713727#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1713723#L1209 assume !(0 == start_simulation_~tmp~3#1); 1713724#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1741984#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1741982#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1741981#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1741979#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1741971#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1741970#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1741968#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1741966#L1190-2 assume !false; 1624965#L1191 [2024-11-13 12:49:42,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:42,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1048388200, now seen corresponding path program 2 times [2024-11-13 12:49:42,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:42,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718730213] [2024-11-13 12:49:42,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:42,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:43,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:43,218 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:43,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:43,245 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:43,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:43,246 INFO L85 PathProgramCache]: Analyzing trace with hash 241460162, now seen corresponding path program 1 times [2024-11-13 12:49:43,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:43,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253824198] [2024-11-13 12:49:43,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:43,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:43,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:43,327 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:43,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:43,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253824198] [2024-11-13 12:49:43,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253824198] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:43,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:43,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:43,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84065076] [2024-11-13 12:49:43,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:43,328 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 12:49:43,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:43,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:43,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:43,328 INFO L87 Difference]: Start difference. First operand 191597 states and 250432 transitions. cyclomatic complexity: 58883 Second operand has 3 states, 3 states have (on average 62.0) internal successors, (186), 3 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:44,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 12:49:44,453 INFO L93 Difference]: Finished difference Result 234587 states and 302939 transitions. [2024-11-13 12:49:44,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234587 states and 302939 transitions. [2024-11-13 12:49:46,234 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 158544 [2024-11-13 12:49:46,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234587 states to 234587 states and 302939 transitions. [2024-11-13 12:49:46,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159898 [2024-11-13 12:49:46,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159898 [2024-11-13 12:49:46,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234587 states and 302939 transitions. [2024-11-13 12:49:46,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-13 12:49:46,743 INFO L218 hiAutomatonCegarLoop]: Abstraction has 234587 states and 302939 transitions. [2024-11-13 12:49:46,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234587 states and 302939 transitions. [2024-11-13 12:49:48,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234587 to 222395. [2024-11-13 12:49:49,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 222395 states, 222395 states have (on average 1.2969850940893455) internal successors, (288443), 222394 states have internal predecessors, (288443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 12:49:50,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222395 states to 222395 states and 288443 transitions. [2024-11-13 12:49:50,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 222395 states and 288443 transitions. [2024-11-13 12:49:50,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 12:49:50,091 INFO L424 stractBuchiCegarLoop]: Abstraction has 222395 states and 288443 transitions. [2024-11-13 12:49:50,091 INFO L331 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-13 12:49:50,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 222395 states and 288443 transitions. [2024-11-13 12:49:50,596 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 150416 [2024-11-13 12:49:50,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 12:49:50,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 12:49:50,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:50,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 12:49:50,597 INFO L745 eck$LassoCheckResult]: Stem: 2018852#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2018853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2020144#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2020145#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2020371#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2019140#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2019141#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2019381#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2019382#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2018940#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2018535#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2018536#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2018862#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2018863#L781 assume !(0 == ~M_E~0); 2019933#L781-2 assume !(0 == ~T1_E~0); 2020414#L786-1 assume !(0 == ~T2_E~0); 2018463#L791-1 assume !(0 == ~T3_E~0); 2018464#L796-1 assume !(0 == ~T4_E~0); 2019547#L801-1 assume !(0 == ~T5_E~0); 2019548#L806-1 assume !(0 == ~T6_E~0); 2019630#L811-1 assume !(0 == ~T7_E~0); 2018872#L816-1 assume !(0 == ~E_M~0); 2018873#L821-1 assume !(0 == ~E_1~0); 2018520#L826-1 assume !(0 == ~E_2~0); 2018521#L831-1 assume !(0 == ~E_3~0); 2019132#L836-1 assume !(0 == ~E_4~0); 2019133#L841-1 assume !(0 == ~E_5~0); 2018780#L846-1 assume !(0 == ~E_6~0); 2018781#L851-1 assume !(0 == ~E_7~0); 2018825#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2018826#L388 assume !(1 == ~m_pc~0); 2018815#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2018816#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2019870#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2018543#L967 assume !(0 != activate_threads_~tmp~1#1); 2018544#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2018421#L407 assume !(1 == ~t1_pc~0); 2018422#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2018427#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2018428#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2018493#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2020138#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2019047#L426 assume !(1 == ~t2_pc~0); 2019048#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2020206#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2020330#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2020320#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2020321#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2019220#L445 assume !(1 == ~t3_pc~0); 2019221#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2019950#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2018419#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2018420#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2019769#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2019696#L464 assume !(1 == ~t4_pc~0); 2018831#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2018581#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2018582#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2018605#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2019181#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2019182#L483 assume !(1 == ~t5_pc~0); 2019683#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2020094#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2019998#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2019999#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2019016#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2019017#L502 assume !(1 == ~t6_pc~0); 2018736#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2018657#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2018658#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2019065#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2019463#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2020028#L521 assume !(1 == ~t7_pc~0); 2020131#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2020211#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2020395#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2020396#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2020045#L1023-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2019848#L869 assume !(1 == ~M_E~0); 2019172#L869-2 assume !(1 == ~T1_E~0); 2019173#L874-1 assume !(1 == ~T2_E~0); 2020240#L879-1 assume !(1 == ~T3_E~0); 2019312#L884-1 assume !(1 == ~T4_E~0); 2018402#L889-1 assume !(1 == ~T5_E~0); 2018403#L894-1 assume !(1 == ~T6_E~0); 2018887#L899-1 assume !(1 == ~T7_E~0); 2019746#L904-1 assume !(1 == ~E_M~0); 2019215#L909-1 assume !(1 == ~E_1~0); 2019216#L914-1 assume !(1 == ~E_2~0); 2019593#L919-1 assume !(1 == ~E_3~0); 2019046#L924-1 assume !(1 == ~E_4~0); 2018722#L929-1 assume !(1 == ~E_5~0); 2018723#L934-1 assume !(1 == ~E_6~0); 2019175#L939-1 assume !(1 == ~E_7~0); 2019176#L944-1 assume { :end_inline_reset_delta_events } true; 2020027#L1190-2 assume !false; 2039146#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2126984#L756-1 [2024-11-13 12:49:50,597 INFO L747 eck$LassoCheckResult]: Loop: 2126984#L756-1 assume !false; 2126982#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2126980#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2126978#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2126976#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2126974#L653 assume 0 != eval_~tmp~0#1; 2126972#L653-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2126969#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 2126967#L661-2 havoc eval_~tmp_ndt_1~0#1; 2126964#L658-1 assume !(0 == ~t1_st~0); 2126873#L672-1 assume !(0 == ~t2_st~0); 2126870#L686-1 assume !(0 == ~t3_st~0); 2126866#L700-1 assume !(0 == ~t4_st~0); 2126862#L714-1 assume !(0 == ~t5_st~0); 2126858#L728-1 assume !(0 == ~t6_st~0); 2126855#L742-1 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0#1;havoc eval_#t~nondet14#1;eval_~tmp_ndt_8~0#1 := eval_#t~nondet14#1;havoc eval_#t~nondet14#1; 2126838#L759 assume !(0 != eval_~tmp_ndt_8~0#1); 2126853#L759-2 havoc eval_~tmp_ndt_8~0#1; 2126984#L756-1 [2024-11-13 12:49:50,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:50,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1859704615, now seen corresponding path program 1 times [2024-11-13 12:49:50,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:50,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800321149] [2024-11-13 12:49:50,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:50,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:50,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:50,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:50,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:50,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:50,648 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:50,648 INFO L85 PathProgramCache]: Analyzing trace with hash 447547879, now seen corresponding path program 1 times [2024-11-13 12:49:50,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:50,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042447702] [2024-11-13 12:49:50,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:50,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:50,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:50,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 12:49:50,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 12:49:50,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 12:49:50,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 12:49:50,664 INFO L85 PathProgramCache]: Analyzing trace with hash 585671565, now seen corresponding path program 1 times [2024-11-13 12:49:50,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 12:49:50,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813331037] [2024-11-13 12:49:50,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 12:49:50,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 12:49:50,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 12:49:50,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 12:49:50,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 12:49:50,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813331037] [2024-11-13 12:49:50,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813331037] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 12:49:50,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 12:49:50,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 12:49:50,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [688194320] [2024-11-13 12:49:50,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 12:49:50,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 12:49:50,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 12:49:50,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 12:49:50,862 INFO L87 Difference]: Start difference. First operand 222395 states and 288443 transitions. cyclomatic complexity: 66144 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)