./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 16:13:40,954 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 16:13:41,056 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 16:13:41,071 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 16:13:41,071 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 16:13:41,131 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 16:13:41,132 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 16:13:41,132 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 16:13:41,133 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 16:13:41,133 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 16:13:41,133 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 16:13:41,133 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 16:13:41,133 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 16:13:41,134 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 16:13:41,134 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 16:13:41,134 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 16:13:41,135 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 16:13:41,135 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 16:13:41,136 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 16:13:41,137 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 16:13:41,137 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 16:13:41,137 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 16:13:41,138 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 16:13:41,139 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 16:13:41,139 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 16:13:41,139 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 16:13:41,140 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 16:13:41,140 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 16:13:41,140 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 16:13:41,140 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 16:13:41,141 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 16:13:41,141 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2024-11-13 16:13:41,569 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 16:13:41,581 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 16:13:41,584 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 16:13:41,586 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 16:13:41,587 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 16:13:41,589 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c Unable to find full path for "g++" [2024-11-13 16:13:44,028 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 16:13:44,381 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 16:13:44,385 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2024-11-13 16:13:44,418 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/data/bd4a4399e/6d12cd988d894679b2c27ce0e6d5f432/FLAGa12e9a4b4 [2024-11-13 16:13:44,441 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/data/bd4a4399e/6d12cd988d894679b2c27ce0e6d5f432 [2024-11-13 16:13:44,446 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 16:13:44,449 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 16:13:44,452 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 16:13:44,452 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 16:13:44,458 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 16:13:44,460 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 04:13:44" (1/1) ... [2024-11-13 16:13:44,461 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@769de16b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:44, skipping insertion in model container [2024-11-13 16:13:44,464 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 04:13:44" (1/1) ... [2024-11-13 16:13:44,532 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 16:13:44,995 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 16:13:45,019 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 16:13:45,137 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 16:13:45,163 INFO L204 MainTranslator]: Completed translation [2024-11-13 16:13:45,164 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45 WrapperNode [2024-11-13 16:13:45,164 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 16:13:45,165 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 16:13:45,166 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 16:13:45,166 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 16:13:45,175 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,195 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,342 INFO L138 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2366 [2024-11-13 16:13:45,342 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 16:13:45,343 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 16:13:45,343 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 16:13:45,345 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 16:13:45,358 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,358 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,377 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,438 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 16:13:45,438 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,438 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,498 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,562 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,570 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,587 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,606 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 16:13:45,611 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 16:13:45,611 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 16:13:45,611 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 16:13:45,613 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (1/1) ... [2024-11-13 16:13:45,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 16:13:45,646 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 16:13:45,666 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 16:13:45,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7f418333-f438-4ae4-be3e-8a54095e960d/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 16:13:45,709 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 16:13:45,710 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 16:13:45,710 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 16:13:45,710 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 16:13:45,908 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 16:13:45,910 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 16:13:48,967 INFO L? ?]: Removed 474 outVars from TransFormulas that were not future-live. [2024-11-13 16:13:48,968 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 16:13:49,034 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 16:13:49,035 INFO L316 CfgBuilder]: Removed 11 assume(true) statements. [2024-11-13 16:13:49,035 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 04:13:49 BoogieIcfgContainer [2024-11-13 16:13:49,035 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 16:13:49,039 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 16:13:49,039 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 16:13:49,046 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 16:13:49,047 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 16:13:49,047 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 04:13:44" (1/3) ... [2024-11-13 16:13:49,049 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39e3c690 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 04:13:49, skipping insertion in model container [2024-11-13 16:13:49,050 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 16:13:49,050 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 04:13:45" (2/3) ... [2024-11-13 16:13:49,052 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39e3c690 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 04:13:49, skipping insertion in model container [2024-11-13 16:13:49,053 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 16:13:49,053 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 04:13:49" (3/3) ... [2024-11-13 16:13:49,055 INFO L333 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2024-11-13 16:13:49,180 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 16:13:49,181 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 16:13:49,181 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 16:13:49,181 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 16:13:49,181 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 16:13:49,182 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 16:13:49,182 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 16:13:49,182 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 16:13:49,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:49,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2024-11-13 16:13:49,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:49,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:49,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:49,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:49,349 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 16:13:49,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:49,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2024-11-13 16:13:49,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:49,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:49,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:49,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:49,406 INFO L745 eck$LassoCheckResult]: Stem: 155#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 920#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 916#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 447#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 987#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 494#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 129#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 284#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 970#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 265#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 567#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504#L854true assume !(0 == ~M_E~0); 332#L854-2true assume !(0 == ~T1_E~0); 639#L859-1true assume !(0 == ~T2_E~0); 68#L864-1true assume !(0 == ~T3_E~0); 123#L869-1true assume !(0 == ~T4_E~0); 877#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 815#L879-1true assume !(0 == ~T6_E~0); 325#L884-1true assume !(0 == ~T7_E~0); 8#L889-1true assume !(0 == ~T8_E~0); 171#L894-1true assume !(0 == ~E_M~0); 981#L899-1true assume !(0 == ~E_1~0); 509#L904-1true assume !(0 == ~E_2~0); 277#L909-1true assume !(0 == ~E_3~0); 438#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 463#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 115#L929-1true assume !(0 == ~E_7~0); 834#L934-1true assume !(0 == ~E_8~0); 263#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16#L418true assume !(1 == ~m_pc~0); 903#L418-2true is_master_triggered_~__retres1~0#1 := 0; 717#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890#L437true assume 1 == ~t1_pc~0; 974#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 632#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 826#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 617#L456true assume !(1 == ~t2_pc~0); 436#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 882#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 661#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 358#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66#L475true assume 1 == ~t3_pc~0; 298#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 190#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713#L494true assume !(1 == ~t4_pc~0); 214#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 417#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 953#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 460#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95#L513true assume 1 == ~t5_pc~0; 584#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 911#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 895#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51#L532true assume !(1 == ~t6_pc~0); 407#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 303#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 849#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 175#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 665#L551true assume 1 == ~t7_pc~0; 675#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 465#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 934#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1007#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 945#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292#L570true assume 1 == ~t8_pc~0; 379#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 749#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 585#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 63#L1125-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L952-2true assume !(1 == ~T1_E~0); 597#L957-1true assume !(1 == ~T2_E~0); 899#L962-1true assume !(1 == ~T3_E~0); 391#L967-1true assume !(1 == ~T4_E~0); 869#L972-1true assume !(1 == ~T5_E~0); 668#L977-1true assume !(1 == ~T6_E~0); 950#L982-1true assume !(1 == ~T7_E~0); 126#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 130#L992-1true assume !(1 == ~E_M~0); 356#L997-1true assume !(1 == ~E_1~0); 821#L1002-1true assume !(1 == ~E_2~0); 346#L1007-1true assume !(1 == ~E_3~0); 9#L1012-1true assume !(1 == ~E_4~0); 564#L1017-1true assume !(1 == ~E_5~0); 349#L1022-1true assume !(1 == ~E_6~0); 370#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 823#L1032-1true assume !(1 == ~E_8~0); 487#L1037-1true assume { :end_inline_reset_delta_events } true; 588#L1303-2true [2024-11-13 16:13:49,413 INFO L747 eck$LassoCheckResult]: Loop: 588#L1303-2true assume !false; 627#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 982#L829-1true assume false; 589#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475#L854-3true assume 0 == ~M_E~0;~M_E~0 := 1; 453#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 926#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 809#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 304#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 357#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 390#L884-3true assume !(0 == ~T7_E~0); 342#L889-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 110#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 499#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 128#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 323#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 100#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 121#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 730#L924-3true assume !(0 == ~E_6~0); 537#L929-3true assume 0 == ~E_7~0;~E_7~0 := 1; 440#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 670#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569#L418-30true assume !(1 == ~m_pc~0); 384#L418-32true is_master_triggered_~__retres1~0#1 := 0; 581#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216#L437-30true assume !(1 == ~t1_pc~0); 679#L437-32true is_transmit1_triggered_~__retres1~1#1 := 0; 374#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 883#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193#L456-30true assume 1 == ~t2_pc~0; 719#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 527#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 285#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766#L475-30true assume !(1 == ~t3_pc~0); 30#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 452#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 389#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 901#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 999#L494-30true assume 1 == ~t4_pc~0; 200#L495-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 833#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1093-30true assume !(0 != activate_threads_~tmp___3~0#1); 698#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956#L513-30true assume 1 == ~t5_pc~0; 988#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 340#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295#L532-30true assume 1 == ~t6_pc~0; 957#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133#L551-30true assume 1 == ~t7_pc~0; 165#L552-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10#L1117-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 191#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 758#L570-30true assume 1 == ~t8_pc~0; 634#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 973#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 236#L1125-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 958#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 752#L957-3true assume !(1 == ~T2_E~0); 769#L962-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 615#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 800#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 508#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 996#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 977#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 226#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 365#L997-3true assume !(1 == ~E_1~0); 224#L1002-3true assume 1 == ~E_2~0;~E_2~0 := 2; 464#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 117#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 170#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 324#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 347#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 23#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 434#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 768#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 830#L1322true assume !(0 == start_simulation_~tmp~3#1); 246#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 753#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 510#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 388#stop_simulation_returnLabel#1true start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 673#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 588#L1303-2true [2024-11-13 16:13:49,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:49,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2024-11-13 16:13:49,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:49,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882518151] [2024-11-13 16:13:49,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:49,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:49,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:49,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:49,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:49,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882518151] [2024-11-13 16:13:49,938 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882518151] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:49,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:49,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:49,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960362429] [2024-11-13 16:13:49,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:49,955 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:49,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:49,956 INFO L85 PathProgramCache]: Analyzing trace with hash -623546031, now seen corresponding path program 1 times [2024-11-13 16:13:49,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:49,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712779106] [2024-11-13 16:13:49,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:49,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:50,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:50,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:50,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:50,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712779106] [2024-11-13 16:13:50,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1712779106] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:50,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:50,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 16:13:50,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463840095] [2024-11-13 16:13:50,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:50,074 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:50,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:50,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:50,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:50,116 INFO L87 Difference]: Start difference. First operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:50,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:50,282 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2024-11-13 16:13:50,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2024-11-13 16:13:50,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:50,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1002 states and 1490 transitions. [2024-11-13 16:13:50,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:50,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:50,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1490 transitions. [2024-11-13 16:13:50,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:50,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-11-13 16:13:50,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1490 transitions. [2024-11-13 16:13:50,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:50,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4870259481037924) internal successors, (1490), 1001 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:50,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1490 transitions. [2024-11-13 16:13:50,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-11-13 16:13:50,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:50,460 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2024-11-13 16:13:50,460 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 16:13:50,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1490 transitions. [2024-11-13 16:13:50,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:50,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:50,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:50,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:50,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:50,478 INFO L745 eck$LassoCheckResult]: Stem: 2347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3011#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2766#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2767#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2364#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2365#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2297#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2298#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2560#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2532#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2533#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2816#L854 assume !(0 == ~M_E~0); 2623#L854-2 assume !(0 == ~T1_E~0); 2624#L859-1 assume !(0 == ~T2_E~0); 2177#L864-1 assume !(0 == ~T3_E~0); 2178#L869-1 assume !(0 == ~T4_E~0); 2288#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2997#L879-1 assume !(0 == ~T6_E~0); 2613#L884-1 assume !(0 == ~T7_E~0); 2040#L889-1 assume !(0 == ~T8_E~0); 2041#L894-1 assume !(0 == ~E_M~0); 2377#L899-1 assume !(0 == ~E_1~0); 2822#L904-1 assume !(0 == ~E_2~0); 2550#L909-1 assume !(0 == ~E_3~0); 2551#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2757#L919-1 assume !(0 == ~E_5~0); 2456#L924-1 assume !(0 == ~E_6~0); 2270#L929-1 assume !(0 == ~E_7~0); 2271#L934-1 assume !(0 == ~E_8~0); 2529#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2057#L418 assume !(1 == ~m_pc~0); 2032#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2031#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2926#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2912#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2845#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L437 assume 1 == ~t1_pc~0; 3014#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2919#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2081#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2406#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2902#L456 assume !(1 == ~t2_pc~0); 2328#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2327#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2489#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2661#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2171#L475 assume 1 == ~t3_pc~0; 2172#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2235#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2049#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2409#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2410#L494 assume !(1 == ~t4_pc~0); 2450#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2451#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2188#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2781#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2230#L513 assume 1 == ~t5_pc~0; 2231#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2452#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2184#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2185#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2137#L532 assume !(1 == ~t6_pc~0); 2138#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2289#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2471#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2381#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2382#L551 assume 1 == ~t7_pc~0; 2939#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2783#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2784#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3023#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3024#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2571#L570 assume 1 == ~t8_pc~0; 2572#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2687#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2877#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2683#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2165#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2166#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2106#L952-2 assume !(1 == ~T1_E~0); 2107#L957-1 assume !(1 == ~T2_E~0); 2883#L962-1 assume !(1 == ~T3_E~0); 2699#L967-1 assume !(1 == ~T4_E~0); 2700#L972-1 assume !(1 == ~T5_E~0); 2942#L977-1 assume !(1 == ~T6_E~0); 2943#L982-1 assume !(1 == ~T7_E~0); 2291#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2292#L992-1 assume !(1 == ~E_M~0); 2299#L997-1 assume !(1 == ~E_1~0); 2659#L1002-1 assume !(1 == ~E_2~0); 2644#L1007-1 assume !(1 == ~E_3~0); 2042#L1012-1 assume !(1 == ~E_4~0); 2043#L1017-1 assume !(1 == ~E_5~0); 2647#L1022-1 assume !(1 == ~E_6~0); 2648#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2673#L1032-1 assume !(1 == ~E_8~0); 2804#L1037-1 assume { :end_inline_reset_delta_events } true; 2805#L1303-2 [2024-11-13 16:13:50,479 INFO L747 eck$LassoCheckResult]: Loop: 2805#L1303-2 assume !false; 2879#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2547#L829-1 assume !false; 2842#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2432#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2367#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2511#L712 assume !(0 != eval_~tmp~0#1); 2772#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2682#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2773#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2774#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3022#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2996#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2589#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2590#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2660#L884-3 assume !(0 == ~T7_E~0); 2638#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2261#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2262#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2295#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2296#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2240#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2241#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2284#L924-3 assume !(0 == ~E_6~0); 2848#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2759#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2760#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2867#L418-30 assume 1 == ~m_pc~0; 2124#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2125#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2502#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2329#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2330#L437-30 assume !(1 == ~t1_pc~0); 2453#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2679#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2680#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2717#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3013#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413#L456-30 assume 1 == ~t2_pc~0; 2414#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2840#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2412#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2218#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2219#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2561#L475-30 assume 1 == ~t3_pc~0; 2935#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2089#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2697#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2698#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2436#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2437#L494-30 assume !(1 == ~t4_pc~0); 2245#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2028#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2029#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3001#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2951#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2952#L513-30 assume 1 == ~t5_pc~0; 3025#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2567#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2636#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2859#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2579#L532-30 assume !(1 == ~t6_pc~0); 2580#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2169#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2170#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2194#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2250#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2251#L551-30 assume !(1 == ~t7_pc~0); 2304#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2369#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2044#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2045#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2411#L570-30 assume 1 == ~t8_pc~0; 2920#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2300#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2301#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2102#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2103#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2526#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2977#L957-3 assume !(1 == ~T2_E~0); 2978#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2900#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2901#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2820#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2821#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3026#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2468#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2469#L997-3 assume !(1 == ~E_1~0); 2464#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2465#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2274#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2275#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2376#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2612#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2072#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2073#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2318#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2319#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2435#L1322 assume !(0 == start_simulation_~tmp~3#1); 2496#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2159#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2160#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2058#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2059#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2695#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2696#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2805#L1303-2 [2024-11-13 16:13:50,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:50,480 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2024-11-13 16:13:50,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:50,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374668319] [2024-11-13 16:13:50,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:50,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:50,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:50,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:50,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:50,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374668319] [2024-11-13 16:13:50,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374668319] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:50,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:50,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:50,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465293502] [2024-11-13 16:13:50,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:50,627 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:50,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:50,628 INFO L85 PathProgramCache]: Analyzing trace with hash -590573839, now seen corresponding path program 1 times [2024-11-13 16:13:50,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:50,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204675346] [2024-11-13 16:13:50,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:50,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:50,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:50,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:50,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:50,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204675346] [2024-11-13 16:13:50,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204675346] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:50,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:50,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:50,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334923108] [2024-11-13 16:13:50,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:50,892 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:50,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:50,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:50,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:50,897 INFO L87 Difference]: Start difference. First operand 1002 states and 1490 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:50,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:50,944 INFO L93 Difference]: Finished difference Result 1002 states and 1489 transitions. [2024-11-13 16:13:50,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1489 transitions. [2024-11-13 16:13:50,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:50,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1489 transitions. [2024-11-13 16:13:50,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:50,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:50,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1489 transitions. [2024-11-13 16:13:50,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:50,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-11-13 16:13:50,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1489 transitions. [2024-11-13 16:13:50,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:51,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4860279441117765) internal successors, (1489), 1001 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:51,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1489 transitions. [2024-11-13 16:13:51,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-11-13 16:13:51,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:51,010 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2024-11-13 16:13:51,012 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 16:13:51,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1489 transitions. [2024-11-13 16:13:51,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:51,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:51,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:51,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,030 INFO L745 eck$LassoCheckResult]: Stem: 4358#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5022#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4778#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4375#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4376#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4308#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4309#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4571#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4543#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4544#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4827#L854 assume !(0 == ~M_E~0); 4634#L854-2 assume !(0 == ~T1_E~0); 4635#L859-1 assume !(0 == ~T2_E~0); 4188#L864-1 assume !(0 == ~T3_E~0); 4189#L869-1 assume !(0 == ~T4_E~0); 4299#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5008#L879-1 assume !(0 == ~T6_E~0); 4624#L884-1 assume !(0 == ~T7_E~0); 4051#L889-1 assume !(0 == ~T8_E~0); 4052#L894-1 assume !(0 == ~E_M~0); 4388#L899-1 assume !(0 == ~E_1~0); 4833#L904-1 assume !(0 == ~E_2~0); 4561#L909-1 assume !(0 == ~E_3~0); 4562#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4768#L919-1 assume !(0 == ~E_5~0); 4467#L924-1 assume !(0 == ~E_6~0); 4281#L929-1 assume !(0 == ~E_7~0); 4282#L934-1 assume !(0 == ~E_8~0); 4540#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4068#L418 assume !(1 == ~m_pc~0); 4043#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4042#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4923#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4856#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4857#L437 assume 1 == ~t1_pc~0; 5025#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4930#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4091#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4092#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4417#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L456 assume !(1 == ~t2_pc~0); 4339#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4338#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4500#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4672#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4182#L475 assume 1 == ~t3_pc~0; 4183#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4246#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4060#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4420#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4421#L494 assume !(1 == ~t4_pc~0); 4461#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4462#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4198#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4199#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4792#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4241#L513 assume 1 == ~t5_pc~0; 4242#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4463#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4939#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4195#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4196#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4148#L532 assume !(1 == ~t6_pc~0); 4149#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4300#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4482#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4392#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4393#L551 assume 1 == ~t7_pc~0; 4950#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4794#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5034#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 5035#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4582#L570 assume 1 == ~t8_pc~0; 4583#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4698#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4888#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4694#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4176#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4177#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4117#L952-2 assume !(1 == ~T1_E~0); 4118#L957-1 assume !(1 == ~T2_E~0); 4894#L962-1 assume !(1 == ~T3_E~0); 4710#L967-1 assume !(1 == ~T4_E~0); 4711#L972-1 assume !(1 == ~T5_E~0); 4953#L977-1 assume !(1 == ~T6_E~0); 4954#L982-1 assume !(1 == ~T7_E~0); 4302#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4303#L992-1 assume !(1 == ~E_M~0); 4310#L997-1 assume !(1 == ~E_1~0); 4670#L1002-1 assume !(1 == ~E_2~0); 4655#L1007-1 assume !(1 == ~E_3~0); 4053#L1012-1 assume !(1 == ~E_4~0); 4054#L1017-1 assume !(1 == ~E_5~0); 4658#L1022-1 assume !(1 == ~E_6~0); 4659#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4684#L1032-1 assume !(1 == ~E_8~0); 4815#L1037-1 assume { :end_inline_reset_delta_events } true; 4816#L1303-2 [2024-11-13 16:13:51,030 INFO L747 eck$LassoCheckResult]: Loop: 4816#L1303-2 assume !false; 4890#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4558#L829-1 assume !false; 4853#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4443#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4378#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L712 assume !(0 != eval_~tmp~0#1); 4783#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4693#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4784#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4785#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5033#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5007#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4600#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4601#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4671#L884-3 assume !(0 == ~T7_E~0); 4649#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4272#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4306#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4307#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4251#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4252#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4295#L924-3 assume !(0 == ~E_6~0); 4859#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4770#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4771#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4878#L418-30 assume 1 == ~m_pc~0; 4135#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4136#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4512#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4513#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4340#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4341#L437-30 assume !(1 == ~t1_pc~0); 4464#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4690#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4728#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5024#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4424#L456-30 assume 1 == ~t2_pc~0; 4425#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4851#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4423#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4229#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4230#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4572#L475-30 assume 1 == ~t3_pc~0; 4946#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4100#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4708#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4709#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4447#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4448#L494-30 assume !(1 == ~t4_pc~0); 4256#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4039#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4040#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5012#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 4962#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4963#L513-30 assume !(1 == ~t5_pc~0); 4577#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4578#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4870#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4590#L532-30 assume 1 == ~t6_pc~0; 4592#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4180#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4181#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4205#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4261#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4262#L551-30 assume 1 == ~t7_pc~0; 4314#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4380#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4860#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4055#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4056#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4422#L570-30 assume 1 == ~t8_pc~0; 4931#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4311#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4312#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4113#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4114#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4493#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4537#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4988#L957-3 assume !(1 == ~T2_E~0); 4989#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4911#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4912#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4831#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4832#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5037#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4479#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4480#L997-3 assume !(1 == ~E_1~0); 4475#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4476#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4285#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4286#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4387#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4623#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4083#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4084#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4329#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4330#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4446#L1322 assume !(0 == start_simulation_~tmp~3#1); 4507#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4170#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4171#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4069#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4070#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4706#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4707#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4816#L1303-2 [2024-11-13 16:13:51,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,031 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2024-11-13 16:13:51,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741479412] [2024-11-13 16:13:51,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741479412] [2024-11-13 16:13:51,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741479412] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107805622] [2024-11-13 16:13:51,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,138 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:51,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,145 INFO L85 PathProgramCache]: Analyzing trace with hash -770468816, now seen corresponding path program 1 times [2024-11-13 16:13:51,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10165064] [2024-11-13 16:13:51,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10165064] [2024-11-13 16:13:51,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10165064] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,283 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386741320] [2024-11-13 16:13:51,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,284 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:51,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:51,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:51,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:51,284 INFO L87 Difference]: Start difference. First operand 1002 states and 1489 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:51,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:51,326 INFO L93 Difference]: Finished difference Result 1002 states and 1488 transitions. [2024-11-13 16:13:51,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1488 transitions. [2024-11-13 16:13:51,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:51,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1488 transitions. [2024-11-13 16:13:51,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:51,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:51,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1488 transitions. [2024-11-13 16:13:51,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:51,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-11-13 16:13:51,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1488 transitions. [2024-11-13 16:13:51,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:51,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4850299401197604) internal successors, (1488), 1001 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:51,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1488 transitions. [2024-11-13 16:13:51,413 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-11-13 16:13:51,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:51,415 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2024-11-13 16:13:51,416 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 16:13:51,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1488 transitions. [2024-11-13 16:13:51,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:51,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:51,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:51,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,427 INFO L745 eck$LassoCheckResult]: Stem: 6369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7033#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6788#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6789#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6386#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6387#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6319#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6320#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6582#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6554#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6555#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6838#L854 assume !(0 == ~M_E~0); 6645#L854-2 assume !(0 == ~T1_E~0); 6646#L859-1 assume !(0 == ~T2_E~0); 6199#L864-1 assume !(0 == ~T3_E~0); 6200#L869-1 assume !(0 == ~T4_E~0); 6310#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7019#L879-1 assume !(0 == ~T6_E~0); 6635#L884-1 assume !(0 == ~T7_E~0); 6062#L889-1 assume !(0 == ~T8_E~0); 6063#L894-1 assume !(0 == ~E_M~0); 6399#L899-1 assume !(0 == ~E_1~0); 6844#L904-1 assume !(0 == ~E_2~0); 6572#L909-1 assume !(0 == ~E_3~0); 6573#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6779#L919-1 assume !(0 == ~E_5~0); 6478#L924-1 assume !(0 == ~E_6~0); 6292#L929-1 assume !(0 == ~E_7~0); 6293#L934-1 assume !(0 == ~E_8~0); 6551#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6079#L418 assume !(1 == ~m_pc~0); 6054#L418-2 is_master_triggered_~__retres1~0#1 := 0; 6053#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6948#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6934#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6867#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6868#L437 assume 1 == ~t1_pc~0; 7036#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6941#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6103#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6428#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6924#L456 assume !(1 == ~t2_pc~0); 6350#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6349#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6510#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6511#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6683#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6193#L475 assume 1 == ~t3_pc~0; 6194#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6071#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6431#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6432#L494 assume !(1 == ~t4_pc~0); 6472#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6473#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6210#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6803#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6252#L513 assume 1 == ~t5_pc~0; 6253#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6474#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6206#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6207#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6159#L532 assume !(1 == ~t6_pc~0); 6160#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6311#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6493#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6403#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6404#L551 assume 1 == ~t7_pc~0; 6961#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6805#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7045#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 7046#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6593#L570 assume 1 == ~t8_pc~0; 6594#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6709#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6705#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6187#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6188#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6128#L952-2 assume !(1 == ~T1_E~0); 6129#L957-1 assume !(1 == ~T2_E~0); 6905#L962-1 assume !(1 == ~T3_E~0); 6721#L967-1 assume !(1 == ~T4_E~0); 6722#L972-1 assume !(1 == ~T5_E~0); 6964#L977-1 assume !(1 == ~T6_E~0); 6965#L982-1 assume !(1 == ~T7_E~0); 6313#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6314#L992-1 assume !(1 == ~E_M~0); 6321#L997-1 assume !(1 == ~E_1~0); 6681#L1002-1 assume !(1 == ~E_2~0); 6666#L1007-1 assume !(1 == ~E_3~0); 6064#L1012-1 assume !(1 == ~E_4~0); 6065#L1017-1 assume !(1 == ~E_5~0); 6669#L1022-1 assume !(1 == ~E_6~0); 6670#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6695#L1032-1 assume !(1 == ~E_8~0); 6826#L1037-1 assume { :end_inline_reset_delta_events } true; 6827#L1303-2 [2024-11-13 16:13:51,428 INFO L747 eck$LassoCheckResult]: Loop: 6827#L1303-2 assume !false; 6901#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6569#L829-1 assume !false; 6864#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6454#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6389#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6532#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6533#L712 assume !(0 != eval_~tmp~0#1); 6794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6704#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6795#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6796#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7044#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7018#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6611#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6612#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6682#L884-3 assume !(0 == ~T7_E~0); 6660#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6283#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6284#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6317#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6318#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6262#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6263#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6306#L924-3 assume !(0 == ~E_6~0); 6870#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6781#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6782#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6889#L418-30 assume 1 == ~m_pc~0; 6146#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6147#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6523#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6524#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6351#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6352#L437-30 assume !(1 == ~t1_pc~0); 6475#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6701#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6739#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7035#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6435#L456-30 assume 1 == ~t2_pc~0; 6436#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6862#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6240#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6241#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6583#L475-30 assume 1 == ~t3_pc~0; 6957#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6111#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6719#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6720#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6458#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6459#L494-30 assume 1 == ~t4_pc~0; 6449#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6050#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6051#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7023#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 6973#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6974#L513-30 assume 1 == ~t5_pc~0; 7047#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6589#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6658#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6815#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6881#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6601#L532-30 assume !(1 == ~t6_pc~0); 6602#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 6191#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6192#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6216#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6272#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6273#L551-30 assume 1 == ~t7_pc~0; 6325#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6391#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6871#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6066#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6067#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L570-30 assume !(1 == ~t8_pc~0); 6787#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6322#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6323#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6124#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6125#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6548#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6999#L957-3 assume !(1 == ~T2_E~0); 7000#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6922#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6923#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6842#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6843#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7048#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6490#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6491#L997-3 assume !(1 == ~E_1~0); 6486#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6487#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6296#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6297#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6398#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6634#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6094#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6095#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6340#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6341#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6456#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6457#L1322 assume !(0 == start_simulation_~tmp~3#1); 6518#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6181#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6182#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6080#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6081#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6717#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6718#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6827#L1303-2 [2024-11-13 16:13:51,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,433 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2024-11-13 16:13:51,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250005426] [2024-11-13 16:13:51,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250005426] [2024-11-13 16:13:51,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250005426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064809816] [2024-11-13 16:13:51,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,537 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:51,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1902590960, now seen corresponding path program 1 times [2024-11-13 16:13:51,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948492316] [2024-11-13 16:13:51,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948492316] [2024-11-13 16:13:51,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948492316] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534377330] [2024-11-13 16:13:51,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,647 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:51,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:51,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:51,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:51,648 INFO L87 Difference]: Start difference. First operand 1002 states and 1488 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:51,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:51,681 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2024-11-13 16:13:51,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1487 transitions. [2024-11-13 16:13:51,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:51,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1487 transitions. [2024-11-13 16:13:51,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:51,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:51,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1487 transitions. [2024-11-13 16:13:51,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:51,704 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-11-13 16:13:51,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1487 transitions. [2024-11-13 16:13:51,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:51,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4840319361277445) internal successors, (1487), 1001 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:51,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1487 transitions. [2024-11-13 16:13:51,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-11-13 16:13:51,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:51,735 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2024-11-13 16:13:51,736 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 16:13:51,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1487 transitions. [2024-11-13 16:13:51,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:51,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:51,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:51,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:51,751 INFO L745 eck$LassoCheckResult]: Stem: 8380#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9044#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8799#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8800#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8397#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8398#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8330#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8331#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8593#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8565#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8566#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8849#L854 assume !(0 == ~M_E~0); 8656#L854-2 assume !(0 == ~T1_E~0); 8657#L859-1 assume !(0 == ~T2_E~0); 8210#L864-1 assume !(0 == ~T3_E~0); 8211#L869-1 assume !(0 == ~T4_E~0); 8321#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L879-1 assume !(0 == ~T6_E~0); 8646#L884-1 assume !(0 == ~T7_E~0); 8073#L889-1 assume !(0 == ~T8_E~0); 8074#L894-1 assume !(0 == ~E_M~0); 8410#L899-1 assume !(0 == ~E_1~0); 8855#L904-1 assume !(0 == ~E_2~0); 8583#L909-1 assume !(0 == ~E_3~0); 8584#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8790#L919-1 assume !(0 == ~E_5~0); 8489#L924-1 assume !(0 == ~E_6~0); 8303#L929-1 assume !(0 == ~E_7~0); 8304#L934-1 assume !(0 == ~E_8~0); 8562#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8090#L418 assume !(1 == ~m_pc~0); 8065#L418-2 is_master_triggered_~__retres1~0#1 := 0; 8064#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8945#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8878#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8879#L437 assume 1 == ~t1_pc~0; 9047#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8952#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8114#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8439#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8935#L456 assume !(1 == ~t2_pc~0); 8361#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8360#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8521#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8522#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8694#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8204#L475 assume 1 == ~t3_pc~0; 8205#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8268#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8082#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8442#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8443#L494 assume !(1 == ~t4_pc~0); 8483#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8484#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8221#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8814#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8263#L513 assume 1 == ~t5_pc~0; 8264#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8485#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8218#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8170#L532 assume !(1 == ~t6_pc~0); 8171#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8322#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8503#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8504#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8414#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8415#L551 assume 1 == ~t7_pc~0; 8972#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8816#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9056#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 9057#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8604#L570 assume 1 == ~t8_pc~0; 8605#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8720#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8910#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8716#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8198#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8199#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8139#L952-2 assume !(1 == ~T1_E~0); 8140#L957-1 assume !(1 == ~T2_E~0); 8916#L962-1 assume !(1 == ~T3_E~0); 8732#L967-1 assume !(1 == ~T4_E~0); 8733#L972-1 assume !(1 == ~T5_E~0); 8975#L977-1 assume !(1 == ~T6_E~0); 8976#L982-1 assume !(1 == ~T7_E~0); 8324#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8325#L992-1 assume !(1 == ~E_M~0); 8332#L997-1 assume !(1 == ~E_1~0); 8692#L1002-1 assume !(1 == ~E_2~0); 8677#L1007-1 assume !(1 == ~E_3~0); 8075#L1012-1 assume !(1 == ~E_4~0); 8076#L1017-1 assume !(1 == ~E_5~0); 8680#L1022-1 assume !(1 == ~E_6~0); 8681#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L1032-1 assume !(1 == ~E_8~0); 8837#L1037-1 assume { :end_inline_reset_delta_events } true; 8838#L1303-2 [2024-11-13 16:13:51,751 INFO L747 eck$LassoCheckResult]: Loop: 8838#L1303-2 assume !false; 8912#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8580#L829-1 assume !false; 8875#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8465#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8400#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8543#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8544#L712 assume !(0 != eval_~tmp~0#1); 8805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8715#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8806#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8807#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9055#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9029#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8622#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8623#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8693#L884-3 assume !(0 == ~T7_E~0); 8671#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8294#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8295#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8328#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8329#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8273#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8274#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8317#L924-3 assume !(0 == ~E_6~0); 8881#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8792#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8793#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8900#L418-30 assume 1 == ~m_pc~0; 8157#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8158#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8362#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8363#L437-30 assume !(1 == ~t1_pc~0); 8486#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 8712#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8713#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8750#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9046#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8446#L456-30 assume !(1 == ~t2_pc~0); 8448#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 8873#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8445#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8251#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8252#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8594#L475-30 assume 1 == ~t3_pc~0; 8968#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8122#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8730#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8731#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8469#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8470#L494-30 assume !(1 == ~t4_pc~0); 8278#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8061#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8062#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9034#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 8984#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8985#L513-30 assume 1 == ~t5_pc~0; 9058#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8600#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8669#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8826#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8892#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8612#L532-30 assume !(1 == ~t6_pc~0); 8613#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 8202#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8203#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8283#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8284#L551-30 assume 1 == ~t7_pc~0; 8336#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8402#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8882#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8077#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8078#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8444#L570-30 assume 1 == ~t8_pc~0; 8953#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8333#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8334#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8135#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8136#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8515#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8559#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9010#L957-3 assume !(1 == ~T2_E~0); 9011#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8933#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8934#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8853#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8854#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9059#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8501#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8502#L997-3 assume !(1 == ~E_1~0); 8497#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8498#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8307#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8308#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8409#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8645#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8105#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8106#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8351#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8352#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8468#L1322 assume !(0 == start_simulation_~tmp~3#1); 8529#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8192#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8193#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8091#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8092#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8728#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8729#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8838#L1303-2 [2024-11-13 16:13:51,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,751 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2024-11-13 16:13:51,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352147883] [2024-11-13 16:13:51,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352147883] [2024-11-13 16:13:51,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352147883] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405388331] [2024-11-13 16:13:51,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,877 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:51,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:51,878 INFO L85 PathProgramCache]: Analyzing trace with hash -357116111, now seen corresponding path program 1 times [2024-11-13 16:13:51,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:51,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707237729] [2024-11-13 16:13:51,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:51,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:51,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:51,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:51,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:51,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707237729] [2024-11-13 16:13:51,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707237729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:51,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:51,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:51,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781766120] [2024-11-13 16:13:51,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:51,996 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:51,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:51,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:51,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:51,997 INFO L87 Difference]: Start difference. First operand 1002 states and 1487 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:52,032 INFO L93 Difference]: Finished difference Result 1002 states and 1486 transitions. [2024-11-13 16:13:52,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1486 transitions. [2024-11-13 16:13:52,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1486 transitions. [2024-11-13 16:13:52,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:52,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:52,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1486 transitions. [2024-11-13 16:13:52,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:52,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-11-13 16:13:52,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1486 transitions. [2024-11-13 16:13:52,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:52,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4830339321357286) internal successors, (1486), 1001 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1486 transitions. [2024-11-13 16:13:52,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-11-13 16:13:52,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:52,081 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2024-11-13 16:13:52,083 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 16:13:52,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1486 transitions. [2024-11-13 16:13:52,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:52,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:52,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,094 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,095 INFO L745 eck$LassoCheckResult]: Stem: 10391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11055#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10810#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10811#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10341#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10342#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10604#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10576#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10577#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10860#L854 assume !(0 == ~M_E~0); 10667#L854-2 assume !(0 == ~T1_E~0); 10668#L859-1 assume !(0 == ~T2_E~0); 10221#L864-1 assume !(0 == ~T3_E~0); 10222#L869-1 assume !(0 == ~T4_E~0); 10332#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11041#L879-1 assume !(0 == ~T6_E~0); 10657#L884-1 assume !(0 == ~T7_E~0); 10084#L889-1 assume !(0 == ~T8_E~0); 10085#L894-1 assume !(0 == ~E_M~0); 10421#L899-1 assume !(0 == ~E_1~0); 10866#L904-1 assume !(0 == ~E_2~0); 10594#L909-1 assume !(0 == ~E_3~0); 10595#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10801#L919-1 assume !(0 == ~E_5~0); 10500#L924-1 assume !(0 == ~E_6~0); 10314#L929-1 assume !(0 == ~E_7~0); 10315#L934-1 assume !(0 == ~E_8~0); 10573#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10101#L418 assume !(1 == ~m_pc~0); 10076#L418-2 is_master_triggered_~__retres1~0#1 := 0; 10075#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10970#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10956#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10889#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10890#L437 assume 1 == ~t1_pc~0; 11058#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10963#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10125#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10450#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10946#L456 assume !(1 == ~t2_pc~0); 10372#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10371#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10533#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10705#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10215#L475 assume 1 == ~t3_pc~0; 10216#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10279#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10093#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10453#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10454#L494 assume !(1 == ~t4_pc~0); 10494#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10495#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10232#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10825#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10274#L513 assume 1 == ~t5_pc~0; 10275#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10496#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10228#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10229#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10181#L532 assume !(1 == ~t6_pc~0); 10182#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10333#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10515#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10425#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10426#L551 assume 1 == ~t7_pc~0; 10983#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10827#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11067#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 11068#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10615#L570 assume 1 == ~t8_pc~0; 10616#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10731#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10921#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10727#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10209#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10210#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10150#L952-2 assume !(1 == ~T1_E~0); 10151#L957-1 assume !(1 == ~T2_E~0); 10927#L962-1 assume !(1 == ~T3_E~0); 10743#L967-1 assume !(1 == ~T4_E~0); 10744#L972-1 assume !(1 == ~T5_E~0); 10986#L977-1 assume !(1 == ~T6_E~0); 10987#L982-1 assume !(1 == ~T7_E~0); 10335#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10336#L992-1 assume !(1 == ~E_M~0); 10343#L997-1 assume !(1 == ~E_1~0); 10703#L1002-1 assume !(1 == ~E_2~0); 10688#L1007-1 assume !(1 == ~E_3~0); 10086#L1012-1 assume !(1 == ~E_4~0); 10087#L1017-1 assume !(1 == ~E_5~0); 10691#L1022-1 assume !(1 == ~E_6~0); 10692#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10717#L1032-1 assume !(1 == ~E_8~0); 10848#L1037-1 assume { :end_inline_reset_delta_events } true; 10849#L1303-2 [2024-11-13 16:13:52,095 INFO L747 eck$LassoCheckResult]: Loop: 10849#L1303-2 assume !false; 10923#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10591#L829-1 assume !false; 10886#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10476#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10411#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10555#L712 assume !(0 != eval_~tmp~0#1); 10816#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10726#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10817#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10818#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11066#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11040#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10633#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10634#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10704#L884-3 assume !(0 == ~T7_E~0); 10682#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10305#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10306#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10339#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10340#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10284#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10285#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10328#L924-3 assume !(0 == ~E_6~0); 10892#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10803#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10804#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10911#L418-30 assume 1 == ~m_pc~0; 10168#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10169#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10545#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10546#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10373#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10374#L437-30 assume !(1 == ~t1_pc~0); 10497#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 10723#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10724#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10761#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11057#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10457#L456-30 assume 1 == ~t2_pc~0; 10458#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10884#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10456#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10262#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10263#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10605#L475-30 assume 1 == ~t3_pc~0; 10979#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10133#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10741#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10742#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10480#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10481#L494-30 assume !(1 == ~t4_pc~0); 10289#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10073#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11045#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 10995#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10996#L513-30 assume !(1 == ~t5_pc~0); 10610#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10611#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10680#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10837#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10903#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10623#L532-30 assume !(1 == ~t6_pc~0); 10624#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10213#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10214#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10238#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10294#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10295#L551-30 assume 1 == ~t7_pc~0; 10347#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10413#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10893#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10088#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10089#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10455#L570-30 assume 1 == ~t8_pc~0; 10964#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10344#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10345#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10146#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10147#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10526#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10570#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11021#L957-3 assume !(1 == ~T2_E~0); 11022#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10944#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10945#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10864#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10865#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11070#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10512#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L997-3 assume !(1 == ~E_1~0); 10508#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10509#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10318#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10319#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10420#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10656#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10116#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10117#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10363#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10479#L1322 assume !(0 == start_simulation_~tmp~3#1); 10540#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10203#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10204#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10102#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10103#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10739#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10740#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10849#L1303-2 [2024-11-13 16:13:52,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2024-11-13 16:13:52,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603424738] [2024-11-13 16:13:52,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603424738] [2024-11-13 16:13:52,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1603424738] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129871143] [2024-11-13 16:13:52,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,171 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:52,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,172 INFO L85 PathProgramCache]: Analyzing trace with hash 697734513, now seen corresponding path program 1 times [2024-11-13 16:13:52,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443015395] [2024-11-13 16:13:52,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443015395] [2024-11-13 16:13:52,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443015395] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635810543] [2024-11-13 16:13:52,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,259 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:52,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:52,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:52,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:52,260 INFO L87 Difference]: Start difference. First operand 1002 states and 1486 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:52,297 INFO L93 Difference]: Finished difference Result 1002 states and 1485 transitions. [2024-11-13 16:13:52,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1485 transitions. [2024-11-13 16:13:52,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1485 transitions. [2024-11-13 16:13:52,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:52,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:52,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1485 transitions. [2024-11-13 16:13:52,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:52,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-11-13 16:13:52,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1485 transitions. [2024-11-13 16:13:52,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:52,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4820359281437125) internal successors, (1485), 1001 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1485 transitions. [2024-11-13 16:13:52,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-11-13 16:13:52,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:52,392 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2024-11-13 16:13:52,392 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 16:13:52,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1485 transitions. [2024-11-13 16:13:52,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:52,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:52,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,405 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,407 INFO L745 eck$LassoCheckResult]: Stem: 12402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13066#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12821#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12822#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12419#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12420#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12352#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12353#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12615#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12587#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12588#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12871#L854 assume !(0 == ~M_E~0); 12678#L854-2 assume !(0 == ~T1_E~0); 12679#L859-1 assume !(0 == ~T2_E~0); 12232#L864-1 assume !(0 == ~T3_E~0); 12233#L869-1 assume !(0 == ~T4_E~0); 12343#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13052#L879-1 assume !(0 == ~T6_E~0); 12668#L884-1 assume !(0 == ~T7_E~0); 12095#L889-1 assume !(0 == ~T8_E~0); 12096#L894-1 assume !(0 == ~E_M~0); 12432#L899-1 assume !(0 == ~E_1~0); 12877#L904-1 assume !(0 == ~E_2~0); 12605#L909-1 assume !(0 == ~E_3~0); 12606#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12812#L919-1 assume !(0 == ~E_5~0); 12511#L924-1 assume !(0 == ~E_6~0); 12325#L929-1 assume !(0 == ~E_7~0); 12326#L934-1 assume !(0 == ~E_8~0); 12584#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12112#L418 assume !(1 == ~m_pc~0); 12087#L418-2 is_master_triggered_~__retres1~0#1 := 0; 12086#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12967#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12900#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12901#L437 assume 1 == ~t1_pc~0; 13069#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12974#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12136#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12461#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12957#L456 assume !(1 == ~t2_pc~0); 12383#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12382#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12544#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12716#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12226#L475 assume 1 == ~t3_pc~0; 12227#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12290#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12104#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12464#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12465#L494 assume !(1 == ~t4_pc~0); 12505#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12506#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12243#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12836#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12285#L513 assume 1 == ~t5_pc~0; 12286#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12507#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12983#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12239#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12240#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12192#L532 assume !(1 == ~t6_pc~0); 12193#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12344#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12525#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12526#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12436#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12437#L551 assume 1 == ~t7_pc~0; 12994#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12838#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12839#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13078#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 13079#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12626#L570 assume 1 == ~t8_pc~0; 12627#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12742#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12932#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12220#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12221#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12161#L952-2 assume !(1 == ~T1_E~0); 12162#L957-1 assume !(1 == ~T2_E~0); 12938#L962-1 assume !(1 == ~T3_E~0); 12754#L967-1 assume !(1 == ~T4_E~0); 12755#L972-1 assume !(1 == ~T5_E~0); 12997#L977-1 assume !(1 == ~T6_E~0); 12998#L982-1 assume !(1 == ~T7_E~0); 12346#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12347#L992-1 assume !(1 == ~E_M~0); 12354#L997-1 assume !(1 == ~E_1~0); 12714#L1002-1 assume !(1 == ~E_2~0); 12699#L1007-1 assume !(1 == ~E_3~0); 12097#L1012-1 assume !(1 == ~E_4~0); 12098#L1017-1 assume !(1 == ~E_5~0); 12702#L1022-1 assume !(1 == ~E_6~0); 12703#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12728#L1032-1 assume !(1 == ~E_8~0); 12859#L1037-1 assume { :end_inline_reset_delta_events } true; 12860#L1303-2 [2024-11-13 16:13:52,408 INFO L747 eck$LassoCheckResult]: Loop: 12860#L1303-2 assume !false; 12934#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12602#L829-1 assume !false; 12897#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12487#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12422#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12565#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12566#L712 assume !(0 != eval_~tmp~0#1); 12827#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12737#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12828#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12829#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13077#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13051#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12644#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12645#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12715#L884-3 assume !(0 == ~T7_E~0); 12693#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12316#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12317#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12350#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12351#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12295#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12296#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12339#L924-3 assume !(0 == ~E_6~0); 12903#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12814#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12815#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12922#L418-30 assume 1 == ~m_pc~0; 12179#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12180#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12556#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12557#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12384#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12385#L437-30 assume !(1 == ~t1_pc~0); 12508#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 12734#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12735#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12772#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13068#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12468#L456-30 assume 1 == ~t2_pc~0; 12469#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12895#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12273#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12274#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12616#L475-30 assume 1 == ~t3_pc~0; 12990#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12144#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12752#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12753#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12491#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12492#L494-30 assume 1 == ~t4_pc~0; 12482#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12083#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12084#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13056#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 13006#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L513-30 assume 1 == ~t5_pc~0; 13080#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12622#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12848#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12914#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12634#L532-30 assume !(1 == ~t6_pc~0); 12635#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 12224#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12249#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12305#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12306#L551-30 assume 1 == ~t7_pc~0; 12358#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12424#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12904#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12099#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12100#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12466#L570-30 assume !(1 == ~t8_pc~0); 12820#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 12355#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12356#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12157#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12158#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12537#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12581#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13032#L957-3 assume !(1 == ~T2_E~0); 13033#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12955#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12956#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12875#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12876#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13081#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12523#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12524#L997-3 assume !(1 == ~E_1~0); 12519#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12520#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12329#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12330#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12431#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12667#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12127#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12128#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12373#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12374#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12490#L1322 assume !(0 == start_simulation_~tmp~3#1); 12551#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12214#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12215#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12113#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12114#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12750#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12751#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12860#L1303-2 [2024-11-13 16:13:52,408 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,409 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2024-11-13 16:13:52,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768551082] [2024-11-13 16:13:52,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768551082] [2024-11-13 16:13:52,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768551082] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80288911] [2024-11-13 16:13:52,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,482 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:52,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,483 INFO L85 PathProgramCache]: Analyzing trace with hash 1902590960, now seen corresponding path program 2 times [2024-11-13 16:13:52,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117577915] [2024-11-13 16:13:52,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117577915] [2024-11-13 16:13:52,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117577915] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50585067] [2024-11-13 16:13:52,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,592 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:52,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:52,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:52,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:52,593 INFO L87 Difference]: Start difference. First operand 1002 states and 1485 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:52,639 INFO L93 Difference]: Finished difference Result 1002 states and 1484 transitions. [2024-11-13 16:13:52,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1484 transitions. [2024-11-13 16:13:52,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1484 transitions. [2024-11-13 16:13:52,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:52,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:52,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1484 transitions. [2024-11-13 16:13:52,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:52,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-11-13 16:13:52,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1484 transitions. [2024-11-13 16:13:52,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:52,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4810379241516967) internal successors, (1484), 1001 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1484 transitions. [2024-11-13 16:13:52,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-11-13 16:13:52,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:52,708 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2024-11-13 16:13:52,708 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 16:13:52,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1484 transitions. [2024-11-13 16:13:52,718 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:52,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:52,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:52,722 INFO L745 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15039#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14832#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14833#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14430#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14431#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14363#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14364#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14626#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14598#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14599#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14882#L854 assume !(0 == ~M_E~0); 14689#L854-2 assume !(0 == ~T1_E~0); 14690#L859-1 assume !(0 == ~T2_E~0); 14243#L864-1 assume !(0 == ~T3_E~0); 14244#L869-1 assume !(0 == ~T4_E~0); 14354#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15063#L879-1 assume !(0 == ~T6_E~0); 14679#L884-1 assume !(0 == ~T7_E~0); 14106#L889-1 assume !(0 == ~T8_E~0); 14107#L894-1 assume !(0 == ~E_M~0); 14443#L899-1 assume !(0 == ~E_1~0); 14888#L904-1 assume !(0 == ~E_2~0); 14616#L909-1 assume !(0 == ~E_3~0); 14617#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14823#L919-1 assume !(0 == ~E_5~0); 14522#L924-1 assume !(0 == ~E_6~0); 14336#L929-1 assume !(0 == ~E_7~0); 14337#L934-1 assume !(0 == ~E_8~0); 14595#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14123#L418 assume !(1 == ~m_pc~0); 14098#L418-2 is_master_triggered_~__retres1~0#1 := 0; 14097#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14992#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14978#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14911#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14912#L437 assume 1 == ~t1_pc~0; 15080#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14985#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14147#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14472#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14968#L456 assume !(1 == ~t2_pc~0); 14394#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14393#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14555#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14727#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14237#L475 assume 1 == ~t3_pc~0; 14238#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14301#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14115#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14475#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14476#L494 assume !(1 == ~t4_pc~0); 14516#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14517#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14253#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14254#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14847#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14296#L513 assume 1 == ~t5_pc~0; 14297#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14518#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14250#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14251#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14203#L532 assume !(1 == ~t6_pc~0); 14204#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14355#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14537#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14447#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14448#L551 assume 1 == ~t7_pc~0; 15005#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14849#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15089#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 15090#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14637#L570 assume 1 == ~t8_pc~0; 14638#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14753#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14749#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14231#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14172#L952-2 assume !(1 == ~T1_E~0); 14173#L957-1 assume !(1 == ~T2_E~0); 14949#L962-1 assume !(1 == ~T3_E~0); 14765#L967-1 assume !(1 == ~T4_E~0); 14766#L972-1 assume !(1 == ~T5_E~0); 15008#L977-1 assume !(1 == ~T6_E~0); 15009#L982-1 assume !(1 == ~T7_E~0); 14357#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14358#L992-1 assume !(1 == ~E_M~0); 14365#L997-1 assume !(1 == ~E_1~0); 14725#L1002-1 assume !(1 == ~E_2~0); 14710#L1007-1 assume !(1 == ~E_3~0); 14108#L1012-1 assume !(1 == ~E_4~0); 14109#L1017-1 assume !(1 == ~E_5~0); 14713#L1022-1 assume !(1 == ~E_6~0); 14714#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14739#L1032-1 assume !(1 == ~E_8~0); 14870#L1037-1 assume { :end_inline_reset_delta_events } true; 14871#L1303-2 [2024-11-13 16:13:52,723 INFO L747 eck$LassoCheckResult]: Loop: 14871#L1303-2 assume !false; 14945#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14613#L829-1 assume !false; 14908#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14498#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14433#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14577#L712 assume !(0 != eval_~tmp~0#1); 14838#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14748#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14839#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14840#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15088#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15062#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14655#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14656#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14726#L884-3 assume !(0 == ~T7_E~0); 14704#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14327#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14328#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14361#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14362#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14306#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14307#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14350#L924-3 assume !(0 == ~E_6~0); 14914#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14825#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14826#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14933#L418-30 assume !(1 == ~m_pc~0); 14192#L418-32 is_master_triggered_~__retres1~0#1 := 0; 14191#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14567#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14568#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14395#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14396#L437-30 assume !(1 == ~t1_pc~0); 14519#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 14745#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15079#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14479#L456-30 assume 1 == ~t2_pc~0; 14480#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14906#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14478#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14284#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14285#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14627#L475-30 assume 1 == ~t3_pc~0; 15001#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14155#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14763#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14764#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14502#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14503#L494-30 assume !(1 == ~t4_pc~0); 14311#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14094#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14095#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15067#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 15017#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15018#L513-30 assume 1 == ~t5_pc~0; 15091#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14633#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14702#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14859#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14925#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14645#L532-30 assume !(1 == ~t6_pc~0); 14646#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14235#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14236#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14260#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14317#L551-30 assume 1 == ~t7_pc~0; 14369#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14435#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14915#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14110#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14111#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14477#L570-30 assume 1 == ~t8_pc~0; 14986#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14367#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14169#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14548#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14592#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15043#L957-3 assume !(1 == ~T2_E~0); 15044#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14966#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14967#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14886#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14887#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15092#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14534#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14535#L997-3 assume !(1 == ~E_1~0); 14530#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14531#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14340#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14341#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14442#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14678#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14138#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14139#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14384#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14385#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14500#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14501#L1322 assume !(0 == start_simulation_~tmp~3#1); 14562#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14225#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14226#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14142#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14124#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14125#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14761#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14762#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14871#L1303-2 [2024-11-13 16:13:52,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,724 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2024-11-13 16:13:52,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692464585] [2024-11-13 16:13:52,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692464585] [2024-11-13 16:13:52,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692464585] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591455054] [2024-11-13 16:13:52,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,806 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:52,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:52,807 INFO L85 PathProgramCache]: Analyzing trace with hash 588676529, now seen corresponding path program 1 times [2024-11-13 16:13:52,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:52,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774763757] [2024-11-13 16:13:52,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:52,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:52,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:52,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:52,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:52,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774763757] [2024-11-13 16:13:52,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774763757] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:52,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:52,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:52,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327332728] [2024-11-13 16:13:52,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:52,895 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:52,896 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:52,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:52,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:52,896 INFO L87 Difference]: Start difference. First operand 1002 states and 1484 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:52,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:52,932 INFO L93 Difference]: Finished difference Result 1002 states and 1483 transitions. [2024-11-13 16:13:52,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1483 transitions. [2024-11-13 16:13:52,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:52,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1483 transitions. [2024-11-13 16:13:52,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2024-11-13 16:13:52,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2024-11-13 16:13:52,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1483 transitions. [2024-11-13 16:13:52,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:52,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-11-13 16:13:52,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1483 transitions. [2024-11-13 16:13:53,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2024-11-13 16:13:53,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4800399201596806) internal successors, (1483), 1001 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:53,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1483 transitions. [2024-11-13 16:13:53,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-11-13 16:13:53,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:53,011 INFO L424 stractBuchiCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2024-11-13 16:13:53,011 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 16:13:53,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1483 transitions. [2024-11-13 16:13:53,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2024-11-13 16:13:53,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:53,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:53,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:53,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:53,023 INFO L745 eck$LassoCheckResult]: Stem: 16424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17088#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16843#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16844#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16441#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16442#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16374#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16375#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16637#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16609#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16610#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16893#L854 assume !(0 == ~M_E~0); 16700#L854-2 assume !(0 == ~T1_E~0); 16701#L859-1 assume !(0 == ~T2_E~0); 16254#L864-1 assume !(0 == ~T3_E~0); 16255#L869-1 assume !(0 == ~T4_E~0); 16365#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17074#L879-1 assume !(0 == ~T6_E~0); 16690#L884-1 assume !(0 == ~T7_E~0); 16117#L889-1 assume !(0 == ~T8_E~0); 16118#L894-1 assume !(0 == ~E_M~0); 16454#L899-1 assume !(0 == ~E_1~0); 16899#L904-1 assume !(0 == ~E_2~0); 16627#L909-1 assume !(0 == ~E_3~0); 16628#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16834#L919-1 assume !(0 == ~E_5~0); 16533#L924-1 assume !(0 == ~E_6~0); 16347#L929-1 assume !(0 == ~E_7~0); 16348#L934-1 assume !(0 == ~E_8~0); 16606#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16134#L418 assume !(1 == ~m_pc~0); 16109#L418-2 is_master_triggered_~__retres1~0#1 := 0; 16108#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16989#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16922#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16923#L437 assume 1 == ~t1_pc~0; 17091#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16996#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16158#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16483#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16979#L456 assume !(1 == ~t2_pc~0); 16405#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16404#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16566#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16738#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16248#L475 assume 1 == ~t3_pc~0; 16249#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16126#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16486#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16487#L494 assume !(1 == ~t4_pc~0); 16527#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16528#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16265#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16858#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16307#L513 assume 1 == ~t5_pc~0; 16308#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16261#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16262#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16214#L532 assume !(1 == ~t6_pc~0); 16215#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16366#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16548#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16458#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16459#L551 assume 1 == ~t7_pc~0; 17016#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16860#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16861#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17100#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 17101#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16648#L570 assume 1 == ~t8_pc~0; 16649#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16764#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16954#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16760#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16242#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16243#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16183#L952-2 assume !(1 == ~T1_E~0); 16184#L957-1 assume !(1 == ~T2_E~0); 16960#L962-1 assume !(1 == ~T3_E~0); 16776#L967-1 assume !(1 == ~T4_E~0); 16777#L972-1 assume !(1 == ~T5_E~0); 17019#L977-1 assume !(1 == ~T6_E~0); 17020#L982-1 assume !(1 == ~T7_E~0); 16368#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16369#L992-1 assume !(1 == ~E_M~0); 16376#L997-1 assume !(1 == ~E_1~0); 16736#L1002-1 assume !(1 == ~E_2~0); 16721#L1007-1 assume !(1 == ~E_3~0); 16119#L1012-1 assume !(1 == ~E_4~0); 16120#L1017-1 assume !(1 == ~E_5~0); 16724#L1022-1 assume !(1 == ~E_6~0); 16725#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16750#L1032-1 assume !(1 == ~E_8~0); 16881#L1037-1 assume { :end_inline_reset_delta_events } true; 16882#L1303-2 [2024-11-13 16:13:53,023 INFO L747 eck$LassoCheckResult]: Loop: 16882#L1303-2 assume !false; 16956#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16624#L829-1 assume !false; 16919#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16509#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16444#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16587#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16588#L712 assume !(0 != eval_~tmp~0#1); 16849#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16758#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16759#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16850#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16851#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17099#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17073#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16666#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16667#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16737#L884-3 assume !(0 == ~T7_E~0); 16715#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16338#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16339#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16372#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16373#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16317#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16318#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16361#L924-3 assume !(0 == ~E_6~0); 16925#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16836#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16837#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16944#L418-30 assume 1 == ~m_pc~0; 16201#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16202#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16578#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16579#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16406#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16407#L437-30 assume !(1 == ~t1_pc~0); 16530#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 16756#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16757#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16794#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17090#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16490#L456-30 assume 1 == ~t2_pc~0; 16491#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16917#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16489#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16295#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16296#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16638#L475-30 assume 1 == ~t3_pc~0; 17012#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16166#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16774#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16775#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16513#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16514#L494-30 assume !(1 == ~t4_pc~0); 16322#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16105#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16106#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17078#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 17028#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17029#L513-30 assume !(1 == ~t5_pc~0); 16643#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16644#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16713#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16870#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16936#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16656#L532-30 assume !(1 == ~t6_pc~0); 16657#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16246#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16247#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16271#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16327#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16328#L551-30 assume 1 == ~t7_pc~0; 16380#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16446#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16926#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16121#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16122#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16488#L570-30 assume 1 == ~t8_pc~0; 16997#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16377#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16378#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16179#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16180#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16559#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16603#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17054#L957-3 assume !(1 == ~T2_E~0); 17055#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16977#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16978#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16897#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16898#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17103#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16545#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16546#L997-3 assume !(1 == ~E_1~0); 16541#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16542#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16351#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16352#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16453#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16689#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16149#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16150#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16395#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16396#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16512#L1322 assume !(0 == start_simulation_~tmp~3#1); 16573#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16236#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16237#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 16135#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16136#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16772#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16773#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1303-2 [2024-11-13 16:13:53,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:53,024 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2024-11-13 16:13:53,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:53,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643764878] [2024-11-13 16:13:53,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:53,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:53,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:53,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:53,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:53,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643764878] [2024-11-13 16:13:53,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643764878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:53,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:53,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:53,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48422417] [2024-11-13 16:13:53,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:53,145 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:53,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:53,146 INFO L85 PathProgramCache]: Analyzing trace with hash 697734513, now seen corresponding path program 2 times [2024-11-13 16:13:53,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:53,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567776188] [2024-11-13 16:13:53,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:53,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:53,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:53,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:53,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:53,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567776188] [2024-11-13 16:13:53,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1567776188] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:53,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:53,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:53,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719124729] [2024-11-13 16:13:53,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:53,211 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:53,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:53,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:13:53,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:13:53,212 INFO L87 Difference]: Start difference. First operand 1002 states and 1483 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:53,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:53,385 INFO L93 Difference]: Finished difference Result 1824 states and 2689 transitions. [2024-11-13 16:13:53,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1824 states and 2689 transitions. [2024-11-13 16:13:53,400 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2024-11-13 16:13:53,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1824 states to 1824 states and 2689 transitions. [2024-11-13 16:13:53,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1824 [2024-11-13 16:13:53,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1824 [2024-11-13 16:13:53,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1824 states and 2689 transitions. [2024-11-13 16:13:53,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:53,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-11-13 16:13:53,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states and 2689 transitions. [2024-11-13 16:13:53,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1824. [2024-11-13 16:13:53,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.4742324561403508) internal successors, (2689), 1823 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:53,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2689 transitions. [2024-11-13 16:13:53,466 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-11-13 16:13:53,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:13:53,468 INFO L424 stractBuchiCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2024-11-13 16:13:53,469 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 16:13:53,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2689 transitions. [2024-11-13 16:13:53,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2024-11-13 16:13:53,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:53,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:53,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:53,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:53,481 INFO L745 eck$LassoCheckResult]: Stem: 19264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19925#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19926#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19976#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19688#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19689#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19281#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19282#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19212#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19213#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19480#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19452#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19453#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19743#L854 assume !(0 == ~M_E~0); 19544#L854-2 assume !(0 == ~T1_E~0); 19545#L859-1 assume !(0 == ~T2_E~0); 19091#L864-1 assume !(0 == ~T3_E~0); 19092#L869-1 assume !(0 == ~T4_E~0); 19203#L874-1 assume !(0 == ~T5_E~0); 19960#L879-1 assume !(0 == ~T6_E~0); 19534#L884-1 assume !(0 == ~T7_E~0); 18953#L889-1 assume !(0 == ~T8_E~0); 18954#L894-1 assume !(0 == ~E_M~0); 19294#L899-1 assume !(0 == ~E_1~0); 19749#L904-1 assume !(0 == ~E_2~0); 19470#L909-1 assume !(0 == ~E_3~0); 19471#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19679#L919-1 assume !(0 == ~E_5~0); 19373#L924-1 assume !(0 == ~E_6~0); 19185#L929-1 assume !(0 == ~E_7~0); 19186#L934-1 assume !(0 == ~E_8~0); 19449#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18970#L418 assume !(1 == ~m_pc~0); 18945#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18944#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19869#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19853#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19776#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19777#L437 assume 1 == ~t1_pc~0; 19982#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19861#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18994#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18995#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19323#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19843#L456 assume !(1 == ~t2_pc~0); 19245#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19244#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19406#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19407#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19583#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19085#L475 assume 1 == ~t3_pc~0; 19086#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19150#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18962#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19326#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19327#L494 assume !(1 == ~t4_pc~0); 19367#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19368#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19101#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19102#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19704#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19144#L513 assume 1 == ~t5_pc~0; 19145#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19369#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19871#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19098#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 19099#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19051#L532 assume !(1 == ~t6_pc~0); 19052#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19204#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19387#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19388#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19298#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19299#L551 assume 1 == ~t7_pc~0; 19883#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19707#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19708#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19994#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19491#L570 assume 1 == ~t8_pc~0; 19492#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19609#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19811#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19605#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 19079#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19080#L952 assume !(1 == ~M_E~0); 19020#L952-2 assume !(1 == ~T1_E~0); 19021#L957-1 assume !(1 == ~T2_E~0); 20063#L962-1 assume !(1 == ~T3_E~0); 20061#L967-1 assume !(1 == ~T4_E~0); 20060#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19886#L977-1 assume !(1 == ~T6_E~0); 19887#L982-1 assume !(1 == ~T7_E~0); 19206#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19207#L992-1 assume !(1 == ~E_M~0); 19214#L997-1 assume !(1 == ~E_1~0); 19581#L1002-1 assume !(1 == ~E_2~0); 20049#L1007-1 assume !(1 == ~E_3~0); 20048#L1012-1 assume !(1 == ~E_4~0); 20047#L1017-1 assume !(1 == ~E_5~0); 20046#L1022-1 assume !(1 == ~E_6~0); 20023#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 20022#L1032-1 assume !(1 == ~E_8~0); 20021#L1037-1 assume { :end_inline_reset_delta_events } true; 19813#L1303-2 [2024-11-13 16:13:53,482 INFO L747 eck$LassoCheckResult]: Loop: 19813#L1303-2 assume !false; 19814#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20015#L829-1 assume !false; 20014#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20007#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19888#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19889#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20003#L712 assume !(0 != eval_~tmp~0#1); 19815#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19603#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19604#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20001#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20748#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20747#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20746#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20745#L874-3 assume !(0 == ~T5_E~0); 20744#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20743#L884-3 assume !(0 == ~T7_E~0); 20742#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20741#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20740#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20739#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20738#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20737#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20736#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20735#L924-3 assume !(0 == ~E_6~0); 20734#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20733#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20732#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20731#L418-30 assume 1 == ~m_pc~0; 20729#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20728#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20727#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20726#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20725#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20724#L437-30 assume !(1 == ~t1_pc~0); 20722#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20721#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20720#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20719#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20718#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20717#L456-30 assume 1 == ~t2_pc~0; 20715#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20714#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20713#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20712#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20711#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20710#L475-30 assume !(1 == ~t3_pc~0); 20708#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 20707#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20706#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20705#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20704#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20703#L494-30 assume 1 == ~t4_pc~0; 19344#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18941#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18942#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19965#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 19903#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19904#L513-30 assume 1 == ~t5_pc~0; 19996#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19487#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19558#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19717#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19791#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19499#L532-30 assume !(1 == ~t6_pc~0); 19500#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 19083#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19084#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19108#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19165#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19166#L551-30 assume 1 == ~t7_pc~0; 19220#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19286#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19780#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18957#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18958#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19328#L570-30 assume !(1 == ~t8_pc~0); 19938#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 20664#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20644#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20643#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20642#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20641#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19445#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20172#L957-3 assume !(1 == ~T2_E~0); 20171#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20169#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20167#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19956#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20163#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20161#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20159#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20157#L997-3 assume !(1 == ~E_1~0); 20155#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20152#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20150#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20148#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20146#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20144#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20143#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20142#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20129#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20128#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20127#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20126#L1322 assume !(0 == start_simulation_~tmp~3#1); 19765#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19073#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19074#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 18971#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18972#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19617#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19618#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19813#L1303-2 [2024-11-13 16:13:53,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:53,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2024-11-13 16:13:53,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:53,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640323044] [2024-11-13 16:13:53,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:53,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:53,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:53,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:53,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:53,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640323044] [2024-11-13 16:13:53,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640323044] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:53,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:53,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:53,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378075051] [2024-11-13 16:13:53,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:53,622 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:53,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:53,623 INFO L85 PathProgramCache]: Analyzing trace with hash 776158835, now seen corresponding path program 1 times [2024-11-13 16:13:53,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:53,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101575834] [2024-11-13 16:13:53,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:53,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:53,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:53,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:53,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:53,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101575834] [2024-11-13 16:13:53,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101575834] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:53,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:53,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:53,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467668609] [2024-11-13 16:13:53,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:53,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:53,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:53,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:13:53,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:13:53,698 INFO L87 Difference]: Start difference. First operand 1824 states and 2689 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:53,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:53,947 INFO L93 Difference]: Finished difference Result 3322 states and 4884 transitions. [2024-11-13 16:13:53,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3322 states and 4884 transitions. [2024-11-13 16:13:53,970 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2024-11-13 16:13:53,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3322 states to 3322 states and 4884 transitions. [2024-11-13 16:13:53,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3322 [2024-11-13 16:13:53,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3322 [2024-11-13 16:13:53,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3322 states and 4884 transitions. [2024-11-13 16:13:54,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:54,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3322 states and 4884 transitions. [2024-11-13 16:13:54,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states and 4884 transitions. [2024-11-13 16:13:54,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3320. [2024-11-13 16:13:54,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3320 states, 3320 states have (on average 1.4704819277108434) internal successors, (4882), 3319 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:54,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3320 states to 3320 states and 4882 transitions. [2024-11-13 16:13:54,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2024-11-13 16:13:54,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:13:54,090 INFO L424 stractBuchiCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2024-11-13 16:13:54,090 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 16:13:54,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3320 states and 4882 transitions. [2024-11-13 16:13:54,109 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2024-11-13 16:13:54,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:54,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:54,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:54,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:54,112 INFO L745 eck$LassoCheckResult]: Stem: 24426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25193#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24874#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24875#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24443#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24444#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24373#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24374#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24653#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24624#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24625#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24932#L854 assume !(0 == ~M_E~0); 24723#L854-2 assume !(0 == ~T1_E~0); 24724#L859-1 assume !(0 == ~T2_E~0); 24248#L864-1 assume !(0 == ~T3_E~0); 24249#L869-1 assume !(0 == ~T4_E~0); 24364#L874-1 assume !(0 == ~T5_E~0); 25170#L879-1 assume !(0 == ~T6_E~0); 24713#L884-1 assume !(0 == ~T7_E~0); 24109#L889-1 assume !(0 == ~T8_E~0); 24110#L894-1 assume !(0 == ~E_M~0); 24458#L899-1 assume !(0 == ~E_1~0); 24938#L904-1 assume !(0 == ~E_2~0); 24643#L909-1 assume !(0 == ~E_3~0); 24644#L914-1 assume !(0 == ~E_4~0); 24865#L919-1 assume !(0 == ~E_5~0); 24544#L924-1 assume !(0 == ~E_6~0); 24345#L929-1 assume !(0 == ~E_7~0); 24346#L934-1 assume !(0 == ~E_8~0); 24621#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24127#L418 assume !(1 == ~m_pc~0); 24101#L418-2 is_master_triggered_~__retres1~0#1 := 0; 24100#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25070#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25053#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24965#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24966#L437 assume 1 == ~t1_pc~0; 25204#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25061#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24491#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25041#L456 assume !(1 == ~t2_pc~0); 24407#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24406#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24580#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24581#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24762#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24242#L475 assume 1 == ~t3_pc~0; 24243#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24310#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24119#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24494#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24495#L494 assume !(1 == ~t4_pc~0); 24538#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24539#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24259#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24260#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24893#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24304#L513 assume 1 == ~t5_pc~0; 24305#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24540#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25072#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24255#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24256#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24208#L532 assume !(1 == ~t6_pc~0); 24209#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24365#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24560#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24561#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24464#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24465#L551 assume 1 == ~t7_pc~0; 25087#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24896#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24897#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25224#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 25228#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24667#L570 assume 1 == ~t8_pc~0; 24668#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24789#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25010#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24785#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24236#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24237#L952 assume !(1 == ~M_E~0); 25065#L952-2 assume !(1 == ~T1_E~0); 25018#L957-1 assume !(1 == ~T2_E~0); 25019#L962-1 assume !(1 == ~T3_E~0); 25398#L967-1 assume !(1 == ~T4_E~0); 25396#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25090#L977-1 assume !(1 == ~T6_E~0); 25091#L982-1 assume !(1 == ~T7_E~0); 25385#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25383#L992-1 assume !(1 == ~E_M~0); 25379#L997-1 assume !(1 == ~E_1~0); 25171#L1002-1 assume !(1 == ~E_2~0); 25172#L1007-1 assume !(1 == ~E_3~0); 25330#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25328#L1017-1 assume !(1 == ~E_5~0); 25308#L1022-1 assume !(1 == ~E_6~0); 25291#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25282#L1032-1 assume !(1 == ~E_8~0); 25274#L1037-1 assume { :end_inline_reset_delta_events } true; 25267#L1303-2 [2024-11-13 16:13:54,113 INFO L747 eck$LassoCheckResult]: Loop: 25267#L1303-2 assume !false; 25263#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25262#L829-1 assume !false; 25261#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25254#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25251#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25250#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25248#L712 assume !(0 != eval_~tmp~0#1); 25247#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25246#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25244#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25245#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26096#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26095#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26093#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26091#L874-3 assume !(0 == ~T5_E~0); 26089#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26087#L884-3 assume !(0 == ~T7_E~0); 26085#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26083#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26081#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26079#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24711#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24315#L914-3 assume !(0 == ~E_4~0); 24316#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24360#L924-3 assume !(0 == ~E_6~0); 24968#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24867#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24868#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24992#L418-30 assume 1 == ~m_pc~0; 24195#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24196#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24593#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24594#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24408#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24409#L437-30 assume !(1 == ~t1_pc~0); 24541#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 24781#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24782#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26725#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26724#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26723#L456-30 assume 1 == ~t2_pc~0; 25116#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25117#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26722#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24292#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24293#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26721#L475-30 assume 1 == ~t3_pc~0; 26720#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24883#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24799#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24800#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24524#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24525#L494-30 assume !(1 == ~t4_pc~0); 24320#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 24097#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24098#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25176#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 25217#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26324#L513-30 assume 1 == ~t5_pc~0; 26321#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26319#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26317#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26315#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26313#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26310#L532-30 assume !(1 == ~t6_pc~0); 26306#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 26304#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26302#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26300#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26297#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26295#L551-30 assume 1 == ~t7_pc~0; 26292#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26290#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26288#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26286#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26172#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26168#L570-30 assume !(1 == ~t8_pc~0); 26165#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26154#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26153#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26149#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24573#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24574#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24618#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25137#L957-3 assume !(1 == ~T2_E~0); 25138#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25039#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25040#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24936#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24937#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25237#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24558#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24559#L997-3 assume !(1 == ~E_1~0); 24554#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24555#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24895#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25773#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25772#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25410#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25408#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25405#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25370#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25369#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25368#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25367#L1322 assume !(0 == start_simulation_~tmp~3#1); 24955#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25339#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25329#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25327#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25307#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25290#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25281#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25273#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25267#L1303-2 [2024-11-13 16:13:54,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:54,113 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2024-11-13 16:13:54,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:54,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014942070] [2024-11-13 16:13:54,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:54,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:54,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:54,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:54,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:54,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014942070] [2024-11-13 16:13:54,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014942070] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:54,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:54,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:13:54,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815365150] [2024-11-13 16:13:54,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:54,230 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:54,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:54,230 INFO L85 PathProgramCache]: Analyzing trace with hash 2021582005, now seen corresponding path program 1 times [2024-11-13 16:13:54,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:54,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329041075] [2024-11-13 16:13:54,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:54,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:54,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:54,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:54,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:54,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329041075] [2024-11-13 16:13:54,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329041075] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:54,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:54,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:54,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321264115] [2024-11-13 16:13:54,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:54,348 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:54,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:54,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 16:13:54,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 16:13:54,349 INFO L87 Difference]: Start difference. First operand 3320 states and 4882 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:54,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:54,812 INFO L93 Difference]: Finished difference Result 3440 states and 5002 transitions. [2024-11-13 16:13:54,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3440 states and 5002 transitions. [2024-11-13 16:13:54,843 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2024-11-13 16:13:54,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3440 states to 3440 states and 5002 transitions. [2024-11-13 16:13:54,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3440 [2024-11-13 16:13:54,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3440 [2024-11-13 16:13:54,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3440 states and 5002 transitions. [2024-11-13 16:13:54,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:54,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-11-13 16:13:54,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3440 states and 5002 transitions. [2024-11-13 16:13:54,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3440 to 3440. [2024-11-13 16:13:54,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3440 states, 3440 states have (on average 1.4540697674418606) internal successors, (5002), 3439 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:54,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3440 states to 3440 states and 5002 transitions. [2024-11-13 16:13:54,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-11-13 16:13:54,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 16:13:54,984 INFO L424 stractBuchiCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2024-11-13 16:13:54,984 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 16:13:54,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3440 states and 5002 transitions. [2024-11-13 16:13:55,005 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2024-11-13 16:13:55,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:55,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:55,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:55,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:55,009 INFO L745 eck$LassoCheckResult]: Stem: 31187#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 31188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 31855#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31856#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31905#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 31621#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31622#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31204#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31205#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31137#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31138#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31406#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31377#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31378#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31676#L854 assume !(0 == ~M_E~0); 31472#L854-2 assume !(0 == ~T1_E~0); 31473#L859-1 assume !(0 == ~T2_E~0); 31016#L864-1 assume !(0 == ~T3_E~0); 31017#L869-1 assume !(0 == ~T4_E~0); 31128#L874-1 assume !(0 == ~T5_E~0); 31887#L879-1 assume !(0 == ~T6_E~0); 31462#L884-1 assume !(0 == ~T7_E~0); 30878#L889-1 assume !(0 == ~T8_E~0); 30879#L894-1 assume !(0 == ~E_M~0); 31217#L899-1 assume !(0 == ~E_1~0); 31682#L904-1 assume !(0 == ~E_2~0); 31396#L909-1 assume !(0 == ~E_3~0); 31397#L914-1 assume !(0 == ~E_4~0); 31612#L919-1 assume !(0 == ~E_5~0); 31299#L924-1 assume !(0 == ~E_6~0); 31109#L929-1 assume !(0 == ~E_7~0); 31110#L934-1 assume !(0 == ~E_8~0); 31374#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30896#L418 assume !(1 == ~m_pc~0); 30870#L418-2 is_master_triggered_~__retres1~0#1 := 0; 31914#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31938#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31782#L1061 assume !(0 != activate_threads_~tmp~1#1); 31706#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31707#L437 assume 1 == ~t1_pc~0; 31910#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31790#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30920#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 31247#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31771#L456 assume !(1 == ~t2_pc~0); 31168#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31167#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31332#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31333#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 31511#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31010#L475 assume 1 == ~t3_pc~0; 31011#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31074#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30888#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 31250#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31251#L494 assume !(1 == ~t4_pc~0); 31293#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31294#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31026#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31027#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 31637#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31069#L513 assume 1 == ~t5_pc~0; 31070#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31295#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31801#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31023#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 31024#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30976#L532 assume !(1 == ~t6_pc~0); 30977#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31129#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31314#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 31222#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31223#L551 assume 1 == ~t7_pc~0; 31815#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31641#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31642#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31926#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 31929#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31419#L570 assume 1 == ~t8_pc~0; 31420#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31538#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31742#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31534#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 31004#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31005#L952 assume !(1 == ~M_E~0); 30945#L952-2 assume !(1 == ~T1_E~0); 30946#L957-1 assume !(1 == ~T2_E~0); 31750#L962-1 assume !(1 == ~T3_E~0); 31553#L967-1 assume !(1 == ~T4_E~0); 31554#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31906#L977-1 assume !(1 == ~T6_E~0); 31930#L982-1 assume !(1 == ~T7_E~0); 31131#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31132#L992-1 assume !(1 == ~E_M~0); 31139#L997-1 assume !(1 == ~E_1~0); 31509#L1002-1 assume !(1 == ~E_2~0); 31888#L1007-1 assume !(1 == ~E_3~0); 32021#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32019#L1017-1 assume !(1 == ~E_5~0); 32017#L1022-1 assume !(1 == ~E_6~0); 32002#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31993#L1032-1 assume !(1 == ~E_8~0); 31985#L1037-1 assume { :end_inline_reset_delta_events } true; 31978#L1303-2 [2024-11-13 16:13:55,010 INFO L747 eck$LassoCheckResult]: Loop: 31978#L1303-2 assume !false; 31974#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31973#L829-1 assume !false; 31972#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 31965#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 31962#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31961#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31959#L712 assume !(0 != eval_~tmp~0#1); 31958#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31957#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31955#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31956#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32896#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32894#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32891#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32890#L874-3 assume !(0 == ~T5_E~0); 32885#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32884#L884-3 assume !(0 == ~T7_E~0); 32883#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32880#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32879#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32876#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32870#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32871#L914-3 assume !(0 == ~E_4~0); 33266#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33264#L924-3 assume !(0 == ~E_6~0); 33262#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33261#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33260#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33134#L418-30 assume 1 == ~m_pc~0; 33131#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33128#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33126#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33120#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33118#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33116#L437-30 assume !(1 == ~t1_pc~0); 33113#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 33111#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33109#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33107#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33105#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33102#L456-30 assume 1 == ~t2_pc~0; 33099#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33097#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33095#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33093#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33091#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33088#L475-30 assume !(1 == ~t3_pc~0); 33085#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 32791#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32789#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32787#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32785#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32782#L494-30 assume 1 == ~t4_pc~0; 32774#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32769#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32764#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32760#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 32754#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32748#L513-30 assume 1 == ~t5_pc~0; 32739#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32732#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32725#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32718#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32709#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32701#L532-30 assume !(1 == ~t6_pc~0); 32693#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 32686#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32680#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32674#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32667#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32659#L551-30 assume 1 == ~t7_pc~0; 32651#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32644#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32637#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32631#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32616#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32613#L570-30 assume !(1 == ~t8_pc~0); 32610#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 32601#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32599#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32597#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32570#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32568#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31370#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32564#L957-3 assume !(1 == ~T2_E~0); 32562#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32560#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32558#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31882#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32527#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32477#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32439#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32421#L997-3 assume !(1 == ~E_1~0); 32419#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31639#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31640#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32401#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32399#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32397#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32394#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32392#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32088#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32087#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 32082#L1322 assume !(0 == start_simulation_~tmp~3#1); 31696#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32056#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32020#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32018#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 32016#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32001#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31992#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 31984#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 31978#L1303-2 [2024-11-13 16:13:55,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:55,011 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2024-11-13 16:13:55,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:55,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901412832] [2024-11-13 16:13:55,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:55,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:55,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:55,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:55,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:55,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901412832] [2024-11-13 16:13:55,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901412832] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:55,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:55,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 16:13:55,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697011882] [2024-11-13 16:13:55,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:55,113 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:55,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:55,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1164423179, now seen corresponding path program 1 times [2024-11-13 16:13:55,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:55,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136821849] [2024-11-13 16:13:55,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:55,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:55,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:55,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:55,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:55,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136821849] [2024-11-13 16:13:55,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136821849] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:55,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:55,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:55,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769882971] [2024-11-13 16:13:55,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:55,250 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:55,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:55,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:55,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:55,251 INFO L87 Difference]: Start difference. First operand 3440 states and 5002 transitions. cyclomatic complexity: 1566 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:55,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:55,453 INFO L93 Difference]: Finished difference Result 6414 states and 9260 transitions. [2024-11-13 16:13:55,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6414 states and 9260 transitions. [2024-11-13 16:13:55,510 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6253 [2024-11-13 16:13:55,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6414 states to 6414 states and 9260 transitions. [2024-11-13 16:13:55,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6414 [2024-11-13 16:13:55,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6414 [2024-11-13 16:13:55,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6414 states and 9260 transitions. [2024-11-13 16:13:55,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:55,588 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6414 states and 9260 transitions. [2024-11-13 16:13:55,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6414 states and 9260 transitions. [2024-11-13 16:13:55,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6414 to 6406. [2024-11-13 16:13:55,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6406 states, 6406 states have (on average 1.444270995941305) internal successors, (9252), 6405 states have internal predecessors, (9252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:55,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6406 states to 6406 states and 9252 transitions. [2024-11-13 16:13:55,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2024-11-13 16:13:55,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:55,826 INFO L424 stractBuchiCegarLoop]: Abstraction has 6406 states and 9252 transitions. [2024-11-13 16:13:55,827 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 16:13:55,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6406 states and 9252 transitions. [2024-11-13 16:13:55,876 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6245 [2024-11-13 16:13:55,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:55,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:55,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:55,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:55,880 INFO L745 eck$LassoCheckResult]: Stem: 41052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 41053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 41766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41832#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 41495#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41496#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41069#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41070#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40999#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41000#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41275#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41247#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41248#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41553#L854 assume !(0 == ~M_E~0); 41344#L854-2 assume !(0 == ~T1_E~0); 41345#L859-1 assume !(0 == ~T2_E~0); 40877#L864-1 assume !(0 == ~T3_E~0); 40878#L869-1 assume !(0 == ~T4_E~0); 40990#L874-1 assume !(0 == ~T5_E~0); 41809#L879-1 assume !(0 == ~T6_E~0); 41334#L884-1 assume !(0 == ~T7_E~0); 40739#L889-1 assume !(0 == ~T8_E~0); 40740#L894-1 assume !(0 == ~E_M~0); 41083#L899-1 assume !(0 == ~E_1~0); 41559#L904-1 assume !(0 == ~E_2~0); 41265#L909-1 assume !(0 == ~E_3~0); 41266#L914-1 assume !(0 == ~E_4~0); 41485#L919-1 assume !(0 == ~E_5~0); 41167#L924-1 assume !(0 == ~E_6~0); 40972#L929-1 assume !(0 == ~E_7~0); 40973#L934-1 assume !(0 == ~E_8~0); 41244#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40757#L418 assume !(1 == ~m_pc~0); 40731#L418-2 is_master_triggered_~__retres1~0#1 := 0; 41750#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41692#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41677#L1061 assume !(0 != activate_threads_~tmp~1#1); 41585#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41586#L437 assume !(1 == ~t1_pc~0); 41797#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41684#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40780#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40781#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 41114#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41664#L456 assume !(1 == ~t2_pc~0); 41030#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41029#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41201#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41202#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 41383#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40871#L475 assume 1 == ~t3_pc~0; 40872#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40937#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40748#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40749#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 41117#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41118#L494 assume !(1 == ~t4_pc~0); 41162#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41163#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40888#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40889#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 41512#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40931#L513 assume 1 == ~t5_pc~0; 40932#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41164#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41694#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40884#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 40885#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40837#L532 assume !(1 == ~t6_pc~0); 40838#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40991#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41183#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41184#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 41089#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41090#L551 assume 1 == ~t7_pc~0; 41709#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41514#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41515#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41850#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 41855#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41287#L570 assume 1 == ~t8_pc~0; 41288#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41412#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41632#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41407#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 40865#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40866#L952 assume !(1 == ~M_E~0); 41688#L952-2 assume !(1 == ~T1_E~0); 45314#L957-1 assume !(1 == ~T2_E~0); 45312#L962-1 assume !(1 == ~T3_E~0); 41427#L967-1 assume !(1 == ~T4_E~0); 41428#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41713#L977-1 assume !(1 == ~T6_E~0); 41714#L982-1 assume !(1 == ~T7_E~0); 40993#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40994#L992-1 assume !(1 == ~E_M~0); 41001#L997-1 assume !(1 == ~E_1~0); 41381#L1002-1 assume !(1 == ~E_2~0); 41364#L1007-1 assume !(1 == ~E_3~0); 41365#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 44771#L1017-1 assume !(1 == ~E_5~0); 44769#L1022-1 assume !(1 == ~E_6~0); 44767#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44765#L1032-1 assume !(1 == ~E_8~0); 44643#L1037-1 assume { :end_inline_reset_delta_events } true; 44626#L1303-2 [2024-11-13 16:13:55,881 INFO L747 eck$LassoCheckResult]: Loop: 44626#L1303-2 assume !false; 44615#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44614#L829-1 assume !false; 44613#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44603#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44596#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44588#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44583#L712 assume !(0 != eval_~tmp~0#1); 44584#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45877#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45874#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45872#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45870#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45868#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45866#L874-3 assume !(0 == ~T5_E~0); 45864#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45861#L884-3 assume !(0 == ~T7_E~0); 45859#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45857#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45855#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45853#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45851#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45848#L914-3 assume !(0 == ~E_4~0); 45846#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45844#L924-3 assume !(0 == ~E_6~0); 45842#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45840#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45838#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45835#L418-30 assume !(1 == ~m_pc~0); 45831#L418-32 is_master_triggered_~__retres1~0#1 := 0; 45829#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45827#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45825#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 45822#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45820#L437-30 assume !(1 == ~t1_pc~0); 45818#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 45816#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45814#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45813#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45812#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45811#L456-30 assume 1 == ~t2_pc~0; 45809#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45808#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45807#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45806#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45805#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45804#L475-30 assume !(1 == ~t3_pc~0); 45801#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 45799#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45797#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45794#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45792#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45790#L494-30 assume 1 == ~t4_pc~0; 45787#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45785#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45783#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45782#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 45779#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45777#L513-30 assume 1 == ~t5_pc~0; 45774#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45772#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45770#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45768#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45765#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45763#L532-30 assume 1 == ~t6_pc~0; 45760#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45757#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45754#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45752#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45750#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45748#L551-30 assume 1 == ~t7_pc~0; 45745#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45743#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45740#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45738#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45736#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45734#L570-30 assume !(1 == ~t8_pc~0); 45731#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 45729#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45727#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45725#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45723#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45721#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41240#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45719#L957-3 assume !(1 == ~T2_E~0); 45717#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45715#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45713#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45709#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45707#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45705#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45704#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45703#L997-3 assume !(1 == ~E_1~0); 45702#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45701#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45697#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45693#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45691#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45689#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45686#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45684#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 45170#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45166#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45164#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 45162#L1322 assume !(0 == start_simulation_~tmp~3#1); 41575#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44782#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44772#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44770#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 44768#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44766#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44764#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 44642#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 44626#L1303-2 [2024-11-13 16:13:55,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:55,882 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2024-11-13 16:13:55,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:55,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745040834] [2024-11-13 16:13:55,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:55,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:55,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:55,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:55,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:55,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745040834] [2024-11-13 16:13:55,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745040834] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:55,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:55,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 16:13:55,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431834055] [2024-11-13 16:13:55,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:55,996 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:55,996 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:55,997 INFO L85 PathProgramCache]: Analyzing trace with hash -612683913, now seen corresponding path program 1 times [2024-11-13 16:13:55,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:55,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960867415] [2024-11-13 16:13:55,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:55,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:56,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:56,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:56,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:56,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960867415] [2024-11-13 16:13:56,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960867415] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:56,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:56,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:56,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636307902] [2024-11-13 16:13:56,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:56,076 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:56,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:56,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:56,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:56,077 INFO L87 Difference]: Start difference. First operand 6406 states and 9252 transitions. cyclomatic complexity: 2854 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:56,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:56,369 INFO L93 Difference]: Finished difference Result 12302 states and 17640 transitions. [2024-11-13 16:13:56,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12302 states and 17640 transitions. [2024-11-13 16:13:56,457 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12126 [2024-11-13 16:13:56,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12302 states to 12302 states and 17640 transitions. [2024-11-13 16:13:56,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12302 [2024-11-13 16:13:56,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12302 [2024-11-13 16:13:56,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12302 states and 17640 transitions. [2024-11-13 16:13:56,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:56,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12302 states and 17640 transitions. [2024-11-13 16:13:56,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12302 states and 17640 transitions. [2024-11-13 16:13:56,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12302 to 12286. [2024-11-13 16:13:56,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12286 states, 12286 states have (on average 1.434478267947257) internal successors, (17624), 12285 states have internal predecessors, (17624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:56,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12286 states to 12286 states and 17624 transitions. [2024-11-13 16:13:56,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2024-11-13 16:13:56,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:56,918 INFO L424 stractBuchiCegarLoop]: Abstraction has 12286 states and 17624 transitions. [2024-11-13 16:13:56,918 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 16:13:56,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12286 states and 17624 transitions. [2024-11-13 16:13:56,991 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12110 [2024-11-13 16:13:56,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:56,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:56,993 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:56,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:56,994 INFO L745 eck$LassoCheckResult]: Stem: 59763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 59764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 60476#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60477#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60538#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 60205#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60206#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59779#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59780#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59710#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59711#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59981#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59953#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59954#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60265#L854 assume !(0 == ~M_E~0); 60049#L854-2 assume !(0 == ~T1_E~0); 60050#L859-1 assume !(0 == ~T2_E~0); 59590#L864-1 assume !(0 == ~T3_E~0); 59591#L869-1 assume !(0 == ~T4_E~0); 59701#L874-1 assume !(0 == ~T5_E~0); 60514#L879-1 assume !(0 == ~T6_E~0); 60039#L884-1 assume !(0 == ~T7_E~0); 59454#L889-1 assume !(0 == ~T8_E~0); 59455#L894-1 assume !(0 == ~E_M~0); 59792#L899-1 assume !(0 == ~E_1~0); 60272#L904-1 assume !(0 == ~E_2~0); 59971#L909-1 assume !(0 == ~E_3~0); 59972#L914-1 assume !(0 == ~E_4~0); 60193#L919-1 assume !(0 == ~E_5~0); 59874#L924-1 assume !(0 == ~E_6~0); 59682#L929-1 assume !(0 == ~E_7~0); 59683#L934-1 assume !(0 == ~E_8~0); 59950#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59472#L418 assume !(1 == ~m_pc~0); 59446#L418-2 is_master_triggered_~__retres1~0#1 := 0; 60552#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60582#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60388#L1061 assume !(0 != activate_threads_~tmp~1#1); 60298#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60299#L437 assume !(1 == ~t1_pc~0); 60507#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60395#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59495#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59496#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 59823#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60378#L456 assume !(1 == ~t2_pc~0); 59741#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59740#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59906#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59907#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 60087#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59585#L475 assume !(1 == ~t3_pc~0); 59586#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59647#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59464#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 59826#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59827#L494 assume !(1 == ~t4_pc~0); 59869#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59870#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59601#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 60220#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59642#L513 assume 1 == ~t5_pc~0; 59643#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59871#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60409#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59597#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 59598#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59551#L532 assume !(1 == ~t6_pc~0); 59552#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59702#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59888#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59889#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 59796#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59797#L551 assume 1 == ~t7_pc~0; 60427#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60222#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60223#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60568#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 60570#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59993#L570 assume 1 == ~t8_pc~0; 59994#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60117#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60347#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60112#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 59579#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59580#L952 assume !(1 == ~M_E~0); 59520#L952-2 assume !(1 == ~T1_E~0); 59521#L957-1 assume !(1 == ~T2_E~0); 60356#L962-1 assume !(1 == ~T3_E~0); 62337#L967-1 assume !(1 == ~T4_E~0); 62334#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62332#L977-1 assume !(1 == ~T6_E~0); 62272#L982-1 assume !(1 == ~T7_E~0); 62270#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62267#L992-1 assume !(1 == ~E_M~0); 62265#L997-1 assume !(1 == ~E_1~0); 62263#L1002-1 assume !(1 == ~E_2~0); 60069#L1007-1 assume !(1 == ~E_3~0); 60070#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 62158#L1017-1 assume !(1 == ~E_5~0); 62156#L1022-1 assume !(1 == ~E_6~0); 61903#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 61901#L1032-1 assume !(1 == ~E_8~0); 61900#L1037-1 assume { :end_inline_reset_delta_events } true; 61789#L1303-2 [2024-11-13 16:13:57,062 INFO L747 eck$LassoCheckResult]: Loop: 61789#L1303-2 assume !false; 61681#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61680#L829-1 assume !false; 61678#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61658#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 61654#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 61642#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 61633#L712 assume !(0 != eval_~tmp~0#1); 61634#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62853#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62842#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62841#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62840#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62837#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62792#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62758#L874-3 assume !(0 == ~T5_E~0); 62756#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62754#L884-3 assume !(0 == ~T7_E~0); 62752#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62750#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62748#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62744#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62743#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62742#L914-3 assume !(0 == ~E_4~0); 62738#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62737#L924-3 assume !(0 == ~E_6~0); 62736#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62735#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62728#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62726#L418-30 assume !(1 == ~m_pc~0); 62722#L418-32 is_master_triggered_~__retres1~0#1 := 0; 62720#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62717#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62715#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 62712#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62710#L437-30 assume !(1 == ~t1_pc~0); 62708#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 62706#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62704#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62702#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62700#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62697#L456-30 assume 1 == ~t2_pc~0; 62694#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62692#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62690#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62688#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62686#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62684#L475-30 assume !(1 == ~t3_pc~0); 62682#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 62680#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62678#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62676#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62674#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62673#L494-30 assume !(1 == ~t4_pc~0); 62672#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 62668#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62666#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62664#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 62662#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62660#L513-30 assume 1 == ~t5_pc~0; 62657#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62654#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62652#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62650#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62648#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62646#L532-30 assume !(1 == ~t6_pc~0); 62643#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 62642#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62641#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62640#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62638#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62636#L551-30 assume 1 == ~t7_pc~0; 62633#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62631#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62629#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62628#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62627#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62502#L570-30 assume !(1 == ~t8_pc~0); 62498#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 62496#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62494#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62492#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62490#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62488#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62483#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62481#L957-3 assume !(1 == ~T2_E~0); 62479#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62477#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62475#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62471#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62470#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62469#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62468#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62467#L997-3 assume !(1 == ~E_1~0); 62466#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62465#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62419#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62415#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62412#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62410#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62398#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62394#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 62363#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 62361#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 62359#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 62358#L1322 assume !(0 == start_simulation_~tmp~3#1); 62356#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 62354#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 62341#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 62316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 62164#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61904#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61902#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 61899#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 61789#L1303-2 [2024-11-13 16:13:57,063 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:57,063 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2024-11-13 16:13:57,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:57,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497360365] [2024-11-13 16:13:57,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:57,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:57,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:57,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:57,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:57,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497360365] [2024-11-13 16:13:57,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497360365] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:57,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:57,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 16:13:57,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624826400] [2024-11-13 16:13:57,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:57,155 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:57,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:57,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1884051577, now seen corresponding path program 1 times [2024-11-13 16:13:57,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:57,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326880684] [2024-11-13 16:13:57,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:57,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:57,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:57,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:57,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:57,239 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326880684] [2024-11-13 16:13:57,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326880684] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:57,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:57,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:57,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374072724] [2024-11-13 16:13:57,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:57,240 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:57,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:57,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:13:57,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:13:57,242 INFO L87 Difference]: Start difference. First operand 12286 states and 17624 transitions. cyclomatic complexity: 5354 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:57,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:13:57,548 INFO L93 Difference]: Finished difference Result 23203 states and 33115 transitions. [2024-11-13 16:13:57,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23203 states and 33115 transitions. [2024-11-13 16:13:57,720 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22972 [2024-11-13 16:13:57,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23203 states to 23203 states and 33115 transitions. [2024-11-13 16:13:57,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23203 [2024-11-13 16:13:57,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23203 [2024-11-13 16:13:57,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23203 states and 33115 transitions. [2024-11-13 16:13:58,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:13:58,057 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23203 states and 33115 transitions. [2024-11-13 16:13:58,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23203 states and 33115 transitions. [2024-11-13 16:13:58,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23203 to 23171. [2024-11-13 16:13:58,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23171 states, 23171 states have (on average 1.4277760994346382) internal successors, (33083), 23170 states have internal predecessors, (33083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:13:58,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23171 states to 23171 states and 33083 transitions. [2024-11-13 16:13:58,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2024-11-13 16:13:58,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:13:58,766 INFO L424 stractBuchiCegarLoop]: Abstraction has 23171 states and 33083 transitions. [2024-11-13 16:13:58,766 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 16:13:58,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23171 states and 33083 transitions. [2024-11-13 16:13:58,888 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22940 [2024-11-13 16:13:58,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:13:58,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:13:58,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:58,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:13:58,893 INFO L745 eck$LassoCheckResult]: Stem: 95261#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 95262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 96020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96110#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 95724#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95725#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95277#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95278#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95206#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95207#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95484#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95456#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95457#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95790#L854 assume !(0 == ~M_E~0); 95561#L854-2 assume !(0 == ~T1_E~0); 95562#L859-1 assume !(0 == ~T2_E~0); 95085#L864-1 assume !(0 == ~T3_E~0); 95086#L869-1 assume !(0 == ~T4_E~0); 95197#L874-1 assume !(0 == ~T5_E~0); 96081#L879-1 assume !(0 == ~T6_E~0); 95548#L884-1 assume !(0 == ~T7_E~0); 94949#L889-1 assume !(0 == ~T8_E~0); 94950#L894-1 assume !(0 == ~E_M~0); 95292#L899-1 assume !(0 == ~E_1~0); 95796#L904-1 assume !(0 == ~E_2~0); 95473#L909-1 assume !(0 == ~E_3~0); 95474#L914-1 assume !(0 == ~E_4~0); 95713#L919-1 assume !(0 == ~E_5~0); 95376#L924-1 assume !(0 == ~E_6~0); 95179#L929-1 assume !(0 == ~E_7~0); 95180#L934-1 assume !(0 == ~E_8~0); 95453#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94966#L418 assume !(1 == ~m_pc~0); 94941#L418-2 is_master_triggered_~__retres1~0#1 := 0; 96002#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95923#L1061 assume !(0 != activate_threads_~tmp~1#1); 95824#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95825#L437 assume !(1 == ~t1_pc~0); 96065#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95931#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94989#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94990#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 95326#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95911#L456 assume !(1 == ~t2_pc~0); 95240#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95239#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95410#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 95602#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95080#L475 assume !(1 == ~t3_pc~0); 95081#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95142#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94958#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 95329#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95330#L494 assume !(1 == ~t4_pc~0); 95371#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95372#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95095#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95096#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 95740#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95137#L513 assume !(1 == ~t5_pc~0); 95138#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 95373#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95942#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95092#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 95093#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95046#L532 assume !(1 == ~t6_pc~0); 95047#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95198#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95389#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95390#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 95298#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95299#L551 assume 1 == ~t7_pc~0; 95962#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95742#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96139#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 96145#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95500#L570 assume 1 == ~t8_pc~0; 95501#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 95633#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95873#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95628#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 95074#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95075#L952 assume !(1 == ~M_E~0); 95935#L952-2 assume !(1 == ~T1_E~0); 109486#L957-1 assume !(1 == ~T2_E~0); 109485#L962-1 assume !(1 == ~T3_E~0); 109483#L967-1 assume !(1 == ~T4_E~0); 109480#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 109481#L977-1 assume !(1 == ~T6_E~0); 110022#L982-1 assume !(1 == ~T7_E~0); 110020#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 110018#L992-1 assume !(1 == ~E_M~0); 110016#L997-1 assume !(1 == ~E_1~0); 110013#L1002-1 assume !(1 == ~E_2~0); 110011#L1007-1 assume !(1 == ~E_3~0); 110009#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 94952#L1017-1 assume !(1 == ~E_5~0); 95588#L1022-1 assume !(1 == ~E_6~0); 95589#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 96083#L1032-1 assume !(1 == ~E_8~0); 95774#L1037-1 assume { :end_inline_reset_delta_events } true; 95775#L1303-2 [2024-11-13 16:13:58,893 INFO L747 eck$LassoCheckResult]: Loop: 95775#L1303-2 assume !false; 95924#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95470#L829-1 assume !false; 95820#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 95821#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 109697#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 109695#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 109692#L712 assume !(0 != eval_~tmp~0#1); 109693#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116104#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116102#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116101#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 116100#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 116099#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 116098#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116096#L874-3 assume !(0 == ~T5_E~0); 116093#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 116091#L884-3 assume !(0 == ~T7_E~0); 116089#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 116088#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 116085#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 116083#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 116081#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116079#L914-3 assume !(0 == ~E_4~0); 116077#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116075#L924-3 assume !(0 == ~E_6~0); 116073#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116071#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 116069#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116066#L418-30 assume 1 == ~m_pc~0; 116064#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 116065#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116103#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116055#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116053#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116050#L437-30 assume !(1 == ~t1_pc~0); 116048#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 116046#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116044#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116042#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 116040#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116037#L456-30 assume !(1 == ~t2_pc~0); 116035#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 116032#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116030#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116028#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116026#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116024#L475-30 assume !(1 == ~t3_pc~0); 116022#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 116020#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116018#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116016#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116014#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116011#L494-30 assume !(1 == ~t4_pc~0); 116009#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 116006#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116004#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116002#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 116000#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115999#L513-30 assume !(1 == ~t5_pc~0); 115998#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 115996#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115995#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 115994#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 115993#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115992#L532-30 assume !(1 == ~t6_pc~0); 115989#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 115987#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115985#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115983#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 115981#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115978#L551-30 assume 1 == ~t7_pc~0; 115975#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115973#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115971#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 115969#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 115967#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 115966#L570-30 assume 1 == ~t8_pc~0; 115963#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 115960#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115958#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 115956#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115954#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115953#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 108912#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 115949#L957-3 assume !(1 == ~T2_E~0); 115947#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 115945#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 115944#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 115941#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 115937#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 115935#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 115933#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 115931#L997-3 assume !(1 == ~E_1~0); 115928#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 115926#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 115924#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110105#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 115921#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 115919#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 115917#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 115915#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 115848#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 96442#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 96443#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 96436#L1322 assume !(0 == start_simulation_~tmp~3#1); 96437#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 116723#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 116715#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 116714#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 116712#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116401#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116399#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 116396#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 95775#L1303-2 [2024-11-13 16:13:58,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:58,895 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2024-11-13 16:13:58,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:58,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061893167] [2024-11-13 16:13:58,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:58,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:58,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:59,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:59,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:59,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061893167] [2024-11-13 16:13:59,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061893167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:59,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:59,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:59,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489709015] [2024-11-13 16:13:59,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:59,074 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:13:59,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:13:59,074 INFO L85 PathProgramCache]: Analyzing trace with hash -237291593, now seen corresponding path program 1 times [2024-11-13 16:13:59,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:13:59,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251309799] [2024-11-13 16:13:59,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:13:59,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:13:59,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:13:59,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:13:59,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:13:59,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251309799] [2024-11-13 16:13:59,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251309799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:13:59,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:13:59,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:13:59,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362570133] [2024-11-13 16:13:59,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:13:59,181 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:13:59,181 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:13:59,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:13:59,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:13:59,183 INFO L87 Difference]: Start difference. First operand 23171 states and 33083 transitions. cyclomatic complexity: 9944 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:00,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:00,083 INFO L93 Difference]: Finished difference Result 54194 states and 76824 transitions. [2024-11-13 16:14:00,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54194 states and 76824 transitions. [2024-11-13 16:14:00,491 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 53740 [2024-11-13 16:14:01,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54194 states to 54194 states and 76824 transitions. [2024-11-13 16:14:01,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54194 [2024-11-13 16:14:01,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54194 [2024-11-13 16:14:01,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54194 states and 76824 transitions. [2024-11-13 16:14:01,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:01,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54194 states and 76824 transitions. [2024-11-13 16:14:01,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54194 states and 76824 transitions. [2024-11-13 16:14:02,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54194 to 43726. [2024-11-13 16:14:02,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43726 states, 43726 states have (on average 1.4220372318529022) internal successors, (62180), 43725 states have internal predecessors, (62180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:02,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43726 states to 43726 states and 62180 transitions. [2024-11-13 16:14:02,955 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2024-11-13 16:14:02,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:02,960 INFO L424 stractBuchiCegarLoop]: Abstraction has 43726 states and 62180 transitions. [2024-11-13 16:14:02,960 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 16:14:02,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43726 states and 62180 transitions. [2024-11-13 16:14:03,353 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43416 [2024-11-13 16:14:03,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:03,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:03,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:03,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:03,357 INFO L745 eck$LassoCheckResult]: Stem: 172633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 172634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 173377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173447#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 173101#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173102#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172657#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172658#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172585#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 172586#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 172868#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172837#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 172838#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173162#L854 assume !(0 == ~M_E~0); 172941#L854-2 assume !(0 == ~T1_E~0); 172942#L859-1 assume !(0 == ~T2_E~0); 172462#L864-1 assume !(0 == ~T3_E~0); 172463#L869-1 assume !(0 == ~T4_E~0); 172574#L874-1 assume !(0 == ~T5_E~0); 173418#L879-1 assume !(0 == ~T6_E~0); 172926#L884-1 assume !(0 == ~T7_E~0); 172324#L889-1 assume !(0 == ~T8_E~0); 172325#L894-1 assume !(0 == ~E_M~0); 172670#L899-1 assume !(0 == ~E_1~0); 173168#L904-1 assume !(0 == ~E_2~0); 172861#L909-1 assume !(0 == ~E_3~0); 172862#L914-1 assume !(0 == ~E_4~0); 173088#L919-1 assume !(0 == ~E_5~0); 172752#L924-1 assume !(0 == ~E_6~0); 172560#L929-1 assume !(0 == ~E_7~0); 172561#L934-1 assume !(0 == ~E_8~0); 172836#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172342#L418 assume !(1 == ~m_pc~0); 172316#L418-2 is_master_triggered_~__retres1~0#1 := 0; 173461#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173494#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 173283#L1061 assume !(0 != activate_threads_~tmp~1#1); 173192#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173193#L437 assume !(1 == ~t1_pc~0); 173409#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173290#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172367#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 172368#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 172699#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173274#L456 assume !(1 == ~t2_pc~0); 172616#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172615#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172788#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172789#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 172977#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172457#L475 assume !(1 == ~t3_pc~0); 172458#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 172522#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172333#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172334#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 172702#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172703#L494 assume !(1 == ~t4_pc~0); 172746#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 172747#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172472#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172473#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 173118#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172518#L513 assume !(1 == ~t5_pc~0); 172519#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 172751#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173302#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172469#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 172470#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172423#L532 assume !(1 == ~t6_pc~0); 172424#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 172575#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172769#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172770#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 172674#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 172675#L551 assume !(1 == ~t7_pc~0); 173169#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173121#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173122#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173474#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 173478#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172883#L570 assume 1 == ~t8_pc~0; 172884#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173007#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173239#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173005#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 172455#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172456#L952 assume !(1 == ~M_E~0); 173295#L952-2 assume !(1 == ~T1_E~0); 173249#L957-1 assume !(1 == ~T2_E~0); 173250#L962-1 assume !(1 == ~T3_E~0); 173022#L967-1 assume !(1 == ~T4_E~0); 173023#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 186815#L977-1 assume !(1 == ~T6_E~0); 173481#L982-1 assume !(1 == ~T7_E~0); 173482#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 172587#L992-1 assume !(1 == ~E_M~0); 172588#L997-1 assume !(1 == ~E_1~0); 173419#L1002-1 assume !(1 == ~E_2~0); 173420#L1007-1 assume !(1 == ~E_3~0); 172326#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 172327#L1017-1 assume !(1 == ~E_5~0); 172964#L1022-1 assume !(1 == ~E_6~0); 172965#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 190219#L1032-1 assume !(1 == ~E_8~0); 190218#L1037-1 assume { :end_inline_reset_delta_events } true; 190166#L1303-2 [2024-11-13 16:14:03,358 INFO L747 eck$LassoCheckResult]: Loop: 190166#L1303-2 assume !false; 190155#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 190148#L829-1 assume !false; 190144#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 190098#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 190091#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190085#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 189937#L712 assume !(0 != eval_~tmp~0#1); 189938#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 190460#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 190458#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 190456#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 190454#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 190452#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 190450#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190448#L874-3 assume !(0 == ~T5_E~0); 190446#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190444#L884-3 assume !(0 == ~T7_E~0); 190443#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 190442#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 190440#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 190439#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 190438#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 190437#L914-3 assume !(0 == ~E_4~0); 190436#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 190435#L924-3 assume !(0 == ~E_6~0); 190434#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 190432#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 190431#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190430#L418-30 assume !(1 == ~m_pc~0); 190428#L418-32 is_master_triggered_~__retres1~0#1 := 0; 190426#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190424#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190423#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 190421#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190420#L437-30 assume !(1 == ~t1_pc~0); 190419#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 190416#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190414#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190412#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 190408#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190406#L456-30 assume 1 == ~t2_pc~0; 190403#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 190401#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190398#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 190396#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 190394#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190392#L475-30 assume !(1 == ~t3_pc~0); 190390#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 190388#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190386#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190384#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 190382#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190379#L494-30 assume 1 == ~t4_pc~0; 190376#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 190374#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 190372#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190370#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 190368#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190366#L513-30 assume !(1 == ~t5_pc~0); 190364#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 190362#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190360#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190358#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 190356#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190353#L532-30 assume !(1 == ~t6_pc~0); 190350#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 190348#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190346#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 190344#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 190342#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 190340#L551-30 assume !(1 == ~t7_pc~0); 180072#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 190337#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190335#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 190333#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 190331#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 190330#L570-30 assume !(1 == ~t8_pc~0); 190328#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 190327#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 190326#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 190322#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 190320#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190318#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 186916#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 190312#L957-3 assume !(1 == ~T2_E~0); 190310#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 190308#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 190306#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 190302#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 190300#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 190298#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 190296#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 190294#L997-3 assume !(1 == ~E_1~0); 190291#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 190289#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 190287#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 190283#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 190281#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 190279#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 190277#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 190275#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 190255#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 190253#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190251#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 190249#L1322 assume !(0 == start_simulation_~tmp~3#1); 190246#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 190238#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 190229#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 190227#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 190225#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 190224#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 190222#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 190217#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 190166#L1303-2 [2024-11-13 16:14:03,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:03,359 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2024-11-13 16:14:03,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:03,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322015147] [2024-11-13 16:14:03,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:03,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:03,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:03,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:03,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:03,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322015147] [2024-11-13 16:14:03,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322015147] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:03,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:03,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 16:14:03,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062543435] [2024-11-13 16:14:03,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:03,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:03,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:03,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1645921082, now seen corresponding path program 1 times [2024-11-13 16:14:03,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:03,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460974977] [2024-11-13 16:14:03,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:03,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:03,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:03,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:03,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:03,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460974977] [2024-11-13 16:14:03,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460974977] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:03,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:03,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:03,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210288910] [2024-11-13 16:14:03,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:03,543 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:03,544 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:03,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:14:03,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:14:03,544 INFO L87 Difference]: Start difference. First operand 43726 states and 62180 transitions. cyclomatic complexity: 18486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:04,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:04,273 INFO L93 Difference]: Finished difference Result 82565 states and 116953 transitions. [2024-11-13 16:14:04,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82565 states and 116953 transitions. [2024-11-13 16:14:05,021 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81968 [2024-11-13 16:14:05,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82565 states to 82565 states and 116953 transitions. [2024-11-13 16:14:05,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82565 [2024-11-13 16:14:05,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82565 [2024-11-13 16:14:05,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82565 states and 116953 transitions. [2024-11-13 16:14:05,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:05,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82565 states and 116953 transitions. [2024-11-13 16:14:05,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82565 states and 116953 transitions. [2024-11-13 16:14:07,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82565 to 82437. [2024-11-13 16:14:07,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82437 states, 82437 states have (on average 1.417142787825855) internal successors, (116825), 82436 states have internal predecessors, (116825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:08,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82437 states to 82437 states and 116825 transitions. [2024-11-13 16:14:08,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2024-11-13 16:14:08,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:14:08,146 INFO L424 stractBuchiCegarLoop]: Abstraction has 82437 states and 116825 transitions. [2024-11-13 16:14:08,146 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 16:14:08,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82437 states and 116825 transitions. [2024-11-13 16:14:08,411 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 81840 [2024-11-13 16:14:08,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:08,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:08,415 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:08,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:08,416 INFO L745 eck$LassoCheckResult]: Stem: 298929#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 298930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 299689#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 299690#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 299767#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 299396#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 299397#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 298950#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 298951#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 298879#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 298880#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 299162#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 299133#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 299134#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299459#L854 assume !(0 == ~M_E~0); 299231#L854-2 assume !(0 == ~T1_E~0); 299232#L859-1 assume !(0 == ~T2_E~0); 298757#L864-1 assume !(0 == ~T3_E~0); 298758#L869-1 assume !(0 == ~T4_E~0); 298868#L874-1 assume !(0 == ~T5_E~0); 299737#L879-1 assume !(0 == ~T6_E~0); 299217#L884-1 assume !(0 == ~T7_E~0); 298621#L889-1 assume !(0 == ~T8_E~0); 298622#L894-1 assume !(0 == ~E_M~0); 298965#L899-1 assume !(0 == ~E_1~0); 299467#L904-1 assume !(0 == ~E_2~0); 299156#L909-1 assume !(0 == ~E_3~0); 299157#L914-1 assume !(0 == ~E_4~0); 299385#L919-1 assume !(0 == ~E_5~0); 299051#L924-1 assume !(0 == ~E_6~0); 298854#L929-1 assume !(0 == ~E_7~0); 298855#L934-1 assume !(0 == ~E_8~0); 299130#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 298638#L418 assume !(1 == ~m_pc~0); 298614#L418-2 is_master_triggered_~__retres1~0#1 := 0; 299664#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 299665#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299588#L1061 assume !(0 != activate_threads_~tmp~1#1); 299496#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299497#L437 assume !(1 == ~t1_pc~0); 299727#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 299596#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 298663#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 298664#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 298998#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299578#L456 assume !(1 == ~t2_pc~0); 298912#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 298911#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299085#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299086#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 299266#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298752#L475 assume !(1 == ~t3_pc~0); 298753#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 298817#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 298629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 298630#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 299001#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299002#L494 assume !(1 == ~t4_pc~0); 299045#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 299046#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 298767#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 298768#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 299415#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 298810#L513 assume !(1 == ~t5_pc~0); 298811#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 299050#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299609#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 298764#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 298765#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 298718#L532 assume !(1 == ~t6_pc~0); 298719#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 298869#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299066#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 299067#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 298969#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 298970#L551 assume !(1 == ~t7_pc~0); 299468#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 299419#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 299420#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 299801#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 299807#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 299174#L570 assume !(1 == ~t8_pc~0); 299175#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 299693#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 299543#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 299293#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 298750#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 298751#L952 assume !(1 == ~M_E~0); 299602#L952-2 assume !(1 == ~T1_E~0); 313135#L957-1 assume !(1 == ~T2_E~0); 313134#L962-1 assume !(1 == ~T3_E~0); 313133#L967-1 assume !(1 == ~T4_E~0); 313131#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 313130#L977-1 assume !(1 == ~T6_E~0); 313129#L982-1 assume !(1 == ~T7_E~0); 313128#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 313127#L992-1 assume !(1 == ~E_M~0); 313123#L997-1 assume !(1 == ~E_1~0); 313121#L1002-1 assume !(1 == ~E_2~0); 313119#L1007-1 assume !(1 == ~E_3~0); 313117#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 298624#L1017-1 assume !(1 == ~E_5~0); 299252#L1022-1 assume !(1 == ~E_6~0); 299253#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 299281#L1032-1 assume !(1 == ~E_8~0); 299446#L1037-1 assume { :end_inline_reset_delta_events } true; 299447#L1303-2 [2024-11-13 16:14:08,416 INFO L747 eck$LassoCheckResult]: Loop: 299447#L1303-2 assume !false; 317555#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 317547#L829-1 assume !false; 317544#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 317496#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 317488#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 317481#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 317474#L712 assume !(0 != eval_~tmp~0#1); 317475#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 318338#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 318336#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 318333#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 318331#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 318328#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 318324#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 318320#L874-3 assume !(0 == ~T5_E~0); 318316#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 318312#L884-3 assume !(0 == ~T7_E~0); 318309#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 318306#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 318302#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 318299#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 318296#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 318292#L914-3 assume !(0 == ~E_4~0); 318289#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 318286#L924-3 assume !(0 == ~E_6~0); 318282#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 318279#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 318276#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318273#L418-30 assume 1 == ~m_pc~0; 318269#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 318265#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318261#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318257#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 318254#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 318250#L437-30 assume !(1 == ~t1_pc~0); 318247#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 318244#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318240#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 318237#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 318234#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 318232#L456-30 assume 1 == ~t2_pc~0; 318229#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 318227#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318225#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318222#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 318219#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 318216#L475-30 assume !(1 == ~t3_pc~0); 318213#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 318194#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318191#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318186#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 318181#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 318176#L494-30 assume 1 == ~t4_pc~0; 318170#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 318165#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 318162#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 318158#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 318153#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 318148#L513-30 assume !(1 == ~t5_pc~0); 318144#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 318141#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 318136#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 318133#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 318130#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 318125#L532-30 assume !(1 == ~t6_pc~0); 318121#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 318119#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 318118#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 318117#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 318116#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 318115#L551-30 assume !(1 == ~t7_pc~0); 312231#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 318113#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 318111#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 318109#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 318107#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 318105#L570-30 assume !(1 == ~t8_pc~0); 318103#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 318101#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 318099#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 318097#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 318095#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 318093#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 313359#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 318090#L957-3 assume !(1 == ~T2_E~0); 318088#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 318086#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 318084#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314194#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 318081#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 318079#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 318077#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 318075#L997-3 assume !(1 == ~E_1~0); 318072#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 318070#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 318068#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 313327#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 318067#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 318065#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 318064#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 318063#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 318025#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 318019#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 318013#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 318007#L1322 assume !(0 == start_simulation_~tmp~3#1); 318003#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 317626#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 317617#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 317615#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 317612#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 317600#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 317590#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 317584#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 299447#L1303-2 [2024-11-13 16:14:08,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:08,417 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2024-11-13 16:14:08,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:08,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762822027] [2024-11-13 16:14:08,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:08,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:08,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:08,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:08,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:08,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762822027] [2024-11-13 16:14:08,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762822027] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:08,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:08,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:08,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834370714] [2024-11-13 16:14:08,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:08,850 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:08,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:08,850 INFO L85 PathProgramCache]: Analyzing trace with hash -374021513, now seen corresponding path program 1 times [2024-11-13 16:14:08,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:08,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296102999] [2024-11-13 16:14:08,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:08,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:08,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:08,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:08,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:08,929 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296102999] [2024-11-13 16:14:08,929 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296102999] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:08,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:08,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:08,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339962868] [2024-11-13 16:14:08,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:08,930 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:08,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:08,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:08,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:08,931 INFO L87 Difference]: Start difference. First operand 82437 states and 116825 transitions. cyclomatic complexity: 34452 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:09,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:09,295 INFO L93 Difference]: Finished difference Result 63030 states and 89131 transitions. [2024-11-13 16:14:09,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63030 states and 89131 transitions. [2024-11-13 16:14:10,043 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 62576 [2024-11-13 16:14:10,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63030 states to 63030 states and 89131 transitions. [2024-11-13 16:14:10,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63030 [2024-11-13 16:14:10,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63030 [2024-11-13 16:14:10,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63030 states and 89131 transitions. [2024-11-13 16:14:10,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:10,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63030 states and 89131 transitions. [2024-11-13 16:14:10,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63030 states and 89131 transitions. [2024-11-13 16:14:11,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63030 to 43649. [2024-11-13 16:14:11,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4146028545900249) internal successors, (61746), 43648 states have internal predecessors, (61746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:11,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61746 transitions. [2024-11-13 16:14:11,407 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2024-11-13 16:14:11,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:11,409 INFO L424 stractBuchiCegarLoop]: Abstraction has 43649 states and 61746 transitions. [2024-11-13 16:14:11,409 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 16:14:11,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61746 transitions. [2024-11-13 16:14:11,609 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-11-13 16:14:11,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:11,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:11,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:11,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:11,613 INFO L745 eck$LassoCheckResult]: Stem: 444406#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 444407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 445129#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 445130#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 445205#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 444858#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 444859#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 444431#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 444432#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 444358#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 444359#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 444634#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 444604#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 444605#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444914#L854 assume !(0 == ~M_E~0); 444704#L854-2 assume !(0 == ~T1_E~0); 444705#L859-1 assume !(0 == ~T2_E~0); 444236#L864-1 assume !(0 == ~T3_E~0); 444237#L869-1 assume !(0 == ~T4_E~0); 444347#L874-1 assume !(0 == ~T5_E~0); 445183#L879-1 assume !(0 == ~T6_E~0); 444689#L884-1 assume !(0 == ~T7_E~0); 444099#L889-1 assume !(0 == ~T8_E~0); 444100#L894-1 assume !(0 == ~E_M~0); 444442#L899-1 assume !(0 == ~E_1~0); 444920#L904-1 assume !(0 == ~E_2~0); 444627#L909-1 assume !(0 == ~E_3~0); 444628#L914-1 assume !(0 == ~E_4~0); 444847#L919-1 assume !(0 == ~E_5~0); 444525#L924-1 assume !(0 == ~E_6~0); 444333#L929-1 assume !(0 == ~E_7~0); 444334#L934-1 assume !(0 == ~E_8~0); 444603#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 444116#L418 assume !(1 == ~m_pc~0); 444091#L418-2 is_master_triggered_~__retres1~0#1 := 0; 445110#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 445111#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 445045#L1061 assume !(0 != activate_threads_~tmp~1#1); 444947#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 444948#L437 assume !(1 == ~t1_pc~0); 445168#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 445052#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444141#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 444142#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 444473#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 445037#L456 assume !(1 == ~t2_pc~0); 444390#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 444389#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 444557#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 444558#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 444739#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 444231#L475 assume !(1 == ~t3_pc~0); 444232#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 444296#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 444107#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 444108#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 444476#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444477#L494 assume !(1 == ~t4_pc~0); 444520#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 444521#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 444246#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 444247#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 444873#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444292#L513 assume !(1 == ~t5_pc~0); 444293#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 444524#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 445062#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 444243#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 444244#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 444197#L532 assume !(1 == ~t6_pc~0); 444198#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 444348#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 444539#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 444540#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 444445#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 444446#L551 assume !(1 == ~t7_pc~0); 444921#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 444876#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 444877#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 445227#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 445236#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 444648#L570 assume !(1 == ~t8_pc~0); 444649#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 445138#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 445001#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 444763#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 444229#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 444230#L952 assume !(1 == ~M_E~0); 444164#L952-2 assume !(1 == ~T1_E~0); 444165#L957-1 assume !(1 == ~T2_E~0); 445013#L962-1 assume !(1 == ~T3_E~0); 444781#L967-1 assume !(1 == ~T4_E~0); 444782#L972-1 assume !(1 == ~T5_E~0); 445080#L977-1 assume !(1 == ~T6_E~0); 445081#L982-1 assume !(1 == ~T7_E~0); 444350#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 444351#L992-1 assume !(1 == ~E_M~0); 444360#L997-1 assume !(1 == ~E_1~0); 444737#L1002-1 assume !(1 == ~E_2~0); 444721#L1007-1 assume !(1 == ~E_3~0); 444101#L1012-1 assume !(1 == ~E_4~0); 444102#L1017-1 assume !(1 == ~E_5~0); 444727#L1022-1 assume !(1 == ~E_6~0); 444728#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 444751#L1032-1 assume !(1 == ~E_8~0); 444904#L1037-1 assume { :end_inline_reset_delta_events } true; 444905#L1303-2 [2024-11-13 16:14:11,614 INFO L747 eck$LassoCheckResult]: Loop: 444905#L1303-2 assume !false; 453859#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 453857#L829-1 assume !false; 453855#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 453838#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 453834#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 453832#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 453829#L712 assume !(0 != eval_~tmp~0#1); 453827#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 453825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 453823#L854-3 assume !(0 == ~M_E~0); 453821#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 453819#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 453817#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 453815#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 453813#L874-3 assume !(0 == ~T5_E~0); 453811#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 453809#L884-3 assume !(0 == ~T7_E~0); 453807#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 453805#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 453803#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 453801#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 453799#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 453481#L914-3 assume !(0 == ~E_4~0); 453480#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 453479#L924-3 assume !(0 == ~E_6~0); 453478#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 453477#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 453476#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453475#L418-30 assume !(1 == ~m_pc~0); 453474#L418-32 is_master_triggered_~__retres1~0#1 := 0; 453500#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 453482#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 453466#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 453463#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 453461#L437-30 assume !(1 == ~t1_pc~0); 453459#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 453456#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453454#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 453452#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 453450#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453448#L456-30 assume !(1 == ~t2_pc~0); 453446#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 453443#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453441#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 453439#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 453436#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 453434#L475-30 assume !(1 == ~t3_pc~0); 453432#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 453430#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 453428#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 453426#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 453424#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 453422#L494-30 assume !(1 == ~t4_pc~0); 453420#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 453417#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453415#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 453413#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 453410#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453408#L513-30 assume !(1 == ~t5_pc~0); 453406#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 453404#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453402#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 453400#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 453398#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 453396#L532-30 assume 1 == ~t6_pc~0; 453394#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 453391#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 453389#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 453387#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 453384#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 453382#L551-30 assume !(1 == ~t7_pc~0); 453376#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 453379#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 453377#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 453374#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 453373#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 453370#L570-30 assume !(1 == ~t8_pc~0); 453368#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 453366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 453364#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 453362#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 453360#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 453358#L952-3 assume !(1 == ~M_E~0); 453356#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 453354#L957-3 assume !(1 == ~T2_E~0); 453352#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 453350#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 453348#L972-3 assume !(1 == ~T5_E~0); 453346#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 453344#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 453342#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 453340#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 453338#L997-3 assume !(1 == ~E_1~0); 453336#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 453334#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 453332#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 453330#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 453328#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 453326#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 453324#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 453322#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 453297#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 453288#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 453278#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 451644#L1322 assume !(0 == start_simulation_~tmp~3#1); 451645#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 457373#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 457364#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 457362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 457360#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 457358#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 454708#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 454707#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 444905#L1303-2 [2024-11-13 16:14:11,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:11,615 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2024-11-13 16:14:11,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:11,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143181673] [2024-11-13 16:14:11,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:11,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:11,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:11,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:11,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:11,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143181673] [2024-11-13 16:14:11,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143181673] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:11,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:11,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:11,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674543865] [2024-11-13 16:14:11,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:11,772 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:11,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:11,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1196204153, now seen corresponding path program 1 times [2024-11-13 16:14:11,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:11,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425787013] [2024-11-13 16:14:11,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:11,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:11,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:11,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:11,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:11,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425787013] [2024-11-13 16:14:11,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425787013] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:11,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:11,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:11,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674373398] [2024-11-13 16:14:11,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:11,865 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:11,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:11,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:11,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:11,866 INFO L87 Difference]: Start difference. First operand 43649 states and 61746 transitions. cyclomatic complexity: 18129 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:12,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:12,354 INFO L93 Difference]: Finished difference Result 69451 states and 98228 transitions. [2024-11-13 16:14:12,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69451 states and 98228 transitions. [2024-11-13 16:14:13,026 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 68912 [2024-11-13 16:14:13,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69451 states to 69451 states and 98228 transitions. [2024-11-13 16:14:13,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69451 [2024-11-13 16:14:13,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69451 [2024-11-13 16:14:13,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69451 states and 98228 transitions. [2024-11-13 16:14:13,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:13,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69451 states and 98228 transitions. [2024-11-13 16:14:13,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69451 states and 98228 transitions. [2024-11-13 16:14:14,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69451 to 49009. [2024-11-13 16:14:14,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49009 states, 49009 states have (on average 1.4169030178130548) internal successors, (69441), 49008 states have internal predecessors, (69441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:14,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49009 states to 49009 states and 69441 transitions. [2024-11-13 16:14:14,605 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2024-11-13 16:14:14,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:14,607 INFO L424 stractBuchiCegarLoop]: Abstraction has 49009 states and 69441 transitions. [2024-11-13 16:14:14,607 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 16:14:14,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49009 states and 69441 transitions. [2024-11-13 16:14:14,780 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2024-11-13 16:14:14,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:14,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:14,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:14,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:14,786 INFO L745 eck$LassoCheckResult]: Stem: 557522#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 557523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 558280#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 558281#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558362#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 557986#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 557987#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 557547#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 557548#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557475#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 557476#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 557749#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 557718#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 557719#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 558049#L854 assume !(0 == ~M_E~0); 557818#L854-2 assume !(0 == ~T1_E~0); 557819#L859-1 assume !(0 == ~T2_E~0); 557349#L864-1 assume !(0 == ~T3_E~0); 557350#L869-1 assume !(0 == ~T4_E~0); 557464#L874-1 assume !(0 == ~T5_E~0); 558337#L879-1 assume !(0 == ~T6_E~0); 557803#L884-1 assume !(0 == ~T7_E~0); 557210#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 557211#L894-1 assume !(0 == ~E_M~0); 558402#L899-1 assume !(0 == ~E_1~0); 558056#L904-1 assume !(0 == ~E_2~0); 558057#L909-1 assume !(0 == ~E_3~0); 557973#L914-1 assume !(0 == ~E_4~0); 557974#L919-1 assume !(0 == ~E_5~0); 557642#L924-1 assume !(0 == ~E_6~0); 557643#L929-1 assume !(0 == ~E_7~0); 558347#L934-1 assume !(0 == ~E_8~0); 558348#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558452#L418 assume !(1 == ~m_pc~0); 558376#L418-2 is_master_triggered_~__retres1~0#1 := 0; 558377#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 558449#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 558446#L1061 assume !(0 != activate_threads_~tmp~1#1); 558445#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558371#L437 assume !(1 == ~t1_pc~0); 558372#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 558191#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 558192#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 557589#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 557590#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 558173#L456 assume !(1 == ~t2_pc~0); 558174#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 558367#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 558368#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 558219#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 558220#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 557344#L475 assume !(1 == ~t3_pc~0); 557345#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 558444#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557220#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 557221#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 557593#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557594#L494 assume !(1 == ~t4_pc~0); 557637#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 557638#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557360#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 557361#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 558002#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 557408#L513 assume !(1 == ~t5_pc~0); 557409#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 557641#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558207#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 557356#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 557357#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 557310#L532 assume !(1 == ~t6_pc~0); 557311#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 557465#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557656#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 557657#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 557562#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 557563#L551 assume !(1 == ~t7_pc~0); 558058#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 558006#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 558007#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 558385#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 558391#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 557762#L570 assume !(1 == ~t8_pc~0); 557763#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 558287#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 558134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 557881#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 557342#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557343#L952 assume !(1 == ~M_E~0); 558200#L952-2 assume !(1 == ~T1_E~0); 558415#L957-1 assume !(1 == ~T2_E~0); 558414#L962-1 assume !(1 == ~T3_E~0); 558413#L967-1 assume !(1 == ~T4_E~0); 558412#L972-1 assume !(1 == ~T5_E~0); 558411#L977-1 assume !(1 == ~T6_E~0); 558410#L982-1 assume !(1 == ~T7_E~0); 558409#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 557468#L992-1 assume !(1 == ~E_M~0); 557477#L997-1 assume !(1 == ~E_1~0); 557852#L1002-1 assume !(1 == ~E_2~0); 557837#L1007-1 assume !(1 == ~E_3~0); 557213#L1012-1 assume !(1 == ~E_4~0); 557214#L1017-1 assume !(1 == ~E_5~0); 557843#L1022-1 assume !(1 == ~E_6~0); 557844#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 557868#L1032-1 assume !(1 == ~E_8~0); 558036#L1037-1 assume { :end_inline_reset_delta_events } true; 558037#L1303-2 [2024-11-13 16:14:14,786 INFO L747 eck$LassoCheckResult]: Loop: 558037#L1303-2 assume !false; 575112#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 575110#L829-1 assume !false; 575107#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 575090#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 575086#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 575084#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 575081#L712 assume !(0 != eval_~tmp~0#1); 575082#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 581300#L854-3 assume !(0 == ~M_E~0); 581298#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 581296#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 581294#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 581292#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 581290#L874-3 assume !(0 == ~T5_E~0); 581288#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 581286#L884-3 assume !(0 == ~T7_E~0); 581283#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 581282#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 581281#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 581280#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 581279#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 581278#L914-3 assume !(0 == ~E_4~0); 581277#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 581276#L924-3 assume !(0 == ~E_6~0); 581275#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 581274#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 581273#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 581272#L418-30 assume 1 == ~m_pc~0; 581270#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 581268#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581266#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 581264#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 581263#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 581262#L437-30 assume !(1 == ~t1_pc~0); 581261#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 581260#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 581259#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 581258#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 581257#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 581256#L456-30 assume 1 == ~t2_pc~0; 581254#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 581253#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 581252#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 581251#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 581250#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 581249#L475-30 assume !(1 == ~t3_pc~0); 581248#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 581247#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 581246#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 581245#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 581244#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 581243#L494-30 assume 1 == ~t4_pc~0; 581241#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 581240#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 581239#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 581238#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 581237#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 581236#L513-30 assume !(1 == ~t5_pc~0); 581235#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 581234#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 581233#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 581232#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 581231#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 581230#L532-30 assume !(1 == ~t6_pc~0); 581228#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 581227#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 581226#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 581225#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 581224#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 581223#L551-30 assume !(1 == ~t7_pc~0); 579712#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 581222#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 581221#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 581220#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 581219#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 581218#L570-30 assume !(1 == ~t8_pc~0); 581217#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 581216#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 581215#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 581214#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 581213#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 581212#L952-3 assume !(1 == ~M_E~0); 581211#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 581210#L957-3 assume !(1 == ~T2_E~0); 581209#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 581208#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 581207#L972-3 assume !(1 == ~T5_E~0); 581206#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 581205#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 581203#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 581202#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 581201#L997-3 assume !(1 == ~E_1~0); 581200#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 581199#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 581197#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 581195#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 581193#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 581191#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 581189#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 581187#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 581147#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 581098#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 580600#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 564615#L1322 assume !(0 == start_simulation_~tmp~3#1); 564616#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 575138#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 575129#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 575128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 575125#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 575124#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 575123#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 575122#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 558037#L1303-2 [2024-11-13 16:14:14,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:14,787 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2024-11-13 16:14:14,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:14,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874380353] [2024-11-13 16:14:14,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:14,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:14,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:14,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:14,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:14,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874380353] [2024-11-13 16:14:14,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874380353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:14,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:14,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:14,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621218722] [2024-11-13 16:14:14,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:14,880 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:14,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:14,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1778911989, now seen corresponding path program 1 times [2024-11-13 16:14:14,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:14,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283223987] [2024-11-13 16:14:14,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:14,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:14,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:14,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:14,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:14,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283223987] [2024-11-13 16:14:14,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283223987] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:14,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:14,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:14,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183213272] [2024-11-13 16:14:14,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:14,948 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:14,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:14,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:14,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:14,948 INFO L87 Difference]: Start difference. First operand 49009 states and 69441 transitions. cyclomatic complexity: 20464 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:15,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:15,190 INFO L93 Difference]: Finished difference Result 43649 states and 61584 transitions. [2024-11-13 16:14:15,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43649 states and 61584 transitions. [2024-11-13 16:14:15,399 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-11-13 16:14:16,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43649 states to 43649 states and 61584 transitions. [2024-11-13 16:14:16,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43649 [2024-11-13 16:14:16,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43649 [2024-11-13 16:14:16,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43649 states and 61584 transitions. [2024-11-13 16:14:16,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:16,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-11-13 16:14:16,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43649 states and 61584 transitions. [2024-11-13 16:14:16,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43649 to 43649. [2024-11-13 16:14:16,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4108914293569155) internal successors, (61584), 43648 states have internal predecessors, (61584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:16,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61584 transitions. [2024-11-13 16:14:16,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-11-13 16:14:16,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:16,666 INFO L424 stractBuchiCegarLoop]: Abstraction has 43649 states and 61584 transitions. [2024-11-13 16:14:16,666 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 16:14:16,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61584 transitions. [2024-11-13 16:14:16,835 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-11-13 16:14:16,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:16,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:16,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:16,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:16,849 INFO L745 eck$LassoCheckResult]: Stem: 650188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 650189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 650921#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 650922#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 651003#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 650635#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 650636#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 650207#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 650208#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 650136#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 650137#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 650411#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 650382#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 650383#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 650691#L854 assume !(0 == ~M_E~0); 650479#L854-2 assume !(0 == ~T1_E~0); 650480#L859-1 assume !(0 == ~T2_E~0); 650014#L864-1 assume !(0 == ~T3_E~0); 650015#L869-1 assume !(0 == ~T4_E~0); 650127#L874-1 assume !(0 == ~T5_E~0); 650971#L879-1 assume !(0 == ~T6_E~0); 650469#L884-1 assume !(0 == ~T7_E~0); 649877#L889-1 assume !(0 == ~T8_E~0); 649878#L894-1 assume !(0 == ~E_M~0); 650222#L899-1 assume !(0 == ~E_1~0); 650697#L904-1 assume !(0 == ~E_2~0); 650400#L909-1 assume !(0 == ~E_3~0); 650401#L914-1 assume !(0 == ~E_4~0); 650623#L919-1 assume !(0 == ~E_5~0); 650307#L924-1 assume !(0 == ~E_6~0); 650109#L929-1 assume !(0 == ~E_7~0); 650110#L934-1 assume !(0 == ~E_8~0); 650379#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 649894#L418 assume !(1 == ~m_pc~0); 649869#L418-2 is_master_triggered_~__retres1~0#1 := 0; 650905#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650906#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 650826#L1061 assume !(0 != activate_threads_~tmp~1#1); 650724#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 650725#L437 assume !(1 == ~t1_pc~0); 650957#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 650835#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 649916#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 649917#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 650255#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 650815#L456 assume !(1 == ~t2_pc~0); 650168#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 650167#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650339#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 650340#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 650517#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 650009#L475 assume !(1 == ~t3_pc~0); 650010#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 650074#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 649885#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 649886#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 650258#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 650259#L494 assume !(1 == ~t4_pc~0); 650301#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 650302#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 650025#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 650026#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 650650#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 650069#L513 assume !(1 == ~t5_pc~0); 650070#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 650303#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650847#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 650021#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 650022#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 649973#L532 assume !(1 == ~t6_pc~0); 649974#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 650128#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 650321#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 650322#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 650227#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 650228#L551 assume !(1 == ~t7_pc~0); 650698#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 650652#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 650653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 651025#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 651031#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 650423#L570 assume !(1 == ~t8_pc~0); 650424#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 650927#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 650779#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 650540#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 650003#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 650004#L952 assume !(1 == ~M_E~0); 649942#L952-2 assume !(1 == ~T1_E~0); 649943#L957-1 assume !(1 == ~T2_E~0); 650793#L962-1 assume !(1 == ~T3_E~0); 650561#L967-1 assume !(1 == ~T4_E~0); 650562#L972-1 assume !(1 == ~T5_E~0); 650865#L977-1 assume !(1 == ~T6_E~0); 650866#L982-1 assume !(1 == ~T7_E~0); 650130#L987-1 assume !(1 == ~T8_E~0); 650131#L992-1 assume !(1 == ~E_M~0); 650138#L997-1 assume !(1 == ~E_1~0); 650515#L1002-1 assume !(1 == ~E_2~0); 650499#L1007-1 assume !(1 == ~E_3~0); 649879#L1012-1 assume !(1 == ~E_4~0); 649880#L1017-1 assume !(1 == ~E_5~0); 650502#L1022-1 assume !(1 == ~E_6~0); 650503#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 650529#L1032-1 assume !(1 == ~E_8~0); 650678#L1037-1 assume { :end_inline_reset_delta_events } true; 650679#L1303-2 [2024-11-13 16:14:16,849 INFO L747 eck$LassoCheckResult]: Loop: 650679#L1303-2 assume !false; 657185#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 657183#L829-1 assume !false; 657181#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 657165#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 657161#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 657159#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 657156#L712 assume !(0 != eval_~tmp~0#1); 657157#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 657421#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657420#L854-3 assume !(0 == ~M_E~0); 657419#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 657418#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 657417#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 657416#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 657414#L874-3 assume !(0 == ~T5_E~0); 657413#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 657412#L884-3 assume !(0 == ~T7_E~0); 657410#L889-3 assume !(0 == ~T8_E~0); 657409#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 657408#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 657407#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 657406#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 657405#L914-3 assume !(0 == ~E_4~0); 657402#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 657400#L924-3 assume !(0 == ~E_6~0); 657398#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 657394#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 657392#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657390#L418-30 assume !(1 == ~m_pc~0); 657386#L418-32 is_master_triggered_~__retres1~0#1 := 0; 657383#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 657381#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 657379#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 657376#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 657374#L437-30 assume !(1 == ~t1_pc~0); 657372#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 657370#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657368#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 657366#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 657363#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 657361#L456-30 assume 1 == ~t2_pc~0; 657358#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 657356#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 657354#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 657352#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 657350#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 657348#L475-30 assume !(1 == ~t3_pc~0); 657346#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 657344#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 657342#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 657340#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 657337#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 657335#L494-30 assume 1 == ~t4_pc~0; 657332#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 657330#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 657328#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 657326#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 657324#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 657322#L513-30 assume !(1 == ~t5_pc~0); 657320#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 657318#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 657316#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 657314#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 657311#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 657309#L532-30 assume !(1 == ~t6_pc~0); 657306#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 657304#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 657302#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 657300#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 657299#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 657297#L551-30 assume !(1 == ~t7_pc~0); 656283#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 657294#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 657292#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 657290#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 657288#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 657286#L570-30 assume !(1 == ~t8_pc~0); 657284#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 657282#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 657280#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 657278#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 657277#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 657274#L952-3 assume !(1 == ~M_E~0); 657273#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 657272#L957-3 assume !(1 == ~T2_E~0); 657271#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 657270#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 657269#L972-3 assume !(1 == ~T5_E~0); 657268#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 657267#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 657266#L987-3 assume !(1 == ~T8_E~0); 657265#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 657264#L997-3 assume !(1 == ~E_1~0); 657262#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 657261#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 657260#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 657259#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 657255#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 657253#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 657251#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 657249#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 657230#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 657227#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 657225#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 657222#L1322 assume !(0 == start_simulation_~tmp~3#1); 657220#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 657214#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 657205#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 657203#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 657201#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 657199#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 657196#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 657194#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 650679#L1303-2 [2024-11-13 16:14:16,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:16,849 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2024-11-13 16:14:16,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:16,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900694168] [2024-11-13 16:14:16,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:16,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:16,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:16,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:16,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:16,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900694168] [2024-11-13 16:14:16,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900694168] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:16,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:16,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:16,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595799373] [2024-11-13 16:14:16,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:16,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:16,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:16,969 INFO L85 PathProgramCache]: Analyzing trace with hash 936685048, now seen corresponding path program 1 times [2024-11-13 16:14:16,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:16,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421291259] [2024-11-13 16:14:16,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:16,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:16,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:17,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:17,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:17,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421291259] [2024-11-13 16:14:17,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421291259] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:17,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:17,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:17,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555045121] [2024-11-13 16:14:17,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:17,030 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:17,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:17,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:17,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:17,031 INFO L87 Difference]: Start difference. First operand 43649 states and 61584 transitions. cyclomatic complexity: 17967 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:17,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:17,881 INFO L93 Difference]: Finished difference Result 67715 states and 95298 transitions. [2024-11-13 16:14:17,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67715 states and 95298 transitions. [2024-11-13 16:14:18,250 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 67152 [2024-11-13 16:14:18,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67715 states to 67715 states and 95298 transitions. [2024-11-13 16:14:18,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67715 [2024-11-13 16:14:18,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67715 [2024-11-13 16:14:18,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67715 states and 95298 transitions. [2024-11-13 16:14:18,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:18,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67715 states and 95298 transitions. [2024-11-13 16:14:18,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67715 states and 95298 transitions. [2024-11-13 16:14:19,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67715 to 48977. [2024-11-13 16:14:19,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48977 states, 48977 states have (on average 1.4089674745288605) internal successors, (69007), 48976 states have internal predecessors, (69007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:19,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48977 states to 48977 states and 69007 transitions. [2024-11-13 16:14:19,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48977 states and 69007 transitions. [2024-11-13 16:14:19,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:19,888 INFO L424 stractBuchiCegarLoop]: Abstraction has 48977 states and 69007 transitions. [2024-11-13 16:14:19,888 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 16:14:19,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48977 states and 69007 transitions. [2024-11-13 16:14:20,016 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48560 [2024-11-13 16:14:20,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:20,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:20,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:20,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:20,019 INFO L745 eck$LassoCheckResult]: Stem: 761560#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 761561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 762309#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 762310#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 762398#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 762011#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 762012#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 761578#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 761579#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 761508#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 761509#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 761786#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 761756#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 761757#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 762074#L854 assume !(0 == ~M_E~0); 761850#L854-2 assume !(0 == ~T1_E~0); 761851#L859-1 assume !(0 == ~T2_E~0); 761385#L864-1 assume !(0 == ~T3_E~0); 761386#L869-1 assume !(0 == ~T4_E~0); 761497#L874-1 assume !(0 == ~T5_E~0); 762368#L879-1 assume !(0 == ~T6_E~0); 761840#L884-1 assume !(0 == ~T7_E~0); 761251#L889-1 assume !(0 == ~T8_E~0); 761252#L894-1 assume !(0 == ~E_M~0); 761593#L899-1 assume !(0 == ~E_1~0); 762081#L904-1 assume !(0 == ~E_2~0); 761774#L909-1 assume !(0 == ~E_3~0); 761775#L914-1 assume !(0 == ~E_4~0); 762000#L919-1 assume !(0 == ~E_5~0); 761680#L924-1 assume !(0 == ~E_6~0); 761478#L929-1 assume 0 == ~E_7~0;~E_7~0 := 1; 761479#L934-1 assume !(0 == ~E_8~0); 761752#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 761753#L418 assume !(1 == ~m_pc~0); 762416#L418-2 is_master_triggered_~__retres1~0#1 := 0; 762417#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 762464#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 762465#L1061 assume !(0 != activate_threads_~tmp~1#1); 762110#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 762111#L437 assume !(1 == ~t1_pc~0); 762349#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 762350#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 761288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 761289#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 762372#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 762373#L456 assume !(1 == ~t2_pc~0); 761539#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 761538#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 761711#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 761712#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 761892#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 761893#L475 assume !(1 == ~t3_pc~0); 761963#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 761964#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 761259#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 761260#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 761629#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 761630#L494 assume !(1 == ~t4_pc~0); 761673#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 761674#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 761395#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 761396#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 762028#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 762029#L513 assume !(1 == ~t5_pc~0); 761675#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 761676#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 762232#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 762233#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 762412#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 762413#L532 assume !(1 == ~t6_pc~0); 761500#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 761499#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 761693#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 761694#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 761597#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 761598#L551 assume !(1 == ~t7_pc~0); 762475#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 762031#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 762032#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 762474#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 762473#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 761799#L570 assume !(1 == ~t8_pc~0); 761800#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 762315#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 762316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 761916#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 761374#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 761375#L952 assume !(1 == ~M_E~0); 761314#L952-2 assume !(1 == ~T1_E~0); 761315#L957-1 assume !(1 == ~T2_E~0); 762471#L962-1 assume !(1 == ~T3_E~0); 761935#L967-1 assume !(1 == ~T4_E~0); 761936#L972-1 assume !(1 == ~T5_E~0); 762400#L977-1 assume !(1 == ~T6_E~0); 762469#L982-1 assume !(1 == ~T7_E~0); 762468#L987-1 assume !(1 == ~T8_E~0); 761510#L992-1 assume !(1 == ~E_M~0); 761511#L997-1 assume !(1 == ~E_1~0); 762369#L1002-1 assume !(1 == ~E_2~0); 762370#L1007-1 assume !(1 == ~E_3~0); 761253#L1012-1 assume !(1 == ~E_4~0); 761254#L1017-1 assume !(1 == ~E_5~0); 761877#L1022-1 assume !(1 == ~E_6~0); 761878#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 761907#L1032-1 assume !(1 == ~E_8~0); 762057#L1037-1 assume { :end_inline_reset_delta_events } true; 762058#L1303-2 [2024-11-13 16:14:20,019 INFO L747 eck$LassoCheckResult]: Loop: 762058#L1303-2 assume !false; 775551#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 775549#L829-1 assume !false; 775547#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 775532#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 775528#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 775527#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 775523#L712 assume !(0 != eval_~tmp~0#1); 775524#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 776012#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 776010#L854-3 assume !(0 == ~M_E~0); 776008#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 776006#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 776003#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 776001#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 775999#L874-3 assume !(0 == ~T5_E~0); 775997#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 775995#L884-3 assume !(0 == ~T7_E~0); 775993#L889-3 assume !(0 == ~T8_E~0); 775991#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 775989#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 775987#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 775985#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 775983#L914-3 assume !(0 == ~E_4~0); 775981#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 775978#L924-3 assume !(0 == ~E_6~0); 775975#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 775976#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 783316#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 783313#L418-30 assume !(1 == ~m_pc~0); 783310#L418-32 is_master_triggered_~__retres1~0#1 := 0; 783306#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 783302#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 783298#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 783295#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783293#L437-30 assume !(1 == ~t1_pc~0); 783291#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 783289#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 783287#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 783285#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 783283#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 783281#L456-30 assume !(1 == ~t2_pc~0); 783279#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 783276#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783274#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 783272#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 783270#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 783267#L475-30 assume !(1 == ~t3_pc~0); 783263#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 783259#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783255#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 783251#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 783248#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 783245#L494-30 assume !(1 == ~t4_pc~0); 783241#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 783237#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 783235#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 783233#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 783230#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 783226#L513-30 assume !(1 == ~t5_pc~0); 783221#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 783217#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 783213#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 783210#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 783207#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 783203#L532-30 assume !(1 == ~t6_pc~0); 783199#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 783196#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 783193#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 783190#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 783187#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 783183#L551-30 assume !(1 == ~t7_pc~0); 772564#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 783177#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 783174#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 783171#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 783168#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 783165#L570-30 assume !(1 == ~t8_pc~0); 783162#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 783159#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 783156#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 783153#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 783150#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 783146#L952-3 assume !(1 == ~M_E~0); 783142#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 783139#L957-3 assume !(1 == ~T2_E~0); 783136#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 783133#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 783130#L972-3 assume !(1 == ~T5_E~0); 783127#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 783125#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 783122#L987-3 assume !(1 == ~T8_E~0); 783119#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 783116#L997-3 assume !(1 == ~E_1~0); 783113#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 783109#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 783105#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 783102#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 783099#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 775820#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 775819#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 775818#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 775798#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 775796#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 775794#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 769494#L1322 assume !(0 == start_simulation_~tmp~3#1); 769495#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 775580#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 775571#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 775569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 775567#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 775565#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 775563#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 775560#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 762058#L1303-2 [2024-11-13 16:14:20,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:20,020 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2024-11-13 16:14:20,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:20,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771642718] [2024-11-13 16:14:20,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:20,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:20,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:20,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:20,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:20,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771642718] [2024-11-13 16:14:20,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771642718] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:20,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:20,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:20,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373612314] [2024-11-13 16:14:20,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:20,104 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:20,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:20,105 INFO L85 PathProgramCache]: Analyzing trace with hash -197762054, now seen corresponding path program 1 times [2024-11-13 16:14:20,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:20,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741328598] [2024-11-13 16:14:20,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:20,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:20,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:20,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:20,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:20,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741328598] [2024-11-13 16:14:20,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741328598] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:20,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:20,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:20,164 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270668460] [2024-11-13 16:14:20,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:20,164 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:20,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:20,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:20,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:20,165 INFO L87 Difference]: Start difference. First operand 48977 states and 69007 transitions. cyclomatic complexity: 20062 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:20,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:20,516 INFO L93 Difference]: Finished difference Result 62017 states and 86974 transitions. [2024-11-13 16:14:20,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62017 states and 86974 transitions. [2024-11-13 16:14:20,821 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 61536 [2024-11-13 16:14:21,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62017 states to 62017 states and 86974 transitions. [2024-11-13 16:14:21,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62017 [2024-11-13 16:14:21,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62017 [2024-11-13 16:14:21,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62017 states and 86974 transitions. [2024-11-13 16:14:21,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:21,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62017 states and 86974 transitions. [2024-11-13 16:14:21,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62017 states and 86974 transitions. [2024-11-13 16:14:22,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62017 to 43649. [2024-11-13 16:14:22,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.401681596371051) internal successors, (61182), 43648 states have internal predecessors, (61182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:22,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61182 transitions. [2024-11-13 16:14:22,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61182 transitions. [2024-11-13 16:14:22,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:22,423 INFO L424 stractBuchiCegarLoop]: Abstraction has 43649 states and 61182 transitions. [2024-11-13 16:14:22,423 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 16:14:22,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61182 transitions. [2024-11-13 16:14:22,580 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-11-13 16:14:22,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:22,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:22,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:22,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:22,583 INFO L745 eck$LassoCheckResult]: Stem: 872562#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 872563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 873271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 873272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 873333#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 873000#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 873001#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 872580#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 872581#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 872510#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 872511#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 872785#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 872754#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 872755#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 873059#L854 assume !(0 == ~M_E~0); 872847#L854-2 assume !(0 == ~T1_E~0); 872848#L859-1 assume !(0 == ~T2_E~0); 872389#L864-1 assume !(0 == ~T3_E~0); 872390#L869-1 assume !(0 == ~T4_E~0); 872501#L874-1 assume !(0 == ~T5_E~0); 873315#L879-1 assume !(0 == ~T6_E~0); 872837#L884-1 assume !(0 == ~T7_E~0); 872256#L889-1 assume !(0 == ~T8_E~0); 872257#L894-1 assume !(0 == ~E_M~0); 872594#L899-1 assume !(0 == ~E_1~0); 873065#L904-1 assume !(0 == ~E_2~0); 872774#L909-1 assume !(0 == ~E_3~0); 872775#L914-1 assume !(0 == ~E_4~0); 872987#L919-1 assume !(0 == ~E_5~0); 872676#L924-1 assume !(0 == ~E_6~0); 872483#L929-1 assume !(0 == ~E_7~0); 872484#L934-1 assume !(0 == ~E_8~0); 872751#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 872272#L418 assume !(1 == ~m_pc~0); 872248#L418-2 is_master_triggered_~__retres1~0#1 := 0; 873252#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 873253#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 873187#L1061 assume !(0 != activate_threads_~tmp~1#1); 873094#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 873095#L437 assume !(1 == ~t1_pc~0); 873304#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 873195#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 872293#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 872294#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 872623#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 873177#L456 assume !(1 == ~t2_pc~0); 872541#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 872540#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 872708#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 872709#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 872885#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 872384#L475 assume !(1 == ~t3_pc~0); 872385#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 872448#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 872264#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 872265#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 872626#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 872627#L494 assume !(1 == ~t4_pc~0); 872670#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 872671#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 872399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 872400#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 873016#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 872443#L513 assume !(1 == ~t5_pc~0); 872444#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 872672#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 873208#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 872396#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 872397#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 872349#L532 assume !(1 == ~t6_pc~0); 872350#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 872502#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 872690#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 872691#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 872598#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 872599#L551 assume !(1 == ~t7_pc~0); 873066#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 873020#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 873021#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 873356#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 873363#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 872797#L570 assume !(1 == ~t8_pc~0); 872798#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 873275#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 873136#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 872907#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 872378#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 872379#L952 assume !(1 == ~M_E~0); 872318#L952-2 assume !(1 == ~T1_E~0); 872319#L957-1 assume !(1 == ~T2_E~0); 873152#L962-1 assume !(1 == ~T3_E~0); 872926#L967-1 assume !(1 == ~T4_E~0); 872927#L972-1 assume !(1 == ~T5_E~0); 873224#L977-1 assume !(1 == ~T6_E~0); 873225#L982-1 assume !(1 == ~T7_E~0); 872504#L987-1 assume !(1 == ~T8_E~0); 872505#L992-1 assume !(1 == ~E_M~0); 872512#L997-1 assume !(1 == ~E_1~0); 872883#L1002-1 assume !(1 == ~E_2~0); 872868#L1007-1 assume !(1 == ~E_3~0); 872258#L1012-1 assume !(1 == ~E_4~0); 872259#L1017-1 assume !(1 == ~E_5~0); 872871#L1022-1 assume !(1 == ~E_6~0); 872872#L1027-1 assume !(1 == ~E_7~0); 872898#L1032-1 assume !(1 == ~E_8~0); 873046#L1037-1 assume { :end_inline_reset_delta_events } true; 873047#L1303-2 [2024-11-13 16:14:22,583 INFO L747 eck$LassoCheckResult]: Loop: 873047#L1303-2 assume !false; 882168#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882063#L829-1 assume !false; 882165#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 882149#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 882145#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 882143#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 882140#L712 assume !(0 != eval_~tmp~0#1); 882141#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 902539#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 902535#L854-3 assume !(0 == ~M_E~0); 902530#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 902526#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 902522#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 902516#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 902512#L874-3 assume !(0 == ~T5_E~0); 902507#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 902503#L884-3 assume !(0 == ~T7_E~0); 902499#L889-3 assume !(0 == ~T8_E~0); 902360#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 902182#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 902179#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 902177#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 902175#L914-3 assume !(0 == ~E_4~0); 902173#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 902171#L924-3 assume !(0 == ~E_6~0); 902169#L929-3 assume !(0 == ~E_7~0); 902166#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 902164#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902162#L418-30 assume 1 == ~m_pc~0; 902159#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 902157#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 902155#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 902137#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 902131#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 902120#L437-30 assume !(1 == ~t1_pc~0); 902110#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 902100#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 902090#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 898953#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 894068#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 894067#L456-30 assume 1 == ~t2_pc~0; 894065#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 894064#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 890116#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 882711#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 882710#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 882709#L475-30 assume !(1 == ~t3_pc~0); 882708#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 882707#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 882705#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 882704#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 882703#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 882702#L494-30 assume !(1 == ~t4_pc~0); 882701#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 882698#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 882696#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 882692#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 882690#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 882688#L513-30 assume !(1 == ~t5_pc~0); 882686#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 882683#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 882681#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 882679#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 882677#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 882675#L532-30 assume 1 == ~t6_pc~0; 882673#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 882670#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 882668#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 882666#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 882663#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 882266#L551-30 assume !(1 == ~t7_pc~0); 882264#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 882263#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 882260#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 882259#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 882257#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882256#L570-30 assume !(1 == ~t8_pc~0); 882255#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 882253#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 882251#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 882249#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 882247#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 882245#L952-3 assume !(1 == ~M_E~0); 882243#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 882241#L957-3 assume !(1 == ~T2_E~0); 882239#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 882237#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 882235#L972-3 assume !(1 == ~T5_E~0); 882233#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 882231#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 882229#L987-3 assume !(1 == ~T8_E~0); 882228#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 882225#L997-3 assume !(1 == ~E_1~0); 882224#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 882223#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 882222#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 882221#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 882219#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 882218#L1027-3 assume !(1 == ~E_7~0); 882217#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 882216#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 882207#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 882206#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 882205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 882203#L1322 assume !(0 == start_simulation_~tmp~3#1); 882202#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 882192#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 882183#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 882181#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 882178#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882176#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 882174#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 882172#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 873047#L1303-2 [2024-11-13 16:14:22,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:22,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2024-11-13 16:14:22,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:22,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090967477] [2024-11-13 16:14:22,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:22,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:22,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:22,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:22,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:22,737 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:22,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:22,738 INFO L85 PathProgramCache]: Analyzing trace with hash 497481205, now seen corresponding path program 1 times [2024-11-13 16:14:22,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:22,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689850767] [2024-11-13 16:14:22,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:22,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:22,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:22,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:22,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:22,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689850767] [2024-11-13 16:14:22,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689850767] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:22,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:22,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:22,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329740780] [2024-11-13 16:14:22,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:22,823 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:22,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:22,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:14:22,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:14:22,823 INFO L87 Difference]: Start difference. First operand 43649 states and 61182 transitions. cyclomatic complexity: 17565 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:23,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:23,051 INFO L93 Difference]: Finished difference Result 49009 states and 68747 transitions. [2024-11-13 16:14:23,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49009 states and 68747 transitions. [2024-11-13 16:14:23,290 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2024-11-13 16:14:23,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49009 states to 49009 states and 68747 transitions. [2024-11-13 16:14:23,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49009 [2024-11-13 16:14:23,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49009 [2024-11-13 16:14:23,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49009 states and 68747 transitions. [2024-11-13 16:14:23,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:23,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2024-11-13 16:14:23,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49009 states and 68747 transitions. [2024-11-13 16:14:24,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49009 to 49009. [2024-11-13 16:14:24,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49009 states, 49009 states have (on average 1.4027423534452856) internal successors, (68747), 49008 states have internal predecessors, (68747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:24,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49009 states to 49009 states and 68747 transitions. [2024-11-13 16:14:24,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2024-11-13 16:14:24,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:14:24,204 INFO L424 stractBuchiCegarLoop]: Abstraction has 49009 states and 68747 transitions. [2024-11-13 16:14:24,204 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 16:14:24,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49009 states and 68747 transitions. [2024-11-13 16:14:24,314 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48592 [2024-11-13 16:14:24,315 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:24,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:24,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:24,316 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:24,316 INFO L745 eck$LassoCheckResult]: Stem: 965232#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 965233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 965990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 965991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 966073#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 965700#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 965701#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 965254#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 965255#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 965181#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 965182#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 965463#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 965431#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 965432#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 965761#L854 assume !(0 == ~M_E~0); 965534#L854-2 assume !(0 == ~T1_E~0); 965535#L859-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 965912#L864-1 assume !(0 == ~T3_E~0); 965169#L869-1 assume !(0 == ~T4_E~0); 965170#L874-1 assume !(0 == ~T5_E~0); 966041#L879-1 assume !(0 == ~T6_E~0); 966042#L884-1 assume !(0 == ~T7_E~0); 964918#L889-1 assume !(0 == ~T8_E~0); 964919#L894-1 assume !(0 == ~E_M~0); 966131#L899-1 assume !(0 == ~E_1~0); 965768#L904-1 assume !(0 == ~E_2~0); 965769#L909-1 assume !(0 == ~E_3~0); 965686#L914-1 assume !(0 == ~E_4~0); 965687#L919-1 assume !(0 == ~E_5~0); 965350#L924-1 assume !(0 == ~E_6~0); 965351#L929-1 assume !(0 == ~E_7~0); 966055#L934-1 assume !(0 == ~E_8~0); 966056#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 966168#L418 assume !(1 == ~m_pc~0); 964911#L418-2 is_master_triggered_~__retres1~0#1 := 0; 966167#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 966165#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 965891#L1061 assume !(0 != activate_threads_~tmp~1#1); 965892#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 966088#L437 assume !(1 == ~t1_pc~0); 966089#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 965900#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 965901#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 965295#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 965296#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 965882#L456 assume !(1 == ~t2_pc~0); 965883#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 966082#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 966083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 965927#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 965928#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 965050#L475 assume !(1 == ~t3_pc~0); 965051#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 965117#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 965118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 966027#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 966028#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 965962#L494 assume !(1 == ~t4_pc~0); 965963#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 965654#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 965655#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 966113#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 966114#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 965113#L513 assume !(1 == ~t5_pc~0); 965114#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 966097#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965917#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 965062#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 965063#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965017#L532 assume !(1 == ~t6_pc~0); 965018#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 965171#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 965366#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 965367#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 965268#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 965269#L551 assume !(1 == ~t7_pc~0); 965770#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 965722#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 965723#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 966108#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 966112#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 965476#L570 assume !(1 == ~t8_pc~0); 965477#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 965995#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 965843#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 965594#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 965048#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 965049#L952 assume !(1 == ~M_E~0); 964984#L952-2 assume !(1 == ~T1_E~0); 964985#L957-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 965858#L962-1 assume !(1 == ~T3_E~0); 965613#L967-1 assume !(1 == ~T4_E~0); 965614#L972-1 assume !(1 == ~T5_E~0); 965934#L977-1 assume !(1 == ~T6_E~0); 965935#L982-1 assume !(1 == ~T7_E~0); 965173#L987-1 assume !(1 == ~T8_E~0); 965174#L992-1 assume !(1 == ~E_M~0); 965183#L997-1 assume !(1 == ~E_1~0); 965566#L1002-1 assume !(1 == ~E_2~0); 965551#L1007-1 assume !(1 == ~E_3~0); 964920#L1012-1 assume !(1 == ~E_4~0); 964921#L1017-1 assume !(1 == ~E_5~0); 965557#L1022-1 assume !(1 == ~E_6~0); 965558#L1027-1 assume !(1 == ~E_7~0); 965582#L1032-1 assume !(1 == ~E_8~0); 965750#L1037-1 assume { :end_inline_reset_delta_events } true; 965751#L1303-2 [2024-11-13 16:14:24,316 INFO L747 eck$LassoCheckResult]: Loop: 965751#L1303-2 assume !false; 972266#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 972264#L829-1 assume !false; 972262#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 971963#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 971959#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 971957#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 971954#L712 assume !(0 != eval_~tmp~0#1); 971955#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 975707#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 975704#L854-3 assume !(0 == ~M_E~0); 975702#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 975699#L859-3 assume !(0 == ~T2_E~0); 975700#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 975986#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 975982#L874-3 assume !(0 == ~T5_E~0); 975978#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 975973#L884-3 assume !(0 == ~T7_E~0); 975967#L889-3 assume !(0 == ~T8_E~0); 975961#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 975955#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 975950#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 975946#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 975942#L914-3 assume !(0 == ~E_4~0); 975938#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 975934#L924-3 assume !(0 == ~E_6~0); 975930#L929-3 assume !(0 == ~E_7~0); 975926#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 975922#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 975889#L418-30 assume 1 == ~m_pc~0; 975884#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 975879#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975871#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 975867#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 975863#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 975858#L437-30 assume !(1 == ~t1_pc~0); 975853#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 975848#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 975843#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 975839#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 975835#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 975831#L456-30 assume 1 == ~t2_pc~0; 975826#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 975822#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 975816#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 975812#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975808#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 975803#L475-30 assume !(1 == ~t3_pc~0); 975799#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 975794#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 975792#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 975788#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 975784#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 975780#L494-30 assume 1 == ~t4_pc~0; 975775#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 975771#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 975764#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 975758#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 975752#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 975745#L513-30 assume !(1 == ~t5_pc~0); 975739#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 975735#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 975728#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 975722#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 975719#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 975715#L532-30 assume !(1 == ~t6_pc~0); 975522#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 975520#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 975518#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 975515#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 975513#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 975511#L551-30 assume !(1 == ~t7_pc~0); 971471#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 975508#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 975506#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 975504#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 975502#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 975500#L570-30 assume !(1 == ~t8_pc~0); 975498#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 975496#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 975480#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 975471#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 975463#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 975457#L952-3 assume !(1 == ~M_E~0); 975450#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 972323#L957-3 assume !(1 == ~T2_E~0); 972320#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 972319#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 972318#L972-3 assume !(1 == ~T5_E~0); 972317#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 972316#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 972315#L987-3 assume !(1 == ~T8_E~0); 972314#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 972313#L997-3 assume !(1 == ~E_1~0); 972312#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 972311#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 972310#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 972309#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 972308#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 972307#L1027-3 assume !(1 == ~E_7~0); 972306#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 972304#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 972295#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 972294#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 972293#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 972291#L1322 assume !(0 == start_simulation_~tmp~3#1); 972290#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 972288#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 972280#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 972279#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 972278#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 972277#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 972275#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 972274#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 965751#L1303-2 [2024-11-13 16:14:24,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:24,317 INFO L85 PathProgramCache]: Analyzing trace with hash 743043657, now seen corresponding path program 1 times [2024-11-13 16:14:24,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:24,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88329020] [2024-11-13 16:14:24,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:24,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:24,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:24,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:24,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:24,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88329020] [2024-11-13 16:14:24,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88329020] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:24,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:24,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:24,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620877368] [2024-11-13 16:14:24,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:24,382 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:24,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:24,383 INFO L85 PathProgramCache]: Analyzing trace with hash -929556301, now seen corresponding path program 1 times [2024-11-13 16:14:24,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:24,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622406241] [2024-11-13 16:14:24,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:24,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:24,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:24,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:24,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:24,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622406241] [2024-11-13 16:14:24,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622406241] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:24,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:24,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:24,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923273060] [2024-11-13 16:14:24,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:24,432 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:24,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:24,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:24,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:24,432 INFO L87 Difference]: Start difference. First operand 49009 states and 68747 transitions. cyclomatic complexity: 19770 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:25,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:25,086 INFO L93 Difference]: Finished difference Result 64097 states and 89673 transitions. [2024-11-13 16:14:25,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64097 states and 89673 transitions. [2024-11-13 16:14:25,396 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63632 [2024-11-13 16:14:25,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64097 states to 64097 states and 89673 transitions. [2024-11-13 16:14:25,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64097 [2024-11-13 16:14:25,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64097 [2024-11-13 16:14:25,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64097 states and 89673 transitions. [2024-11-13 16:14:25,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:25,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64097 states and 89673 transitions. [2024-11-13 16:14:25,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64097 states and 89673 transitions. [2024-11-13 16:14:26,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64097 to 43649. [2024-11-13 16:14:26,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43649 states, 43649 states have (on average 1.4001924442713465) internal successors, (61117), 43648 states have internal predecessors, (61117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:26,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43649 states to 43649 states and 61117 transitions. [2024-11-13 16:14:26,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43649 states and 61117 transitions. [2024-11-13 16:14:26,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:26,179 INFO L424 stractBuchiCegarLoop]: Abstraction has 43649 states and 61117 transitions. [2024-11-13 16:14:26,179 INFO L331 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-13 16:14:26,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43649 states and 61117 transitions. [2024-11-13 16:14:26,310 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43312 [2024-11-13 16:14:26,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:26,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:26,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:26,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:26,313 INFO L745 eck$LassoCheckResult]: Stem: 1078337#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1078338#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1079073#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1079074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1079141#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1078786#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1078787#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1078359#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1078360#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1078290#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1078291#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1078561#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1078531#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1078532#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1078854#L854 assume !(0 == ~M_E~0); 1078631#L854-2 assume !(0 == ~T1_E~0); 1078632#L859-1 assume !(0 == ~T2_E~0); 1078168#L864-1 assume !(0 == ~T3_E~0); 1078169#L869-1 assume !(0 == ~T4_E~0); 1078279#L874-1 assume !(0 == ~T5_E~0); 1079117#L879-1 assume !(0 == ~T6_E~0); 1078616#L884-1 assume !(0 == ~T7_E~0); 1078035#L889-1 assume !(0 == ~T8_E~0); 1078036#L894-1 assume !(0 == ~E_M~0); 1078370#L899-1 assume !(0 == ~E_1~0); 1078861#L904-1 assume !(0 == ~E_2~0); 1078555#L909-1 assume !(0 == ~E_3~0); 1078556#L914-1 assume !(0 == ~E_4~0); 1078773#L919-1 assume !(0 == ~E_5~0); 1078450#L924-1 assume !(0 == ~E_6~0); 1078265#L929-1 assume !(0 == ~E_7~0); 1078266#L934-1 assume !(0 == ~E_8~0); 1078530#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1078051#L418 assume !(1 == ~m_pc~0); 1078027#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1079059#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1079060#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1078991#L1061 assume !(0 != activate_threads_~tmp~1#1); 1078891#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1078892#L437 assume !(1 == ~t1_pc~0); 1079107#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1078998#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1078075#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1078076#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1078399#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1078983#L456 assume !(1 == ~t2_pc~0); 1078321#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1078320#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1078483#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1078484#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1078666#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1078163#L475 assume !(1 == ~t3_pc~0); 1078164#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1078228#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1078043#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1078044#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1078402#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1078403#L494 assume !(1 == ~t4_pc~0); 1078445#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1078446#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1078178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1078179#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1078802#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1078224#L513 assume !(1 == ~t5_pc~0); 1078225#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1078449#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1079009#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1078175#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1078176#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1078130#L532 assume !(1 == ~t6_pc~0); 1078131#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1078280#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1078464#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1078465#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1078372#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1078373#L551 assume !(1 == ~t7_pc~0); 1078862#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1078805#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1078806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1079158#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1079163#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1078573#L570 assume !(1 == ~t8_pc~0); 1078574#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1079080#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1078940#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1078692#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1078161#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1078162#L952 assume !(1 == ~M_E~0); 1078097#L952-2 assume !(1 == ~T1_E~0); 1078098#L957-1 assume !(1 == ~T2_E~0); 1078956#L962-1 assume !(1 == ~T3_E~0); 1078710#L967-1 assume !(1 == ~T4_E~0); 1078711#L972-1 assume !(1 == ~T5_E~0); 1079023#L977-1 assume !(1 == ~T6_E~0); 1079024#L982-1 assume !(1 == ~T7_E~0); 1078282#L987-1 assume !(1 == ~T8_E~0); 1078283#L992-1 assume !(1 == ~E_M~0); 1078292#L997-1 assume !(1 == ~E_1~0); 1078664#L1002-1 assume !(1 == ~E_2~0); 1078648#L1007-1 assume !(1 == ~E_3~0); 1078037#L1012-1 assume !(1 == ~E_4~0); 1078038#L1017-1 assume !(1 == ~E_5~0); 1078654#L1022-1 assume !(1 == ~E_6~0); 1078655#L1027-1 assume !(1 == ~E_7~0); 1078680#L1032-1 assume !(1 == ~E_8~0); 1078839#L1037-1 assume { :end_inline_reset_delta_events } true; 1078840#L1303-2 [2024-11-13 16:14:26,314 INFO L747 eck$LassoCheckResult]: Loop: 1078840#L1303-2 assume !false; 1094822#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1094821#L829-1 assume !false; 1094820#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1094811#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1094799#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1094797#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1094794#L712 assume !(0 != eval_~tmp~0#1); 1094795#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1098137#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1098133#L854-3 assume !(0 == ~M_E~0); 1098128#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1098124#L859-3 assume !(0 == ~T2_E~0); 1098121#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1098117#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1098110#L874-3 assume !(0 == ~T5_E~0); 1098102#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1098096#L884-3 assume !(0 == ~T7_E~0); 1098091#L889-3 assume !(0 == ~T8_E~0); 1098086#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1098080#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1098076#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1098072#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1098068#L914-3 assume !(0 == ~E_4~0); 1098064#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1098060#L924-3 assume !(0 == ~E_6~0); 1098055#L929-3 assume !(0 == ~E_7~0); 1098051#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1098048#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1098045#L418-30 assume 1 == ~m_pc~0; 1098037#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1098029#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1098021#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1098013#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1098005#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1097998#L437-30 assume !(1 == ~t1_pc~0); 1097991#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1097984#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1097978#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1097973#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1097968#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1097963#L456-30 assume 1 == ~t2_pc~0; 1097957#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1097951#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1097947#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1097942#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1097935#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1097928#L475-30 assume !(1 == ~t3_pc~0); 1097921#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1097913#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1097908#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1097903#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1097897#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1097892#L494-30 assume 1 == ~t4_pc~0; 1097886#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1097879#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1097873#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1097868#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1097861#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1097858#L513-30 assume !(1 == ~t5_pc~0); 1097855#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1097854#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1097853#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1097852#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1097851#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1097850#L532-30 assume !(1 == ~t6_pc~0); 1097848#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1097847#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1097846#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1097845#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1097844#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1097843#L551-30 assume !(1 == ~t7_pc~0); 1093071#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1097841#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1097839#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1097837#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1097834#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1097832#L570-30 assume !(1 == ~t8_pc~0); 1097830#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1097829#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1097826#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1097824#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1097822#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1097820#L952-3 assume !(1 == ~M_E~0); 1097818#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1097816#L957-3 assume !(1 == ~T2_E~0); 1097814#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1097812#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1097810#L972-3 assume !(1 == ~T5_E~0); 1097807#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1097805#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1097803#L987-3 assume !(1 == ~T8_E~0); 1097801#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1097799#L997-3 assume !(1 == ~E_1~0); 1097797#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1097794#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1097792#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1097790#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1097788#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1097786#L1027-3 assume !(1 == ~E_7~0); 1097784#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1097783#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1097708#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1097375#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1092193#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1085572#L1322 assume !(0 == start_simulation_~tmp~3#1); 1085573#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1094839#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1094831#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1094830#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1094829#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1094828#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1094827#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1094826#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1078840#L1303-2 [2024-11-13 16:14:26,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:26,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2024-11-13 16:14:26,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:26,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474566332] [2024-11-13 16:14:26,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:26,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:26,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:26,336 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:26,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:26,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:26,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:26,377 INFO L85 PathProgramCache]: Analyzing trace with hash -929556301, now seen corresponding path program 2 times [2024-11-13 16:14:26,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:26,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133714075] [2024-11-13 16:14:26,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:26,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:26,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:26,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:26,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:26,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133714075] [2024-11-13 16:14:26,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133714075] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:26,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:26,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:26,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103130576] [2024-11-13 16:14:26,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:26,440 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:26,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:26,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:14:26,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:14:26,441 INFO L87 Difference]: Start difference. First operand 43649 states and 61117 transitions. cyclomatic complexity: 17500 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:27,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:27,012 INFO L93 Difference]: Finished difference Result 65665 states and 91482 transitions. [2024-11-13 16:14:27,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65665 states and 91482 transitions. [2024-11-13 16:14:27,283 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65168 [2024-11-13 16:14:27,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65665 states to 65665 states and 91482 transitions. [2024-11-13 16:14:27,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65665 [2024-11-13 16:14:27,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65665 [2024-11-13 16:14:27,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65665 states and 91482 transitions. [2024-11-13 16:14:27,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:27,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65665 states and 91482 transitions. [2024-11-13 16:14:27,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65665 states and 91482 transitions. [2024-11-13 16:14:28,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65665 to 65505. [2024-11-13 16:14:28,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65505 states, 65505 states have (on average 1.393145561407526) internal successors, (91258), 65504 states have internal predecessors, (91258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:28,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65505 states to 65505 states and 91258 transitions. [2024-11-13 16:14:28,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65505 states and 91258 transitions. [2024-11-13 16:14:28,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:14:28,802 INFO L424 stractBuchiCegarLoop]: Abstraction has 65505 states and 91258 transitions. [2024-11-13 16:14:28,802 INFO L331 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-13 16:14:28,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65505 states and 91258 transitions. [2024-11-13 16:14:28,950 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65008 [2024-11-13 16:14:28,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:28,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:28,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:28,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:28,952 INFO L745 eck$LassoCheckResult]: Stem: 1187664#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1187665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1188438#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1188439#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1188532#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1188136#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1188137#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1187685#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1187686#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1187613#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1187614#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1187894#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1187866#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1187867#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1188198#L854 assume !(0 == ~M_E~0); 1187965#L854-2 assume !(0 == ~T1_E~0); 1187966#L859-1 assume !(0 == ~T2_E~0); 1187490#L864-1 assume !(0 == ~T3_E~0); 1187491#L869-1 assume !(0 == ~T4_E~0); 1187600#L874-1 assume !(0 == ~T5_E~0); 1188500#L879-1 assume !(0 == ~T6_E~0); 1187952#L884-1 assume !(0 == ~T7_E~0); 1187354#L889-1 assume !(0 == ~T8_E~0); 1187355#L894-1 assume !(0 == ~E_M~0); 1187697#L899-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1188605#L904-1 assume !(0 == ~E_2~0); 1187884#L909-1 assume !(0 == ~E_3~0); 1187885#L914-1 assume !(0 == ~E_4~0); 1188155#L919-1 assume !(0 == ~E_5~0); 1188156#L924-1 assume !(0 == ~E_6~0); 1187587#L929-1 assume !(0 == ~E_7~0); 1187588#L934-1 assume !(0 == ~E_8~0); 1187863#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1187370#L418 assume !(1 == ~m_pc~0); 1187371#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1188419#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1188420#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1188325#L1061 assume !(0 != activate_threads_~tmp~1#1); 1188326#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1188547#L437 assume !(1 == ~t1_pc~0); 1188548#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1188334#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1188335#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1187728#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1187729#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1188316#L456 assume !(1 == ~t2_pc~0); 1188317#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1188542#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1188543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1188369#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1188370#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1187485#L475 assume !(1 == ~t3_pc~0); 1187486#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1187549#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1187550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1188482#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1188483#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1188409#L494 assume !(1 == ~t4_pc~0); 1188410#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1188088#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1188089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1188590#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1188591#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1187545#L513 assume !(1 == ~t5_pc~0); 1187546#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1188561#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1188562#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1187497#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1187498#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1187450#L532 assume !(1 == ~t6_pc~0); 1187451#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1187928#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1187929#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1188521#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1188522#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1188374#L551 assume !(1 == ~t7_pc~0); 1188206#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1188207#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1188577#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1188578#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1188612#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1187908#L570 assume !(1 == ~t8_pc~0); 1187909#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1188444#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1188445#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1188027#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1188028#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1188342#L952 assume !(1 == ~M_E~0); 1188343#L952-2 assume !(1 == ~T1_E~0); 1188290#L957-1 assume !(1 == ~T2_E~0); 1188291#L962-1 assume !(1 == ~T3_E~0); 1188046#L967-1 assume !(1 == ~T4_E~0); 1188047#L972-1 assume !(1 == ~T5_E~0); 1188377#L977-1 assume !(1 == ~T6_E~0); 1188378#L982-1 assume !(1 == ~T7_E~0); 1187605#L987-1 assume !(1 == ~T8_E~0); 1187606#L992-1 assume !(1 == ~E_M~0); 1187615#L997-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1187999#L1002-1 assume !(1 == ~E_2~0); 1187983#L1007-1 assume !(1 == ~E_3~0); 1187356#L1012-1 assume !(1 == ~E_4~0); 1187357#L1017-1 assume !(1 == ~E_5~0); 1187989#L1022-1 assume !(1 == ~E_6~0); 1187990#L1027-1 assume !(1 == ~E_7~0); 1188015#L1032-1 assume !(1 == ~E_8~0); 1188186#L1037-1 assume { :end_inline_reset_delta_events } true; 1188187#L1303-2 [2024-11-13 16:14:28,953 INFO L747 eck$LassoCheckResult]: Loop: 1188187#L1303-2 assume !false; 1216152#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1213487#L829-1 assume !false; 1216149#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216134#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216130#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216128#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1216125#L712 assume !(0 != eval_~tmp~0#1); 1216126#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1216393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1216392#L854-3 assume !(0 == ~M_E~0); 1216391#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1216390#L859-3 assume !(0 == ~T2_E~0); 1216389#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1216387#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1216386#L874-3 assume !(0 == ~T5_E~0); 1216385#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1216383#L884-3 assume !(0 == ~T7_E~0); 1216382#L889-3 assume !(0 == ~T8_E~0); 1216381#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1216380#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1216378#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1216376#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1216374#L914-3 assume !(0 == ~E_4~0); 1216372#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1216370#L924-3 assume !(0 == ~E_6~0); 1216368#L929-3 assume !(0 == ~E_7~0); 1216366#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1216364#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1216360#L418-30 assume 1 == ~m_pc~0; 1216358#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1216359#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1216388#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1216348#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1216346#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1216344#L437-30 assume !(1 == ~t1_pc~0); 1216342#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1216340#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1216338#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1216336#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1216334#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1216332#L456-30 assume 1 == ~t2_pc~0; 1216328#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1216326#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1216324#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1216322#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1216320#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1216318#L475-30 assume !(1 == ~t3_pc~0); 1216316#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1216314#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1216312#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1216310#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1216308#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1216306#L494-30 assume 1 == ~t4_pc~0; 1216302#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1216300#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1216298#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1216296#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1216294#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1216292#L513-30 assume !(1 == ~t5_pc~0); 1216290#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1216288#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1216286#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1216284#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1216282#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1216280#L532-30 assume !(1 == ~t6_pc~0); 1216276#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1216274#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1216272#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1216270#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1216268#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1216266#L551-30 assume !(1 == ~t7_pc~0); 1212802#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1216264#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1216262#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1216260#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1216258#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1216256#L570-30 assume !(1 == ~t8_pc~0); 1216254#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1216252#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1216250#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1216248#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1216246#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1216244#L952-3 assume !(1 == ~M_E~0); 1216242#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1216240#L957-3 assume !(1 == ~T2_E~0); 1216238#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1216236#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1216234#L972-3 assume !(1 == ~T5_E~0); 1216232#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1216230#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1216228#L987-3 assume !(1 == ~T8_E~0); 1216226#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1216225#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1216223#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1216222#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1216221#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1216220#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1216218#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1216216#L1027-3 assume !(1 == ~E_7~0); 1216214#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1216212#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216191#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216189#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216187#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1216184#L1322 assume !(0 == start_simulation_~tmp~3#1); 1216182#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216176#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216167#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1216163#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1216161#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1216159#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1216157#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1188187#L1303-2 [2024-11-13 16:14:28,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:28,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1215057335, now seen corresponding path program 1 times [2024-11-13 16:14:28,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:28,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785941146] [2024-11-13 16:14:28,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:28,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:28,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:29,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:29,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:29,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785941146] [2024-11-13 16:14:29,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785941146] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:29,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:29,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:29,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791930020] [2024-11-13 16:14:29,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:29,018 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 16:14:29,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:29,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1352258127, now seen corresponding path program 1 times [2024-11-13 16:14:29,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:29,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317959664] [2024-11-13 16:14:29,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:29,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:29,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:29,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:29,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:29,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317959664] [2024-11-13 16:14:29,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317959664] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:29,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:29,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:14:29,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256326296] [2024-11-13 16:14:29,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:29,095 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:29,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:29,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 16:14:29,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 16:14:29,096 INFO L87 Difference]: Start difference. First operand 65505 states and 91258 transitions. cyclomatic complexity: 25785 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:29,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:29,601 INFO L93 Difference]: Finished difference Result 90225 states and 125606 transitions. [2024-11-13 16:14:29,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90225 states and 125606 transitions. [2024-11-13 16:14:30,022 INFO L131 ngComponentsAnalysis]: Automaton has 56 accepting balls. 87952 [2024-11-13 16:14:30,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90225 states to 90225 states and 125606 transitions. [2024-11-13 16:14:30,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90225 [2024-11-13 16:14:30,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90225 [2024-11-13 16:14:30,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90225 states and 125606 transitions. [2024-11-13 16:14:30,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:30,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 90225 states and 125606 transitions. [2024-11-13 16:14:30,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90225 states and 125606 transitions. [2024-11-13 16:14:31,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90225 to 62801. [2024-11-13 16:14:31,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62801 states, 62801 states have (on average 1.391761277686661) internal successors, (87404), 62800 states have internal predecessors, (87404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:31,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62801 states to 62801 states and 87404 transitions. [2024-11-13 16:14:31,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62801 states and 87404 transitions. [2024-11-13 16:14:31,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 16:14:31,638 INFO L424 stractBuchiCegarLoop]: Abstraction has 62801 states and 87404 transitions. [2024-11-13 16:14:31,638 INFO L331 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-13 16:14:31,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62801 states and 87404 transitions. [2024-11-13 16:14:31,803 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62384 [2024-11-13 16:14:31,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:31,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:31,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:31,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:31,809 INFO L745 eck$LassoCheckResult]: Stem: 1343398#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1343399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1344139#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1344140#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1344217#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1343858#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1343859#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1343420#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1343421#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1343350#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1343351#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1343623#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1343591#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1343592#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1343922#L854 assume !(0 == ~M_E~0); 1343701#L854-2 assume !(0 == ~T1_E~0); 1343702#L859-1 assume !(0 == ~T2_E~0); 1343230#L864-1 assume !(0 == ~T3_E~0); 1343231#L869-1 assume !(0 == ~T4_E~0); 1343339#L874-1 assume !(0 == ~T5_E~0); 1344189#L879-1 assume !(0 == ~T6_E~0); 1343685#L884-1 assume !(0 == ~T7_E~0); 1343097#L889-1 assume !(0 == ~T8_E~0); 1343098#L894-1 assume !(0 == ~E_M~0); 1343431#L899-1 assume !(0 == ~E_1~0); 1343928#L904-1 assume !(0 == ~E_2~0); 1343616#L909-1 assume !(0 == ~E_3~0); 1343617#L914-1 assume !(0 == ~E_4~0); 1343847#L919-1 assume !(0 == ~E_5~0); 1343516#L924-1 assume !(0 == ~E_6~0); 1343326#L929-1 assume !(0 == ~E_7~0); 1343327#L934-1 assume !(0 == ~E_8~0); 1343590#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1343113#L418 assume !(1 == ~m_pc~0); 1343090#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1344117#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1344118#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1344042#L1061 assume !(0 != activate_threads_~tmp~1#1); 1343955#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1343956#L437 assume !(1 == ~t1_pc~0); 1344177#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1344049#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1343137#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1343138#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1343463#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1344034#L456 assume !(1 == ~t2_pc~0); 1343380#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1343379#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1343548#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1343549#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1343738#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1343225#L475 assume !(1 == ~t3_pc~0); 1343226#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1343289#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1343105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1343106#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1343466#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1343467#L494 assume !(1 == ~t4_pc~0); 1343511#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1343512#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1343240#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1343241#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1343874#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1343285#L513 assume !(1 == ~t5_pc~0); 1343286#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1343515#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344061#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1343237#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1343238#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1343192#L532 assume !(1 == ~t6_pc~0); 1343193#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1343340#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1343530#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1343531#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1343433#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1343434#L551 assume !(1 == ~t7_pc~0); 1343929#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1343878#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1343879#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1344235#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1344240#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1343640#L570 assume !(1 == ~t8_pc~0); 1343641#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1344147#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1343999#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1343764#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1343223#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1343224#L952 assume !(1 == ~M_E~0); 1343159#L952-2 assume !(1 == ~T1_E~0); 1343160#L957-1 assume !(1 == ~T2_E~0); 1344012#L962-1 assume !(1 == ~T3_E~0); 1343783#L967-1 assume !(1 == ~T4_E~0); 1343784#L972-1 assume !(1 == ~T5_E~0); 1344081#L977-1 assume !(1 == ~T6_E~0); 1344082#L982-1 assume !(1 == ~T7_E~0); 1343342#L987-1 assume !(1 == ~T8_E~0); 1343343#L992-1 assume !(1 == ~E_M~0); 1343352#L997-1 assume !(1 == ~E_1~0); 1343736#L1002-1 assume !(1 == ~E_2~0); 1343720#L1007-1 assume !(1 == ~E_3~0); 1343099#L1012-1 assume !(1 == ~E_4~0); 1343100#L1017-1 assume !(1 == ~E_5~0); 1343726#L1022-1 assume !(1 == ~E_6~0); 1343727#L1027-1 assume !(1 == ~E_7~0); 1343752#L1032-1 assume !(1 == ~E_8~0); 1343909#L1037-1 assume { :end_inline_reset_delta_events } true; 1343910#L1303-2 [2024-11-13 16:14:31,809 INFO L747 eck$LassoCheckResult]: Loop: 1343910#L1303-2 assume !false; 1381035#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1380979#L829-1 assume !false; 1380978#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1380806#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1380797#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1380790#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1380782#L712 assume !(0 != eval_~tmp~0#1); 1380783#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1401496#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401494#L854-3 assume !(0 == ~M_E~0); 1401492#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1401490#L859-3 assume !(0 == ~T2_E~0); 1401488#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1401474#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1401469#L874-3 assume !(0 == ~T5_E~0); 1401462#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1401455#L884-3 assume !(0 == ~T7_E~0); 1401450#L889-3 assume !(0 == ~T8_E~0); 1401444#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1401437#L899-3 assume !(0 == ~E_1~0); 1401431#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1401424#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1401417#L914-3 assume !(0 == ~E_4~0); 1401412#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1401406#L924-3 assume !(0 == ~E_6~0); 1401401#L929-3 assume !(0 == ~E_7~0); 1401395#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1401390#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1401382#L418-30 assume !(1 == ~m_pc~0); 1401376#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1401427#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1401419#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1401291#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1401286#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1401284#L437-30 assume !(1 == ~t1_pc~0); 1401282#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1401280#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1401278#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1401276#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1401274#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1401271#L456-30 assume !(1 == ~t2_pc~0); 1401269#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1401266#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1401264#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1401262#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1401260#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1401258#L475-30 assume !(1 == ~t3_pc~0); 1401256#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1401254#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1401252#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1401250#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1401248#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1401245#L494-30 assume !(1 == ~t4_pc~0); 1401243#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1401240#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1401238#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1401236#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1401234#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1401231#L513-30 assume !(1 == ~t5_pc~0); 1401229#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1401227#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1401225#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1401223#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1401221#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1401218#L532-30 assume 1 == ~t6_pc~0; 1401216#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1401213#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1401211#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1401210#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1400525#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1372177#L551-30 assume !(1 == ~t7_pc~0); 1372176#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1372175#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1372173#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1372171#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1372170#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1372166#L570-30 assume !(1 == ~t8_pc~0); 1372164#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1372162#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1372160#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1372157#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1372155#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1372152#L952-3 assume !(1 == ~M_E~0); 1372150#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1372148#L957-3 assume !(1 == ~T2_E~0); 1372146#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1372144#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1372142#L972-3 assume !(1 == ~T5_E~0); 1372140#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1372137#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1372135#L987-3 assume !(1 == ~T8_E~0); 1372133#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1372131#L997-3 assume !(1 == ~E_1~0); 1372129#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1372127#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1372124#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1372122#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1372120#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1372118#L1027-3 assume !(1 == ~E_7~0); 1372116#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1372114#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1372093#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1372091#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1372089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1358755#L1322 assume !(0 == start_simulation_~tmp~3#1); 1358756#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1381316#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1381301#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1381286#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1381285#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1381259#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1381066#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1381062#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1343910#L1303-2 [2024-11-13 16:14:31,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:31,809 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2024-11-13 16:14:31,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:31,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627471001] [2024-11-13 16:14:31,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:31,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:31,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:31,839 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:31,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:31,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:31,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:31,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1163728245, now seen corresponding path program 1 times [2024-11-13 16:14:31,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:31,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638776517] [2024-11-13 16:14:31,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:31,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:31,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:31,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:31,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:31,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638776517] [2024-11-13 16:14:31,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638776517] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:31,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:31,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:14:31,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600056943] [2024-11-13 16:14:31,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:31,962 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:31,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:31,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 16:14:31,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 16:14:31,963 INFO L87 Difference]: Start difference. First operand 62801 states and 87404 transitions. cyclomatic complexity: 24635 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:32,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:32,751 INFO L93 Difference]: Finished difference Result 63345 states and 87948 transitions. [2024-11-13 16:14:32,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63345 states and 87948 transitions. [2024-11-13 16:14:33,007 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62928 [2024-11-13 16:14:33,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63345 states to 63345 states and 87948 transitions. [2024-11-13 16:14:33,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63345 [2024-11-13 16:14:33,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63345 [2024-11-13 16:14:33,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63345 states and 87948 transitions. [2024-11-13 16:14:33,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:33,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63345 states and 87948 transitions. [2024-11-13 16:14:33,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63345 states and 87948 transitions. [2024-11-13 16:14:33,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63345 to 63089. [2024-11-13 16:14:33,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63089 states, 63089 states have (on average 1.3899728954334354) internal successors, (87692), 63088 states have internal predecessors, (87692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:34,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63089 states to 63089 states and 87692 transitions. [2024-11-13 16:14:34,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63089 states and 87692 transitions. [2024-11-13 16:14:34,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 16:14:34,090 INFO L424 stractBuchiCegarLoop]: Abstraction has 63089 states and 87692 transitions. [2024-11-13 16:14:34,090 INFO L331 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-13 16:14:34,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63089 states and 87692 transitions. [2024-11-13 16:14:34,532 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62672 [2024-11-13 16:14:34,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:34,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:34,533 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:34,533 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:34,533 INFO L745 eck$LassoCheckResult]: Stem: 1469554#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1469555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1470288#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1470289#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1470377#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1470007#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1470008#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1469576#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1469577#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1469506#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1469507#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1469781#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1469745#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1469746#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1470067#L854 assume !(0 == ~M_E~0); 1469848#L854-2 assume !(0 == ~T1_E~0); 1469849#L859-1 assume !(0 == ~T2_E~0); 1469384#L864-1 assume !(0 == ~T3_E~0); 1469385#L869-1 assume !(0 == ~T4_E~0); 1469495#L874-1 assume !(0 == ~T5_E~0); 1470342#L879-1 assume !(0 == ~T6_E~0); 1469833#L884-1 assume !(0 == ~T7_E~0); 1469251#L889-1 assume !(0 == ~T8_E~0); 1469252#L894-1 assume !(0 == ~E_M~0); 1469587#L899-1 assume !(0 == ~E_1~0); 1470073#L904-1 assume !(0 == ~E_2~0); 1469773#L909-1 assume !(0 == ~E_3~0); 1469774#L914-1 assume !(0 == ~E_4~0); 1469995#L919-1 assume !(0 == ~E_5~0); 1469668#L924-1 assume !(0 == ~E_6~0); 1469482#L929-1 assume !(0 == ~E_7~0); 1469483#L934-1 assume !(0 == ~E_8~0); 1469744#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1469267#L418 assume !(1 == ~m_pc~0); 1469243#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1470269#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1470270#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1470193#L1061 assume !(0 != activate_threads_~tmp~1#1); 1470103#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1470104#L437 assume !(1 == ~t1_pc~0); 1470333#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1470201#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1469291#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1469292#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1469615#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1470186#L456 assume !(1 == ~t2_pc~0); 1469537#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1469536#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1469701#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1469702#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1469884#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1469379#L475 assume !(1 == ~t3_pc~0); 1469380#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1469445#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1469259#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1469260#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1469618#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1469619#L494 assume !(1 == ~t4_pc~0); 1469661#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1469662#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1469395#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1469396#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1470024#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1469441#L513 assume !(1 == ~t5_pc~0); 1469442#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1469667#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1470215#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1469391#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1469392#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1469346#L532 assume !(1 == ~t6_pc~0); 1469347#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1469496#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1469681#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1469682#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1469589#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1469590#L551 assume !(1 == ~t7_pc~0); 1470074#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1470028#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1470029#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1470402#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1470408#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1469793#L570 assume !(1 == ~t8_pc~0); 1469794#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1470293#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1470151#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1469909#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1469377#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1469378#L952 assume !(1 == ~M_E~0); 1469313#L952-2 assume !(1 == ~T1_E~0); 1469314#L957-1 assume !(1 == ~T2_E~0); 1470163#L962-1 assume !(1 == ~T3_E~0); 1469926#L967-1 assume !(1 == ~T4_E~0); 1469927#L972-1 assume !(1 == ~T5_E~0); 1470233#L977-1 assume !(1 == ~T6_E~0); 1470234#L982-1 assume !(1 == ~T7_E~0); 1469498#L987-1 assume !(1 == ~T8_E~0); 1469499#L992-1 assume !(1 == ~E_M~0); 1469508#L997-1 assume !(1 == ~E_1~0); 1469882#L1002-1 assume !(1 == ~E_2~0); 1469866#L1007-1 assume !(1 == ~E_3~0); 1469253#L1012-1 assume !(1 == ~E_4~0); 1469254#L1017-1 assume !(1 == ~E_5~0); 1469872#L1022-1 assume !(1 == ~E_6~0); 1469873#L1027-1 assume !(1 == ~E_7~0); 1469898#L1032-1 assume !(1 == ~E_8~0); 1470057#L1037-1 assume { :end_inline_reset_delta_events } true; 1470058#L1303-2 [2024-11-13 16:14:34,533 INFO L747 eck$LassoCheckResult]: Loop: 1470058#L1303-2 assume !false; 1493550#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1493543#L829-1 assume !false; 1493539#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1493508#L650 assume !(0 == ~m_st~0); 1493509#L654 assume !(0 == ~t1_st~0); 1493513#L658 assume !(0 == ~t2_st~0); 1493506#L662 assume !(0 == ~t3_st~0); 1493507#L666 assume !(0 == ~t4_st~0); 1493512#L670 assume !(0 == ~t5_st~0); 1493515#L674 assume !(0 == ~t6_st~0); 1493510#L678 assume !(0 == ~t7_st~0); 1493511#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1493514#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1493496#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1493497#L712 assume !(0 != eval_~tmp~0#1); 1497230#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1497211#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1497212#L854-3 assume !(0 == ~M_E~0); 1497189#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1497190#L859-3 assume !(0 == ~T2_E~0); 1497167#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1497168#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1497148#L874-3 assume !(0 == ~T5_E~0); 1497149#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1497133#L884-3 assume !(0 == ~T7_E~0); 1497134#L889-3 assume !(0 == ~T8_E~0); 1497115#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1497116#L899-3 assume !(0 == ~E_1~0); 1497095#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1497096#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1497074#L914-3 assume !(0 == ~E_4~0); 1497075#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1497054#L924-3 assume !(0 == ~E_6~0); 1497055#L929-3 assume !(0 == ~E_7~0); 1497036#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1497037#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1497017#L418-30 assume 1 == ~m_pc~0; 1497018#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1496995#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1496996#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1496966#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1496967#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1496940#L437-30 assume !(1 == ~t1_pc~0); 1496941#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1496912#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1496913#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1496885#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1496886#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1496859#L456-30 assume 1 == ~t2_pc~0; 1496860#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1496834#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1496835#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1496810#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1496811#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1496784#L475-30 assume !(1 == ~t3_pc~0); 1496785#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1496697#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1496698#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1496537#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1496538#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1496377#L494-30 assume !(1 == ~t4_pc~0); 1496378#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1496154#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1496155#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1496065#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1496066#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1495900#L513-30 assume !(1 == ~t5_pc~0); 1495901#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1495775#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1495776#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1495422#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1495423#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1495022#L532-30 assume 1 == ~t6_pc~0; 1495024#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1494584#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494585#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1494558#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1494559#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1494282#L551-30 assume !(1 == ~t7_pc~0); 1494280#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1494278#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1494275#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1494273#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1494271#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1494269#L570-30 assume !(1 == ~t8_pc~0); 1494267#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1494265#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1494262#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1494260#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1494258#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1494256#L952-3 assume !(1 == ~M_E~0); 1494254#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1494252#L957-3 assume !(1 == ~T2_E~0); 1494249#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1494247#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1494245#L972-3 assume !(1 == ~T5_E~0); 1494243#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1494241#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1494239#L987-3 assume !(1 == ~T8_E~0); 1494237#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1494235#L997-3 assume !(1 == ~E_1~0); 1494233#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1494231#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1494229#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1494227#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1494224#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1494222#L1027-3 assume !(1 == ~E_7~0); 1494220#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1494218#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1494198#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1494190#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1494169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1494167#L1322 assume !(0 == start_simulation_~tmp~3#1); 1494166#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1494162#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1493960#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1493694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1493603#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1493593#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1493583#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1493569#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1470058#L1303-2 [2024-11-13 16:14:34,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:34,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2024-11-13 16:14:34,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:34,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738935062] [2024-11-13 16:14:34,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:34,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:34,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:34,548 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:34,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:34,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:34,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:34,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1909128165, now seen corresponding path program 1 times [2024-11-13 16:14:34,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:34,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427155241] [2024-11-13 16:14:34,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:34,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:34,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:34,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:34,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:34,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427155241] [2024-11-13 16:14:34,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427155241] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:34,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:34,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:14:34,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188779035] [2024-11-13 16:14:34,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:34,705 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:34,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:34,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 16:14:34,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 16:14:34,705 INFO L87 Difference]: Start difference. First operand 63089 states and 87692 transitions. cyclomatic complexity: 24635 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:35,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:35,192 INFO L93 Difference]: Finished difference Result 63857 states and 87979 transitions. [2024-11-13 16:14:35,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63857 states and 87979 transitions. [2024-11-13 16:14:35,385 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 63440 [2024-11-13 16:14:35,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63857 states to 63857 states and 87979 transitions. [2024-11-13 16:14:35,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63857 [2024-11-13 16:14:35,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63857 [2024-11-13 16:14:35,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63857 states and 87979 transitions. [2024-11-13 16:14:35,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:35,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63857 states and 87979 transitions. [2024-11-13 16:14:35,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63857 states and 87979 transitions. [2024-11-13 16:14:36,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63857 to 63857. [2024-11-13 16:14:36,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63857 states, 63857 states have (on average 1.3777502857948227) internal successors, (87979), 63856 states have internal predecessors, (87979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:36,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63857 states to 63857 states and 87979 transitions. [2024-11-13 16:14:36,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63857 states and 87979 transitions. [2024-11-13 16:14:36,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 16:14:36,702 INFO L424 stractBuchiCegarLoop]: Abstraction has 63857 states and 87979 transitions. [2024-11-13 16:14:36,702 INFO L331 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-13 16:14:36,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63857 states and 87979 transitions. [2024-11-13 16:14:36,871 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 63440 [2024-11-13 16:14:36,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:36,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:36,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:36,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:36,873 INFO L745 eck$LassoCheckResult]: Stem: 1596507#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1596508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1597244#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1597245#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1597319#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1596960#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1596961#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1596529#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1596530#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1596459#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1596460#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1596729#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1596698#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1596699#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1597022#L854 assume !(0 == ~M_E~0); 1596803#L854-2 assume !(0 == ~T1_E~0); 1596804#L859-1 assume !(0 == ~T2_E~0); 1596338#L864-1 assume !(0 == ~T3_E~0); 1596339#L869-1 assume !(0 == ~T4_E~0); 1596448#L874-1 assume !(0 == ~T5_E~0); 1597295#L879-1 assume !(0 == ~T6_E~0); 1596788#L884-1 assume !(0 == ~T7_E~0); 1596205#L889-1 assume !(0 == ~T8_E~0); 1596206#L894-1 assume !(0 == ~E_M~0); 1596540#L899-1 assume !(0 == ~E_1~0); 1597028#L904-1 assume !(0 == ~E_2~0); 1596722#L909-1 assume !(0 == ~E_3~0); 1596723#L914-1 assume !(0 == ~E_4~0); 1596948#L919-1 assume !(0 == ~E_5~0); 1596621#L924-1 assume !(0 == ~E_6~0); 1596435#L929-1 assume !(0 == ~E_7~0); 1596436#L934-1 assume !(0 == ~E_8~0); 1596697#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1596221#L418 assume !(1 == ~m_pc~0); 1596197#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1597230#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1597231#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1597158#L1061 assume !(0 != activate_threads_~tmp~1#1); 1597059#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1597060#L437 assume !(1 == ~t1_pc~0); 1597283#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1597164#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1596245#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1596246#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1596569#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1597151#L456 assume !(1 == ~t2_pc~0); 1596489#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1596488#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1596653#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1596654#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1596837#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1596333#L475 assume !(1 == ~t3_pc~0); 1596334#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1596398#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1596213#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1596214#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1596572#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1596573#L494 assume !(1 == ~t4_pc~0); 1596615#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1596616#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1596348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1596349#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1596977#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1596394#L513 assume !(1 == ~t5_pc~0); 1596395#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1596620#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1597177#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1596345#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1596346#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1596300#L532 assume !(1 == ~t6_pc~0); 1596301#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1596449#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1596635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1596636#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1596542#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1596543#L551 assume !(1 == ~t7_pc~0); 1597029#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1596979#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1596980#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1597340#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1597344#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1596746#L570 assume !(1 == ~t8_pc~0); 1596747#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1597251#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1597111#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1596862#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1596331#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1596332#L952 assume !(1 == ~M_E~0); 1596267#L952-2 assume !(1 == ~T1_E~0); 1596268#L957-1 assume !(1 == ~T2_E~0); 1597126#L962-1 assume !(1 == ~T3_E~0); 1596881#L967-1 assume !(1 == ~T4_E~0); 1596882#L972-1 assume !(1 == ~T5_E~0); 1597196#L977-1 assume !(1 == ~T6_E~0); 1597197#L982-1 assume !(1 == ~T7_E~0); 1596451#L987-1 assume !(1 == ~T8_E~0); 1596452#L992-1 assume !(1 == ~E_M~0); 1596461#L997-1 assume !(1 == ~E_1~0); 1596835#L1002-1 assume !(1 == ~E_2~0); 1596819#L1007-1 assume !(1 == ~E_3~0); 1596207#L1012-1 assume !(1 == ~E_4~0); 1596208#L1017-1 assume !(1 == ~E_5~0); 1596825#L1022-1 assume !(1 == ~E_6~0); 1596826#L1027-1 assume !(1 == ~E_7~0); 1596850#L1032-1 assume !(1 == ~E_8~0); 1597009#L1037-1 assume { :end_inline_reset_delta_events } true; 1597010#L1303-2 [2024-11-13 16:14:36,873 INFO L747 eck$LassoCheckResult]: Loop: 1597010#L1303-2 assume !false; 1603597#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1603596#L829-1 assume !false; 1603595#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1603587#L650 assume !(0 == ~m_st~0); 1603588#L654 assume !(0 == ~t1_st~0); 1603592#L658 assume !(0 == ~t2_st~0); 1603585#L662 assume !(0 == ~t3_st~0); 1603586#L666 assume !(0 == ~t4_st~0); 1603591#L670 assume !(0 == ~t5_st~0); 1603594#L674 assume !(0 == ~t6_st~0); 1603589#L678 assume !(0 == ~t7_st~0); 1603590#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1603593#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1606163#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1605912#L712 assume !(0 != eval_~tmp~0#1); 1605913#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1606044#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1606043#L854-3 assume !(0 == ~M_E~0); 1606042#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1606041#L859-3 assume !(0 == ~T2_E~0); 1606040#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1606039#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1606038#L874-3 assume !(0 == ~T5_E~0); 1606037#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1606036#L884-3 assume !(0 == ~T7_E~0); 1606035#L889-3 assume !(0 == ~T8_E~0); 1606034#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1606033#L899-3 assume !(0 == ~E_1~0); 1606032#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1606031#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1606030#L914-3 assume !(0 == ~E_4~0); 1606029#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1606028#L924-3 assume !(0 == ~E_6~0); 1606027#L929-3 assume !(0 == ~E_7~0); 1606026#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1606025#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1605864#L418-30 assume 1 == ~m_pc~0; 1605865#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1606024#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606022#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1606020#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1606019#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1606018#L437-30 assume !(1 == ~t1_pc~0); 1606017#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1606016#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1606015#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1606014#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 1606013#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1606012#L456-30 assume 1 == ~t2_pc~0; 1606010#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1606009#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1606008#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1606007#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1606006#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1606005#L475-30 assume !(1 == ~t3_pc~0); 1606004#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1606003#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1606002#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1605782#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1605783#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1605775#L494-30 assume !(1 == ~t4_pc~0); 1605776#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1605768#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1605769#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1605762#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1605763#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1605757#L513-30 assume !(1 == ~t5_pc~0); 1605755#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1605753#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1605751#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1605749#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1605747#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1605745#L532-30 assume !(1 == ~t6_pc~0); 1605742#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1605740#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1605625#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1604691#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1604680#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1604554#L551-30 assume !(1 == ~t7_pc~0); 1604550#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1604546#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1604541#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1604538#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1604535#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1604530#L570-30 assume !(1 == ~t8_pc~0); 1604466#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1604465#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1604463#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1604461#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1604460#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1604459#L952-3 assume !(1 == ~M_E~0); 1604456#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1604454#L957-3 assume !(1 == ~T2_E~0); 1604452#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1604450#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1604448#L972-3 assume !(1 == ~T5_E~0); 1604446#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1604444#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1604442#L987-3 assume !(1 == ~T8_E~0); 1604440#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1604428#L997-3 assume !(1 == ~E_1~0); 1604424#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1604420#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1604415#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1604411#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1604407#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1604403#L1027-3 assume !(1 == ~E_7~0); 1604398#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1604393#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1604383#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1604381#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1604379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1604377#L1322 assume !(0 == start_simulation_~tmp~3#1); 1604375#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1604372#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1604363#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1604361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1604359#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1604357#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1604354#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1604352#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1597010#L1303-2 [2024-11-13 16:14:36,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:36,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 5 times [2024-11-13 16:14:36,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:36,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072387550] [2024-11-13 16:14:36,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:36,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:36,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:36,891 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:36,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:36,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:36,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:36,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1293179614, now seen corresponding path program 1 times [2024-11-13 16:14:36,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:36,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167185725] [2024-11-13 16:14:36,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:36,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:36,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:37,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:37,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:37,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167185725] [2024-11-13 16:14:37,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [167185725] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:37,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:37,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:14:37,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097809862] [2024-11-13 16:14:37,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:37,024 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:37,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:37,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 16:14:37,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 16:14:37,024 INFO L87 Difference]: Start difference. First operand 63857 states and 87979 transitions. cyclomatic complexity: 24154 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:37,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:37,565 INFO L93 Difference]: Finished difference Result 65057 states and 88826 transitions. [2024-11-13 16:14:37,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65057 states and 88826 transitions. [2024-11-13 16:14:37,806 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 64640 [2024-11-13 16:14:37,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65057 states to 65057 states and 88826 transitions. [2024-11-13 16:14:37,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65057 [2024-11-13 16:14:37,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65057 [2024-11-13 16:14:37,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65057 states and 88826 transitions. [2024-11-13 16:14:38,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:38,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65057 states and 88826 transitions. [2024-11-13 16:14:38,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65057 states and 88826 transitions. [2024-11-13 16:14:39,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65057 to 65057. [2024-11-13 16:14:39,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65057 states, 65057 states have (on average 1.365356533501391) internal successors, (88826), 65056 states have internal predecessors, (88826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:39,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65057 states to 65057 states and 88826 transitions. [2024-11-13 16:14:39,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65057 states and 88826 transitions. [2024-11-13 16:14:39,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 16:14:39,329 INFO L424 stractBuchiCegarLoop]: Abstraction has 65057 states and 88826 transitions. [2024-11-13 16:14:39,329 INFO L331 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-13 16:14:39,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65057 states and 88826 transitions. [2024-11-13 16:14:39,536 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 64640 [2024-11-13 16:14:39,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:39,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:39,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:39,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:39,538 INFO L745 eck$LassoCheckResult]: Stem: 1725432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1725433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1726161#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1726162#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1726227#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1725889#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1725890#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1725454#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1725455#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1725383#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1725384#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1725656#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1725626#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1725627#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1725950#L854 assume !(0 == ~M_E~0); 1725729#L854-2 assume !(0 == ~T1_E~0); 1725730#L859-1 assume !(0 == ~T2_E~0); 1725260#L864-1 assume !(0 == ~T3_E~0); 1725261#L869-1 assume !(0 == ~T4_E~0); 1725372#L874-1 assume !(0 == ~T5_E~0); 1726209#L879-1 assume !(0 == ~T6_E~0); 1725714#L884-1 assume !(0 == ~T7_E~0); 1725127#L889-1 assume !(0 == ~T8_E~0); 1725128#L894-1 assume !(0 == ~E_M~0); 1725466#L899-1 assume !(0 == ~E_1~0); 1725956#L904-1 assume !(0 == ~E_2~0); 1725649#L909-1 assume !(0 == ~E_3~0); 1725650#L914-1 assume !(0 == ~E_4~0); 1725876#L919-1 assume !(0 == ~E_5~0); 1725547#L924-1 assume !(0 == ~E_6~0); 1725359#L929-1 assume !(0 == ~E_7~0); 1725360#L934-1 assume !(0 == ~E_8~0); 1725625#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1725143#L418 assume !(1 == ~m_pc~0); 1725119#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1726143#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1726144#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1726073#L1061 assume !(0 != activate_threads_~tmp~1#1); 1725982#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1725983#L437 assume !(1 == ~t1_pc~0); 1726196#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1726080#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1725167#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1725168#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1725493#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1726066#L456 assume !(1 == ~t2_pc~0); 1725413#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1725412#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1725580#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1725581#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1725764#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1725255#L475 assume !(1 == ~t3_pc~0); 1725256#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1725320#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1725135#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1725136#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1725496#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1725497#L494 assume !(1 == ~t4_pc~0); 1725541#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1725542#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1725270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1725271#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1725907#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1725316#L513 assume !(1 == ~t5_pc~0); 1725317#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1725546#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1726092#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1725267#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1725268#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1725222#L532 assume !(1 == ~t6_pc~0); 1725223#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1725373#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1725561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1725562#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1725468#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1725469#L551 assume !(1 == ~t7_pc~0); 1725957#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1725909#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1725910#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1726251#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1726258#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1725672#L570 assume !(1 == ~t8_pc~0); 1725673#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1726167#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1726030#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1725790#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1725253#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1725254#L952 assume !(1 == ~M_E~0); 1725189#L952-2 assume !(1 == ~T1_E~0); 1725190#L957-1 assume !(1 == ~T2_E~0); 1726041#L962-1 assume !(1 == ~T3_E~0); 1725810#L967-1 assume !(1 == ~T4_E~0); 1725811#L972-1 assume !(1 == ~T5_E~0); 1726108#L977-1 assume !(1 == ~T6_E~0); 1726109#L982-1 assume !(1 == ~T7_E~0); 1725375#L987-1 assume !(1 == ~T8_E~0); 1725376#L992-1 assume !(1 == ~E_M~0); 1725385#L997-1 assume !(1 == ~E_1~0); 1725762#L1002-1 assume !(1 == ~E_2~0); 1725747#L1007-1 assume !(1 == ~E_3~0); 1725129#L1012-1 assume !(1 == ~E_4~0); 1725130#L1017-1 assume !(1 == ~E_5~0); 1725753#L1022-1 assume !(1 == ~E_6~0); 1725754#L1027-1 assume !(1 == ~E_7~0); 1725777#L1032-1 assume !(1 == ~E_8~0); 1725936#L1037-1 assume { :end_inline_reset_delta_events } true; 1725937#L1303-2 [2024-11-13 16:14:39,539 INFO L747 eck$LassoCheckResult]: Loop: 1725937#L1303-2 assume !false; 1750820#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1750816#L829-1 assume !false; 1750815#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1750803#L650 assume !(0 == ~m_st~0); 1750804#L654 assume !(0 == ~t1_st~0); 1750808#L658 assume !(0 == ~t2_st~0); 1750801#L662 assume !(0 == ~t3_st~0); 1750802#L666 assume !(0 == ~t4_st~0); 1750807#L670 assume !(0 == ~t5_st~0); 1750810#L674 assume !(0 == ~t6_st~0); 1750805#L678 assume !(0 == ~t7_st~0); 1750806#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1750809#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1753903#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1753700#L712 assume !(0 != eval_~tmp~0#1); 1753701#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1755584#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1755583#L854-3 assume !(0 == ~M_E~0); 1755582#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1755581#L859-3 assume !(0 == ~T2_E~0); 1755580#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1755579#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1755578#L874-3 assume !(0 == ~T5_E~0); 1755577#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1755576#L884-3 assume !(0 == ~T7_E~0); 1755575#L889-3 assume !(0 == ~T8_E~0); 1755574#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1755573#L899-3 assume !(0 == ~E_1~0); 1755572#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1755571#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1755570#L914-3 assume !(0 == ~E_4~0); 1755569#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1755568#L924-3 assume !(0 == ~E_6~0); 1755567#L929-3 assume !(0 == ~E_7~0); 1755566#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1755565#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1753580#L418-30 assume !(1 == ~m_pc~0); 1753582#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1753560#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1753561#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1753555#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1753554#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1753546#L437-30 assume !(1 == ~t1_pc~0); 1753547#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1753539#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1753540#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1753533#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 1753534#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1753525#L456-30 assume 1 == ~t2_pc~0; 1753526#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1753518#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1753519#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1753511#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1753512#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1753505#L475-30 assume !(1 == ~t3_pc~0); 1753506#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1753500#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1753501#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1753492#L1085-30 assume !(0 != activate_threads_~tmp___2~0#1); 1753493#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1753485#L494-30 assume !(1 == ~t4_pc~0); 1753486#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1753477#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1753478#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1753470#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1753471#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1753464#L513-30 assume !(1 == ~t5_pc~0); 1753465#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1753458#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1753459#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1753452#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1753453#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1753445#L532-30 assume !(1 == ~t6_pc~0); 1753446#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1753438#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1753439#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1753431#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1753432#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1753419#L551-30 assume !(1 == ~t7_pc~0); 1753417#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1753415#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1753413#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1753411#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1753409#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1753407#L570-30 assume !(1 == ~t8_pc~0); 1753405#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1753403#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1753401#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1753399#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1753397#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1753395#L952-3 assume !(1 == ~M_E~0); 1753393#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1753391#L957-3 assume !(1 == ~T2_E~0); 1753389#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1753387#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1753385#L972-3 assume !(1 == ~T5_E~0); 1753383#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1753381#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1753380#L987-3 assume !(1 == ~T8_E~0); 1753379#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1753378#L997-3 assume !(1 == ~E_1~0); 1753376#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1753374#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1753372#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1753370#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1753367#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1753365#L1027-3 assume !(1 == ~E_7~0); 1753363#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1753362#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1753349#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1753348#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1753347#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1753345#L1322 assume !(0 == start_simulation_~tmp~3#1); 1753344#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1753338#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1753329#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1753327#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1753325#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1753323#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1753321#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1753319#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1725937#L1303-2 [2024-11-13 16:14:39,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:39,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 6 times [2024-11-13 16:14:39,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:39,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490265318] [2024-11-13 16:14:39,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:39,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:39,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:39,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:39,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:39,600 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:39,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:39,601 INFO L85 PathProgramCache]: Analyzing trace with hash -1399241693, now seen corresponding path program 1 times [2024-11-13 16:14:39,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:39,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519130779] [2024-11-13 16:14:39,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:39,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:39,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:39,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:39,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:39,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519130779] [2024-11-13 16:14:39,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519130779] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:39,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:39,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 16:14:39,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263143334] [2024-11-13 16:14:39,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:39,654 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:39,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:39,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 16:14:39,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 16:14:39,655 INFO L87 Difference]: Start difference. First operand 65057 states and 88826 transitions. cyclomatic complexity: 23801 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:40,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:40,893 INFO L93 Difference]: Finished difference Result 123953 states and 167434 transitions. [2024-11-13 16:14:40,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123953 states and 167434 transitions. [2024-11-13 16:14:41,526 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 123232 [2024-11-13 16:14:41,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123953 states to 123953 states and 167434 transitions. [2024-11-13 16:14:41,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123953 [2024-11-13 16:14:41,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123953 [2024-11-13 16:14:41,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123953 states and 167434 transitions. [2024-11-13 16:14:41,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:41,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123953 states and 167434 transitions. [2024-11-13 16:14:41,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123953 states and 167434 transitions. [2024-11-13 16:14:43,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123953 to 120209. [2024-11-13 16:14:43,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120209 states, 120209 states have (on average 1.3526607824705306) internal successors, (162602), 120208 states have internal predecessors, (162602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:43,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120209 states to 120209 states and 162602 transitions. [2024-11-13 16:14:43,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120209 states and 162602 transitions. [2024-11-13 16:14:43,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 16:14:43,867 INFO L424 stractBuchiCegarLoop]: Abstraction has 120209 states and 162602 transitions. [2024-11-13 16:14:43,867 INFO L331 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-13 16:14:43,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120209 states and 162602 transitions. [2024-11-13 16:14:44,183 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119488 [2024-11-13 16:14:44,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 16:14:44,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 16:14:44,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:44,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 16:14:44,184 INFO L745 eck$LassoCheckResult]: Stem: 1914447#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1914448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1915201#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1915202#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1915289#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1914906#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1914907#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1914469#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1914470#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1914398#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1914399#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1914678#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1914645#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1914646#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1914972#L854 assume !(0 == ~M_E~0); 1914747#L854-2 assume !(0 == ~T1_E~0); 1914748#L859-1 assume !(0 == ~T2_E~0); 1914275#L864-1 assume !(0 == ~T3_E~0); 1914276#L869-1 assume !(0 == ~T4_E~0); 1914387#L874-1 assume !(0 == ~T5_E~0); 1915261#L879-1 assume !(0 == ~T6_E~0); 1914732#L884-1 assume !(0 == ~T7_E~0); 1914143#L889-1 assume !(0 == ~T8_E~0); 1914144#L894-1 assume !(0 == ~E_M~0); 1914481#L899-1 assume !(0 == ~E_1~0); 1914978#L904-1 assume !(0 == ~E_2~0); 1914672#L909-1 assume !(0 == ~E_3~0); 1914673#L914-1 assume !(0 == ~E_4~0); 1914895#L919-1 assume !(0 == ~E_5~0); 1914564#L924-1 assume !(0 == ~E_6~0); 1914374#L929-1 assume !(0 == ~E_7~0); 1914375#L934-1 assume !(0 == ~E_8~0); 1914644#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1914159#L418 assume !(1 == ~m_pc~0); 1914136#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1915181#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1915182#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1915102#L1061 assume !(0 != activate_threads_~tmp~1#1); 1915004#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1915005#L437 assume !(1 == ~t1_pc~0); 1915244#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1915109#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1914183#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1914184#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1914510#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1915095#L456 assume !(1 == ~t2_pc~0); 1914429#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1914428#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1914598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1914599#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1914782#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1914270#L475 assume !(1 == ~t3_pc~0); 1914271#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1914337#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1914151#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1914152#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1914513#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1914514#L494 assume !(1 == ~t4_pc~0); 1914558#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1914559#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1914286#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1914287#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1914926#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1914333#L513 assume !(1 == ~t5_pc~0); 1914334#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1914563#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1915121#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1914282#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1914283#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1914238#L532 assume !(1 == ~t6_pc~0); 1914239#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1914388#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1914579#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1914580#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1914485#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1914486#L551 assume !(1 == ~t7_pc~0); 1914979#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1914928#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1914929#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1915320#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1915325#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1914692#L570 assume !(1 == ~t8_pc~0); 1914693#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1915207#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1915056#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1914807#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1914268#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1914269#L952 assume !(1 == ~M_E~0); 1914205#L952-2 assume !(1 == ~T1_E~0); 1914206#L957-1 assume !(1 == ~T2_E~0); 1915071#L962-1 assume !(1 == ~T3_E~0); 1914823#L967-1 assume !(1 == ~T4_E~0); 1914824#L972-1 assume !(1 == ~T5_E~0); 1915138#L977-1 assume !(1 == ~T6_E~0); 1915139#L982-1 assume !(1 == ~T7_E~0); 1914390#L987-1 assume !(1 == ~T8_E~0); 1914391#L992-1 assume !(1 == ~E_M~0); 1914400#L997-1 assume !(1 == ~E_1~0); 1914780#L1002-1 assume !(1 == ~E_2~0); 1914765#L1007-1 assume !(1 == ~E_3~0); 1914145#L1012-1 assume !(1 == ~E_4~0); 1914146#L1017-1 assume !(1 == ~E_5~0); 1914771#L1022-1 assume !(1 == ~E_6~0); 1914772#L1027-1 assume !(1 == ~E_7~0); 1914795#L1032-1 assume !(1 == ~E_8~0); 1914958#L1037-1 assume { :end_inline_reset_delta_events } true; 1914959#L1303-2 [2024-11-13 16:14:44,185 INFO L747 eck$LassoCheckResult]: Loop: 1914959#L1303-2 assume !false; 1958342#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1958340#L829-1 assume !false; 1958338#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1958336#L650 assume !(0 == ~m_st~0); 1945856#L654 assume !(0 == ~t1_st~0); 1945855#L658 assume !(0 == ~t2_st~0); 1945854#L662 assume !(0 == ~t3_st~0); 1945853#L666 assume !(0 == ~t4_st~0); 1945852#L670 assume !(0 == ~t5_st~0); 1945851#L674 assume !(0 == ~t6_st~0); 1945849#L678 assume !(0 == ~t7_st~0); 1945847#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1945846#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1945845#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1945844#L712 assume !(0 != eval_~tmp~0#1); 1945842#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1945841#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1945840#L854-3 assume !(0 == ~M_E~0); 1945838#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1945835#L859-3 assume !(0 == ~T2_E~0); 1945833#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1945831#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1945830#L874-3 assume !(0 == ~T5_E~0); 1945829#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1945828#L884-3 assume !(0 == ~T7_E~0); 1945824#L889-3 assume !(0 == ~T8_E~0); 1945822#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1945820#L899-3 assume !(0 == ~E_1~0); 1945818#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1945814#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1945812#L914-3 assume !(0 == ~E_4~0); 1945810#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1945808#L924-3 assume !(0 == ~E_6~0); 1945806#L929-3 assume !(0 == ~E_7~0); 1945804#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1945802#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1945800#L418-30 assume 1 == ~m_pc~0; 1945797#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1945794#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1945792#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1945789#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1945787#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1945785#L437-30 assume !(1 == ~t1_pc~0); 1945781#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1945779#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1945777#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1945775#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 1945772#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1945770#L456-30 assume !(1 == ~t2_pc~0); 1945768#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1945764#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1945762#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1945760#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1945758#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1945756#L475-30 assume !(1 == ~t3_pc~0); 1945754#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1945752#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1945750#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1945748#L1085-30 assume !(0 != activate_threads_~tmp___2~0#1); 1945746#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1945744#L494-30 assume 1 == ~t4_pc~0; 1945741#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1945738#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1945736#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1945734#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1945732#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1945730#L513-30 assume !(1 == ~t5_pc~0); 1945728#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1945727#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1945725#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1945723#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1945721#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1945719#L532-30 assume 1 == ~t6_pc~0; 1945717#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1945714#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1945712#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1945710#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1945708#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1945706#L551-30 assume !(1 == ~t7_pc~0); 1929350#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1945702#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1945700#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1945698#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1945697#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1945694#L570-30 assume !(1 == ~t8_pc~0); 1945690#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1945686#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1945682#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1945679#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1945676#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1945673#L952-3 assume !(1 == ~M_E~0); 1945671#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1945669#L957-3 assume !(1 == ~T2_E~0); 1945666#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1945664#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1945662#L972-3 assume !(1 == ~T5_E~0); 1945661#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1945660#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1945658#L987-3 assume !(1 == ~T8_E~0); 1945657#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1945656#L997-3 assume !(1 == ~E_1~0); 1945655#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1945654#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1945652#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1945650#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1945648#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1945646#L1027-3 assume !(1 == ~E_7~0); 1945644#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1945642#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1945639#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1945637#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1945635#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1945631#L1322 assume !(0 == start_simulation_~tmp~3#1); 1945632#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1958363#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1958361#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1958359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1958357#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1958355#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1958353#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1958351#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1914959#L1303-2 [2024-11-13 16:14:44,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:44,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 7 times [2024-11-13 16:14:44,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:44,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123137937] [2024-11-13 16:14:44,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:44,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:44,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:44,200 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 16:14:44,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 16:14:44,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 16:14:44,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 16:14:44,232 INFO L85 PathProgramCache]: Analyzing trace with hash 511035551, now seen corresponding path program 1 times [2024-11-13 16:14:44,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 16:14:44,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590247990] [2024-11-13 16:14:44,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 16:14:44,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 16:14:44,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 16:14:44,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 16:14:44,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 16:14:44,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590247990] [2024-11-13 16:14:44,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590247990] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 16:14:44,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 16:14:44,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 16:14:44,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593387458] [2024-11-13 16:14:44,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 16:14:44,311 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 16:14:44,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 16:14:44,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 16:14:44,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 16:14:44,312 INFO L87 Difference]: Start difference. First operand 120209 states and 162602 transitions. cyclomatic complexity: 42425 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 16:14:45,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 16:14:45,837 INFO L93 Difference]: Finished difference Result 124532 states and 166925 transitions. [2024-11-13 16:14:45,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124532 states and 166925 transitions. [2024-11-13 16:14:46,301 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 123808 [2024-11-13 16:14:46,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124532 states to 124532 states and 166925 transitions. [2024-11-13 16:14:46,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124532 [2024-11-13 16:14:46,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124532 [2024-11-13 16:14:46,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124532 states and 166925 transitions. [2024-11-13 16:14:46,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 16:14:46,604 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124532 states and 166925 transitions. [2024-11-13 16:14:46,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124532 states and 166925 transitions.